1 # ====================================================================
5 # FR30/mb91301 variant architectural HAL package configuration data
7 # ====================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
9 ## -------------------------------------------
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40 # ====================================================================
41 ######DESCRIPTIONBEGIN####
44 # Original data: bartv, nickg
48 #####DESCRIPTIONEND####
50 # ====================================================================
52 cdl_package CYGPKG_HAL_FR30_MB91301 {
53 display "MB91301 variant"
54 parent CYGPKG_HAL_FR30
55 implements CYGINT_HAL_FR30_VARIANT
58 define_header hal_fr30_mb91301.h
60 The MB91301 architecture HAL package provides generic support
61 for this processor architecture. It is also necessary to
62 select a specific target platform HAL package."
66 puts $::cdl_header "#include <pkgconf/hal_fr30.h>"
69 cdl_component CYGHWR_HAL_FR30_MB91301_SYSTEM_CLOCK_MHZ {
70 display "System clock speed in MHz"
72 calculated { (CYGHWR_HAL_FR30_MB91301_CRYSTAL_SPEED * \
73 CYGHWR_HAL_FR30_MB91301_CLKR) }
74 description "This is the resulting base clock speed for the board.
77 This is NOT the CPU Frequency."
79 cdl_option CYGHWR_HAL_FR30_MB91301_CRYSTAL_SPEED {
80 display "Crystal speed in Mhz"
82 description "You have to enter the speed of the mounted crystal here.
83 The resulting base clock is calculated:
84 CLKR * CRYSTAL_SPEED / CLKB_DIVIDER"
89 cdl_option CYGHWR_HAL_FR30_MB91301_CLKR {
90 display "Main PLL multiply-by rate"
92 description "Using this value you can set the resulting base clock
93 speed. It is calculated:
95 DO NOT DO A SETTING HIGHER THAN 4 UNLESS YOU EXACTLY
96 KNOW WHAT YOU A DOING! "
101 cdl_option CYGHWR_HAL_FR30_MB91301_CLKB_DIVIDER {
102 display "Base clock divider"
104 description "Using this value you can limit the base clock speed.
105 You set the divider. The resulting base clock speed
107 CLKB = system clock / divider
108 CPU, internal memory and internal buses use this base clock!
109 A value other than 1 can cause problems when using the stop
111 See Fujitsu MB91301 hardware manual Chapter 5 for
112 constraints on setting this value!"
117 cdl_option CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER {
118 display "Peripheral clock divider"
120 description "Using this value you can set the peripheral clock
121 speed. You set the divider. The resulting peripheral clock
123 CLKP = system clock / divider
124 See Fujitsu MB91301 hardware manual Chapter 5 for constraints on setting
130 cdl_option CYGHWR_HAL_FR30_MB91301_CLKT_DIVIDER {
131 display "External buses clock divider"
133 description "Using this value you can set the external buses clock
134 speed. You set the divider. The resulting external buses
135 clock speed is calculated:
136 CLKT = system clock / divider
137 See Fujitsu MB91301 hardware manual Chapter 5 for constraints on setting
146 # Real-time clock/counter specifics
147 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
148 display "Real-time clock constants."
151 cdl_option CYGNUM_HAL_RTC_NUMERATOR {
152 display "Real-time clock numerator"
154 default_value 1000000000
156 cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
157 display "Real-time clock denominator"
161 cdl_option CYGNUM_HAL_RTC_PERIOD {
162 display "Real-time clock period"
164 default_value {(CYGHWR_HAL_FR30_MB91301_CRYSTAL_SPEED * CYGHWR_HAL_FR30_MB91301_CLKR * 1000000) / (CYGHWR_HAL_FR30_MB91301_CLKP_DIVIDER * CYGNUM_HAL_RTC_DENOMINATOR * 32)}
166 The tick timer facility is used
167 to drive the eCos kernel RTC. Reload Timer 1 is used. The count
168 register decrements at the CLKP clock speed. We use prescaler 32.
169 By default we want 100 Hz."
174 compile hal_diag.c var_misc.c variant.S
177 <PREFIX>/lib/target.ld: <PACKAGE>/src/fr30_mb91301.ld
178 $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
179 @echo $@ ": \\" > $(notdir $@).deps
180 @tail -n +2 target.tmp >> $(notdir $@).deps
181 @echo >> $(notdir $@).deps
185 cdl_option CYGBLD_LINKER_SCRIPT {
186 display "Linker script"
189 calculated { "src/fr30_mb91301.ld" }