packages/hal/fr30/mb91301/v2_0/include/var_intr.h

   1 #ifndef CYGONCE_HAL_IMP_INTR_H
   2 #define CYGONCE_HAL_IMP_INTR_H
   3
   4 //==========================================================================
   5 //
   6 //      var_intr.h
   7 //
   8 //      MB91301 Interrupt and clock support
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    larsi
  47 // Contributors: larsi
  48 // Date:         2006-07-14
  49 // Purpose:      MB91301 Interrupt support
  50 // Description:  The macros defined here provide the HAL APIs for handling
  51 //               interrupts and the clock for variants of the MB91301
  52 //               architecture.
  53 //
  54 // Usage:
  55 //              #include <cyg/hal/imp_intr.h>
  56 //              ...
  57 //
  58 //
  59 //####DESCRIPTIONEND####
  60 //
  61 //==========================================================================
  62
  63 #include <pkgconf/hal.h>
  64
  65 #include <cyg/infra/cyg_type.h>
  66
  67 #include <cyg/hal/hal_io.h>
  68
  69 #include <cyg/hal/plf_intr.h>
  70
  71 //--------------------------------------------------------------------------
  72 // Interrupt vectors.
  73
  74 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
  75
  76 #define CYGNUM_HAL_INTERRUPT_0                     16
  77 #define CYGNUM_HAL_INTERRUPT_1                     17
  78 #define CYGNUM_HAL_INTERRUPT_2                     18
  79 #define CYGNUM_HAL_INTERRUPT_3                     19
  80 #define CYGNUM_HAL_INTERRUPT_4                     20
  81 #define CYGNUM_HAL_INTERRUPT_5                     21
  82 #define CYGNUM_HAL_INTERRUPT_6                     22
  83 #define CYGNUM_HAL_INTERRUPT_7                     23
  84 #define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER0         24
  85 #define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER1         25
  86 #define CYGNUM_HAL_INTERRUPT_RELOAD_TIMER2         26
  87 #define CYGNUM_HAL_INTERRUPT_UART0_RX              27
  88 #define CYGNUM_HAL_INTERRUPT_UART1_RX              28
  89 #define CYGNUM_HAL_INTERRUPT_UART2_RX              29
  90 #define CYGNUM_HAL_INTERRUPT_UART0_TX              30
  91 #define CYGNUM_HAL_INTERRUPT_UART1_TX              31
  92 #define CYGNUM_HAL_INTERRUPT_UART2_TX              32
  93 #define CYGNUM_HAL_INTERRUPT_DMAC0                 33
  94 #define CYGNUM_HAL_INTERRUPT_DMAC1                 34
  95 #define CYGNUM_HAL_INTERRUPT_DMAC2                 35
  96 #define CYGNUM_HAL_INTERRUPT_DMAC3                 36
  97 #define CYGNUM_HAL_INTERRUPT_DMAC4                 37
  98 #define CYGNUM_HAL_INTERRUPT_AD                    38
  99 #define CYGNUM_HAL_INTERRUPT_PPG0                  39
 100 #define CYGNUM_HAL_INTERRUPT_PPG1                  40
 101 #define CYGNUM_HAL_INTERRUPT_PPG2                  41
 102 #define CYGNUM_HAL_INTERRUPT_PPG3                  42
 103 // system reserved #define CYGNUM_HAL_INTERRUPT_                43
 104 #define CYGNUM_HAL_INTERRUPT_UTIMER0               44
 105 #define CYGNUM_HAL_INTERRUPT_UTIMER1               45
 106 #define CYGNUM_HAL_INTERRUPT_UTIMER2               46
 107 #define CYGNUM_HAL_INTERRUPT_TIMEBASE_OVERFLOW     47
 108 #define CYGNUM_HAL_INTERRUPT_I2C0                  48
 109 #define CYGNUM_HAL_INTERRUPT_I2C1                  49
 110 // system reserved #define CYGNUM_HAL_INTERRUPT_                 50
 111 // system reserved #define CYGNUM_HAL_INTERRUPT_                 51
 112 #define CYGNUM_HAL_INTERRUPT_FREERUN_TIMER         52
 113 #define CYGNUM_HAL_INTERRUPT_ICU0                  53
 114 #define CYGNUM_HAL_INTERRUPT_ICU1                  54
 115 #define CYGNUM_HAL_INTERRUPT_ICU2                  55
 116 #define CYGNUM_HAL_INTERRUPT_ICU3                  56
 117 // system reserved #define CYGNUM_HAL_INTERRUPT_             57
 118 // system reserved #define CYGNUM_HAL_INTERRUPT_             58
 119 // system reserved #define CYGNUM_HAL_INTERRUPT_             59
 120 // system reserved #define CYGNUM_HAL_INTERRUPT_             60
 121 // system reserved #define CYGNUM_HAL_INTERRUPT_             61
 122 // system reserved #define CYGNUM_HAL_INTERRUPT_             62
 123 #define CYGNUM_HAL_INTERRUPT_DELAYED_IRQ           63
 124
 125 // The interrupt vector used by the RTC, aka tick timer
 126 #define CYGNUM_HAL_INTERRUPT_RTC            CYGNUM_HAL_INTERRUPT_RELOAD_TIMER1
 127
 128 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
 129
 130 #endif
 131
 132 //--------------------------------------------------------------------------
 133 // Interrupt controller access.
 134
 135 // currently only external interrupts are masked using the external
 136 // interrupt controller. This means only vectors 16 to 23 are valid.
 137 // Other interrupts may be masked in the future
 138 // using the mask mechanism for interrupt levels, if needed.
 139
 140 #ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 141
 142 #define CYG_HAL_FR30_MB91301_ENIR     0x41
 143 #define CYG_HAL_FR30_MB91301_EIRR     0x40
 144 #define CYG_HAL_FR30_MB91301_ELVR     0x42
 145 #define CYG_HAL_FR30_MB91301_ICR00    0x440
 146
 147 // Array which stores the configured priority levels for the configured
 148 // interrupts.
 149 // this will be useful, if we implement masking of non external interrupts
 150 // externC volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
 151
 152
 153 #define HAL_INTERRUPT_MASK( _vector_ )                       \
 154 {                                                            \
 155     CYG_WORD32 _ilr_;                                        \
 156     if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) &&              \
 157           (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){             \
 158         HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ );  \
 159         _ilr_ &= ~(1<<((_vector_)>>4));                      \
 160         HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \
 161     }                                                        \
 162     /* Handle RTC masking special */                         \
 163     if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC)                \
 164         asm volatile("ldi:8     #0x57,  r0;\n"               \
 165                      "bandl     #0x7,   @r0;\n"              \
 166                       : : :"r0");                            \
 167 }
 168
 169 #define HAL_INTERRUPT_UNMASK( _vector_ )                     \
 170 {                                                            \
 171     CYG_WORD32 _ilr_;                                        \
 172     if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) &&              \
 173           (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){             \
 174         HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ );  \
 175         _ilr_ |= (1<<((_vector_)>>4));                       \
 176         HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ENIR, _ilr_ ); \
 177     }                                                        \
 178     /* Handle RTC unmasking special */                       \
 179     if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC)                \
 180         asm volatile("ldi:8     #0x57,  r0;\n"               \
 181                      "borl      #0x8,   @r0;\n"              \
 182                       : : :"r0");                            \
 183 }
 184
 185 #define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )                \
 186 {                                                            \
 187     CYG_WORD32 _ilr_;                                        \
 188     if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) &&              \
 189           (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){             \
 190         HAL_READ_UINT8( CYG_HAL_FR30_MB91301_EIRR, _ilr_ );  \
 191         _ilr_ &= ~(1<<((_vector_)>>4));                      \
 192         HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_EIRR, _ilr_ ); \
 193     }                                                        \
 194     /* Handle RTC acknowledging special */                   \
 195     if (_vector_ == CYGNUM_HAL_INTERRUPT_RTC)                \
 196         asm volatile("ldi:8     #0x57,  r0;\n"               \
 197                      "bandl     #0xb,   @r0;\n"              \
 198                       : : :"r0");                            \
 199 }
 200
 201 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )              \
 202 {                                                                       \
 203         /* subtract 15 from vector */                                   \
 204         cyg_uint32 _v_ = _vector_ >> 4;                                 \
 205         cyg_uint16 _val_ = 0;                                           \
 206         cyg_uint16 _reg_;                                               \
 207                                                                         \
 208             if ((_vector_ >= CYGNUM_HAL_INTERRUPT_7) &&                 \
 209                 (_vector_ <= CYGNUM_HAL_INTERRUPT_0)){                  \
 210                                                                         \
 211         /* set bits according to requirements */                        \
 212         if( _up_ ) _val_ |= 1;                                          \
 213         if( !(_level_) ) _val_ |= 2;                                    \
 214                                                                         \
 215         /* get old ELVR */                                              \
 216         HAL_READ_UINT16( CYG_HAL_FR30_MB91301_ELVR, _reg_ );            \
 217                                                                         \
 218         /* clear old value and set new */                               \
 219         _reg_ &= ~(3 << _v_);                                           \
 220         _reg_ |= _val_ << _v_;                                          \
 221         HAL_WRITE_UINT16( CYG_HAL_FR30_MB91301_ELVR, _reg_ );           \
 222     }                                                                   \
 223 }
 224
 225 #define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )                    \
 226 {                                                                       \
 227     /* subtract 15 from vector */                                       \
 228     cyg_uint32 _v_ = _vector_ >> 4;                                     \
 229     CYG_WORD32 _ilr_;                                                   \
 230 /*    HAL_READ_UINT8( CYG_HAL_FR30_MB91301_ICR00 + _vector_, _ilr_ );*/ \
 231 /* reading before writing is only needed, if UINT8 writing is not */    \
 232 /* possible to IO 0x440   */                                              \
 233     _ilr_ = (_level_);                                                  \
 234     HAL_WRITE_UINT8( CYG_HAL_FR30_MB91301_ICR00 + _vector_, _ilr_ );    \
 235 /*  for later use:  */                                                    \
 236 /*    hal_interrupt_level[_vector_] = _level_;      */                    \
 237 }
 238
 239 #define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 240
 241 #endif
 242
 243 //--------------------------------------------------------------------------
 244 // Clock control registers
 245
 246 // MB91301 series has 3 built-in timer channels.
 247 // Timer 2 is used for delay and timer 1 for RTC/*delay*/.
 248 // Timer 0 and 1 can activate DMA and this feature is propably needed by
 249 // the application. Timer 0 is free to use by the application.
 250
 251 #define CYG_HAL_FR30_DLY_TMCSR          0x5e
 252 #define CYG_HAL_FR30_DLY_TMR            0x5a
 253 #define CYG_HAL_FR30_DLY_TMRLR          0x58
 254 #define CYG_HAL_FR30_RTC_TMCSR          0x56
 255 #define CYG_HAL_FR30_RTC_TMR            0x52
 256 #define CYG_HAL_FR30_RTC_TMRLR          0x50
 257
 258
 259
 260 //--------------------------------------------------------------------------
 261 // Control-C support.
 262
 263 #if defined(CYGDBG_HAL_FR30_DEBUG_GDB_CTRLC_SUPPORT)
 264
 265 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_DUART
 266
 267 externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 268
 269 #define HAL_CTRLC_ISR hal_ctrlc_isr
 270
 271 #endif
 272
 273 //--------------------------------------------------------------------------
 274 #endif // ifndef CYGONCE_HAL_IMP_INTR_H
 275 // End of imp_intr.h