1 #ifndef CYGONCE_HAL_PLATFORM_INC
2 #define CYGONCE_HAL_PLATFORM_INC
3 ##=============================================================================
7 ## Fujitsu Starterkit MB91302 board assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
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43 ##=============================================================================
44 #######DESCRIPTIONBEGIN####
49 ## Purpose: Fujitsu Starterkit MB91302 board definitions.
50 ## Description: This file contains various definitions and macros that are
51 ## useful for writing assembly code for the skmb91302 board.
53 ## #include <cyg/hal/platform.inc>
57 ######DESCRIPTIONEND####
59 ##=============================================================================
61 #include <cyg/hal/fr30.inc>
64 ##------------------------------------------------------------------------------
65 ## ext Bus (memory controller) initialisation macros
70 #define CYGPKG_HAL_FR30_FLASH_INIT_DEFINED
71 ## flash init is empty for this platform because it is initialized in the
72 ## special hal_fr30_ram_startup_trampoline to map flash to 0x1000000
76 ## and the following macro is used in the special
77 ## hal_fr30_ram_startup_trampoline for flash initialisation
78 .macro hal_flash_init_from_ram
80 ldi:20 #FR30_MB91301_ASR0, r10 ; CS0 area starts at
81 ldi:20 0x100, r0 ; 0x01000000
84 ldi:20 #FR30_MB91301_ACR0, r11 ; configuration parameters for CS0
85 ldi:20 #0x7422, r1 ; 8MB(0x0-0x7FFFFF),16bit data bus,
86 sth r1, @r11 ; pre-fetch off, single access,
87 ; write enable, big endian,
88 ; normal access(asynchronous),
89 ; WR pin enabled for write,
90 ; wait by RDY pin disabled
92 ldi:20 #FR30_MB91301_AWR0, r12 ; first access auto-wait 3cyc
93 ldi:20 #0x3378, r2 ; inpage access auto-wait 3cyc
94 sth r2, @r12 ; read/write idle 1cyc
96 ; async write strobe outp enabled
98 ; CS read/write setup delay 0
99 ; RD/WR -> CS hold extension 0 cyc
101 ldi:20 #FR30_MB91301_PFR9, r13 ; WRn, BAAE, ASXE enable
105 ## following would chip select enable
106 ## we only use cs0 until here, which is already set by reset
114 #define CYGPKG_HAL_FR30_MEMC_INIT_DEFINED
118 ## The following instruction is without function. It is only to reference
119 ## hal_fr30_rom_startup_trampoline, because when not referenced the linker
120 ## does not include the file platform.S in the link. If somewhen some other
121 ## referenced code appears in platform.S the instruction here can be deleted
122 ## (including the surrounding macro)!
124 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
125 ldi:32 #hal_fr30_rom_startup_trampoline, r10
128 ldi:20 #FR30_MB91301_ASR6, r10 ; CS6 area starts at
129 ldi:20 0x200, r0 ; 0x02000000
132 ldi:20 #FR30_MB91301_ACR6, r11 ; configuration parameters for CS6
133 ldi:20 #0x7868, r1 ; 64MB(0x2000000-0x27FFFFF),32bit data bus,
134 sth r1, @r11 ; pre-fetch on, single access(no burst),
135 ; write enable, big endian,
138 ldi:20 #FR30_MB91301_AWR6, r12 ; first access auto-wait 1cyc ??
139 ldi:20 #0x1159, r2 ; inpage access auto-wait 1cyc ??
140 sth r2, @r12 ; read/write idle 1cyc ??
141 ; write recover 1cyc ??
142 ; async write strobe outp enabled ??
143 ; CS delay disabled ??
144 ; CS read/write setup delay 0 ??
145 ; RD/WR -> CS hold extension 1 cyc ??
146 ; see Hardware Manual page 156ff
148 ldi:20 #FR30_MB91301_MCRA, r13 ; 8 columns, single write,
149 ldi:8 #0x07, r3 ; 4 banks for burst write,
150 stb r3, @r13 ; 4 active banks
152 ldi:20 #FR30_MB91301_PFR9, r10 ; enable WRn, BAAE, ASXE,
153 ldi:8 #0x7e, r0 ; sysclk, MCKE, MCKEE
156 ldi:20 #FR30_MB91301_PFR8, r11 ; enable WR3XE, WR2XE, WR1XE
160 ldi:20 #FR30_MB91301_CSER, r12 ; switch on CS6 & CS0
164 ldi:20 #FR30_MB91301_RCR, r13 ; power on SDRAM I/F
165 ldi:20 #0xe247, r3 ; 0xe247 -> 0xe24f
172 #------------------------------------------------------------------------------
173 ## Vector table for storage. platform.S defines a vector table and wants to
174 ## override the one from variant.S with this define
176 #define CYGPKG_HAL_FR30_ROM_VECTORS_DEFINED
178 #------------------------------------------------------------------------------
179 # Difference of the flash memory from the linkers LMA (loadmemoryaddress) after
180 # the new mapping in (mapping is done in hal_fr30_ram_startup_trampoline).
182 #define CYGPKG_HAL_FR30_LMA_OFFSET 0x1000000
186 #------------------------------------------------------------------------------
187 #endif // ifndef CYGONCE_HAL_PLATFORM_INC
188 # end of platform.inc