packages/hal/mips/idt32334/v2_0/include/var_cache.h

   1 #ifndef CYGONCE_VAR_CACHE_H
   2 #define CYGONCE_VAR_CACHE_H
   3 //=============================================================================
   4 //
   5 //      var_cache.h
   6 //
   7 //      HAL cache control API
   8 //
   9 //=============================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 //
  15 // eCos is free software; you can redistribute it and/or modify it under
  16 // the terms of the GNU General Public License as published by the Free
  17 // Software Foundation; either version 2 or (at your option) any later version.
  18 //
  19 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  21 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  22 // for more details.
  23 //
  24 // You should have received a copy of the GNU General Public License along
  25 // with eCos; if not, write to the Free Software Foundation, Inc.,
  26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  27 //
  28 // As a special exception, if other files instantiate templates or use macros
  29 // or inline functions from this file, or you compile this file and link it
  30 // with other works to produce a work based on this file, this file does not
  31 // by itself cause the resulting work to be covered by the GNU General Public
  32 // License. However the source code for this file must still be made available
  33 // in accordance with section (3) of the GNU General Public License.
  34 //
  35 // This exception does not invalidate any other reasons why a work based on
  36 // this file might be covered by the GNU General Public License.
  37 //
  38 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  39 // at http://sources.redhat.com/ecos/ecos-license/
  40 // -------------------------------------------
  41 //####ECOSGPLCOPYRIGHTEND####
  42 //=============================================================================
  43 //#####DESCRIPTIONBEGIN####
  44 //
  45 // Author(s):    tmichals
  46 // Contributors: nickg, dmoseley
  47 // Date:         2003-02-13
  48 // Purpose:      Cache control API
  49 // Description:  The macros defined here provide the HAL APIs for handling
  50 //               cache control operations.
  51 // Usage:
  52 //               #include <cyg/hal/var_cache.h>
  53 //               ...
  54 //
  55 //
  56 //####DESCRIPTIONEND####
  57 //
  58 //=============================================================================
  59
  60 #include <pkgconf/hal.h>
  61 #include <cyg/infra/cyg_type.h>
  62
  63 #include <cyg/hal/mips-regs.h>
  64 #include <cyg/hal/hal_arch.h>
  65 #include <cyg/hal/plf_cache.h>
  66 #include <cyg/hal/var_arch.h>
  67
  68
  69
  70 //-----------------------------------------------------------------------------
  71 // Cache dimensions
  72
  73 // Data cache
  74 #define HAL_DCACHE_SIZE                 (1024 *8)   // Size of data cache in bytes
  75 #define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
  76 #define HAL_DCACHE_WAYS                 4       // Associativity of the cache
  77
  78 // Instruction cache
  79 #define HAL_ICACHE_SIZE                 (1024*16)   // Size of cache in bytes
  80 #define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
  81 #define HAL_ICACHE_WAYS                 4       // Associativity of the cache
  82
  83 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  84 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  85
  86 #define HAL_DCACHE_WRITETHRU_MODE       1
  87 #define HAL_DCACHE_WRITEBACK_MODE       0
  88
  89
  90 //-----------------------------------------------------------------------------
  91 // General cache defines.
  92 #define HAL_CLEAR_TAGLO()  asm volatile (" mtc0 $0, $28;" \
  93                                              " nop;"      \
  94                                              " nop;"      \
  95                                              " nop;")
  96 #define HAL_CLEAR_TAGHI()  asm volatile (" mtc0 $0, $29;" \
  97                                              " nop;"      \
  98                                              " nop;"      \
  99                                              " nop;")
 100
 101 /* Cache instruction opcodes */
 102 #define HAL_CACHE_OP(which, op)             (which | (op << 2))
 103
 104 #define HAL_WHICH_ICACHE                    0x0
 105 #define HAL_WHICH_DCACHE                    0x1
 106
 107 #define HAL_INDEX_INVALIDATE                0x0
 108 #define HAL_INDEX_LOAD_TAG                  0x1
 109 #define HAL_INDEX_STORE_TAG                 0x2
 110 #define HAL_HIT_INVALIDATE                  0x4
 111 #define HAL_ICACHE_FILL                     0x5
 112 #define HAL_DCACHE_HIT_INVALIDATE           0x5
 113 #define HAL_DCACHE_HIT_WRITEBACK            0x6
 114 #define HAL_FETCH_AND_LOCK                  0x7
 115
 116 //-----------------------------------------------------------------------------
 117 // Global control of data cache
 118
 119 // Invalidate the entire cache
 120 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
 121 #define HAL_DCACHE_INVALIDATE_ALL()                                                     \
 122     CYG_MACRO_START                                                                     \
 123     register volatile CYG_BYTE *addr;                                                   \
 124     HAL_CLEAR_TAGLO();                                                                  \
 125     HAL_CLEAR_TAGHI();                                                                  \
 126     for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE;                                    \
 127          addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_DCACHE_SIZE);                \
 128          addr += HAL_DCACHE_LINE_SIZE )                                                 \
 129     {                                                                                  \
 130         asm volatile (" cache %0, 0(%1)"                                                \
 131                       :                                                                 \
 132                       : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_INDEX_STORE_TAG)),      \
 133                         "r"(addr));                                                     \
 134     }                                                                                   \
 135     CYG_MACRO_END
 136
 137 // Synchronize the contents of the cache with memory.
 138 __externC void hal_dcache_sync(void);
 139 #define HAL_DCACHE_SYNC_DEFINED
 140 #define HAL_DCACHE_SYNC() hal_dcache_sync()
 141
 142 // Set the data cache refill burst size
 143 //#define HAL_DCACHE_BURST_SIZE(_asize_)
 144
 145 // Set the data cache write mode
 146 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 147
 148 // Load the contents of the given address range into the data cache
 149 // and then lock the cache so that it stays there.
 150 #define HAL_DCACHE_LOCK_DEFINED
 151 #define HAL_DCACHE_LOCK(_base_, _asize_)                                                \
 152     CYG_MACRO_START                                                                     \
 153     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 154     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 155     register CYG_WORD _size_ = (_asize_);                                               \
 156     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
 157       asm volatile (" cache %0, 0(%1)"                                                  \
 158                     :                                                                   \
 159                     : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)),         \
 160                       "r"(_addr_));                                                     \
 161     CYG_MACRO_END
 162
 163 // Undo a previous lock operation
 164 #define HAL_DCACHE_UNLOCK_DEFINED
 165 #define HAL_DCACHE_UNLOCK(_base_, _asize_)                                              \
 166     CYG_MACRO_START                                                                     \
 167     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 168     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 169     register CYG_WORD _size_ = (_asize_);                                               \
 170     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
 171       asm volatile (" cache %0, 0(%1)"                                                  \
 172                     :                                                                   \
 173                     : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)),         \
 174                       "r"(_addr_));                                                     \
 175     CYG_MACRO_END
 176
 177 // Unlock entire cache
 178 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
 179 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
 180
 181
 182 //-----------------------------------------------------------------------------
 183 // Data cache line control
 184
 185 // Allocate cache lines for the given address range without reading its
 186 // contents from memory.
 187 //#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ )
 188
 189 // Write dirty cache lines to memory and invalidate the cache entries
 190 // for the given address range.
 191 #define HAL_DCACHE_FLUSH_DEFINED
 192 #if HAL_DCACHE_WRITETHRU_MODE == 1
 193 // No need to flush a writethrough cache
 194 #define HAL_DCACHE_FLUSH( _base_ , _asize_ )
 195 #else
 196 #error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache
 197 #endif
 198
 199 // Write dirty cache lines to memory for the given address range.
 200 #define HAL_DCACHE_STORE_DEFINED
 201 #if HAL_DCACHE_WRITETHRU_MODE == 1
 202 // No need to store a writethrough cache
 203 #define HAL_DCACHE_STORE( _base_ , _asize_ )
 204 #else
 205 #error HAL_DCACHE_STORE undefined for MIPS32 writeback cache
 206 #endif
 207
 208 // Invalidate cache lines in the given range without writing to memory.
 209 #define HAL_DCACHE_INVALIDATE_DEFINED
 210 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ )                                       \
 211     CYG_MACRO_START                                                                     \
 212     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 213     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 214     register CYG_WORD _size_ = (_asize_);                                               \
 215     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
 216       asm volatile (" cache %0, 0(%1)"                                                  \
 217                     :                                                                   \
 218                     : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)),         \
 219                       "r"(_addr_));                                                       \
 220     CYG_MACRO_END
 221
 222
 223
 224
 225
 226
 227 //-----------------------------------------------------------------------------
 228 // Global control of Instruction cache
 229
 230 // Invalidate the entire cache
 231 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
 232 #define HAL_ICACHE_INVALIDATE_ALL()                                                     \
 233     CYG_MACRO_START                                                                     \
 234     register volatile CYG_BYTE *addr;                                                   \
 235     HAL_CLEAR_TAGLO();                                                                  \
 236     HAL_CLEAR_TAGHI();                                                                  \
 237     for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE;                                    \
 238          addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE);                \
 239          addr += HAL_ICACHE_LINE_SIZE )                                                 \
 240     {                                                                                   \
 241         asm volatile (" cache %0, 0(%1)"                                                \
 242                       :                                                                 \
 243                       : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)),      \
 244                         "r"(addr));                                                     \
 245     }                                                                                   \
 246     CYG_MACRO_END
 247
 248 // Synchronize the contents of the cache with memory.
 249 //extern void hal_icache_sync(void);
 250 //#define HAL_ICACHE_SYNC_DEFINED
 251 //#define HAL_ICACHE_SYNC() hal_icache_sync()
 252
 253 // Set the instruction cache refill burst size
 254 //#define HAL_ICACHE_BURST_SIZE(_asize_)
 255
 256 // Load the contents of the given address range into the data cache
 257 // and then lock the cache so that it stays there.
 258 #define HAL_ICACHE_LOCK_DEFINED
 259 #define HAL_ICACHE_LOCK(_base_, _asize_)                                                \
 260     CYG_MACRO_START                                                                     \
 261     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 262     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 263     register CYG_WORD _size_ = (_asize_);                                               \
 264     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
 265       asm volatile (" cache %0, 0(%1)"                                                  \
 266                     :                                                                   \
 267                     : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)),         \
 268                       "r"(_addr_));                                                     \
 269     CYG_MACRO_END
 270
 271 // Undo a previous lock operation
 272 #define HAL_ICACHE_UNLOCK_DEFINED
 273 #define HAL_ICACHE_UNLOCK(_base_, _asize_)                                              \
 274     CYG_MACRO_START                                                                     \
 275     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 276     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 277     register CYG_WORD _size_ = (_asize_);                                               \
 278     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
 279       asm volatile (" cache %0, 0(%1)"                                                  \
 280                     :                                                                   \
 281                     : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)),         \
 282                       "r"(_addr_));                                                     \
 283     CYG_MACRO_END
 284
 285 // Unlock entire cache
 286 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
 287 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE)
 288
 289 //-----------------------------------------------------------------------------
 290 // Instruction cache line control
 291
 292 // Invalidate cache lines in the given range without writing to memory.
 293 #define HAL_ICACHE_INVALIDATE_DEFINED
 294 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ )                                       \
 295     CYG_MACRO_START                                                                     \
 296     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 297     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 298     register CYG_WORD _size_ = (_asize_);                                               \
 299     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
 300       asm volatile (" cache %0, 0(%1)"                                                  \
 301                     :                                                                   \
 302                     : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)),         \
 303                       "r"(_addr_));                                                     \
 304     CYG_MACRO_END
 305
 306 //-----------------------------------------------------------------------------
 307 #endif // ifndef CYGONCE_VAR_CACHE_H
 308 // End of var_cache.h