1 #ifndef CYGONCE_HAL_VARIANT_INC
2 #define CYGONCE_HAL_VARIANT_INC
3 ##=============================================================================
7 ## MIPS 32 family assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
11 ## -------------------------------------------
12 ## This file is part of eCos, the Embedded Configurable Operating System.
13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 ## eCos is free software; you can redistribute it and/or modify it under
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20 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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26 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 ## As a special exception, if other files instantiate templates or use macros
29 ## or inline functions from this file, or you compile this file and link it
30 ## with other works to produce a work based on this file, this file does not
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32 ## License. However the source code for this file must still be made available
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39 ## at http://sources.redhat.com/ecos/ecos-license/
40 ## -------------------------------------------
41 #####ECOSGPLCOPYRIGHTEND####
42 ##=============================================================================
43 #######DESCRIPTIONBEGIN####
45 ## Author(s): dmoseley
46 ## Contributors: dmoseley
48 ## Purpose: MIPS64 family definitions.
49 ## Description: This file contains various definitions and macros that are
50 ## useful for writing assembly code for the MIPS64 CPU family.
52 ## #include <cyg/hal/variant.inc>
56 ######DESCRIPTIONEND####
58 ##=============================================================================
60 #include <pkgconf/hal.h>
62 #include <cyg/hal/mips.inc>
64 #include <cyg/hal/platform.inc>
66 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
67 #include <cyg/hal/mips-regs.h>
68 #include <cyg/hal/var_arch.h>
70 ##-----------------------------------------------------------------------------
71 ## Define CPU variant for architecture HAL.
73 #define CYG_HAL_MIPS_MIPS64
75 # Set the KX bit to use 64 bit addressing in kernel mode.
77 #define INITIAL_SR_VAR 0x00000080
79 #------------------------------------------------------------------------------
82 #ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED
86 # Setup a temporary stack pointer for running C code.
87 la a0,__interrupt_stack
89 CYGARC_ADDRESS_REG_UNCACHED(sp)
91 # Read the CONFIG1 register into a0
97 # Jump to C-code to initialize caches (uncached)
98 lar k0, hal_c_cache_init
99 CYGARC_ADDRESS_REG_UNCACHED(k0)
104 #define CYGPKG_HAL_MIPS_CACHE_DEFINED
108 #------------------------------------------------------------------------------
109 # Monitor initialization.
111 #ifndef CYGPKG_HAL_MIPS_MON_DEFINED
113 #if defined(CYG_HAL_STARTUP_ROM) || \
114 ( defined(CYG_HAL_STARTUP_RAM) && \
115 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
116 # If we are starting up from ROM, or we are starting in
117 # RAM and NOT using a ROM monitor, initialize the VSR table.
120 la a0,__default_interrupt_vsr
121 la a1,__default_exception_vsr
145 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
147 # Initialize the VSR table entries
148 # We only take control of the interrupt vector,
149 # the rest are left to the ROM for now...
152 la a0,__default_interrupt_vsr
165 #define CYGPKG_HAL_MIPS_MON_DEFINED
169 #------------------------------------------------------------------------------
170 # Decide whether the VSR table is defined externally, or is to be defined
173 #if defined(CYGPKG_HAL_MIPS_SIM) || \
174 ( defined(CYGPKG_HAL_MIPS_ATLAS) && \
175 defined(CYG_HAL_STARTUP_RAM) && \
176 !defined(CYGSEM_HAL_USE_ROM_MONITOR) \
179 ## VSR table defined in linker script
183 #define CYG_HAL_MIPS_VSR_TABLE_DEFINED
187 #------------------------------------------------------------------------------
188 #endif // ifndef CYGONCE_HAL_VARIANT_INC