#include <pkgconf/devs_flash_onmxc.h>
#include "mxc_nand_specifics.h"
-#define NFC_DEBUG_NONE 0
-#define NFC_DEBUG_MIN 1
-#define NFC_DEBUG_MED 2
-#define NFC_DEBUG_MAX 3
-#define NFC_DEBUG_DEF NFC_DEBUG_NONE
-#define PG_2K_DATA_OP_MULTI_CYCLES() true
-
-typedef unsigned short u16;
-typedef unsigned int u32;
-typedef unsigned char u8;
+#if defined(NFC_V1_1)
+#define PG_2K_DATA_OP_MULTI_CYCLES() false
+#else
+#define PG_2K_DATA_OP_MULTI_CYCLES() true
+#endif
-#define ADDR_INPUT_SIZE 8
-//----------------------------------------------------------------------------
-// Common device details.
-#define FLASH_Read_ID (0x90)
-#if CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
-#define FLASH_Reset 0xFFFF
+#define ADDR_INPUT_SIZE 8
+#define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
+#define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
+#define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
+#define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
+#if defined(NFC_V1_1)
+#define NAND_MAIN_BUF4 (NFC_BASE + 0x800)
+#define NAND_MAIN_BUF5 (NFC_BASE + 0xA00)
+#define NAND_MAIN_BUF6 (NFC_BASE + 0xC00)
+#define NAND_MAIN_BUF7 (NFC_BASE + 0xE00)
+#define NAND_SPAR_BUF0 (NFC_BASE + 0x1000)
+#define NAND_SPAR_BUF1 (NFC_BASE + 0x1040)
+#define NAND_SPAR_BUF2 (NFC_BASE + 0x1080)
+#define NAND_SPAR_BUF3 (NFC_BASE + 0x10C0)
+#define NAND_SPAR_BUF4 (NFC_BASE + 0x1100)
+#define NAND_SPAR_BUF5 (NFC_BASE + 0x1140)
+#define NAND_SPAR_BUF6 (NFC_BASE + 0x1180)
+#define NAND_SPAR_BUF7 (NFC_BASE + 0x11C0)
+#define NFC_BUF_COUNT 8
+#define NFC_SPARE_BUF_SZ 64
#else
-#define FLASH_Reset (0xFF)
+#define NAND_SPAR_BUF0 (NFC_BASE + 0x800)
+#define NAND_SPAR_BUF1 (NFC_BASE + 0x810)
+#define NAND_SPAR_BUF2 (NFC_BASE + 0x820)
+#define NAND_SPAR_BUF3 (NFC_BASE + 0x830)
+#define NAND_RESERVED (NFC_BASE + 0x840)
+#define NFC_BUF_COUNT 4
+#define NFC_SPARE_BUF_SZ 16
#endif
-#define FLASH_Read_Mode1 (0x00)
-#define FLASH_Read_Mode1_2K (0x30)
-#define FLASH_Read_Mode2 (0x01)
-#define FLASH_Read_Mode3 (0x50)
-#define FLASH_Program (0x10)
-#define FLASH_Send_Data (0x80)
-#define FLASH_Status (0x70)
-#define FLASH_Block_Erase (0x60)
-#define FLASH_Start_Erase (0xD0)
-#define NAND_MAIN_BUF0 (NFC_BASE + 0x000)
-#define NAND_MAIN_BUF1 (NFC_BASE + 0x200)
-#define NAND_MAIN_BUF2 (NFC_BASE + 0x400)
-#define NAND_MAIN_BUF3 (NFC_BASE + 0x600)
-#define NAND_SPAR_BUF0 (NFC_BASE + 0x800)
-#define NAND_SPAR_BUF1 (NFC_BASE + 0x810)
-#define NAND_SPAR_BUF2 (NFC_BASE + 0x820)
-#define NAND_SPAR_BUF3 (NFC_BASE + 0x830)
-#define NAND_RESERVED (NFC_BASE + 0x840)
+#define NFC_BUFSIZE_REG (NAND_REG_BASE + 0x00)
+#define RAM_BUFFER_ADDRESS_REG (NAND_REG_BASE + 0x04)
+#define NAND_FLASH_ADD_REG (NAND_REG_BASE + 0x06)
+#define NAND_FLASH_CMD_REG (NAND_REG_BASE + 0x08)
+#define NFC_CONFIGURATION_REG (NAND_REG_BASE + 0x0A)
+#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x0C)
+#define ECC_RSLT_MAIN_AREA_REG (NAND_REG_BASE + 0x0E)
+#define ECC_RSLT_SPARE_AREA_REG (NAND_REG_BASE + 0x10)
+#define NF_WR_PROT_REG (NAND_REG_BASE + 0x12)
+#define NAND_FLASH_WR_PR_ST_REG (NAND_REG_BASE + 0x18)
+#define NAND_FLASH_CONFIG1_REG (NAND_REG_BASE + 0x1A)
+#define NAND_FLASH_CONFIG2_REG (NAND_REG_BASE + 0x1C)
+#if defined(NFC_V1_1)
+#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x20)
+#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x22)
+#define UNLOCK_START_BLK_ADD1_REG (NAND_REG_BASE + 0x24)
+#define UNLOCK_END_BLK_ADD1_REG (NAND_REG_BASE + 0x26)
+#define UNLOCK_START_BLK_ADD2_REG (NAND_REG_BASE + 0x28)
+#define UNLOCK_END_BLK_ADD2_REG (NAND_REG_BASE + 0x2A)
+#define UNLOCK_START_BLK_ADD3_REG (NAND_REG_BASE + 0x2C)
+#define UNLOCK_END_BLK_ADD3_REG (NAND_REG_BASE + 0x2E)
+#else
+#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x14)
+#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x16)
+#endif
-#define NFC_BUFSIZE_REG (NAND_REG_BASE + 0x00)
-#define RAM_BUFFER_ADDRESS_REG (NAND_REG_BASE + 0x04)
-#define NAND_FLASH_ADD_REG (NAND_REG_BASE + 0x06)
-#define NAND_FLASH_CMD_REG (NAND_REG_BASE + 0x08)
-#define NFC_CONFIGURATION_REG (NAND_REG_BASE + 0x0A)
-#define ECC_STATUS_RESULT_REG (NAND_REG_BASE + 0x0C)
-#define ECC_RSLT_MAIN_AREA_REG (NAND_REG_BASE + 0x0E)
-#define ECC_RSLT_SPARE_AREA_REG (NAND_REG_BASE + 0x10)
-#define NF_WR_PROT_REG (NAND_REG_BASE + 0x12)
-#define UNLOCK_START_BLK_ADD_REG (NAND_REG_BASE + 0x14)
-#define UNLOCK_END_BLK_ADD_REG (NAND_REG_BASE + 0x16)
-#define NAND_FLASH_WR_PR_ST_REG (NAND_REG_BASE + 0x18)
-#define NAND_FLASH_CONFIG1_REG (NAND_REG_BASE + 0x1A)
-#define NAND_FLASH_CONFIG2_REG (NAND_REG_BASE + 0x1C)
+#define NUM_OF_CS_LINES 1
+#define NFC_BUFSIZE 0
enum nfc_internal_buf {
RAM_BUF_0,
RAM_BUF_1,
RAM_BUF_2,
RAM_BUF_3,
+ RAM_BUF_4,
+ RAM_BUF_5,
+ RAM_BUF_6,
+ RAM_BUF_7,
};
enum nfc_output_mode {
FDO_FLASH_STATUS = 0x0020,
};
-/*!
- * Defined the "complete" address input operations which may involve
- * more than one cycle of single address input operation.
- */
-enum nfc_addr_ops {
- ADDRESS_INPUT_READ_ID,
- ADDRESS_INPUT_READ_PAGE,
- ADDRESS_INPUT_PROGRAM_PAGE,
- ADDRESS_INPUT_ERASE_BLOCK,
-};
-
-enum nfc_page_area {
- NFC_SPARE_ONLY,
- NFC_MAIN_ONLY,
-};
-
-enum {
- MXC_NAND_8_BIT = 8,
- MXC_NAND_16_BIT = 16,
-};
-
-enum {
- NAND_SLC = 0,
- NAND_MLC = 1,
-};
-
-// read column 464-465 byte but only 464 for bad block marker
-#define BAD_BLK_MARKER_464 (NAND_MAIN_BUF3 + 464)
-// read column 4-5 byte, but only 5 is used for swapped main area data
-#define BAD_BLK_MARKER_SP_5 (NAND_SPAR_BUF3 + 4)
+#define wait_for_auto_prog_done()
// Polls the NANDFC to wait for an operation to complete
-static inline void wait_op_done(void)
-{
- int mxc_nfc_wait_loop;
- while (!(readw(NAND_FLASH_CONFIG2_REG) & NAND_FLASH_CONFIG2_INT_DONE)) {
- for (mxc_nfc_wait_loop = 0; mxc_nfc_wait_loop < 100; mxc_nfc_wait_loop++);
- }
-}
-
-int nfc_read_region(u32 la, u32 maddr, int len);
-int nfc_program_region(u32 la, u32 maddr, int len);
-int nfc_erase_region(u32 la, int len);
-
+#define wait_op_done() CYG_MACRO_START \
+ volatile int mxc_nfc_wait_loop; \
+ while (!(readw(NAND_FLASH_CONFIG2_REG) & NAND_FLASH_CONFIG2_INT_DONE)) { \
+ for (mxc_nfc_wait_loop = 0; mxc_nfc_wait_loop < 100; mxc_nfc_wait_loop++); \
+ } \
+CYG_MACRO_END
/*!
* NAND flash data output operation (reading data from NAND flash)
* @param buf_no internal ram buffer number that will contain data
* to be outputted from the NAND flash after operation done
* @param mode one of the mode defined in enum nfc_output_mode
+ * @param ecc_en 1 - ecc enabled; 0 - ecc disabled
*/
static void NFC_DATA_OUTPUT(enum nfc_internal_buf buf_no, enum nfc_output_mode mode,
int ecc_en)
if (mode == FDO_SPARE_ONLY) {
config1 |= NAND_FLASH_CONFIG1_SP_EN;
-#ifdef CYGPKG_HAL_ARM_MXC91221
- config1 &= ~NAND_FLASH_CONFIG1_ECC_EN;
-#endif
}
writew(config1, NAND_FLASH_CONFIG1_REG);
flash_status = readw(NAND_MAIN_BUF0) & 0x00FF;
// restore
- writew(saved, NAND_MAIN_BUF0);
+ writew(saved, NAND_MAIN_BUF0);
return flash_status;
}
writew(NF_WR_PROT_UNLOCK, NF_WR_PROT_REG);
}
+static void NFC_SET_NFC_ACTIVE_CS(u32 cs_line)
+{
+ // not needed.
+}
+
/*!
* Issue the address input operation
* @param addr the address for the address input operation
wait_op_done();
}
+#if defined(NFC_V1_1)
+#define NFC_ARCH_INIT() CYG_MACRO_START \
+ unsigned int tmp, reg; \
+ tmp = flash_dev_info->page_size / 512; \
+ if (flash_dev_info->spare_size) { \
+ writew((flash_dev_info->spare_size >> 1), \
+ ECC_RSLT_SPARE_AREA_REG); \
+ } \
+ writew(0x2, NFC_CONFIGURATION_REG); \
+ reg = readw(NAND_FLASH_CONFIG1_REG) | 0x800; \
+ if ((flash_dev_info->spare_size / tmp) > 16) \
+ reg &= ~1; \
+ else \
+ reg |= 1; \
+ writew(reg, NAND_FLASH_CONFIG1_REG); \
+CYG_MACRO_END
+#else
+#define NFC_ARCH_INIT()
+#endif /*NFC_V1_1*/
+
+#define NAND_ADD0_REG 0xDEADDAED
+#define NAND_ADD8_REG 0xDEADDAED
+#define NAND_CMD_REG 0xDEADDAED
+#define NAND_LAUNCH_AUTO_PROG 0xDEADDAED
+#define NAND_STATUS_SUM_REG 0xDEADDAED
+#define NAND_LAUNCH_AUTO_READ 0xDEADDAED
+#define NAND_LAUNCH_AUTO_ERASE 0xDEADDAED
+
#endif // _MXC_NFC_H_
projects / karo-tx-redboot.git / blobdiff