TX51 pre-release

[karo-tx-redboot.git] / packages / devs / flash / arm / mxc / v2_0 / include / mxcmci_host.h

diff --git a/packages/devs/flash/arm/mxc/v2_0/include/mxcmci_host.h b/packages/devs/flash/arm/mxc/v2_0/include/mxcmci_host.h
index 2006048438477a5315aba9d87a992af01562c5c7..8e1d979bca12d1bb0bfb9b743e65ac38cc22866d 100644 (file)
--- a/packages/devs/flash/arm/mxc/v2_0/include/mxcmci_host.h
+++ b/packages/devs/flash/arm/mxc/v2_0/include/mxcmci_host.h
@@ -57,7 +57,7 @@
 #include <cyg/infra/cyg_type.h>
 
 
-#define ESDHC_SOFTWARE_RESET   0x01000000  /* RSTA bit of ESDHC system control register*/
+#define ESDHC_SOFTWARE_RESET   0x01000000  /* RSTA bit of ESDHC system control register*/
 #define ESDHC_CMD_INHIBIT       0x00000003  /* Command inhibit bits*/
 #define ESDHC_SOFTWARE_INIT     0x08000000  /* INITA bit of ESDHC system control register */
 #define ESDHC_LITTLE_ENDIAN_MODE 0x00000020  /* Little Endian mode */
@@ -66,13 +66,13 @@
 #define ESDHC_ONE_BIT_SUPPORT    0x00000000  /* 1 Bit Mode support */
 #define ESDHC_FOUR_BIT_SUPPORT   0x00000002  /* 4 Bit Mode support */
 #define ESDHC_EIGHT_BIT_SUPPORT  0x00000004  /* 8 Bit Mode support */
-#define ESDHC_CLOCK_ENABLE             0x00000007    /* Clock Enable */
+#define ESDHC_CLOCK_ENABLE             0x00000007    /* Clock Enable */
 #define ESDHC_ENABLE                        0x00000008    /* Enable SD */
 
 #define ESDHC_FREQ_MASK 0xffff0007
 #define ESDHC_IDENT_FREQ 0x0000800e  /* SDCLKFS 0x08 ; DVS 0xe */
 #define ESDHC_OPERT_FREQ 0x00000200  /* SDCLKFS 0x02 ; DVS 0x0 */
-#define ESDHC_INTERRUPT_ENABLE         0x007f0123        /* Enable Interrupts */
+#define ESDHC_INTERRUPT_ENABLE 0x007f0123        /* Enable Interrupts */
 #define ESDHC_CONFIG_BLOCK 0x00010200             /* 512 byte block size*/
 #define ESDHC_CLEAR_INTERRUPT 0xffffffff
 
@@ -108,7 +108,7 @@
 #define ONE 1
 #define ESDHC1 0
 /*==================================================================================================
-                                             ENUS
+                                             ENUMS
 ==================================================================================================*/
 #define ESDHC_STATUS_END_CMD_RESP_MSK 0x1
 #define ESDHC_STATUS_END_CMD_RESP_TIME_MSK 0x00010001
@@ -127,57 +127,57 @@
 
 typedef enum
 {
-    WRITE = 0,
-    READ = 1,
+       WRITE = 0,
+       READ = 1,
 }xfer_type_t;
 
 typedef enum
 {
-    RESPONSE_NONE,
-    RESPONSE_136,
-    RESPONSE_48,
-    RESPONSE_48_CHECK_BUSY
+       RESPONSE_NONE,
+       RESPONSE_136,
+       RESPONSE_48,
+       RESPONSE_48_CHECK_BUSY
 }response_format_t;
 
 
 typedef enum
 {
-       DATA_PRESENT_NONE = 0,
-       DATA_PRESENT = 1
+       DATA_PRESENT_NONE = 0,
+       DATA_PRESENT = 1
 }data_present_select;
 
 typedef enum
 {
-       DISABLE = 0,
-       ENABLE = 1
+       DISABLE = 0,
+       ENABLE = 1
 }crc_check_enable,cmdindex_check_enable,block_count_enable;
 
 typedef enum
 {
        SINGLE = 0,
-       MULTIPLE = 1
+       MULTIPLE = 1
 }multi_single_block_select;
 
 typedef struct
 {
-    cyg_uint32 command;
-    cyg_uint32 arg;
-    xfer_type_t data_transfer;
-    response_format_t response_format;
-    data_present_select data_present;
-    crc_check_enable crc_check;
-    cmdindex_check_enable cmdindex_check;
+       cyg_uint32 command;
+       cyg_uint32 arg;
+       xfer_type_t data_transfer;
+       response_format_t response_format;
+       data_present_select data_present;
+       crc_check_enable crc_check;
+       cmdindex_check_enable cmdindex_check;
        block_count_enable block_count_enable_check;
        multi_single_block_select multi_single_block;
 }command_t;
 
 typedef struct
 {
-    response_format_t format;
-    cyg_uint32 cmd_rsp0;
-    cyg_uint32 cmd_rsp1;
-    cyg_uint32 cmd_rsp2;
-    cyg_uint32 cmd_rsp3;
+       response_format_t format;
+       cyg_uint32 cmd_rsp0;
+       cyg_uint32 cmd_rsp1;
+       cyg_uint32 cmd_rsp2;
+       cyg_uint32 cmd_rsp3;
 }command_response_t;
 
 typedef enum
@@ -189,8 +189,8 @@ typedef enum
 
 typedef enum
 {
-    OPERATING_FREQ = 20000,   /* in kHz */
-    IDENTIFICATION_FREQ = 400   /* in kHz */
+       OPERATING_FREQ = 20000,   /* in kHz */
+       IDENTIFICATION_FREQ = 400   /* in kHz */
 }sdhc_freq_t;
 
 
@@ -214,30 +214,30 @@ enum esdhc_reset_status
 
 typedef struct
 {
-    volatile cyg_uint32 dma_system_address;
-    volatile cyg_uint32 block_attributes;
-    volatile cyg_uint32 command_argument;
-    volatile cyg_uint32 command_transfer_type;
-    volatile cyg_uint32 command_response0;
-    volatile cyg_uint32 command_response1;
-    volatile cyg_uint32 command_response2;
-    volatile cyg_uint32 command_response3;
-    volatile cyg_uint32 data_buffer_access;
-    volatile cyg_uint32 present_state;
-    volatile cyg_uint32 protocol_control;
-    volatile cyg_uint32 system_control;
-    volatile cyg_uint32 interrupt_status;
-    volatile cyg_uint32 interrupt_status_enable;
-    volatile cyg_uint32 interrupt_signal_enable;
-    volatile cyg_uint32 autocmd12_status;
-    volatile cyg_uint32 host_controller_capabilities;
-    volatile cyg_uint32 watermark_level;
-    cyg_uint32 reserved1[2];
-    volatile cyg_uint32 force_event;
-    volatile cyg_uint32 adma_error_status_register;
-    volatile cyg_uint32 adma_system_address;
-    cyg_uint32 reserved[40];
-    volatile cyg_uint32 host_controller_version;
+       volatile cyg_uint32 dma_system_address;
+       volatile cyg_uint32 block_attributes;
+       volatile cyg_uint32 command_argument;
+       volatile cyg_uint32 command_transfer_type;
+       volatile cyg_uint32 command_response0;
+       volatile cyg_uint32 command_response1;
+       volatile cyg_uint32 command_response2;
+       volatile cyg_uint32 command_response3;
+       volatile cyg_uint32 data_buffer_access;
+       volatile cyg_uint32 present_state;
+       volatile cyg_uint32 protocol_control;
+       volatile cyg_uint32 system_control;
+       volatile cyg_uint32 interrupt_status;
+       volatile cyg_uint32 interrupt_status_enable;
+       volatile cyg_uint32 interrupt_signal_enable;
+       volatile cyg_uint32 autocmd12_status;
+       volatile cyg_uint32 host_controller_capabilities;
+       volatile cyg_uint32 watermark_level;
+       cyg_uint32 reserved1[2];
+       volatile cyg_uint32 force_event;
+       volatile cyg_uint32 adma_error_status_register;
+       volatile cyg_uint32 adma_system_address;
+       cyg_uint32 reserved[40];
+       volatile cyg_uint32 host_controller_version;
 }host_register, *host_register_ptr;
 
 
@@ -253,5 +253,6 @@ extern cyg_uint32 host_data_write(cyg_uint32 *,cyg_uint32);
 extern void host_cfg_block(cyg_uint32 blk_len, cyg_uint32 nob);
 extern void host_init(cyg_uint32 base_address);
 extern void esdhc_softreset(cyg_uint32 mask);
+extern cyg_uint32 card_get_capacity_size (void);
 /*================================================================================================*/
 #endif  /* _MXCMCI_HOST_H_ */