Added TX25 bootsplash support

[karo-tx-redboot.git] / packages / hal / arm / mx25 / karo / v1_0 / include / plf_mmap.h

diff --git a/packages/hal/arm/mx25/karo/v1_0/include/plf_mmap.h b/packages/hal/arm/mx25/karo/v1_0/include/plf_mmap.h
index d2a32a21843373c9c96f5a3651f4b86db029d3a4..056a63b88c9804d9901c727c9944c326de31022f 100644 (file)
--- a/packages/hal/arm/mx25/karo/v1_0/include/plf_mmap.h
+++ b/packages/hal/arm/mx25/karo/v1_0/include/plf_mmap.h
@@ -56,12 +56,7 @@
 
 #define HAL_VIRT_TO_PHYS_ADDRESS(vaddr, paddr)                 \
        CYG_MACRO_START                                                                         \
-       cyg_uint32 _v_ = (cyg_uint32)(vaddr);                           \
-       if (_v_ < 128 * SZ_1M)           /* SDRAM */            \
-               _v_ += SDRAM_BASE_ADDR;                                                 \
-       else                                                     /* Rest of it */       \
-               /* no change */ ;                                                               \
-       (paddr) = _v_;                                                                          \
+       paddr = hal_virt_to_phy((unsigned long)(vaddr));        \
        CYG_MACRO_END
 
 /*
@@ -76,16 +71,21 @@
 static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
 {
        /* SDRAM mappings:
-          80000000 -> 80000000
-          90000000 -> 80000000 + (SDRAM_SIZE / 2)
+        * virt               -> phys
+        * 00000000..01ffffff -> 80000000..81ffffff
+        * 02000000..03ffffff -> 90000000..91ffffff
+        * 80000000..81ffffff -> 80000000..81ffffff
+        * 82000000..83ffffff -> 90000000..91ffffff
+        * 88000000..89ffffff -> 80000000..81ffffff (uncached)
+        * 8a000000..8bffffff -> 90000000..91ffffff (uncached)
         */
-       if (virt < 0x08000000) {
+       if (virt < SDRAM_SIZE) {
                return virt | (virt < RAM_BANK0_SIZE ? CSD0_BASE_ADDR : CSD1_BASE_ADDR);
        }
        if ((virt & 0xF0000000) == CSD0_BASE_ADDR) {
-               virt &= ~0x08000000;
+               virt &= ~0x08000000; /* clear uncached mapping indicator */
                if (virt >= CSD0_BASE_ADDR + RAM_BANK0_SIZE) {
-                       virt = virt - CSD0_BASE_ADDR + CSD1_BASE_ADDR - RAM_BANK0_SIZE;
+                       virt = virt - (CSD0_BASE_ADDR + RAM_BANK0_SIZE) + CSD1_BASE_ADDR;
                }
        }
        return virt;
@@ -97,7 +97,7 @@ static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
  */
 static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
 {
-       /* 0x88000000~0x88FFFFFF is uncacheable memory space which is mapped to SDRAM */
+       /* 0x88000000~0x8BFFFFFF is uncacheable memory space which is mapped to SDRAM */
        if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
                phy |= 0x08000000;
        }