unified MX27, MX25, MX37 trees

[karo-tx-redboot.git] / packages / hal / arm / mx25 / var / v2_0 / include / hal_mm.h

diff --git a/packages/hal/arm/mx25/var/v2_0/include/hal_mm.h b/packages/hal/arm/mx25/var/v2_0/include/hal_mm.h
index 1970034103641c232b4231b87c5f6d618a2aa9b0..42913243ed8fa6013794a3bac0589d9af771c71f 100644 (file)
--- a/packages/hal/arm/mx25/var/v2_0/include/hal_mm.h
+++ b/packages/hal/arm/mx25/var/v2_0/include/hal_mm.h
@@ -101,29 +101,28 @@ struct ARM_MMU_FIRST_LEVEL_RESERVED {
 
 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
 
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,              \
-                        cacheable, bufferable, perm)                      \
-    CYG_MACRO_START                                                       \
-        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;               \
-                                                                          \
-        desc.word = 0;                                                    \
-        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                 \
-        desc.section.domain = 0;                                          \
-        desc.section.c = (cacheable);                                     \
-        desc.section.b = (bufferable);                                    \
-        desc.section.ap = (perm);                                         \
-        desc.section.base_address = (actual_base);                        \
-        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
-                            = desc.word;                                  \
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,                   \
+                        cacheable, bufferable, perm)                                   \
+    CYG_MACRO_START                                                                                                            \
+        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;                            \
+                                                                                                                                               \
+        desc.word = 0;                                                                                                 \
+        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                              \
+        desc.section.domain = 0;                                                                               \
+        desc.section.c = cacheable;                                                                            \
+        desc.section.b = bufferable;                                                                   \
+        desc.section.ap = perm;                                                                                        \
+        desc.section.base_address = actual_base;                                               \
+        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, virtual_base)        \
+                            = desc.word;                                                               \
     CYG_MACRO_END
 
-#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access)                 \
-      {                                                            \
-        int i; int j = abase; int k = vbase;                              \
-        for (i = size; i > 0 ; i--,j++,k++) {                             \
-        ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);      \
-      }                                                            \
-    }
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access) {                \
+       int i; int j = abase; int k = vbase;                                                    \
+       for (i = size; i > 0 ; i--, j++, k++) {                                                 \
+        ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);          \
+       }                                                                                                                               \
+}
 
 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
         unsigned long word;
@@ -165,6 +164,48 @@ union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
         ARM_ACCESS_TYPE_NO_ACCESS(13) |         \
         ARM_ACCESS_TYPE_NO_ACCESS(14) |         \
         ARM_ACCESS_TYPE_NO_ACCESS(15) )
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+#ifndef RAM_BANK0_SIZE
+#warning using SDRAM_SIZE for RAM_BANK0_SIZE
+#define RAM_BANK0_SIZE         SDRAM_SIZE
+#endif
+
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+       /* SDRAM mappings:
+          80000000 -> 80000000
+          90000000 -> 80000000 + (SDRAM_SIZE / 2)
+        */
+       if (virt < 0x08000000) {
+               return virt | (virt < RAM_BANK0_SIZE ? CSD0_BASE_ADDR : CSD1_BASE_ADDR);
+       }
+       if ((virt & 0xF0000000) == CSD0_BASE_ADDR) {
+               virt &= ~0x08000000;
+               if (virt >= CSD0_BASE_ADDR + RAM_BANK0_SIZE) {
+                       virt = virt - CSD0_BASE_ADDR + CSD1_BASE_ADDR - RAM_BANK0_SIZE;
+               }
+       }
+       return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+       /* 0x88000000~0x88FFFFFF is uncacheable memory space which is mapped to SDRAM */
+       if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
+               phy |= 0x08000000;
+       }
+       if ((phy & 0xF0000000) == CSD1_BASE_ADDR) {
+               phy = (phy - CSD1_BASE_ADDR + CSD0_BASE_ADDR + RAM_BANK0_SIZE) | 0x08000000;
+       }
+       return phy;
+}
 
 // ------------------------------------------------------------------------
 #endif // ifndef CYGONCE_HAL_MM_H