-#define ARM_ACCESS_DACR_DEFAULT ( \
- ARM_ACCESS_TYPE_MANAGER(0) | \
- ARM_ACCESS_TYPE_NO_ACCESS(1) | \
- ARM_ACCESS_TYPE_NO_ACCESS(2) | \
- ARM_ACCESS_TYPE_NO_ACCESS(3) | \
- ARM_ACCESS_TYPE_NO_ACCESS(4) | \
- ARM_ACCESS_TYPE_NO_ACCESS(5) | \
- ARM_ACCESS_TYPE_NO_ACCESS(6) | \
- ARM_ACCESS_TYPE_NO_ACCESS(7) | \
- ARM_ACCESS_TYPE_NO_ACCESS(8) | \
- ARM_ACCESS_TYPE_NO_ACCESS(9) | \
- ARM_ACCESS_TYPE_NO_ACCESS(10) | \
- ARM_ACCESS_TYPE_NO_ACCESS(11) | \
- ARM_ACCESS_TYPE_NO_ACCESS(12) | \
- ARM_ACCESS_TYPE_NO_ACCESS(13) | \
- ARM_ACCESS_TYPE_NO_ACCESS(14) | \
- ARM_ACCESS_TYPE_NO_ACCESS(15) )
-/*
- * translate the virtual address of ram space to physical address
- * It is dependent on the implementation of hal_mmu_init
- */
-#ifndef RAM_BANK0_SIZE
-#warning using SDRAM_SIZE for RAM_BANK0_SIZE
-#define RAM_BANK0_SIZE SDRAM_SIZE
-#endif
-
-static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
-{
- /* SDRAM mappings:
- 80000000 -> 80000000
- 90000000 -> 80000000 + (SDRAM_SIZE / 2)
- */
- if (virt < 0x08000000) {
- return virt | (virt < RAM_BANK0_SIZE ? CSD0_BASE_ADDR : CSD1_BASE_ADDR);
- }
- if ((virt & 0xF0000000) == CSD0_BASE_ADDR) {
- virt &= ~0x08000000;
- if (virt >= CSD0_BASE_ADDR + RAM_BANK0_SIZE) {
- virt = virt - CSD0_BASE_ADDR + CSD1_BASE_ADDR - RAM_BANK0_SIZE;
- }
- }
- return virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
-{
- /* 0x88000000~0x88FFFFFF is uncacheable memory space which is mapped to SDRAM */
- if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
- phy |= 0x08000000;
- }
- if ((phy & 0xF0000000) == CSD1_BASE_ADDR) {
- phy = (phy - CSD1_BASE_ADDR + CSD0_BASE_ADDR + RAM_BANK0_SIZE) | 0x08000000;
- }
- return phy;
-}
+#define ARM_ACCESS_DACR_DEFAULT ( \
+ ARM_ACCESS_TYPE_MANAGER(0) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(1) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(2) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(3) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(4) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(5) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(6) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(7) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(8) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(9) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(10) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(11) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(12) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(13) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(14) | \
+ ARM_ACCESS_TYPE_NO_ACCESS(15) )