#include <cyg/hal/hal_mm.h> // MMap table definitions
#include <cyg/infra/diag.h> // diag_printf
+#include <cyg/io/imx_nfc.h>
// Most initialization has already been done before we get here.
// All we do here is set up the interrupt environment.
#define IIM_SREV_REV_SH 4
#define IIM_SREV_REV_LEN 4
-#define PROD_SIGNATURE_MX25 0x1
+#define PROD_SIGNATURE_MX25 0x1F
#define PROD_SIGNATURE_SUPPORTED_1 PROD_SIGNATURE_MX25
#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
-#define PART_NUMBER_OFFSET (12)
-#define MAJOR_NUMBER_OFFSET (4)
-#define MINOR_NUMBER_OFFSET (0)
+#define PART_NUMBER_OFFSET 12
+#define MAJOR_NUMBER_OFFSET 4
+#define MINOR_NUMBER_OFFSET 0
/*
* System_rev will have the following format
*/
unsigned int system_rev = CHIP_REV_1_0;
static int find_correct_chip;
-extern char HAL_PLATFORM_EXTRA[55];
/*
* This functions reads the IIM module and returns the system revision number.
val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
system_rev = 0x25 << PART_NUMBER_OFFSET; /* For MX25 Platform*/
- /* If the IIM doesn't contain valid product signature, return
+ /* If the IIM doesn't contain a valid product signature, return
* the lowest revision number */
if ((MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) !=
PROD_SIGNATURE_SUPPORTED_1)) {
+#if 0
return CHIP_VERSION_NONE;
+#endif
}
/* Now trying to retrieve the silicon rev from IIM's SREV register */
ver = read_system_rev();
find_correct_chip = ver;
+ if (ver != CHIP_VERSION_NONE) {
+ /* Valid product revision found. Check actual silicon rev from the ROM code. */
+ if (ver == 0x0) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (ver == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else {
+ HAL_PLATFORM_EXTRA[5] = 'z';
+ HAL_PLATFORM_EXTRA[7] = 'z';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+ }
+
// Mask all interrupts
writel(0xFFFFFFFF, ASIC_NIMASK);
unsigned int hal_timer_count(void)
{
- return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+ return 0 - readl(EPIT_BASE_ADDR + EPITCNR);
}
#define WDT_MAGIC_1 0x5555
static unsigned int led_on = 0;
//
-// Delay for some number of micro-seconds
+// Delay for some number of microseconds
//
void hal_delay_us(unsigned int usecs)
{
* unsigned int delayCount = (usecs * 32000) / 1000000;
* So use the following one instead
*/
- unsigned int delayCount = (usecs*4 + 124) / 125;
+ unsigned int delayCount = (usecs * 512) / 16000;
if (delayCount == 0) {
return;
// Interrupt priorities are not configurable.
}
-unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc,
+ unsigned int num_of_chips)
{
unsigned int tmp ;
if (is_mlc) {
tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) | (1 << 8);
} else {
- tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & (~(1 << 8));
+ tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & ~(1 << 8);
}
writew(tmp, NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF);
if (io_sz == 16) {
tmp |= (1 << 14);
} else {
- tmp &= (~(1 << 14));
+ tmp &= ~(1 << 14);
}
tmp &= ~(3<<8);
- switch(pg_sz = 2048){
+ switch (pg_sz) {
case 2048:
- tmp |= (1<<8);
- break;
+ tmp |= (1<<8);
+ break;
case 4096:
- tmp |= (1<<9);
- break;
+ tmp |= (1<<9);
+ break;
}
writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
- diag_printf("NAND: RCSR=%x\n", tmp);
- return 0x10;
+ return MXC_NFC_V1_1;
}
+#define WDOG_WRSR ((CYG_WORD16 *)(WDOG_BASE_ADDR + 0x4))
+#define CRM_RCSR ((CYG_WORD32 *)(CCM_BASE_ADDR + 0x28))
+
static void check_reset_source(void)
{
+#if 1
+ char *reset_cause = "UNKNOWN";
+ CYG_WORD16 wrsr;
+ CYG_WORD32 rcsr;
+
+ HAL_READ_UINT32(CRM_RCSR, rcsr);
+ HAL_READ_UINT16(WDOG_WRSR, wrsr);
+ rcsr &= 0x0f;
+ if (rcsr == 0) {
+ reset_cause = "POWER_ON RESET";
+ } else if (rcsr == 1) {
+ reset_cause = "EXTERNAL RESET";
+ } else if (rcsr & (1 << 3)) {
+ reset_cause = "JTAG RESET";
+ } else if (rcsr & (1 << 2)) {
+ reset_cause = "SOFT RESET";
+ } else if (rcsr & (1 << 1)) {
+ if (wrsr & (1 << 0)) {
+ reset_cause = "SOFTWARE RESET";
+ } else if (wrsr & (1 << 1)) {
+ reset_cause = "WATCHDOG TIMEOUT";
+ }
+ } else {
+ diag_printf("Unknown RESET cause: RCSR=0x%08x WRSR=0x%04x\n", rcsr, wrsr);
+ return;
+ }
+ diag_printf("Last RESET cause: %s\n", reset_cause);
+#else
unsigned int rest = readl(CCM_BASE_ADDR + CLKCTL_RCSR) & 0xF;
if (rest == 0)
diag_printf("hardware reset by POR\n");
else if (rest == 1)
diag_printf("hardware reset by Board reset signal\n");
- else if ((rest & 2) == 2)
+ else if (rest & 2)
diag_printf("hardware reset by WDOG\n");
- else if ((rest & 4) == 4)
+ else if (rest & 4)
diag_printf("hardware reset by SOFT RESET\n");
- else if ((rest & 8) == 8)
+ else if (rest & 8)
diag_printf("hardware reset by JTAG SW RESET\n");
else
diag_printf("hardware reset by unknown source (REST=%x)\n", rest);
+#endif
}
RedBoot_init(check_reset_source, RedBoot_INIT_LAST);
projects / karo-tx-redboot.git / blobdiff