#define CYGHWR_HAL_ROM_VADDR 0x0
+//#define NFC_2K_BI_SWAP
+
// This macro represents the initial startup code for the platform
// r11 is reserved to contain chip rev info in this file
.macro _platform_setup1
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+ mov r0, #NFC_BASE
+ add r1, r0, #0x400
+ cmp pc, r0
+ blo init_aipi_start
+ cmp pc, r1
+ bhi init_aipi_start
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+
init_aipi_start:
init_aipi
ldr r0, SOC_SYSCTRL_BASE_W
mov r1, #0x03
str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
- mov r1, #0xFFFFFFC9
+ ldr r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
+ and r1, r1, #0xFFFFFFF0
+ orr r1, r1, #9
str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
init_max_start:
blo Normal_Boot_Continue
cmp pc, r2
bhi Normal_Boot_Continue
+
NAND_Boot_Start:
/* Copy image from flash to SDRAM first */
ldr r1, MXC_REDBOOT_ROM_START
nop
nop
+NAND_Copy_Main:
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
mov r0, #NAND_FLASH_BOOT
ldr r1, AVIC_VECTOR0_ADDR_W
str r0, [r1]
mov r0, #MXCFIS_NAND
ldr r1, AVIC_VECTOR1_ADDR_W
str r0, [r1]
-NAND_Copy_Main:
+
ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying
mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
- add r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
+ add r2, r0, #0x800 //2K Page:: r2: end of 1st RAM buf. Doesn't change
+ addeq r2, r0, #0x200 //512 Page:: r2: end of 1st RAM buf. Doesn't change
add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
- ldr r14, MXC_REDBOOT_ROM_START
- add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
- add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
+ ldr r11, MXC_REDBOOT_ROM_START
+ add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+ add r11, r11, r1 //r11: starting SDRAM address for copying. Updated constantly
//unlock internal buffer
mov r3, #0x2
strh r3, [r12, #0xA]
Nfc_Read_Page:
-// writew(FLASH_Read_Mode1, NAND_FLASH_CMD_REG);
- mov r3, #0x0;
- strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
- mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- do_wait_op_done
-
+// NFC_CMD_INPUT(FLASH_Read_Mode1);
+ mov r3, #0x0
+ nfc_cmd_input
+
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+ bne nfc_addr_ops_2kb
// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
mov r3, r1
do_addr_input //1st addr cycle
do_addr_input //2nd addr cycle
mov r3, r1, lsr #17
do_addr_input //3rd addr cycle
-
mov r3, r1, lsr #25
do_addr_input //4th addr cycle
+ b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+ mov r3, #0
+ do_addr_input //1st addr cycle
+ mov r3, #0
+ do_addr_input //2nd addr cycle
+ mov r3, r1, lsr #11
+ do_addr_input //3rd addr cycle
+ mov r3, r1, lsr #19
+ do_addr_input //4th addr cycle
+ mov r3, r1, lsr #27
+ do_addr_input //4th addr cycle
+// NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
+ mov r3, #0x30
+ nfc_cmd_input
+end_of_nfc_addr_ops:
// NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
-// writew(NAND_FLASH_CONFIG1_ECC_EN, NAND_FLASH_CONFIG1_REG);
- mov r3, #(NAND_FLASH_CONFIG1_ECC_EN)
- strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
-
-// writew(buf_no, RAM_BUFFER_ADDRESS_REG);
- mov r3, #0
- strh r3, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
-// writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
- mov r3, #FDO_PAGE_SPARE_VAL
- strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
-// wait_op_done();
- do_wait_op_done
+// writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
+// NAND_FLASH_CONFIG1_REG);
+ mov r8, #0
+ bl nfc_data_output
+ bl do_wait_op_done
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+ beq nfc_addr_data_output_done_512
+
+// For 2K page - 2nd 512
+ mov r8, #1
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 3rd 512
+ mov r8, #2
+ bl nfc_data_output
+ bl do_wait_op_done
+
+// 4th 512
+ mov r8, #3
+ bl nfc_data_output
+ bl do_wait_op_done
+// end of 4th
+#ifdef NFC_2K_BI_SWAP
+ ldr r3, [r0, #0x7D0] // load word at addr 464 of last 512 RAM buffer
+ and r3, r3, #0xFFFFFF00 // mask off the LSB
+ ldr r4, [r0, #0x834] // load word at addr 4 of the 3rd spare area buffer
+ mov r4, r4, lsr #8 // shift it to get the byte at addr 5
+ and r4, r4, #0xFF // throw away upper 3 bytes
+ add r3, r4, r3 // construct the word
+ str r3, [r0, #0x7D0] // write back
+#endif
+ // check for bad block
+ mov r3, r1, lsl #(32-17) // get rid of block number
+ cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+ b nfc_addr_data_output_done
+nfc_addr_data_output_done_512:
// check for bad block
- mov r3, r1, lsl #(32-5-9)
- cmp r3, #(512 << (32-5-9))
- bhi Copy_Good_Blk
+ mov r3, r1, lsl #(32-5-9) // get rid of block number
+ cmp r3, #(512 << (32-5-9)) // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+ b Copy_Good_Blk // workaround for now. See ENGR00067497
+// bhi Copy_Good_Blk
add r4, r0, #0x800 //r3 -> spare area buf 0
ldrh r4, [r4, #0x4]
and r4, r4, #0xFF00
cmp r3, #0x0
beq Skip_bad_block
// even suckier since we already read the first page!
- sub r14, r14, #512 //rewind 1 page for the sdram pointer
- sub r1, r1, #512 //rewind 1 page for the flash pointer
+
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ subeq r11, r11, #512 //rewind 1 page for the sdram pointer
+ subeq r1, r1, #512 //rewind 1 page for the flash pointer
+
+ // for 2k page
+ subne r11, r11, #0x800 //rewind 1 page for the sdram pointer
+ subne r1, r1, #0x800 //rewind 1 page for the flash pointer
+
Skip_bad_block:
- add r1, r1, #(32*512)
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ addeq r1, r1, #(32*512)
+ addne r1, r1, #(64*2048)
+
b Nfc_Read_Page
Copy_Good_Blk:
//copying page
1: ldmia r0!, {r3-r10}
- stmia r14!, {r3-r10}
+ stmia r11!, {r3-r10}
cmp r0, r2
blo 1b
- cmp r14, r13
+ cmp r11, r13
bge NAND_Copy_Main_done
- add r1, r1, #0x200
- ldr r0, NFC_BASE_W
+ // Check if x16/2kb page
+ ldr r7, SOC_SYSCTRL_BASE_W
+ ldr r7, [r7, #0x14]
+ ands r7, r7, #(1 << 5)
+
+ addeq r1, r1, #0x200
+ addne r1, r1, #0x800
+ mov r0, #NFC_BASE
b Nfc_Read_Page
NAND_Copy_Main_done:
.endm // _platform_setup1
+do_wait_op_done:
+ 1:
+ ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+ beq 1b
+ bx lr // do_wait_op_done
+
+nfc_data_output:
+ mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+ strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+ // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
+ strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+ // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
+ mov r3, #FDO_PAGE_SPARE_VAL
+ strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+ bx lr
+
#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define PLATFORM_SETUP1
#endif
str r1, [r0, #CSCRA_OFFSET]
.endm /* init_cs0_sync */
- .macro init_cs4: /* ADS board expanded IOs */
+ .macro init_cs4 /* ADS board expanded IOs */
ldr r1, SOC_CS4_CTL_BASE_W
ldr r2, CS4_CSCRU_0x0000DCF6
str r2, [r1, #CSCRU_OFFSET]
ldr r1, [r1]
ands r1, r1, #0xF0000000
// add Latency on CAS only for TO2
- ldreq r1, SDRAM_0x00795729
- ldrne r1, SDRAM_0x00795429
-
+ // TO 1.0's ID = 0x0 ==>> CAS = 3
+ bne 2f
+ ldr r1, SDRAM_0x00795729
+ b 3f
+ // now handles TO 2.x
+ 2:
+ ands r1, r1, #0xE0000000
+ // TO 2.0's ID = 0x1 => CAS = 4 due to the MPEG4 issue
+ ldreq r1, SDRAM_0x00795429
+ // subesquent TO's are OK w/ CAS = 3
+ ldrne r1, SDRAM_0x00795729
+ 3:
str r1, [r0, #0x4]
ldr r1, SDRAM_0x92200000
str r1, [r0, #0x0]
str r1, [r0, #0x0]
.endm // setup_sdram_ddr
- .macro do_wait_op_done
- 1:
- ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
- beq 1b
- mov r3, #0x0
+ .macro nfc_cmd_input
+ strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+ mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- .endm // do_wait_op_done
+ bl do_wait_op_done
+ .endm // nfc_cmd_input
.macro do_addr_input
and r3, r3, #0xFF
strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
mov r3, #NAND_FLASH_CONFIG2_FADD_EN
strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
- do_wait_op_done
+ bl do_wait_op_done
.endm // do_addr_input
#define PLATFORM_VECTORS _platform_vectors
projects / karo-tx-redboot.git / blobdiff