Bugfix Release STK5 2010-10-04

[karo-tx-redboot.git] / packages / hal / arm / mx27 / karo / v1_0 / include / hal_platform_setup.h

diff --git a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h
index d3d8e100e8a1ce8898027b9a226ba3ca8e420b0c..f5ec325dff12f00b6038119742041f2842c6b212 100644 (file)
--- a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h
@@ -63,6 +63,9 @@
 
 #define CYGHWR_HAL_ROM_VADDR           0x0
 
+#define DEBUG_LED_BIT                  13
+#define DEBUG_LED_PORT                 GPIOF_BASE
+
 #ifndef CYGOPT_HAL_ARM_TX27_DEBUG
 #define LED_ON
 #define LED_OFF
@@ -76,6 +79,7 @@
 #define CYGHWR_LED_MACRO       LED_BLINK #\x
 #define LED_ON                 bl      led_on
 #define LED_OFF                        bl      led_off
+
        .macro  DELAY,ms
        ldr     r10, =\ms
 111:
@@ -92,12 +96,13 @@
 
        .macro LED_CTRL,val
        // switch user LED (PF13) on STK5
-       ldr     r10, GPIOF_BASE
+       ldr     r10, DEBUG_LED_PORT
        // PTF_DR
        mov     r9, \val
        cmp     r9, #0
-       movne   r9, #(1 << 13)  // LED ON
-       moveq   r9, #0          // LED OFF
+       ldr     r9, [r10, #GPIO_DR]
+       orrne   r9, #(1 << DEBUG_LED_BIT)       // LED ON
+       biceq   r9, #(1 << DEBUG_LED_BIT)       // LED OFF
        str     r9, [r10, #GPIO_DR]
        .endm
 
@@ -118,19 +123,35 @@
 
        .macro LED_INIT
        // initialize GPIO PF13 for LED on STK5
-       ldr     r10, GPIOF_BASE
+       ldr     r10, DEBUG_LED_PORT
+       // PTF_DR
+       ldr     r9, [r10, #GPIO_DR]
+       bic     r9, #(1 << DEBUG_LED_BIT)
+       str     r9, [r10, #GPIO_DR]
        // PTF_OCR1
-       mov     r9, #(3 << (2 * 13))
+       ldr     r9, [r10, #GPIO_OCR1]
+       orr     r9, #(3 << (2 * (DEBUG_LED_BIT % 16)))
        str     r9, [r10, #GPIO_OCR1]
        // PTF_GIUS
        ldr     r9, [r10, #GPIO_GIUS]
-       orr     r9, r9, #(1 << 13)
+       orr     r9, r9, #(1 << DEBUG_LED_BIT)
        str     r9, [r10, #GPIO_GIUS]
        // PTF_DDIR
-       mov     r9,#(1 << 13)
+       ldr     r9, [r10, #GPIO_DDIR]
+       orr     r9, #(1 << DEBUG_LED_BIT)
        str     r9, [r10, #GPIO_DDIR]
        .endm
 
+       .macro  WDOG_RESET
+       ldr     r10, SOC_CRM_BASE_W
+       ldr     r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+       orr     r9, r9, #(1 << 2)       /* enable FPM */
+       str     r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+       ldr     r10, WDOG_BASE
+       mov     r9, #0
+       str     r9, [r10, #0]
+       .endm
 // This macro represents the initial startup code for the platform
 // r11 is reserved to contain chip rev info in this file
        .macro  _platform_setup1
@@ -146,9 +167,9 @@ init_aipi_start:
 
        /* configure GPIO PB22 (OSC26M enable) as output high */
        ldr     r10, GPIOB_BASE
-
        // PTB_OCR1
-       mov     r9, #(3 << (2 * (22 - 16)))
+       ldr     r9, [r10, #GPIO_OCR2]
+       orr     r9, #(3 << (2 * (22 % 16)))
        str     r9, [r10, #GPIO_OCR2]
        // PTB_DR
        ldr     r9, [r10, #GPIO_DR]
@@ -159,7 +180,8 @@ init_aipi_start:
        orr     r9, r9, #(1 << 22)
        str     r9, [r10, #GPIO_GIUS]
        // PTB_DDIR
-       mov     r9,#(1 << 22)
+       ldr     r9, [r10, #GPIO_DDIR]
+       orr     r9, #(1 << 22)
        str     r9, [r10, #GPIO_DDIR]
 
        LED_INIT
@@ -175,7 +197,7 @@ init_aipi_start:
 init_max_start:
        init_max
 init_drive_strength_start:
-       init_drive_strength
+@      init_drive_strength
 
        // check if sdram has been setup
        cmp     pc, #SDRAM_BASE_ADDR
@@ -220,7 +242,11 @@ NAND_Boot_Start:
        LED_OFF
        b       4f
 3:
+#ifdef CYGOPT_HAL_ARM_TX27_DEBUG
        LED_BLINK #3
+#else
+       WDOG_RESET
+#endif
        b       3b
 4:
        LED_ON
@@ -280,14 +306,12 @@ Nfc_Read_Page:
        LED_ON
        strh    r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF]
        bl      nfc_data_output
-#if 1
+
        // check for bad block
        mov     r3, r1, lsl #(32-17)    // get rid of block number
        cmp     r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block
        bhi     Copy_Good_Blk
-#else
-       b       Copy_Good_Blk
-#endif
+
        add     r9, r0, #TX27_NAND_PAGE_SIZE            //r3 -> spare area buf 0
        ldrh    r9, [r9, #0x4]
        and     r9, r9, #0xFF00
@@ -388,7 +412,7 @@ NAND_ClockSetup:
        b       9f
        .align  5
 9:
-       mov     pc,r2   /* Change address spaces */
+       mov     pc, r2  /* Change address spaces */
 10:
        nop
        .endm                   // _platform_setup1
@@ -422,11 +446,9 @@ NAND_ClockSetup:
        orr     r1, r1, #0x000C0000             // restart SPLL and MPLL
        orr     r1, r1, #0x00000003             // enable SPLL and MPLL
        str     r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
-
-       // add some delay here
-       mov     r1, #0x1000
 1:
-       subs    r1, r1, #0x1
+       ldr     r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+       tst     r1, #0x000C0000
        bne     1b
 
        ldr     r1, SOC_CRM_CSCR2_W
@@ -586,7 +608,7 @@ NAND_ClockSetup:
        add     r3, r2, #(2 << 24)
        @ select drive strength via extended mode register:
        @ 0=full 1=half 2=quarter 3=3-quarter
-       ldrb    r1, [r2, #(0 << 5)]
+       ldrb    r1, [r3, #(0 << 5)]
 
        ldrb    r1, [r2, #0x033]        @ write to SDRAM MODE register (via A0-A12)
 
@@ -613,7 +635,7 @@ led_off:
        str     r9, [r10, #GPIO_DR]
        mov     pc, lr
 #endif
-       
+
 nfc_cmd_input:
        strh    r3, [r4, #NAND_FLASH_CMD_REG_OFF]
        mov     r3, #NAND_FLASH_CONFIG2_FCMD_EN
@@ -749,6 +771,7 @@ NS_VAL      tRC,    138, 1  /* 0: 20 *: clks - 1 (0..15) */
                         (tRCD << 4) | (tRC << 0))
 
 // All these constants need to be in the first 2KiB of FLASH
+WDOG_BASE:                     .word   WDOG_BASE_ADDR
 GPIOB_BASE:                    .word   0x10015100
 GPIOF_BASE:                    .word   0x10015500
 SDRAM_ADDR_MASK:               .word   0xffff0000