.macro LED_INIT
// initialize GPIO PF13 for LED on STK5
ldr r10, GPIOF_BASE
+ // PTF_OCR1
+ mov r9, #(3 << (2 * 13))
+ str r9, [r10, #GPIO_OCR1]
// PTF_GIUS
ldr r9, [r10, #GPIO_GIUS]
orr r9, r9, #(1 << 13)
// PTF_DDIR
mov r9,#(1 << 13)
str r9, [r10, #GPIO_DDIR]
- // PTF_OCR1
- mov r9, #(3 << (2 * 13))
- str r9, [r10, #GPIO_OCR1]
.endm
// This macro represents the initial startup code for the platform
init_aipi_start:
init_aipi
+ /* configure GPIO PB22 (OSC26M enable) as output high */
+ ldr r10, GPIOB_BASE
+
+ // PTB_OCR1
+ mov r9, #(3 << (2 * (22 - 16)))
+ str r9, [r10, #GPIO_OCR2]
+ // PTB_DR
+ ldr r9, [r10, #GPIO_DR]
+ orr r9, r9, #(1 << 22)
+ str r9, [r10, #GPIO_DR]
+ // PTB_GIUS
+ ldr r9, [r10, #GPIO_GIUS]
+ orr r9, r9, #(1 << 22)
+ str r9, [r10, #GPIO_GIUS]
+ // PTB_DDIR
+ mov r9,#(1 << 22)
+ str r9, [r10, #GPIO_DDIR]
+
LED_INIT
// setup System Controls
init_max
init_drive_strength_start:
init_drive_strength
-#if 0
-init_cs4_start:
- init_cs4
-#endif
-
-#if 0
-init_cs0_start:
- init_cs0
-#endif
- LED_INIT
// check if sdram has been setup
cmp pc, #SDRAM_BASE_ADDR
// add some delay here
mov r1, #0x1000
1:
- subs r1, r1, #0x1
+ subs r1, r1, #0x1
bne 1b
- ldr r2, SOC_CRM_CSCR2_W
- str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ ldr r1, SOC_CRM_CSCR2_W
+ str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
// Set divider of H264_CLK to zero, NFC to 3.
- ldr r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
- bic r2, r2, #0x0000FC00
- str r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+ ldr r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+ bic r1, r1, #0x0000FC00
+ str r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
/* Configure PCDR1 */
ldr r1, SOC_CRM_PCDR1_W
ldr r1, SDRAM_ESDCFG0_VAL
str r1, [r0, #ESDCTL_ESDCFG0]
+ ldr r1, SDRAM_DLY_VAL
+ str r1, [r0, #ESDCTL_ESDCDLY1]
+ str r1, [r0, #ESDCTL_ESDCDLY2]
+ str r1, [r0, #ESDCTL_ESDCDLY3]
+ str r1, [r0, #ESDCTL_ESDCDLY4]
+ str r1, [r0, #ESDCTL_ESDCDLY5]
+
ldr r1, SDRAM_PRE_ALL_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
.align 5
.ascii "KARO TX27 " __DATE__ " " __TIME__
.align
+
+/* SDRAM configuration */
+#define RA_BITS 2 /* row addr bits - 11 */
+#define CA_BITS (SDRAM_SIZE / SZ_64M) /* 0-2: col addr bits - 8 3: rsrvd */
+#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
+#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
+#define PWDT 1 /* 0: disabled 1: precharge pwdn
+ 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
+#define FP 0 /* 0: not full page 1: full page */
+#define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
+#define PRCT 5 /* 0: disabled *: clks / 2 (0..63) */
+#define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
+ (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
+ (BL << 7) | (PRCT << 0))
+
+/* SDRAM timing definitions */
+#define SDRAM_CLK 133
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - 16
+ .set \name, \clks - \offs
+ .else
+ .set \name, 0
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs
+ .endif
+ .endm
+
+#if SDRAM_SIZE <= SZ_64M
+/* MT46H16M32LF-75 */
+CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+/* tRC is actually max(tRC,tRFC,tXSR) */
+NS_VAL tRC, 120, 1 /* 0: 20 *: clks - 1 (0..15) */
+#else
+/* MT46H32M32LF-6 or -75 */
+NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */
+#endif
+
+#define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
+ (tRCD << 4) | (tRC << 0))
+
// All these constants need to be in the first 2KiB of FLASH
+GPIOB_BASE: .word 0x10015100
GPIOF_BASE: .word 0x10015500
SDRAM_ADDR_MASK: .word 0xffff0000
MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
CS4_CSCRA_VAL: .word 0x44443302
NFC_BASE_W: .word NFC_BASE
SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
-SDRAM_ESDCFG0_VAL: .word 0x00395729
+SDRAM_ESDCFG0_VAL: .word ESDCFGVAL
+SDRAM_DLY_VAL: .word 0x002c0000
SDRAM_PRE_ALL_CMD: .word 0x92120000
SDRAM_AUTO_REF_CMD: .word 0xA2120000
SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
-#if SDRAM_SIZE > SZ_64M
-SDRAM_NORMAL_MODE: .word 0x82226485
-#else
-SDRAM_NORMAL_MODE: .word 0x82126485
-#endif
+SDRAM_NORMAL_MODE: .word ESDCTLVAL
CS0_CSCRU_VAL: .word 0x0000CC03
CS0_CSCRL_VAL: .word 0xA0330D01
CS0_CSCRA_VAL: .word 0x00220800
projects / karo-tx-redboot.git / blobdiff