ldr r0, SOC_CRM_BASE_W
// disable PLL update first
ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ /* clear ARM_SRC & ARM_DIV required as workaround for ENGcm12387 */
+ bic r1, r1, #((1 << 15) | (3 << 12))
orr r1, r1, #(1 << 31)
#ifdef PLL_REF_CLK_32768HZ
- orr r1, r1, #(1 << 3) // disable OSC26M
+ orr r1, r1, #(1 << 3) // disable 26MHz osc
#else
bic r1, r1, #(1 << 3) // enable 26MHz osc
#endif
str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+#ifdef PLL_REF_CLK_32768HZ
+ // Make sure to use CKIL
+ bic r1, r1, #(3 << 16)
+#else
+ orr r1, r1, #(3 << 16) // select 26MHz
+#endif
orr r1, r1, #(0x3 << 18) // SPLL_RESTART | MPLL_RESTART
orr r1, r1, #(0x3 << 0) // SPLL_ENABLE | MPLL_ENABLE
str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]