TX51 pre-release

[karo-tx-redboot.git] / packages / hal / arm / mx27 / karo / v1_0 / src / tx27_misc.c

diff --git a/packages/hal/arm/mx27/karo/v1_0/src/tx27_misc.c b/packages/hal/arm/mx27/karo/v1_0/src/tx27_misc.c
index 6446d77d9dcd1792923e76e178f0e662ed8e7e17..e37aaa88ce7b4fda34c0dc32bf1b142c6f815df0 100644 (file)
--- a/packages/hal/arm/mx27/karo/v1_0/src/tx27_misc.c
+++ b/packages/hal/arm/mx27/karo/v1_0/src/tx27_misc.c
@@ -90,9 +90,9 @@ void hal_mmu_init(void)
        X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
        X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* Internal Registers */
        X_ARM_MMU_SECTION(0x800, 0x800, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* CSI/ATA Registers */
-       X_ARM_MMU_SECTION(0xA00, 0x000, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
-       X_ARM_MMU_SECTION(0xA00, 0xA00, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
-       X_ARM_MMU_SECTION(0xA00, 0xA80, TX27_SDRAM_SIZE >> 20,  ARM_UNCACHEABLE,  ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* SDRAM */
+       X_ARM_MMU_SECTION(0xA00, 0x000, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+       X_ARM_MMU_SECTION(0xA00, 0xA00, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+       X_ARM_MMU_SECTION(0xA00, 0xA80, TX27_SDRAM_SIZE >> 20,  ARM_UNCACHEABLE,  ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* SDRAM */
 //     X_ARM_MMU_SECTION(0xC00, 0xC00, 0x020, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Flash */
        X_ARM_MMU_SECTION(0xD40, 0xD40, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* CS4 for External I/O */
        X_ARM_MMU_SECTION(0xD60, 0xD60, 0x020, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* CS5 PSRAM */
@@ -115,7 +115,7 @@ static void fec_gpio_init(void)
 {
        /* GPIOs to set up for TX27/Starterkit-5:
           Function       GPIO  Dir  act.  FCT
-                                     Lvl   
+                                     Lvl
           FEC_RESET      PB30  OUT  LOW   GPIO
           FEC_ENABLE     PB27  OUT  HIGH  GPIO
           OSCM26_ENABLE  PB22  OUT  HIGH  GPIO
@@ -184,28 +184,28 @@ extern int fuse_blow(int bank, int row, int bit);
 #define SOC_I2C2_BASE          UL(0x1001D000)
 
 /* Address offsets of the I2C registers */
-#define MXC_IADR                0x00   /* Address Register */
-#define MXC_IFDR                0x04   /* Freq div register */
-#define MXC_I2CR                0x08   /* Control regsiter */
-#define MXC_I2SR                0x0C   /* Status register */
-#define MXC_I2DR                0x10   /* Data I/O register */
+#define MXC_IADR                               0x00    /* Address Register */
+#define MXC_IFDR                               0x04    /* Freq div register */
+#define MXC_I2CR                               0x08    /* Control regsiter */
+#define MXC_I2SR                               0x0C    /* Status register */
+#define MXC_I2DR                               0x10    /* Data I/O register */
 
 /* Bit definitions of I2CR */
-#define MXC_I2CR_IEN            0x0080
-#define MXC_I2CR_IIEN           0x0040
-#define MXC_I2CR_MSTA           0x0020
-#define MXC_I2CR_MTX            0x0010
-#define MXC_I2CR_TXAK           0x0008
-#define MXC_I2CR_RSTA           0x0004
+#define MXC_I2CR_IEN                   0x0080
+#define MXC_I2CR_IIEN                  0x0040
+#define MXC_I2CR_MSTA                  0x0020
+#define MXC_I2CR_MTX                   0x0010
+#define MXC_I2CR_TXAK                  0x0008
+#define MXC_I2CR_RSTA                  0x0004
 
 /* Bit definitions of I2SR */
-#define MXC_I2SR_ICF            0x0080
-#define MXC_I2SR_IAAS           0x0040
-#define MXC_I2SR_IBB            0x0020
-#define MXC_I2SR_IAL            0x0010
-#define MXC_I2SR_SRW            0x0004
-#define MXC_I2SR_IIF            0x0002
-#define MXC_I2SR_RXAK           0x0001
+#define MXC_I2SR_ICF                   0x0080
+#define MXC_I2SR_IAAS                  0x0040
+#define MXC_I2SR_IBB                   0x0020
+#define MXC_I2SR_IAL                   0x0010
+#define MXC_I2SR_SRW                   0x0004
+#define MXC_I2SR_IIF                   0x0002
+#define MXC_I2SR_RXAK                  0x0001
 
 #define LP3972_SLAVE_ADDR      0x34
 
@@ -433,7 +433,7 @@ int tx27_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
 
                if ((fuse | mac_addr[i]) != mac_addr[i]) {
                        diag_printf("MAC address fuse cannot be programmed: fuse[%d]=0x%02x -> 0x%02x\n",
-                                   i, fuse, mac_addr[i]);
+                                               i, fuse, mac_addr[i]);
                        return -1;
                }
                if (fuse != mac_addr[i]) {
@@ -465,7 +465,7 @@ int tx27_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
                        }
                        if (fuse_blow(0, i + 5, bit)) {
                                diag_printf("Failed to blow fuse bank 0 row %d bit %d\n",
-                                           i, bit);
+                                                       i, bit);
                                ret = -1;
                                goto out;
                        }