// PD MFD MFI MFN
#define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) ((((pd)-1)<<26) + (((fd)-1)<<16) + ((fi)<<10) + (((fn) & 0x3ff) << 0))
+
+#define SPLL_REF_CLK_kHz 240000
+
#if (PLL_REF_CLK == FREQ_32768HZ)
#define PLL_REF_CLK_32768HZ
// SPCTL0 for 240 MHz
#define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 124, 7, 19)
#define CRM_SPCTL0_VAL_27MHZ CRM_SPCTL0_VAL
- #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 755, 11, -205)
+ #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(4, 567, 14, 173)
#define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL2
#if defined (CLOCK_266_133_66)
+ #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1500)
#define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 400, 7, 371)
#define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
#define CRM_CSCR_VAL 0x33F00307
#define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
#define CRM_CSCR_VAL2 0x33F00107
#elif defined (CLOCK_399_133_66)
+ #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
#define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
#define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
#define CRM_CSCR_VAL 0x33F00507
#define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2
#define CRM_CSCR_VAL2 0x33F08107
#elif defined (CLOCK_399_100_50)
+ #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
#define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89)
#define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL
#define CRM_CSCR_VAL 0x33F00307
#else
#error This clock is not supported !!!!
#endif // CLOCK_266_133_66
-#else
+#else // PLL_REF_CLK == FREQ_32768HZ
+#define PLL_VAL_239_999 CRM_PLL_PCTL_PARAM(2, 13, 9, 3)
+#define PLL_VAL_240 CRM_PLL_PCTL_PARAM(3, 13, 13, 11)
+#define PLL_VAL_265_999 CRM_PLL_PCTL_PARAM(2, 26, 10, 6)
+#define PLL_VAL_266 CRM_PLL_PCTL_PARAM(3, 26, 15, 9)
+#define PLL_VAL_399 CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
+#define PLL_VAL_399_ALT CRM_PLL_PCTL_PARAM(2, 26, 15, 9)
+#define PLL_VAL_400 CRM_PLL_PCTL_PARAM(2, 13, 15, 5)
+#define PLL_VAL_600 CRM_PLL_PCTL_PARAM(1, 13, 11, 7)
+#define PLL_VAL_600_ALT CRM_PLL_PCTL_PARAM(1, 52, 11, 28)
+#define PLL_VAL_598_5 CRM_PLL_PCTL_PARAM(1, 104, 11, 53)
+
// SPCTL0 for 240 MHz
- #define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 13, 9, 3)
+ #define CRM_SPCTL0_VAL PLL_VAL_240
#define CRM_SPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 9, 8, 8)
#define CRM_SPCTL0_VAL2 CRM_SPCTL0_VAL
#define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL_27MHZ
#if defined (CLOCK_266_133_66)
- #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 26, 10, 6)
- #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 15, 9, 13) // 266.4MHz
+ #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1500)
+ #define CRM_MPCTL0_VAL PLL_VAL_266 // 265.999
+ #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 15, 9, 13) // 266.4 MHz
#define CRM_CSCR_VAL 0x33F30307
- #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
- #define CRM_MPCTL0_VAL2_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
+ #define CRM_MPCTL0_VAL2 PLL_VAL_399
+ #define CRM_MPCTL0_VAL2_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6 MHz
#define CRM_CSCR_VAL2 0x33F30107
#elif defined (CLOCK_399_133_66)
- #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
- #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
+ #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
+ #define CRM_MPCTL0_VAL PLL_VAL_399
+ #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6 MHz
#define CRM_CSCR_VAL 0x33F30507
#define CRM_MPCTL0_VAL2 CRM_MPCTL0_VAL
#define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ
#define CRM_CSCR_VAL2 0x33F38107
#elif defined (CLOCK_399_100_50)
- #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35)
- #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz
+ #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000)
+ #define CRM_MPCTL0_VAL PLL_VAL_399
+ #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6 MHz
#define CRM_CSCR_VAL 0x33F30307
- #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 11, 28)
+ #define CRM_MPCTL0_VAL2 PLL_VAL_399
#define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ
- #define CRM_CSCR_VAL2 0x33F30307
+ #define CRM_CSCR_VAL2 0x33F38307
#else
#error This clock is not supported !!!!
#endif // CLOCK_266_133_66