#include <cyg/hal/hal_mmu.h> // MMU definitions
#include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
+//#define BOOT_FROM_MMC
+
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
#define PLATFORM_SETUP1 _platform_setup1
+#if defined(BOOT_FROM_MMC)
+#define PLATFORM_PREAMBLE flash_header
+#endif
#define CYGHWR_HAL_ARM_HAS_MMU
#ifdef CYG_HAL_STARTUP_ROMRAM
#define CYGSEM_HAL_ROM_RESET_USES_JUMP
#endif
-#define SDRAM_FULL_PAGE_BIT 0x100
-#define SDRAM_FULL_PAGE_MODE 0x37
-#define SDRAM_BURST_MODE 0x33
+//#define ARM_399MHZ
+#define ARM_532MHZ
+
+#define SDRAM_FULL_PAGE_BIT 0x100
+#define SDRAM_FULL_PAGE_MODE 0x37
+#define SDRAM_BURST_MODE 0x33
+#define MMC_BLK_LEN 0x200
+#define MMC_START_ADDR 0x0
+#define MMC_LOAD_SIZE 0x30000
#define CYGHWR_HAL_ROM_VADDR 0x0
#if 0
//#define TURN_OFF_IMPRECISE_ABORT
+ .macro flash_header
+ b 1f
+ //0x400
+ .org 0x400
+ .long 0x0
+ .long 0x0
+ MMC_SDHC1_BASE_ADDR_W: .word MMC_SDHC1_BASE_ADDR
+ ESDHC_INTERRUPT_ENABLE_W: .word ESDHC_INTERRUPT_ENABLE
+ ESDHC_CLEAR_INTERRUPT_W: .word ESDHC_CLEAR_INTERRUPT
+ MXC_REDBOOT_ROM_ST_ADDR: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+ REDBOOT_RESET_VECTOR: .word reset_vector
+1:
+ /* Check if booting from IRAM for MMC boot */
+ mov r0, #SDRAM_BASE_ADDR
+ cmp pc, r0
+ bhs 100f
+ setup_sdram ddr X32 DDR 0
+ mmcsd_read
+ mov r12, #MMC_BOOT
+100:
+ ldr r0, REDBOOT_RESET_VECTOR
+ mov pc, r0
+ .endm
+
+ .macro mmcsd_read
+ //Configure interface block and number of blocks 1 block and size is 512 Bytes
+ mov r2, #MMC_BLK_LEN
+ ldr r3, MMC_SDHC1_BASE_ADDR_W
+ str r2, [r3, #ESDHC_REG_BLK_LEN]
+ mov r2, #1
+ str r2, [r3, #ESDHC_REG_NOB]
+ //set block size and number of blocks of card
+ mov r1, #MMC_START_ADDR
+ mov r2, #MMC_BLK_LEN
+ sub r10, r1, r2
+ ldr r11, MXC_REDBOOT_ROM_ST_ADDR
+ mov r12, #MMC_LOAD_SIZE
+ add r12, r11, r12
+
+ //set read data length, Comfigure command CMD16 for single block read
+ mov r0, #MMC_BLK_LEN
+ mov r1, #0x10
+ mov r2, #0x1
+ send_cmd_wait_resp
+
+read_a_blk:
+ //set read data address
+ //CMD17 data_present Y
+ mov r2, #MMC_BLK_LEN
+ add r10, r10, r2
+ mov r0, r10
+ mov r1, #0x11
+ mov r2, #0x9
+ send_cmd_wait_resp
+ mov r5, #MMC_BLK_LEN
+ add r5, r11, r5
+
+ //enable interrupt
+ ldr r4, ESDHC_INTERRUPT_ENABLE_W
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+read_from_buffer:
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r2, #0x80 //ESDHC_STATUS_BUF_READ_RDY_MSK
+ ands r4, r4, r2
+ beq read_from_buffer
+
+four_times: //transfer data from SDHC buffer to ddr(4 words once)
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ ldr r4, [r3, #ESDHC_REG_BUFFER_DATA]
+ str r4, [r11]
+ add r11, r11, #0x4
+ cmp r11, r5
+ blo read_from_buffer
+
+check_tran_done: //check if the transfer is over
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r2, #0x800 //ESDHC_STATUS_TRANSFER_COMPLETE_MSK
+ ands r2, r4, r2
+ beq check_tran_done
+ ands r2, r2, #0x8
+ bne check_tran_done
+ cmp r11, r12
+ blo read_a_blk
+ .endm
+
+ //r0~r2 are reserved
+ .macro send_cmd_wait_resp
+ //start clk
+ ldr r3, MMC_SDHC1_BASE_ADDR_W
+ mov r4, #0x2
+ str r4, [r3, #ESDHC_REG_CLK]
+
+ //wait until the clk has started
+1:
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS]
+ mov r5, #0x100
+ ands r4, r4, r5
+ beq 1b
+
+ //Clear Interrupt status register
+ ldr r4, ESDHC_CLEAR_INTERRUPT_W
+ str r4, [r3, #ESDHC_REG_INT_STATUS]
+ /* Enable Interrupt */
+ ldr r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+ ldr r5, ESDHC_INTERRUPT_ENABLE_W
+ orr r4, r4, r5
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+
+ /* Write Command Argument in Command Argument Register */
+ str r1, [r3, #ESDHC_REG_COMMAND]
+ str r0, [r3, #ESDHC_REG_COMMAND_TRANS_TYPE]
+ str r2, [r3, #ESDHC_REG_COMMAND_DAT_CONT]
+
+2: //wait for responds
+ mov r0, #0
+ mov r1, #0x1000
+3:
+ add r0,r0,#1
+ cmp r0,r1
+ bne 3b
+
+ ldr r0, [r3, #ESDHC_REG_INT_STATUS]
+ mov r1, #0x2000
+ ands r1, r0, r1
+ beq 2b
+
+ //mask all int
+ mov r4, #0
+ str r4, [r3, #ESDHC_REG_INT_STATUS_ENABLE]
+ .endm
+
// This macro represents the initial startup code for the platform
// r11 is reserved to contain chip rev info in this file
.macro _platform_setup1
bic r0, r0, #0x100
msr cpsr, r0
#endif
-
mov r0, #0
mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
ldr r0, ARM_PPMRR /* start from AIPS 2GB region */
mcr p15, 0, r0, c15, c2, 4
+ /* Reload data from spare area to 0x400 of main area if booting from NAND */
+ mov r0, #NFC_BASE
+ add r1, r0, #0x400
+ cmp pc, r0
+ blo 1f
+ cmp pc, r1
+ bhi 1f
+
+1:
/*** L2 Cache setup/invalidation/disable ***/
/* Disable L2 cache first */
mov r0, #L2CC_BASE_ADDR
init_cs0_async_start:
// init_cs0_async
+
/* If SDRAM has been setup, bypass clock/WEIM setup */
+ cmp r12, #MMC_BOOT
+ ldreq r1, AVIC_VECTOR0_ADDR_W
+ streq r12, [r1]
+ beq init_cs4_start
+
cmp pc, #SDRAM_BASE_ADDR
blo init_clock_start
cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
init_clock_start:
init_clock
+ cmp r12, #MMC_BOOT
+ beq HWInitialise_skip_SDRAM_setup
+
/* Based on chip rev, setup params for SDRAM controller */
ldr r10, =0
mov r4, #SDRAM_BURST_MODE
init_sdram_start:
-
+#ifndef BOOT_FROM_MMC
/* Assuming DDR memory first */
setup_sdram ddr X32 DDR 0
-#if 0
- beq HWInitialise_skip_SDRAM_setup
- setup_sdram ddr X16 DDR 0
- beq HWInitialise_skip_SDRAM_setup
- setup_sdram sdr X32 SDR 0
- beq HWInitialise_skip_SDRAM_setup
- setup_sdram sdr X16 SDR 0
- beq HWInitialise_skip_SDRAM_setup
-
- /* Reach hear means memory setup problem. Try to
- * increase the HCLK divider */
- ldr r0, CCM_BASE_ADDR_W
- ldr r1, [r0, #CLKCTL_PDR0]
- and r2, r1, #0x38
- cmp r2, #0x38
- beq loop_forever
- add r1, r1, #0x8
- str r1, [r0, #CLKCTL_PDR0]
- b init_sdram_start
-
-loop_forever:
- b loop_forever /* shouldn't get here */
#endif
HWInitialise_skip_SDRAM_setup:
bl nfc_data_output
bl do_wait_op_done
// end of 4th
-
// check for bad block
mov r3, r1, lsl #(32-17) // get rid of block number
cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
Normal_Boot_Continue:
-#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
+#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(BOOT_FROM_MMC) /* enable running from RAM */
/* Copy image from flash to SDRAM first */
ldr r0, =0xFFFFF000
and r0, r0, pc
ldr r2, =10f
mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
orr r1, r1, #7 // enable MMU bit
+ orr r1, r1, #0x800 // enable z bit
mcr MMU_CP, 0, r1, MMU_Control, c0
mov pc,r2 /* Change address spaces */
nop
ands r1, r1, #CLK_INPUT_27MHZ_SET
// 532-133-66.5
- ldr r1, CCM_PDR0_532_133_66_W
+ ldr r1, CCM_PDR0_W
str r1, [r0, #CLKCTL_PDR0]
- ldr r1, MPCTL_PARAM_532_W
+ ldr r1, MPCTL_PARAM_W
ldrne r1, MPCTL_PARAM_532_27_W
str r1, [r0, #CLKCTL_MPCTL]
.macro setup_sdram, name, bus_width, mode, full_page
/* It sets the "Z" flag in the CPSR at the end of the macro */
+ b 1f
+ ESDCTL_BASE_W: .word ESDCTL_BASE
+ SDRAM_0x0075E73A: .word 0x0075E73A
+ SDRAM_PARAM1_DDR: .word 0x4
+ SDRAM_PARAM1_SDR: .word 0x0
+ SDRAM_PARAM2_DDR: .word 0x80000F00
+ SDRAM_PARAM2_SDR: .word 0x80000400
+ SDRAM_PARAM3_DDR: .word 0x00100000
+ SDRAM_PARAM3_SDR: .word 0x0
+ SDRAM_PARAM4_X32: .word 0x00010000
+ SDRAM_PARAM4_X16: .word 0x0
+ SDRAM_0x55555555: .word 0x55555555
+ SDRAM_0xAAAAAAAA: .word 0xAAAAAAAA
+ SDRAM_0x92100000: .word 0x92100000
+ SDRAM_0xA2100000: .word 0xA2100000
+ SDRAM_0xB2100000: .word 0xB2100000
+ SDRAM_0x82116080: .word 0x82116080
+1:
ldr r0, ESDCTL_BASE_W
mov r2, #SDRAM_BASE_ADDR
ldr r1, SDRAM_0x0075E73A
.else
strb r1, [r2, #SDRAM_BURST_MODE]
.endif
-
+
ldr r1, =0xFF
ldr r12, =0x81000000
strb r1, [r12]
ldr r0, [r1, #0x6C]
bic r0, r0, #(1 << 12)
str r0, [r1, #0x6C]
-
+
// CAS
ldr r0, [r1, #0x70]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x70]
-
+
// RAS
ldr r0, [r1, #0x74]
bic r0, r0, #(1 << 2)
str r0, [r1, #0x74]
-
+
// CS2 (CSD0)
ldr r0, [r1, #0x7C]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x7C]
-
+
// DQM3
ldr r0, [r1, #0x84]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x84]
-
+
// DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
ldr r2, =22 // (0x2E0 - 0x288) / 4 = 22
pad_loop:
MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
MAX_PARAM1: .word 0x00302154
CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
-ESDCTL_BASE_W: .word ESDCTL_BASE
M3IF_BASE_W: .word M3IF_BASE
-SDRAM_PARAM1_DDR: .word 0x4
-SDRAM_PARAM1_SDR: .word 0x0
-SDRAM_PARAM2_DDR: .word 0x80000F00
-SDRAM_PARAM2_SDR: .word 0x80000400
-SDRAM_PARAM3_DDR: .word 0x00100000
-SDRAM_PARAM3_SDR: .word 0x0
-SDRAM_PARAM4_X32: .word 0x00010000
-SDRAM_PARAM4_X16: .word 0x0
-SDRAM_0x55555555: .word 0x55555555
-SDRAM_0xAAAAAAAA: .word 0xAAAAAAAA
-SDRAM_0x92100000: .word 0x92100000
-SDRAM_0xA2100000: .word 0xA2100000
-SDRAM_0xB2100000: .word 0xB2100000
-SDRAM_0x82116080: .word 0x82116080
-SDRAM_0x0075E73A: .word 0x0075E73A
WEIM_CTRL_CS0_W: .word WEIM_CTRL_CS0
CS0_CSCRU_0x11414C80: .word 0x11414C80
CS0_CSCRL_0x30000D03: .word 0x30000D03
CS0_CSCRA_0x00310800: .word 0x00310800
IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR
-CCM_PDR0_532_133_66_W: .word PDR0_532_133_66
-MPCTL_PARAM_532_W: .word MPCTL_PARAM_532
+#ifdef ARM_399MHZ
+CCM_PDR0_W: .word PDR0_399_133_66
+MPCTL_PARAM_W: .word MPCTL_PARAM_399
+#endif
+#ifdef ARM_532MHZ
+CCM_PDR0_W: .word PDR0_532_133_66
+MPCTL_PARAM_W: .word MPCTL_PARAM_532
+#endif
+
MPCTL_PARAM_532_27_W: .word MPCTL_PARAM_532_27
CCM_PDR1_0x49FCFE7F: .word 0x49FCFE7F
CCM_UPCTL_PARAM_240: .word UPCTL_PARAM_240
projects / karo-tx-redboot.git / blobdiff