//==========================================================================
//
-// soc_misc.c
+// soc_misc.c
//
-// HAL misc board support code
+// HAL misc board support code
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
#include <pkgconf/system.h>
#include CYGBLD_HAL_PLATFORM_H
-#include <cyg/infra/cyg_type.h> // base types
-#include <cyg/infra/cyg_trac.h> // tracing macros
-#include <cyg/infra/cyg_ass.h> // assertion macros
+#include <cyg/infra/cyg_type.h> // base types
+#include <cyg/infra/cyg_trac.h> // tracing macros
+#include <cyg/infra/cyg_ass.h> // assertion macros
-#include <cyg/hal/hal_misc.h> // Size constants
-#include <cyg/hal/hal_io.h> // IO macros
-#include <cyg/hal/hal_arch.h> // Register state info
+#include <cyg/hal/hal_misc.h> // Size constants
+#include <cyg/hal/hal_io.h> // IO macros
+#include <cyg/hal/hal_arch.h> // Register state info
#include <cyg/hal/hal_diag.h>
-#include <cyg/hal/hal_intr.h> // Interrupt names
-#include <cyg/hal/hal_cache.h> // Cache control
-#include <cyg/hal/hal_soc.h> // Hardware definitions
-#include <cyg/hal/hal_mm.h> // MMap table definitions
+#include <cyg/hal/hal_intr.h> // Interrupt names
+#include <cyg/hal/hal_cache.h> // Cache control
+#include <cyg/hal/hal_soc.h> // Hardware definitions
+#include <cyg/hal/hal_mm.h> // MMap table definitions
-#include <cyg/infra/diag.h> // diag_printf
+#include <cyg/infra/diag.h> // diag_printf
+#include <cyg/io/imx_nfc.h>
// Most initialization has already been done before we get here.
// All we do here is set up the interrupt environment.
externC void plf_hardware_init(void);
int _mxc_boot, _mxc_fis;
-#define IIM_PROD_REV_SH 3
-#define IIM_PROD_REV_LEN 5
-#define IIM_SREV_REV_SH 4
-#define IIM_SREV_REV_LEN 4
-#define PROD_SIGNATURE_MX37 0x1
+#define IIM_PROD_REV_SH 3
+#define IIM_PROD_REV_LEN 5
+#define IIM_SREV_REV_SH 4
+#define IIM_SREV_REV_LEN 4
+#define PROD_SIGNATURE_MX37 0x1
#define PROD_SIGNATURE_SUPPORTED PROD_SIGNATURE_MX37
-#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
-#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
+#define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
+#define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
/*
* System_rev will have the following format
*/
static int read_system_rev(void)
{
- int val;
+ int val;
- val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
+ val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
- system_rev = 0x37 << PART_NUMBER_OFFSET; /* For MX37 Platform*/
+ system_rev = 0x37 << PART_NUMBER_OFFSET; /* For MX37 Platform*/
- /* Now trying to retrieve the silicon rev from IIM's SREV register */
- return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
+ /* Now trying to retrieve the silicon rev from IIM's SREV register */
+ return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
}
extern nfc_setup_func_t *nfc_setup;
unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
- unsigned int is_mlc, unsigned int num_of_chips);
+ unsigned int is_mlc, unsigned int num_of_chips);
void hal_hardware_init(void)
{
- volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
- volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
- volatile unsigned int sbmr;
- int bt_mem_type = 0, bt_mem_control = 0;
- int ver = read_system_rev();
- unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
-
- switch (*fis_addr) {
- case FROM_MMC_FLASH:
- _mxc_fis = FROM_MMC_FLASH;
- break;
- case FROM_NAND_FLASH:
- _mxc_fis = FROM_NAND_FLASH;
- break;
- default:
- sbmr = readl(SRC_BASE_ADDR + 0x4);
- bt_mem_control = sbmr & 0x3;
- bt_mem_type = (sbmr & 0x180) >> 7;
- if (bt_mem_control == 0x3) {
- if (bt_mem_type == 0) {
- _mxc_fis = FROM_MMC_FLASH;
- _mxc_boot = FROM_MMC_FLASH;
- } else if (bt_mem_type == 3) {
- _mxc_fis = FROM_SPI_NOR_FLASH;
- _mxc_boot = FROM_SPI_NOR_FLASH;
- }
- } else if (bt_mem_control == 0x1) {
- _mxc_fis = FROM_NAND_FLASH;
- _mxc_boot = FROM_NAND_FLASH;
- }
- }
-
- find_correct_chip = ver;
-
- if (ver != CHIP_VERSION_NONE) {
- /* Valid product revision found. Check actual silicon rev and
- * NOT use the version from the ROM code. */
- if (((ver >> 4) & 0xF) == 0x0) {
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '0';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- } else if (((ver >> 4) & 0xF) == 0x1) {
- HAL_PLATFORM_EXTRA[5] = '1';
- HAL_PLATFORM_EXTRA[7] = '1';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- } else {
- HAL_PLATFORM_EXTRA[5] = 'x';
- HAL_PLATFORM_EXTRA[7] = 'x';
- system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
- system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
- find_correct_chip = CHIP_VERSION_UNKNOWN;
- }
- }
-
- if ((esdmisc & 0x4) == 0) {
- HAL_PLATFORM_EXTRA[14] = 'S';
- }
- if ((esdctl0 & 0x30000) != 0x20000) {
- HAL_PLATFORM_EXTRA[11] = '1';
- HAL_PLATFORM_EXTRA[12] = '6';
- }
-
- // Enable caches
- HAL_ICACHE_ENABLE();
- HAL_DCACHE_ENABLE();
-
- // enable EPIT and start it with 32KHz input clock
- writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
-
- // make sure reset is complete
- while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
- }
-
- writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
- writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
-
- writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
-
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- // increase the WDOG timeout value to the max
- writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
- }
-
- // Perform any platform specific initializations
- plf_hardware_init();
-
- // Set up eCos/ROM interfaces
- hal_if_init();
-
- nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+ volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
+ volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
+ volatile unsigned int sbmr;
+ int bt_mem_type = 0, bt_mem_control = 0;
+ int ver = read_system_rev();
+ unsigned int *fis_addr = (unsigned int *)IRAM_BASE_ADDR;
+
+ switch (*fis_addr) {
+ case FROM_MMC_FLASH:
+ _mxc_fis = FROM_MMC_FLASH;
+ break;
+ case FROM_NAND_FLASH:
+ _mxc_fis = FROM_NAND_FLASH;
+ break;
+ default:
+ sbmr = readl(SRC_BASE_ADDR + 0x4);
+ bt_mem_control = sbmr & 0x3;
+ bt_mem_type = (sbmr & 0x180) >> 7;
+ if (bt_mem_control == 0x3) {
+ if (bt_mem_type == 0) {
+ _mxc_fis = FROM_MMC_FLASH;
+ _mxc_boot = FROM_MMC_FLASH;
+ } else if (bt_mem_type == 3) {
+ _mxc_fis = FROM_SPI_NOR_FLASH;
+ _mxc_boot = FROM_SPI_NOR_FLASH;
+ }
+ } else if (bt_mem_control == 0x1) {
+ _mxc_fis = FROM_NAND_FLASH;
+ _mxc_boot = FROM_NAND_FLASH;
+ }
+ }
+
+ find_correct_chip = ver;
+
+ if (ver != CHIP_VERSION_NONE) {
+ /* Valid product revision found. Check actual silicon rev and
+ * NOT use the version from the ROM code. */
+ if (((ver >> 4) & 0xF) == 0x0) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '0';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else if (((ver >> 4) & 0xF) == 0x1) {
+ HAL_PLATFORM_EXTRA[5] = '1';
+ HAL_PLATFORM_EXTRA[7] = '1';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ } else {
+ HAL_PLATFORM_EXTRA[5] = 'x';
+ HAL_PLATFORM_EXTRA[7] = 'x';
+ system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/
+ system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/
+ find_correct_chip = CHIP_VERSION_UNKNOWN;
+ }
+ }
+
+ if ((esdmisc & 0x4) == 0) {
+ HAL_PLATFORM_EXTRA[14] = 'S';
+ }
+ if ((esdctl0 & 0x30000) != 0x20000) {
+ HAL_PLATFORM_EXTRA[11] = '1';
+ HAL_PLATFORM_EXTRA[12] = '6';
+ }
+
+ // Enable caches
+ HAL_ICACHE_ENABLE();
+ HAL_DCACHE_ENABLE();
+
+ // enable EPIT and start it with 32KHz input clock
+ writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+ // make sure reset is complete
+ while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+ }
+
+ writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+ writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+ writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
+
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ // increase the WDOG timeout value to the max
+ writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+ }
+
+ // Perform any platform specific initializations
+ plf_hardware_init();
+
+ // Set up eCos/ROM interfaces
+ hal_if_init();
+
+ nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
}
// -------------------------------------------------------------------------
// This routine is called during a clock interrupt.
// Define this if you want to ensure that the clock is perfect (i.e. does
-// not drift). One reason to leave it turned off is that it costs some
+// not drift). One reason to leave it turned off is that it costs some
// us per system clock interrupt for this maintenance.
#undef COMPENSATE_FOR_CLOCK_DRIFT
// Note: The "contract" for this function is that the value is the number
// of hardware clocks that have happened since the last interrupt (i.e.
-// when it was reset). This value is used to measure interrupt latencies.
+// when it was reset). This value is used to measure interrupt latencies.
// However, since the hardware counter runs freely, this routine computes
// the difference between the current clock period and the number of hardware
// ticks left before the next timer interrupt.
unsigned int hal_timer_count(void)
{
- return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+ return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
}
-#define WDT_MAGIC_1 0x5555
-#define WDT_MAGIC_2 0xAAAA
-#define MXC_WDT_WSR 0x2
+#define WDT_MAGIC_1 0x5555
+#define WDT_MAGIC_2 0xAAAA
+#define MXC_WDT_WSR 0x2
unsigned int i2c_base_addr[] = {
- I2C_BASE_ADDR,
- I2C2_BASE_ADDR,
- I2C3_BASE_ADDR
+ I2C_BASE_ADDR,
+ I2C2_BASE_ADDR,
+ I2C3_BASE_ADDR
};
unsigned int i2c_num = 3;
//
void hal_delay_us(unsigned int usecs)
{
- /*
- * This causes overflow.
- * unsigned int delayCount = (usecs * 32768) / 1000000;
- * So use the following one instead
- */
- unsigned int delayCount = (usecs * 512) / 15625;
+ /*
+ * This causes overflow.
+ * unsigned int delayCount = (usecs * 32768) / 1000000;
+ * So use the following one instead
+ */
+ unsigned int delayCount = (usecs * 512) / 15625;
+ static unsigned int led_on;
- if (delayCount == 0) {
- return;
- }
+ if (delayCount == 0) {
+ return;
+ }
- // issue the service sequence instructions
- if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
- writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
- writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
- }
+ // issue the service sequence instructions
+ if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+ writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+ }
- writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+ writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
- writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+ writel(delayCount, EPIT_BASE_ADDR + EPITLR);
- while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+ while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+
+ if ((++led_on % 3000) == 0)
+ BOARD_DEBUG_LED(0);
}
// -------------------------------------------------------------------------
-// This routine is called to respond to a hardware interrupt (IRQ). It
+// This routine is called to respond to a hardware interrupt (IRQ). It
// should interrogate the hardware and return the IRQ vector number.
int hal_IRQ_handler(void)
{
#ifdef HAL_EXTENDED_IRQ_HANDLER
- cyg_uint32 index;
+ cyg_uint32 index;
- // Use platform specific IRQ handler, if defined
- // Note: this macro should do a 'return' with the appropriate
- // interrupt number if such an extended interrupt exists. The
- // assumption is that the line after the macro starts 'normal' processing.
- HAL_EXTENDED_IRQ_HANDLER(index);
+ // Use platform specific IRQ handler, if defined
+ // Note: this macro should do a 'return' with the appropriate
+ // interrupt number if such an extended interrupt exists. The
+ // assumption is that the line after the macro starts 'normal' processing.
+ HAL_EXTENDED_IRQ_HANDLER(index);
#endif
- return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+ return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
}
//
void hal_interrupt_mask(int vector)
{
-// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+// diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_MASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_MASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_MASK(vector);
#endif
}
void hal_interrupt_unmask(int vector)
{
-// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+// diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_UNMASK(vector);
#endif
}
void hal_interrupt_acknowledge(int vector)
{
-// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+// diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
#endif
}
{
#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
- // Use platform specific handling, if defined
- // Note: this macro should do a 'return' for "extended" values of 'vector'
- // Normal vectors are handled by code subsequent to the macro call.
- HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+ // Use platform specific handling, if defined
+ // Note: this macro should do a 'return' for "extended" values of 'vector'
+ // Normal vectors are handled by code subsequent to the macro call.
+ HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
#endif
- // Interrupt priorities are not configurable.
+ // Interrupt priorities are not configurable.
}
-unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+ unsigned int is_mlc, unsigned int num_of_chips)
{
- return 0x20; // NFC version 2
+ return MXC_NFC_V2; // NFC version 2
}
static void check_correct_chip(void)
{
- if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
- diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
- diag_printf("Assuming chip version=0x%x\n", system_rev);
- } else if (find_correct_chip == CHIP_VERSION_NONE) {
- diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
- }
+ if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+ diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
+ diag_printf("Assuming chip version=0x%x\n", system_rev);
+ } else if (find_correct_chip == CHIP_VERSION_NONE) {
+ diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+ }
}
RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);
projects / karo-tx-redboot.git / blobdiff