//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
-#define REMOVE_THIS_CRAP
-//#define BORKED
-#define USE_DCD
-//#define USE_LED
-//#define MX51_3STACK
-
#include <pkgconf/system.h> // System-wide configuration info
#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
#define TX51_NAND_PAGE_SIZE 2048
#define TX51_NAND_BLKS_PER_PAGE 64
-#ifndef MX51_3STACK
-#define DEBUG_LED_BIT 10
-#define LED_GPIO_BASE GPIO4_BASE_ADDR
-#define LED_MUX_OFFSET 0x1d0
-#define LED_MUX_MODE 0x13
-#else
#define DEBUG_LED_BIT 0
#define LED_GPIO_BASE GPIO1_BASE_ADDR
#define LED_MUX_OFFSET 0x3ac
#define LED_MUX_MODE 0x11
-#endif
#define LED_ON LED_CTRL #1
#define LED_OFF LED_CTRL #0
// This macro represents the initial startup code for the platform
.macro _platform_setup1
-#ifndef BORKED
KARO_TX51_SETUP_START:
mrs r0, CPSR
mov r0, #0x1f
.align 5
10:
LED_BLINK #3
-#endif // BORKED
.endm @ _platform_setup1
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/* Switch peripheral to PLL 2 */
ldr r1, CCM_CBCDR_VAL1
str r1, [r0, #CLKCTL_CBCDR]
+ /* Use lp_apm (24MHz) source for perclk */
ldr r1, CCM_CBCMR_VAL2
str r1, [r0, #CLKCTL_CBCMR]
str r1, [r0, #CLKCTL_CCSR]
/* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
- ldr r1, CCM_CBCMR_VAL2
- str r1, [r0, #CLKCTL_CBCMR]
@ ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
ldr r1, CCM_CBCDR_VAL3
-
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
str r1, [r0, #CLKCTL_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, CCM_VAL_0xA5A2A020
+ ldr r1, CCM_CSCMR1_VAL
str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, CCM_VAL_0x00C30321
+ ldr r1, CCM_CSCDR1_VAL
str r1, [r0, #CLKCTL_CSCDR1]
/* make sure divider effective */
/* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
ldr r0, M4IF_FBPM0_VAL
str r0, [r1, #M4IF_FBPM0]
+
+ ldr r0, M4IF_FPWC_VAL
+ str r0, [r1, #M4IF_FPWC]
.endm /* init_m4if */
.macro setup_sdram
- cmp r11, #0x10 // r11 contains the silicon rev
- bls skip_setup
#if 0
- /* Decrease the DRAM SDCLK to HIGH Drive strength */
- ldr r0, =IOMUXC_BASE_ADDR
- ldr r1, =0x000000e5
- str r1, [r0, #0x4b8]
- /* Change the delay line configuration */
- ldr r0, =ESDCTL_BASE_ADDR
- ldr r1, =0x00f49400
- str r1, [r0, #ESDCTL_ESDCDLY1]
- ldr r1, =0x00f49a00
- str r1, [r0, #ESDCTL_ESDCDLY2]
- ldr r1, =0x00f49100
- str r1, [r0, #ESDCTL_ESDCDLY3]
- ldr r1, =0x00f48900
- str r1, [r0, #ESDCTL_ESDCDLY4]
- ldr r1, =0x00f49400
- str r1, [r0, #ESDCTL_ESDCDLY5]
+ cmp r11, #0x10 // r11 contains the silicon rev
+ bls skip_setup
+ /* Decrease the DRAM SDCLK pads to HIGH Drive strength */
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x000000e5
+ str r1, [r0, #0x4b8]
+ /* Change the delay line configuration */
+ ldr r0, =ESDCTL_BASE_ADDR
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY1]
+ ldr r1, =0x00f49a00
+ str r1, [r0, #ESDCTL_ESDCDLY2]
+ ldr r1, =0x00f49100
+ str r1, [r0, #ESDCTL_ESDCDLY3]
+ ldr r1, =0x00f48900
+ str r1, [r0, #ESDCTL_ESDCDLY4]
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY5]
#endif
skip_setup:
.endm
#define RALAT 1
#define LHD 0
-#define RA_BITS 2 /* row addr bits - 11 */
-#define CA_BITS 2 /* 0-2: col addr bits - 8 3: rsrvd */
+#if SDRAM_SIZE <= SZ_128M
+#define RA_BITS (13 - 11) /* row addr bits - 11 */
+#else
+#define RA_BITS (14 - 11) /* row addr bits - 11 */
+#endif
+
+#define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */
#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
#define SRT 0 /* 0: disabled *: 1: self refr. ... */
#define PWDT 0 /* 0: disabled 1: precharge pwdn
2: pwdn after 64 clocks 3: pwdn after 128 clocks */
-#define ESDCTL0_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
+#define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
(DSIZ << 16) | (SRT << 14) | (PWDT << 12))
-#define tRFC 17 /* clks - 1 (0..15) */ // 17
-#define tXSR 19 /* clks - 1 (0..15) */ // 19
-#define tXP 0 /* clks - 1 (0..7) */ // N/A
-#define tWTR 0 /* clks - 1 (0..1) */ // N/A
-#define tRP 1 /* clks - 2 (0..3) */ // 1
-#define tMRD 1 /* clks - 1 (0..3) */ // 1
-#define tWR 0 /* clks - 2 (0..1) */ // 0
-#define tRAS 5 /* clks - 1 (0..15) */ // 5
-#define tRRD 1 /* clks - 1 (0..3) */ // 1
-#define tRCD 2 /* clks - 1 (0..7) */ // 2
-#define tRC 8 /* 0: 20 *: clks - 1 (0..15) */ // 8
-
-#define ESDCFG0_VAL ((((tRFC) - 10) << 28) | ((tXSR) << 24) | ((tXP) << 21) | \
- ((tWTR) << 20) | ((tRP) << 18) | ((tMRD) << 16) | \
- ((tRAS) << 12) | ((tRRD) << 10) | ((tWR) << 7) | \
- ((tRCD) << 4) | ((tRC) << 0))
+#define SDRAM_CLK 200
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+ .macro CK_VAL, name, clks, offs
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .set \name, \clks - \offs
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs
+ .endif
+ .endm
+
+#if SDRAM_SIZE <= SZ_128M
+/* MT46H32M32LF-6 */
+NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */
+NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */
+NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
+NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
+#else
+/* MT46H64M32LF-5 or -6 */
+NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */
+NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */
+CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
+NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
+#endif
+
+#define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
+ (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \
+ (tRCD << 4) | (tRC << 0))
+/*
+ 0x70655427
+*/
#define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
#define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
#define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
.long dcd_data
app_dest_ptr:
#ifndef RAM_BANK1_SIZE
- .long RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
+ .long RAM_BANK0_BASE + SDRAM_SIZE - REDBOOT_OFFSET
#else
.long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
#endif
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
- DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL0_VAL)
- DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG0_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG_VAL)
+#ifdef RAM_BANK1_SIZE
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, ESDCTL_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, ESDCFG_VAL)
+#endif
DCDGEN(4, ESDCTL_BASE_ADDR + 0x34, 0x00020000 | ((RALAT & 0x3) << 29))
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL)
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
SRC_BASE_ADDR_W: .long SRC_BASE_ADDR
WDOG_BASE_ADDR_W: .long WDOG_BASE_ADDR
AIPS1_PARAM: .word 0x77777777
-M4IF_M4IF4_VAL: .word 0x00000203
-M4IF_FIDBP_VAL: .word 0x00000a01
-M4IF_FBPM0_VAL: .word 0x00000404
+M4IF_FBPM0_VAL: .word 0x00000103
+M4IF_M4IF4_VAL: .word 0x00230185
+M4IF_FPWC_VAL: .word 0x00240126
MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
CCM_CBCDR_VAL1: .word 0x19239145
CCM_CBCDR_VAL2: .word 0x13239145
-CCM_CBCDR_VAL3: .word 0x61E35100
+#if SDRAM_CLK == 200
+CCM_CBCDR_VAL3: .word 0x59E35100
+#else
+CCM_CBCDR_VAL3: .word 0x21E35100
+#endif
CCM_CBCMR_VAL1: .word 0x000010C0
CCM_CBCMR_VAL2: .word 0x000020C0
+CCM_CSCMR1_VAL: .word 0xA5A2A020
+CCM_CSCDR1_VAL: .word 0x00C30321
BASE_ADDR_PLL1: .long PLL1_BASE_ADDR
BASE_ADDR_PLL2: .long PLL2_BASE_ADDR
BASE_ADDR_PLL3: .long PLL3_BASE_ADDR
-//PLL_VAL_0x222: .word 0x222
-//PLL_VAL_0x232: .word 0x232
PLL_VAL_0x1232: .word 0x1232
W_DP_OP_800: .word DP_OP_800
W_DP_MFD_800: .word DP_MFD_800
W_DP_MFN_216: .word DP_MFN_216
PLATFORM_CLOCK_DIV: .word 0x00000124
-#ifdef REMOVE_THIS_CRAP
-CCM_VAL_0xA5A2A020: .word 0xA5A2A020
-CCM_VAL_0x00C30321: .word 0x00C30321
-#endif
-
/*----------------------------------------------------------------------*/
/* end of hal_platform_setup.h */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
projects / karo-tx-redboot.git / blobdiff