TX51 Release 2011-07-27

[karo-tx-redboot.git] / packages / hal / arm / mx51 / karo / v1_0 / include / hal_platform_setup.h

diff --git a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
index 60117ce3c34a3da7c4100deba39ad443546e897c..ca4d18b9929bacf76c1910c238a3e31987defed3 100644 (file)
--- a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
@@ -50,6 +50,9 @@
 #include <cyg/hal/karo_tx51.h>                 // Platform specific hardware definitions
 #include CYGHWR_MEMORY_LAYOUT_H
 
+#define CPU_CLK                                CYGNUM_HAL_ARM_TX51_CPU_CLK
+#define SDRAM_CLK                      CYGNUM_HAL_ARM_TX51_SDRAM_CLK
+
 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
 #define PLATFORM_SETUP1 _platform_setup1
 #define CYGHWR_HAL_ARM_HAS_MMU
@@ -192,6 +195,7 @@ Normal_Boot_Continue:
  * Note:
  *     IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
  */
+
 STACK_Setup:
        @ Set up a stack [for calling C code]
        ldr     r1, =__startup_stack
@@ -296,7 +300,13 @@ osc_ok:
        mov     r1, #0x4
        str     r1, [r0, #CLKCTL_CCSR]
 
+#if CPU_CLK == 800
        setup_pll PLL1, 800
+#elif CPU_CLK == 600
+       setup_pll PLL1, 600
+#else
+#error Bad CPU clock
+#endif
        setup_pll PLL3, 665
 
        /* Switch peripheral to PLL 3 */
@@ -487,8 +497,6 @@ _KARO_CECFG_END:
 #define ESDCTL_VAL     (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
                         (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
 
-#define SDRAM_CLK      CYGNUM_HAL_ARM_TX51_SDRAM_CLK
-
 #define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)
 
        .macro          CK_VAL, name, clks, offs
@@ -603,10 +611,33 @@ M4IF_FPWC_VAL:            .word   0x00240126
 MXC_REDBOOT_ROM_START: .long   SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
 CCM_CBCDR_VAL1:                .word   0x19239145
 CCM_CBCDR_VAL2:                .word   0x13239145
+#if (CPU_CLK % SDRAM_CLK == 0)
+CCM_CBCDR_VAL3:                .word   (((CPU_CLK + SDRAM_CLK - 1) / SDRAM_CLK - 1) << 27) | (1 << 30) | 0x01e35100
+#else
+CCM_CBCDR_VAL3:                .word   0x01e35100
+#endif
+#if 0
+
 #if SDRAM_CLK == 200
+#if CPU_CLK == 800
 CCM_CBCDR_VAL3:                .word   0x59E35100
+#elif CPU_CLK == 600
+CCM_CBCDR_VAL3:                .word   0x51E35100
 #else
+#error Bad CPU_CLK
+#endif
+#elif SDRAM_CLK == 166
+#if CPU_CLK == 800
 CCM_CBCDR_VAL3:                .word   0x01E35100
+#elif CPU_CLK == 600
+CCM_CBCDR_VAL3:                .word   0x01E35100
+#else
+#error Bad CPU_CLK
+#endif
+#else
+#error Bad SDRAM_CLK
+#endif
+
 #endif
 CCM_CBCMR_VAL1:                .word   0x000010C0
 CCM_CBCMR_VAL2:                .word   0x000020C0
@@ -622,6 +653,9 @@ W_DP_MFN_800:               .word   DP_MFN_800
 W_DP_OP_700:           .word   DP_OP_700
 W_DP_MFD_700:          .word   DP_MFD_700
 W_DP_MFN_700:          .word   DP_MFN_700
+W_DP_OP_600:           .word   DP_OP_600
+W_DP_MFD_600:          .word   DP_MFD_600
+W_DP_MFN_600:          .word   DP_MFN_600
 W_DP_OP_400:           .word   DP_OP_400
 W_DP_MFD_400:          .word   DP_MFD_400
 W_DP_MFN_400:          .word   DP_MFN_400