unsigned int system_rev = CHIP_REV_1_0;
static int find_correct_chip;
-static int _reset_reason;
-
#define SBMR_BT_MEM_CTL_SHIFT 0
#define SBMR_BT_MEM_CTL_MASK (3 << SBMR_BT_MEM_CTL_SHIFT)
#define SBMR_BT_MEM_CTL(r) (((r) & SBMR_BT_MEM_CTL_MASK) >> SBMR_BT_MEM_CTL_SHIFT)
_mxc_fis = FROM_NAND_FLASH;
#endif
- _reset_reason = readl(SRC_BASE_ADDR + 0x8);
-
find_correct_chip = ver;
if (ver != CHIP_VERSION_NONE) {
static void show_sys_info(void)
{
- unsigned int sbmr = readl(SRC_BASE_ADDR + 0x4);
+ cyg_uint32 sbmr = readl(SRC_BASE_ADDR + 0x4);
+ cyg_uint32 srsr = readl(SRC_BASE_ADDR + 0x8);
const char *dlm = "";
if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
diag_printf("Reset reason: ");
- if (_reset_reason & (1 << 0)) {
+ if (srsr & (1 << 0)) {
diag_printf("%sPOWER_ON", dlm);
dlm = " | ";
}
- if (_reset_reason & (1 << 2)) {
+ if (srsr & (1 << 2)) {
diag_printf("%sCSU", dlm);
dlm = " | ";
}
- if (_reset_reason & (1 << 3)) {
+ if (srsr & (1 << 3)) {
diag_printf("%sUSER", dlm);
dlm = " | ";
}
- if (_reset_reason & (1 << 4)) {
+ if (srsr & (1 << 4)) {
CYG_WORD16 wrsr;
HAL_READ_UINT16(WDOG_BASE_ADDR + 4, wrsr);
- if (wrsr & 0x01) {
+ if (wrsr & (1 << 0)) {
diag_printf("%sSOFT", dlm);
dlm = " | ";
}
- if (wrsr & 0x10) {
+ if (wrsr & (1 << 1)) {
diag_printf("%sWATCHDOG", dlm);
dlm = " | ";
}
}
- if (_reset_reason & (1 << 5)) {
+ if (srsr & (1 << 5)) {
diag_printf("%sJTAG_HW", dlm);
dlm = " | ";
}
- if (_reset_reason & (1 << 6)) {
+ if (srsr & (1 << 6)) {
diag_printf("%sJTAG_SW", dlm);
dlm = " | ";
}
- if (_reset_reason & (1 << 16)) {
+ if (srsr & (1 << 16)) {
diag_printf("%sWARM BOOT", dlm);
dlm = " | ";
}
if (*dlm == '\0') {
- diag_printf("UNKNOWN: %08x\n", _reset_reason);
+ diag_printf("UNKNOWN: %08x\n", srsr);
} else {
diag_printf(" RESET\n");
}
diag_printf("Use \"factive [MMC|SPI|NAND]\" to choose fis/fconfig storage\n");
}
- diag_printf("SBMR = 0x%08x\n", readl(SRC_BASE_ADDR + 0x4));
diag_printf("Boot switch: ");
if ((SBMR_BMOD(sbmr)) == 0) {
diag_printf("INTERNAL (GPIO)\n");