X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-redboot.git;a=blobdiff_plain;f=packages%2Fhal%2Farm%2Fmx27%2Fvar%2Fv2_0%2Fsrc%2Fsoc_diag.c;h=d0ae04f4990b505d9833ba538f8ce1217ff15bbf;hp=76865985c44cac0e371524b395948b4aa93d5466;hb=7a4ea0a4d67744fd3f6b5f207d857005fc707b46;hpb=f0c1bd5d9f8457be4a43912a28ca2df207a7f5a4

diff --git a/packages/hal/arm/mx27/var/v2_0/src/soc_diag.c b/packages/hal/arm/mx27/var/v2_0/src/soc_diag.c
index 76865985..d0ae04f4 100644
--- a/packages/hal/arm/mx27/var/v2_0/src/soc_diag.c
+++ b/packages/hal/arm/mx27/var/v2_0/src/soc_diag.c
@@ -155,6 +155,21 @@
 #define MXC_UART_REFFREQ                        (get_peri_clock(PER_CLK1) / 4)
 #endif
 
+/* The Freescale MX27ADS board has two external UART ports which are mapped first
+ * for whatever strange reason.
+ * Other manufacturers may not have these UARTS on their boards but would
+ * as well like to have their serial ports start at '0'!
+ */
+#ifdef CYGPKG_HAL_ARM_MX27ADS
+#define MXC_UART_CHAN_OFFSET	2
+#else
+#define MXC_UART_CHAN_OFFSET	0
+#endif
+
+#ifndef REMOVE_ME
+#include <cyg/infra/diag.h>
+#endif
+
 #if 0
 void
 cyg_hal_plf_comms_init(void)
@@ -531,7 +546,7 @@ void cyg_hal_plf_serial_init(void)
 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
     for (i = 0;  i < NUMOF(channels);  i++) {
         init_serial_channel(&channels[i]);
-        CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i + MXC_UART_CHAN_OFFSET);
         comm = CYGACC_CALL_IF_CONSOLE_PROCS();
         CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
         CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
@@ -545,7 +560,6 @@ void cyg_hal_plf_serial_init(void)
             cyg_hal_plf_serial_putc(&channels[i], '+');
             jjj++;
         }
-        cyg_hal_plf_serial_putc(&channels[i], '+');
     }
 
     // Restore original console
@@ -569,24 +583,31 @@ void cyg_hal_plf_serial_stop(void)
 
 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
+#define MXC_UART1_CHAN		(0 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART2_CHAN		(1 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART3_CHAN		(2 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART4_CHAN		(3 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART5_CHAN		(4 + MXC_UART_CHAN_OFFSET)
+#define MXC_UART6_CHAN		(5 + MXC_UART_CHAN_OFFSET)
+
 #include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
 
-#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART1_CHAN)
 #define __BASE ((void*)SOC_UART1_BASE)
 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART2_CHAN)
 #define __BASE ((void*)SOC_UART2_BASE)
 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART3_CHAN)
 #define __BASE ((void*)SOC_UART3_BASE)
 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 5)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART4_CHAN)
 #define __BASE ((void*)SOC_UART4_BASE)
 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 6)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART5_CHAN)
 #define __BASE ((void*)SOC_UART5_BASE)
 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5
-#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 7)
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == MXC_UART6_CHAN)
 #define __BASE ((void*)SOC_UART6_BASE)
 #define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART6
 #endif