]> git.kernelconcepts.de Git - karo-tx-redboot.git/commitdiff
TX51 pre-release
authorlothar <lothar>
Thu, 14 Jan 2010 16:31:00 +0000 (16:31 +0000)
committerlothar <lothar>
Thu, 14 Jan 2010 16:31:00 +0000 (16:31 +0000)
16 files changed:
packages/devs/eth/arm/tx51karo/v1_0/cdl/tx51_eth_drivers.cdl [new file with mode: 0644]
packages/devs/eth/arm/tx51karo/v1_0/include/devs_eth_arm_tx51.inl [new file with mode: 0644]
packages/devs/eth/fec/v2_0/include/fec.h
packages/devs/eth/fec/v2_0/src/if_fec.c
packages/devs/i2c/arm/mxc/v2_0/src/mxc_i2c.c
packages/devs/ipu/arm/imx/v1_0/cdl/imx_ipu.cdl [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/include/ipu_common.h [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/include/ipuv3d_reg_def.h [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/include/ipuv3ex_reg_def.h [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/include/rgb2ipt_lut.h [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/include/tve_reg_def.h [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/include/xec_dls.h [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/src/ipu_common.c [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/src/ipu_display.c [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/src/ipu_dma.c [new file with mode: 0644]
packages/devs/ipu/arm/imx/v1_0/src/ipu_proc.c [new file with mode: 0644]

diff --git a/packages/devs/eth/arm/tx51karo/v1_0/cdl/tx51_eth_drivers.cdl b/packages/devs/eth/arm/tx51karo/v1_0/cdl/tx51_eth_drivers.cdl
new file mode 100644 (file)
index 0000000..cd55a2a
--- /dev/null
@@ -0,0 +1,89 @@
+# ====================================================================
+#
+#      tx51_eth_drivers.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_DEVS_ETH_ARM_TX51 {
+    display       "Ethernet driver for Ka-Ro electronics TX51 processor module"
+
+    parent        CYGPKG_IO_ETH_DRIVERS
+    active_if    CYGPKG_IO_ETH_DRIVERS
+
+    include_dir   cyg/io
+
+    cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+        display   "FEC ethernet driver required"
+    }
+
+    cdl_component CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0 {
+        display       "Ka-Ro TX51 ethernet port driver"
+        flavor        bool
+        default_value 1
+        description   "
+            This option includes the ethernet device driver for the
+            MXC Board port."
+
+        implements CYGHWR_NET_DRIVER_ETH0
+        implements CYGINT_DEVS_ETH_FEC_REQUIRED
+        requires CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+        requires CYGHWR_DEVS_ETH_PHY_LAN8700
+
+        cdl_option CYGDAT_DEVS_ETH_ARM_MXCBOARD_ETH0_NAME {
+            display       "Device name for the ETH0 ethernet driver"
+            flavor        data
+            default_value {"\"eth0\""}
+            description   "
+                This option sets the name of the ethernet device."
+        }
+
+        cdl_option CYGDAT_DEVS_ETH_ARM_TX51KARO_OUI {
+            display       "OUI part of MAC address"
+            flavor        data
+            active_if     CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+            default_value { "{ 0x00, 0x0c, 0xc6 }" }
+            description   "
+                This option sets OUI part (manufacturer ID) of the MAC address
+                for validation."
+        }
+    }
+
+    define_proc {
+        puts $::cdl_system_header "/***** ethernet driver proc output start *****/"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_FEC_CFG <pkgconf/devs_eth_arm_tx51.h>"
+        puts $::cdl_system_header "#define CYGDAT_DEVS_ETH_FEC_INL <cyg/io/devs_eth_arm_tx51.inl>"
+        puts $::cdl_system_header "/*****  ethernet driver proc output end  *****/"
+    }
+}
diff --git a/packages/devs/eth/arm/tx51karo/v1_0/include/devs_eth_arm_tx51.inl b/packages/devs/eth/arm/tx51karo/v1_0/include/devs_eth_arm_tx51.inl
new file mode 100644 (file)
index 0000000..1576cf1
--- /dev/null
@@ -0,0 +1,500 @@
+//==========================================================================
+//
+//      devs_eth_arm_tx51.inl
+//
+//      Board ethernet I/O definitions.
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_intr.h>                  // CYGNUM_HAL_INTERRUPT_ETHR
+#include <cyg/hal/hal_if.h>
+#include <cyg/hal/mx51_iomux.h>
+
+#ifdef CYGPKG_REDBOOT
+#include <pkgconf/redboot.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <redboot.h>
+#include <flash_config.h>
+#endif
+#endif
+
+
+#ifdef __WANT_DEVS
+
+#ifdef CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+
+static char  mxc_fec_name[] = "mxc_fec";
+
+#define MX51_GPIO_ADDR(bank)                   (GPIO1_BASE_ADDR + (((bank) - 1) << 14))
+#define FEC_POWER_GPIO                                 1, 3
+#define FEC_RESET_GPIO                                 2, 14
+
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+//
+// Verify that the given ESA is valid for this platform
+//
+static char oui[3] = CYGDAT_DEVS_ETH_ARM_TX51KARO_OUI;
+
+bool
+cyg_plf_redboot_esa_validate(unsigned char *val)
+{
+       return (val[0] == oui[0]) && (val[1] == oui[1]) && (val[2] == oui[2]);
+}
+#endif
+
+extern int tx51_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN]);
+
+#define dmb()  asm volatile("dmb" : : : "memory")
+
+static inline void tx51_write_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset, CYG_WORD32 val)
+{
+       if (net_debug) {
+               diag_printf("Changing reg %08x from %08x to %08x\n",
+                                       base_addr + offset, readl(base_addr + offset), val);
+       }
+       HAL_WRITE_UINT32(base_addr + offset, val);
+}
+
+static inline CYG_WORD32 tx51_read_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset)
+{
+       CYG_WORD32 val;
+
+       HAL_READ_UINT32(base_addr + offset, val);
+       if (net_debug) diag_printf("Read %08x from reg %08x\n", val, base_addr + offset);
+       return val;
+}
+
+static inline void tx51_set_reg(CYG_ADDRWORD base_addr, CYG_WORD32 offset,
+                                                               CYG_WORD32 set_mask, CYG_WORD32 clr_mask)
+{
+       CYG_WORD32 val;
+
+       HAL_READ_UINT32(base_addr + offset, val);
+       if (net_debug) diag_printf("Changing reg %08x from %08x to %08x\n", base_addr + offset, val,
+                                  (val & ~clr_mask) | set_mask);
+       val = (val & ~clr_mask) | set_mask;
+       HAL_WRITE_UINT32(base_addr + offset, val);
+}
+
+static struct tx51_gpio_setup {
+       cyg_uint32 iomux_addr;
+       cyg_uint8 on_func;
+       cyg_uint8 off_func;
+       cyg_uint8 grp;
+       cyg_uint8 shift;
+} tx51_fec_gpio_data[] = {
+       /* iomux reg offset,                    func,       gpgrp, */
+       /*                                                                    gpiofn,  gpshift, */
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3,              0x12, 0x13, 3, 19, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_EB2,                0x13, 0x11, 2, 22, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB3,              0x11, 0x13, 3, 11, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_D11,              0x12, 0x13, 3, 29, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_D9,               0x12, 0x13, 3, 31, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_EB3,                0x13, 0x11, 2, 23, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_CS2,                0x13, 0x11, 2, 27, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_CS3,                0x13, 0x11, 2, 28, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_CS4,                0x13, 0x11, 2, 29, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_RDY_INT,  0x11, 0x13, 3, 24, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS7,              0x11, 0x13, 3, 23, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_D8,               0x12, 0x13, 4,  0, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4,              0x12, 0x13, 3, 20, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5,              0x12, 0x13, 3, 21, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6,              0x12, 0x13, 3, 22, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_RB2,              0x11, 0x13, 3, 10, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_CS5,                0x13, 0x11, 2, 30, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2,              0x13, 0x13, 3, 18, },
+};
+
+static struct tx51_gpio_setup tx51_fec_pwr_pins[] = {
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_A20,                0x11, 0x11, 2, 14, }, /* PHY reset */
+       { IOMUXC_SW_MUX_CTL_PAD_GPIO1_3,                0x10, 0x10, 1,  3, }, /* PHY power enable */
+};
+
+static struct tx51_gpio_setup tx51_fec_strap_pins[] = {
+       { IOMUXC_SW_MUX_CTL_PAD_GPIO1_3,                0x10, 0x10, 1,  3, },
+       { IOMUXC_SW_MUX_CTL_PAD_NANDF_D9,               0x12, 0x13, 3, 31, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_EB3,                0x13, 0x11, 2, 23, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_CS2,                0x13, 0x11, 2, 27, },
+       { IOMUXC_SW_MUX_CTL_PAD_EIM_CS3,                0x13, 0x11, 2, 28, },
+};
+
+static inline void tx51_phy_power_off(void)
+{
+       int i;
+
+       if (net_debug) diag_printf("Switching PHY POWER off\n");
+#if 1
+       for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
+
+               if (net_debug) diag_printf("%s: GPIO%d_%d[%d] is %d\n", __FUNCTION__,
+                                                                  gs->grp, gs->shift, i,
+                                                                  gpio_tst_bit(gs->grp, gs->shift));
+       }
+#endif
+       /* deassert all pins attached to the PHY */
+       for (i = 0; i < NUM_ELEMS(tx51_fec_pwr_pins); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_pwr_pins[i];
+
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_DR, 0, 1 << gs->shift);
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_GDIR, 1 << gs->shift, 0);
+       }
+       for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
+#if 0
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_GDIR, 0, 1 << gs->shift);
+#else
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_DR, 0, 1 << gs->shift);
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_GDIR, 1 << gs->shift, 0);
+#endif
+               tx51_write_reg(0, gs->iomux_addr, gs->off_func);
+       }
+       for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
+
+               if (gpio_tst_bit(gs->grp, gs->shift)) {
+                       diag_printf("%s: GPIO%d_%d[%d] is not low\n", __FUNCTION__,
+                                               gs->grp, gs->shift, i);
+               }
+       }
+       if (net_debug) diag_printf("PHY POWER off done\n");
+}
+
+static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
+static bool tx51_fec_init(struct cyg_netdevtab_entry *tab)
+{
+#if 1
+       cyg_bool esa_set;
+       int ok;
+
+       /* Check, whether MAC address is enabled */
+       ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+                                                                        "fec_esa", &esa_set, CONFIG_BOOL);
+#if 0
+ok |= 0;
+//esa_set |= ok;
+net_debug |= 1;
+#endif
+       if (!(ok && esa_set)) {
+               diag_printf("FEC disabled; set fec_esa=true to enable networking\n");
+               return false;
+       }
+#endif
+       return mxc_fec_init(tab);
+}
+
+static void tx51_fec_phy_init(void)
+{
+       int i;
+       int phy_reset_delay = 100;
+       int dbg = net_debug;
+
+#if 0
+       net_debug |= 1;
+#endif
+       /*
+        * make sure the ETH PHY strap pins are pulled to the right voltage
+        * before deasserting the PHY reset GPIO
+        */
+       /* assert FEC PHY Reset (GPIO2_14) and switch PHY power on (GPIO1_3) */
+
+#if 0
+       tx51_phy_power_off();
+#endif
+
+       if (!gpio_tst_bit(1, 3)) {
+               if (0 || net_debug) diag_printf("Switching PHY POWER on\n");
+               gpio_clr_bit(2, 14);
+               gpio_set_bit(1, 3);
+               /* wait for 22ms for LAN8700 to power up */
+               phy_reset_delay = 22000;
+#if 1
+               if (!gpio_tst_bit(1, 3)) {
+                       diag_printf("**Failed to switch PHY power on: GPIO1_PSR[%08lx]=%08x\n",
+                                               MX51_GPIO_ADDR(1) + GPIO_PSR,
+                                               tx51_read_reg(MX51_GPIO_ADDR(1), GPIO_PSR));
+               }
+#endif
+#if 1
+               if (gpio_tst_bit(2, 14)) {
+                       diag_printf("**Failed to assert PHY reset: GPIO2_PSR[%08lx]=%08x\n",
+                                               MX51_GPIO_ADDR(2) + GPIO_PSR,
+                                               tx51_read_reg(MX51_GPIO_ADDR(2), GPIO_PSR));
+               }
+#endif
+       } else {
+               if (0 || net_debug) diag_printf("Asserting PHY RESET\n");
+               gpio_clr_bit(2, 14);
+#if 1
+               if (gpio_tst_bit(2, 14)) {
+                       diag_printf("**Failed to assert PHY reset: GPIO2_PSR[%08lx]=%08x\n",
+                                               MX51_GPIO_ADDR(2) + GPIO_PSR,
+                                               tx51_read_reg(MX51_GPIO_ADDR(2), GPIO_PSR));
+               }
+#endif
+       }
+       for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
+               int j;
+               int strap = 0;
+
+               for (j = 0; j < NUM_ELEMS(tx51_fec_strap_pins); j++) {
+                       struct tx51_gpio_setup *sp = &tx51_fec_strap_pins[j];
+
+                       if (gs->grp == sp->grp && gs->shift == sp->shift) {
+                               strap = 1;
+                               break;
+                       }
+               }
+               if (strap) {
+                       gpio_set_bit(gs->grp, gs->shift);
+                       if (net_debug) diag_printf("Setting GPIO%d_%d[%d] high\n",
+                                                                          gs->grp, gs->shift, i);
+               } else {
+                       gpio_clr_bit(gs->grp, gs->shift);
+                       if (net_debug) diag_printf("Setting GPIO%d_%d[%d] low\n",
+                                                                          gs->grp, gs->shift, i);
+               }
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_GDIR, 1 << gs->shift, 0);
+               tx51_write_reg(0, gs->iomux_addr,
+                                          gs->off_func);
+       }
+#if 1
+       /* configure FEC strap pins to their required values */
+       for (i = 0; i < NUM_ELEMS(tx51_fec_strap_pins); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_strap_pins[i];
+
+               if (net_debug) diag_printf("Asserting GPIO%d_%d\n", gs->grp,
+                                                                  gs->shift);
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_GDIR, 1 << gs->shift, 0);
+               tx51_set_reg(MX51_GPIO_ADDR(gs->grp),
+                                        GPIO_DR, 1 << gs->shift, 0);
+               tx51_write_reg(0, gs->iomux_addr,
+                                          gs->off_func);
+               gpio_set_bit(gs->grp, gs->shift);
+               if (!gpio_tst_bit(gs->grp, gs->shift)) {
+                       diag_printf("**Failed to assert GPIO%d_%d: GPIO%d_PSR[%08lx]=%08x\n",
+                                               gs->grp, gs->shift, gs->grp,
+                                               MX51_GPIO_ADDR(gs->grp) + GPIO_PSR,
+                                               tx51_read_reg(MX51_GPIO_ADDR(gs->grp), GPIO_PSR));
+               }
+       }
+#endif
+       for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
+               int j;
+               int strap = 0;
+
+               for (j = 0; j < NUM_ELEMS(tx51_fec_strap_pins); j++) {
+                       struct tx51_gpio_setup *sp = &tx51_fec_strap_pins[j];
+
+                       if (gs->grp == sp->grp && gs->shift == sp->shift) {
+                               strap = 1;
+                               break;
+                       }
+               }
+               if (strap) {
+                       if (!gpio_tst_bit(gs->grp, gs->shift)) {
+                               diag_printf("GPIO%d_%d[%d] is low instead of high\n",
+                                                       gs->grp, gs->shift, i);
+                       }
+               } else {
+                       if (gpio_tst_bit(gs->grp, gs->shift)) {
+                               diag_printf("GPIO%d_%d[%d] is high instead of low\n",
+                                                       gs->grp, gs->shift, i);
+                       }
+               }
+       }
+       /* wait for 100us according to LAN8700 spec. before ... */
+       HAL_DELAY_US(phy_reset_delay);
+       /* ... deasserting FEC PHY reset */
+       if (0 || net_debug) diag_printf("Releasing PHY RESET\n");
+       gpio_set_bit(2, 14);
+       if (!gpio_tst_bit(2, 14)) {
+               diag_printf("**Failed to release PHY reset\n");
+       }
+
+       /* configure all FEC pins to their required functions */
+       for (i = 0; i < NUM_ELEMS(tx51_fec_gpio_data); i++) {
+               struct tx51_gpio_setup *gs = &tx51_fec_gpio_data[i];
+
+               tx51_write_reg(0, gs->iomux_addr, gs->on_func);
+               HAL_DELAY_US(10000);
+       }
+       net_debug = dbg;
+}
+
+ETH_PHY_REG_LEVEL_ACCESS_FUNS(eth0_phy,
+                                                         tx51_fec_phy_init,
+                                                         mxc_fec_phy_reset,
+                                                         mxc_fec_phy_write,
+                                                         mxc_fec_phy_read);
+
+cyg_bool _tx51_provide_fec_esa(unsigned char *addr)
+{
+       cyg_bool enabled;
+       int ok;
+
+       ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+                                        "fec_esa", &enabled, CONFIG_BOOL);
+       if (ok && enabled) {
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+               cyg_uint8 addr2[ETHER_ADDR_LEN];
+
+               addr[0] = readl(SOC_FEC_MAC_BASE + 0x14);
+               addr[1] = readl(SOC_FEC_MAC_BASE + 0x10);
+               addr[2] = readl(SOC_FEC_MAC_BASE + 0xC);
+               addr[3] = readl(SOC_FEC_MAC_BASE + 0x8);
+               addr[4] = readl(SOC_FEC_MAC_BASE + 0x4);
+               addr[5] = readl(SOC_FEC_MAC_BASE + 0x0);
+
+               if (cyg_plf_redboot_esa_validate(addr)) {
+                       diag_printf("Ethernet FEC MAC address from fuse bank: ");
+                       diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+                                               addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+                       CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+                                                                               "fec_esa_data", addr2, CONFIG_ESA);
+                       if (memcmp(addr, addr2, sizeof(addr)) != 0) {
+                               CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_SET,
+                                                                                       "fec_esa_data", addr, CONFIG_ESA);
+                       }
+#ifdef SOC_MAC_ADDR_LOCK_FUSE
+                       if ((readl(IIM_BASE_ADDR + 0x800 + SOC_MAC_ADDR_FUSE_BANK * 0x400 +
+                                          SOC_MAC_ADDR_LOCK_FUSE * 4) &
+                                SOC_MAC_ADDR_LOCK_BIT) == 0) {
+                               tx51_mac_addr_program(addr);
+                       }
+#endif // SOC_MAC_ADDR_LOCK_FUSE
+                       return true;
+               }
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+
+               CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+                                                                       "fec_esa_data", addr, CONFIG_ESA);
+
+               diag_printf("Ethernet FEC MAC address from fconfig: ");
+               diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+                                       addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+#ifdef CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+               if (cyg_plf_redboot_esa_validate(addr)) {
+                       tx51_mac_addr_program(addr);
+                       return true;
+               }
+
+               diag_printf("** Error: Invalid MAC address: ");
+               diag_printf("%02x:%02x:%02x:%02x:%02x:%02x\n",
+                                       addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
+
+               writel(addr[0], SOC_FEC_MAC_BASE + 0x14);
+               writel(addr[1], SOC_FEC_MAC_BASE + 0x10);
+               writel(addr[2], SOC_FEC_MAC_BASE + 0xC);
+               writel(addr[3], SOC_FEC_MAC_BASE + 0x8);
+               writel(addr[4], SOC_FEC_MAC_BASE + 0x4);
+               writel(addr[5], SOC_FEC_MAC_BASE + 0x0);
+
+#ifdef SOC_MAC_ADDR_LOCK_FUSE
+               if ((readl(IIM_BASE_ADDR + 0x800 + SOC_MAC_ADDR_FUSE_BANK * 0x400 +
+                                  SOC_MAC_ADDR_LOCK_FUSE * 4) &
+                        SOC_MAC_ADDR_LOCK_BIT) == 0) {
+                       diag_printf("Use 'fconfig fec_esa_data' to set the MAC address\n");
+                       return false;
+               } else {
+                       diag_printf("Using MAC address from fconfig\n");
+               }
+#else
+               diag_printf("Using MAC address from fconfig\n");
+#endif // SOC_MAC_ADDR_LOCK_FUSE
+#endif // CYGSEM_REDBOOT_PLF_ESA_VALIDATE
+               return true;
+       }
+       return false;
+}
+
+static mxc_fec_priv_t mxc_fec_private = {
+       .phy = &eth0_phy,                                                         // PHY access routines
+       .provide_esa = _tx51_provide_fec_esa,
+};
+
+ETH_DRV_SC(mxc_fec_sc,
+                  &mxc_fec_private, // Driver specific data
+                  mxc_fec_name,
+                  mxc_fec_start,
+                  mxc_fec_stop,
+                  mxc_fec_control,
+                  mxc_fec_can_send,
+                  mxc_fec_send,
+                  mxc_fec_recv,
+                  mxc_fec_deliver,             // "pseudoDSR" called from fast net thread
+                  mxc_fec_poll,                // poll function, encapsulates ISR and DSR
+                  mxc_fec_int_vector);
+
+NETDEVTAB_ENTRY(mxc_fec_netdev,
+                               mxc_fec_name,
+                               tx51_fec_init,
+                               &mxc_fec_sc);
+#endif
+
+#if defined(CYGPKG_REDBOOT) && defined(CYGSEM_REDBOOT_FLASH_CONFIG)
+RedBoot_config_option("Set FEC network hardware address [MAC]",
+                                         fec_esa,
+                                         ALWAYS_ENABLED, true,
+                                         CONFIG_BOOL, false
+                                        );
+RedBoot_config_option("FEC network hardware address [MAC]",
+                                         fec_esa_data,
+                                         "fec_esa", true,
+                                         CONFIG_ESA, 0
+                                        );
+#endif // CYGPKG_REDBOOT && CYGSEM_REDBOOT_FLASH_CONFIG
+
+#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+// Note that this section *is* active in an application, outside RedBoot,
+// where the above section is not included.
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
+#endif // CYGPKG_DEVS_ETH_ARM_MXCBOARD_ETH0
+
+#endif // __WANT_DEVS
index 36d19b92a648a21042276901c9f7ded73d4b4888..2f3f2a9349dd425295a0679119127b0514a774e6 100644 (file)
@@ -4,7 +4,7 @@
 //
 //      dev/mxc_fec.h
 //
-//             Fast Ethernet MAC controller in i.MXx
+//             Fast Ethernet MAC controller in i.MXx
 //
 //==========================================================================
 //####ECOSGPLCOPYRIGHTBEGIN####
 #include <cyg/infra/cyg_type.h>
 
 #include <cyg/hal/hal_io.h>
+
+#ifdef CYGPKG_DEVS_ETH_PHY
+/* generic PHY device access functions */
+void mxc_fec_phy_init(void);
+void mxc_fec_phy_reset(void);
+bool mxc_fec_phy_read(int reg, int unit, unsigned short *data);
+void mxc_fec_phy_write(int reg, int unit, unsigned short data);
+
+#include <cyg/io/eth_phy.h>
+#endif
+
 /* The defines of event bits */
-#define FEC_EVENT_HBERR        0x80000000
-#define FEC_EVENT_BABR 0x40000000
-#define FEC_EVENT_BABT 0x20000000
-#define FEC_EVENT_GRA  0x10000000
-#define FEC_EVENT_TXF  0x08000000
-#define FEC_EVENT_TXB  0x04000000
-#define FEC_EVENT_RXF  0x02000000
-#define FEC_EVENT_RXB  0x01000000
-#define FEC_EVENT_MII  0x00800000
-#define FEC_EVENT_EBERR        0x00400000
-#define FEC_EVENT_LC   0x00200000
-#define FEC_EVENT_RL   0x00100000
-#define FEC_EVENT_UN   0x00080000
+#define FEC_EVENT_HBERR                0x80000000
+#define FEC_EVENT_BABR         0x40000000
+#define FEC_EVENT_BABT         0x20000000
+#define FEC_EVENT_GRA          0x10000000
+#define FEC_EVENT_TXF          0x08000000
+#define FEC_EVENT_TXB          0x04000000
+#define FEC_EVENT_RXF          0x02000000
+#define FEC_EVENT_RXB          0x01000000
+#define FEC_EVENT_MII          0x00800000
+#define FEC_EVENT_EBERR                0x00400000
+#define FEC_EVENT_LC           0x00200000
+#define FEC_EVENT_RL           0x00100000
+#define FEC_EVENT_UN           0x00080000
 
 #define FEC_EVENT_TX           FEC_EVENT_TXF
 #define FEC_EVENT_TX_ERR       (FEC_EVENT_BABT | FEC_EVENT_LC | FEC_EVENT_RL | FEC_EVENT_UN)
 #define FEC_EVENT_RX           FEC_EVENT_RXF
 #define FEC_EVENT_ERR          (FEC_EVENT_HBERR | FEC_EVENT_EBERR)
 
-#define FEC_RX_FRAMES          ((CYGNUM_IO_ETH_DRIVERS_NUM_PKT/2)+1)
-#define FEC_FRAME_LEN          (1540+4)
+#define FEC_RX_FRAMES          ((CYGNUM_IO_ETH_DRIVERS_NUM_PKT / 2) + 1)
+#define FEC_FRAME_LEN          (1540 + 4)
 
 /* the defines to active transmit or receive frame */
 #define FEC_RX_TX_ACTIVE       0x01000000
 
 /* the defines of Ethernet Control register */
-#define FEC_RESET      0x00000001
-#define FEC_ETHER_EN   0x00000002
+#define FEC_RESET                      0x00000001
+#define FEC_ETHER_EN           0x00000002
 
 /* the defins of MII operation */
-#define FEC_MII_ST     0x40000000
-#define FEC_MII_OP_OFF 28
-#define FEC_MII_OP_MASK 0x03
-#define FEC_MII_OP_RD  0x02
-#define FEC_MII_OP_WR  0x01
-#define FEC_MII_PA_OFF 23
-#define FEC_MII_PA_MASK 0xFF
-#define FEC_MII_RA_OFF 18
-#define FEC_MII_RA_MASK        0xFF
-#define FEC_MII_TA     0x00020000
-#define FEC_MII_DATA_OFF 0
-#define FEC_MII_DATA_MASK 0x0000FFFF
-
-#define FEC_MII_FRAME  ( FEC_MII_ST | FEC_MII_TA )
-#define FEC_MII_OP(x)  ( ((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF )
-#define FEC_MII_PA(pa)  (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF)
-#define FEC_MII_RA(ra) (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF)
-#define FEC_MII_SET_DATA(v) (((v) & FEC_MII_DATA_MASK) << FEC_MII_DATA_OFF)
-#define FEC_MII_GET_DATA(v) (((v) >> FEC_MII_DATA_OFF) & FEC_MII_DATA_MASK )
-#define FEC_MII_READ(pa, ra) ( ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_RD) )|\
-                                       FEC_MII_PA(pa) | FEC_MII_RA(ra) )
-#define FEC_MII_WRITE(pa, ra, v) ( FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_WR)|\
-                               FEC_MII_PA(pa) | FEC_MII_RA(ra) |FEC_MII_SET_DATA(v) )
-
-#define MII_SPEED_SHIFT        1
-#define MII_SPEED_MASK         0x0000003F
-#define MII_SPEED(x)   ( (((((x)+499999)/2500000)&(MII_SPEED_MASK))>>1)<<(MII_SPEED_SHIFT) )
-
-/*the defines of MIB control */
-#define FEC_MIB_DISABLE        0x80000000
-
-/*the defines of Receive Control*/
-#define FEC_RCR_FCE    0x00000020
-#define FEC_RCR_BC_REJ 0x00000010
-#define FEC_RCR_PROM   0x00000008
+#define FEC_MII_ST                     0x40000000
+#define FEC_MII_OP_OFF         28
+#define FEC_MII_OP_MASK                0x03
+#define FEC_MII_OP_RD          0x02
+#define FEC_MII_OP_WR          0x01
+#define FEC_MII_PA_OFF         23
+#define FEC_MII_PA_MASK                0xFF
+#define FEC_MII_RA_OFF         18
+#define FEC_MII_RA_MASK                0xFF
+#define FEC_MII_TA                     0x00020000
+#define FEC_MII_DATA_OFF       0
+#define FEC_MII_DATA_MASK      0x0000FFFF
+
+#define FEC_MII_FRAME          (FEC_MII_ST | FEC_MII_TA)
+#define FEC_MII_OP(x)          (((x) & FEC_MII_OP_MASK) << FEC_MII_OP_OFF)
+#define FEC_MII_PA(pa)         (((pa)& FEC_MII_PA_MASK) << FEC_MII_PA_OFF)
+#define FEC_MII_RA(ra)         (((ra)& FEC_MII_RA_MASK) << FEC_MII_RA_OFF)
+#define FEC_MII_SET_DATA(v)    (((v) & FEC_MII_DATA_MASK) << FEC_MII_DATA_OFF)
+#define FEC_MII_GET_DATA(v)    (((v) >> FEC_MII_DATA_OFF) & FEC_MII_DATA_MASK)
+#define FEC_MII_READ(pa, ra) ((FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_RD)) | \
+                                                               FEC_MII_PA(pa) | FEC_MII_RA(ra))
+#define FEC_MII_WRITE(pa, ra, v) (FEC_MII_FRAME | FEC_MII_OP(FEC_MII_OP_WR) | \
+                                                                       FEC_MII_PA(pa) | FEC_MII_RA(ra) | \
+                                                                       FEC_MII_SET_DATA(v))
+
+#define MII_SPEED_SHIFT                1
+#define MII_SPEED_MASK         0x0000003F
+#define MII_SPEED(x)           ((((((x) + 499999) / 2500000) & MII_SPEED_MASK) >> 1) << MII_SPEED_SHIFT)
+
+/* the defines of MIB control */
+#define FEC_MIB_DISABLE                0x80000000
+
+/* the defines of Receive Control*/
+#define FEC_RCR_FCE                    0x00000020
+#define FEC_RCR_BC_REJ         0x00000010
+#define FEC_RCR_PROM           0x00000008
 #define FEC_RCR_MII_MODE       0x00000004
 
-/*the defines of Transmit Control*/
+/* the defines of Transmit Control*/
 #define FEC_TCR_RFC_PAUSE      0x00000010
 #define FEC_TCR_FDEN           0x00000004
 
-/*the defines of buffer description*/
-#define FEC_BD_RX_NUM  256
-#define FEC_BD_TX_NUM  2
+/* the defines of buffer description*/
+#define FEC_BD_RX_NUM          256
+#define FEC_BD_TX_NUM          2
 
 #ifdef CYGPKG_HAL_ARM_MX25
-/*the defines for MIIGSK */
+/* the defines for MIIGSK */
 
 /* RMII frequency control: 0=50MHz, 1=5MHz */
-#define MIIGSK_CFGR_FRCONT             (1 << 6)
+#define MIIGSK_CFGR_FRCONT                     (1 << 6)
 
 /* loopback mode */
-#define MIIGSK_CFGR_LBMODE             (1 << 4)
+#define MIIGSK_CFGR_LBMODE                     (1 << 4)
 
 /* echo mode */
-#define MIIGSK_CFGR_EMODE              (1 << 3)
+#define MIIGSK_CFGR_EMODE                      (1 << 3)
 
 /* MII gasket mode field */
 #define MIIGSK_CFGR_IF_MODE_MASK       (3 << 0)
 #define MIIGSK_CFGR_IF_MODE_RMII       (1 << 0)
 
 /* reflects MIIGSK Enable bit (RO) */
-#define MIIGSK_ENR_READY               (1 << 2)
+#define MIIGSK_ENR_READY                       (1 << 2)
 
 /* enable MIGSK (set by default) */
-#define MIIGSK_ENR_EN                  (1 << 1)
+#define MIIGSK_ENR_EN                          (1 << 1)
 #endif
 
-typedef struct mxc_fec_reg_s
-{
-               unsigned long res1;
-/*0x004*/      unsigned long eir;      /* Interrupt Event Register */
-/*0x008*/      unsigned long eimr;     /* Interrupt Mask Register */
-               unsigned long res2;
-/*0x010*/      unsigned long rdar;     /* Receive Descriptor Active Register*/
-/*0x014*/      unsigned long tdar;     /* Transmit Descriptor Active Register*/
-               unsigned long res3[3];
-/*0x024*/      unsigned long ecr;      /*Receive Descriptor Active Register*/
-               unsigned long res4[6];
-/*0x040*/      unsigned long mmfr;     /*MII Management Frame Register */
-/*0x044*/      unsigned long mscr;     /*MII Speed Control Register */
-               unsigned long res5[7];
-/*0x064*/      unsigned long mibc;     /*MII Control/Status Register */
-               unsigned long res6[7];
-/*0x084*/      unsigned long rcr;      /*Receive Control Register */
-               unsigned long res7[15];
-/*0x0C4*/      unsigned long tcr;      /*Transmit Control register */
-               unsigned long res8[7];
-/*0x0E4*/      unsigned long palr;     /*Physical Address Low Register*/
-/*0x0E8*/      unsigned long paur;     /*Physical Address High+Type Register*/
-/*0x0EC*/      unsigned long opd;      /*Opcode+Pause Duration */
-               unsigned long res9[10];
-/*0x118*/      unsigned long iaur;     /*Upper 32bits Individual Hash Table*/
-/*0x11c*/      unsigned long ialr;     /*lower 32bits Individual Hash Table*/
-/*0x120*/      unsigned long gaur;     /*Upper 32bits Group Hash Table*/
-/*0x124*/      unsigned long galr;     /*lower 32bits Group Hash Table*/
-               unsigned long res10[7];
-/*0x144*/      unsigned long tfwr;     /*Trasmit FIFO Watermark */
-               unsigned long res11;
-/*0x14c*/      unsigned long frbr;     /*FIFO Receive Bound Register*/
-/*0x150*/      unsigned long frsr;     /*FIFO Receive FIFO Start Registers*/
-               unsigned long res12[11];
-/*0x180*/      unsigned long erdsr;    /*Pointer to Receive Descriptor Ring*/
-/*0x184*/      unsigned long etdsr;    /*Pointer to Transmit Descriptor Ring*/
-/*0x188*/      unsigned long emrbr;    /*Maximum Receive Buffer size*/
+typedef        volatile void mxc_fec_reg_t;
+#define eir                            0x004   /* Interrupt Event Register */
+#define eimr                   0x008   /* Interrupt Mask Register */
+#define rdar                   0x010   /* Receive Descriptor Active Register*/
+#define tdar                   0x014   /* Transmit Descriptor Active Register*/
+#define ecr                            0x024   /*Receive Descriptor Active Register*/
+#define mmfr                   0x040   /*MII Management Frame Register */
+#define mscr                   0x044   /*MII Speed Control Register */
+#define mibc                   0x064   /*MII Control/Status Register */
+#define rcr                            0x084   /*Receive Control Register */
+#define tcr                            0x0C4   /*Transmit Control register */
+#define palr                   0x0E4   /*Physical Address Low Register*/
+#define paur                   0x0E8   /*Physical Address High+Type Register*/
+#define opd                            0x0EC   /*Opcode+Pause Duration */
+#define iaur                   0x118   /*Upper 32bits Individual Hash Table*/
+#define ialr                   0x11c   /*lower 32bits Individual Hash Table*/
+#define gaur                   0x120   /*Upper 32bits Group Hash Table*/
+#define galr                   0x124   /*lower 32bits Group Hash Table*/
+#define tfwr                   0x144   /*Trasmit FIFO Watermark */
+#define frbr                   0x14c   /*FIFO Receive Bound Register*/
+#define frsr                   0x150   /*FIFO Receive FIFO Start Registers*/
+#define erdsr                  0x180   /*Pointer to Receive Descriptor Ring*/
+#define etdsr                  0x184   /*Pointer to Transmit Descriptor Ring*/
+#define emrbr                  0x188   /*Maximum Receive Buffer size*/
 #ifdef CYGPKG_HAL_ARM_MX25
-               unsigned long res13[93];
-/*0x300*/      unsigned short miigsk_cfgr; /* MIIGSK Configuration Register */
-               unsigned short res14[3];
-/*0x308*/      unsigned short miigsk_enr;  /* MIIGSK Enable Register */
+#define miigsk_cfgr            0x300 /* MIIGSK Configuration Register */
+#define miigsk_enr             0x308  /* MIIGSK Enable Register */
 #endif
-} mxc_fec_reg_t;
 
-#define BD_RX_ST_EMPTY 0x8000
-#define BD_RX_ST_WRAP  0x2000
-#define BD_RX_ST_LAST  0x0800
-#define BD_RX_ST_ERRS  0x0037
+#define BD_RX_ST_EMPTY 0x8000
+#define BD_RX_ST_WRAP  0x2000
+#define BD_RX_ST_LAST  0x0800
+#define BD_RX_ST_ERRS  0x0037
 
 #define BD_TX_ST_RDY   0x8000
 #define BD_TX_ST_WRAP  0x2000
-#define BD_TX_ST_LAST          0x0800
-#define BD_TX_ST_TC    0x0400
+#define BD_TX_ST_LAST  0x0800
+#define BD_TX_ST_TC            0x0400
 #define BD_TX_ST_ABC   0x0200
 
 typedef struct mxc_fec_bd_t
@@ -236,8 +232,8 @@ typedef struct mxc_fec_priv_s
 #endif
        unsigned char   tx_busy;        /*0:free, 1:transmitting frame*/
        unsigned char   res[2];
-       unsigned long   status;         /*the status of FEC device:link-status etc.*/
-       unsigned long   tx_key;         /*save the key delivered from send function*/
+       unsigned long   status;         /*the status of FEC device:link-status etc.*/
+       unsigned long   tx_key;         /*save the key delivered from send function*/
        mxc_fec_bd_t   *rx_bd;          /*the receive buffer description ring*/
        mxc_fec_bd_t   *rx_cur;         /*the next recveive buffer description*/
        mxc_fec_bd_t   *tx_bd;          /*the transmit buffer description rign*/
@@ -248,56 +244,56 @@ typedef struct mxc_fec_priv_s
 #define MXC_FEC_PRIVATE(x)     ((mxc_fec_priv_t *)(x)->driver_private)
 
 /*The defines of the status field of mxc_fec_priv_t */
-#define FEC_STATUS_LINK_ON     0x80000000
+#define FEC_STATUS_LINK_ON             0x80000000
 #define FEC_STATUS_FULL_DPLX   0x40000000
-#define FEC_STATUS_AUTO_NEG    0x20000000
-#define FEC_STATUS_100M                0x10000000
+#define FEC_STATUS_AUTO_NEG            0x20000000
+#define FEC_STATUS_100M                        0x10000000
 
 /*The defines about PHY */
 #ifndef FEC_PHY_ADDR
-#define PHY_PORT_ADDR          0x01
+#define PHY_PORT_ADDR                  0x01
 #else
-#define PHY_PORT_ADDR          FEC_PHY_ADDR
+#define PHY_PORT_ADDR                  FEC_PHY_ADDR
 #endif
 
-#define PHY_CTRL_REG           0x00
-#define PHY_CTRL_RESET         0x8000
-#define PHY_CTRL_AUTO_NEG      0x1000
-#define PHY_CTRL_FULL_DPLX     0x0100
-
-#define PHY_STATUS_REG         0x01
-#define PHY_STATUS_LINK_ST     0x0004
-
-#define PHY_IDENTIFY_1         0x02
-#define PHY_IDENTIFY_2         0x03
-#define PHY_ID1_SHIFT          2
-#define PHY_ID1_MASK           0xFFFF
-#define PHY_ID2_SHIFT          8
-#define PHY_ID2_MASK           0xFC00
-#define PHY_MODE_NUM           0x03F0
-#define PHY_REV_NUM            0x000F
-
-#define PHY_DIAG_REG           0x12
-#define PHY_DIAG_DPLX          0x0800
-#define PHY_DIAG_RATE          0x0400
-
-#define PHY_MODE_REG           0x15
-#define PHY_LED_SEL                    0x200
-
-#define PHY_AUTO_NEG_REG       0x5
-#define PHY_AUTO_10BASET       0x20
-#define PHY_AUTO_10BASET_DPLX          0x40
-#define PHY_AUTO_100BASET      0x80
+#define PHY_CTRL_REG                   0x00
+#define PHY_CTRL_RESET                 0x8000
+#define PHY_CTRL_AUTO_NEG              0x1000
+#define PHY_CTRL_FULL_DPLX             0x0100
+
+#define PHY_STATUS_REG                 0x01
+#define PHY_STATUS_LINK_ST             0x0004
+
+#define PHY_IDENTIFY_1                 0x02
+#define PHY_IDENTIFY_2                 0x03
+#define PHY_ID1_SHIFT                  2
+#define PHY_ID1_MASK                   0xFFFF
+#define PHY_ID2_SHIFT                  8
+#define PHY_ID2_MASK                   0xFC00
+#define PHY_MODE_NUM                   0x03F0
+#define PHY_REV_NUM                            0x000F
+
+#define PHY_DIAG_REG                   0x12
+#define PHY_DIAG_DPLX                  0x0800
+#define PHY_DIAG_RATE                  0x0400
+
+#define PHY_MODE_REG                   0x15
+#define PHY_LED_SEL                            0x200
+
+#define PHY_AUTO_NEG_REG               0x5
+#define PHY_AUTO_10BASET               0x20
+#define PHY_AUTO_10BASET_DPLX  0x40
+#define PHY_AUTO_100BASET              0x80
 #define PHY_AUTO_100BASET_DPLX 0x100
 
 #define PHY_AUTO_NEG_EXP_REG   0x6
 #define PHY_AUTO_NEG_NEW_PAGE  0x2
 #define PHY_AUTO_NEG_CAP               0x1
 
-#define PHY_INT_SRC_REG        29
-#define PHY_INT_AUTO_NEG       0x40
-#define FEC_COMMON_TICK        2
-#define FEC_COMMON_TIMEOUT     (1000*1000)
-#define FEC_MII_TICK   2
-#define FEC_MII_TIMEOUT        (1000*1000)
+#define PHY_INT_SRC_REG                        29
+#define PHY_INT_AUTO_NEG               0x40
+#define FEC_COMMON_TICK                        2
+#define FEC_COMMON_TIMEOUT             (1000 * 1000)
+#define FEC_MII_TICK                   2
+#define FEC_MII_TIMEOUT                        (1000 * 1000)
 #endif // _CYGONCE_ETH_FEC_H_
index 5d157e8b4746e61d2258cd18f174aeaa6df5c508..c2b6e61641ae15c30ac96fa8456b084c4fadaa39 100644 (file)
 #include <cyg/io/eth/eth_drv.h>
 #include <cyg/io/eth/netdev.h>
 
-#ifdef CYGPKG_DEVS_ETH_PHY
-/* generic PHY device access functions */
-void mxc_fec_phy_init(void);
-void mxc_fec_phy_reset(void);
-bool mxc_fec_phy_read(int reg, int unit, unsigned short *data);
-void mxc_fec_phy_write(int reg, int unit, unsigned short data);
-
-#include <cyg/io/eth_phy.h>
-#endif
 static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
 
 #include <cyg/io/fec.h>
@@ -100,16 +91,16 @@ static bool mxc_fec_init(struct cyg_netdevtab_entry *tab);
 
 #include <redboot.h>
 
-#include <cyg/hal/hal_mm.h>
+#include <cyg/hal/plf_mmap.h>
 #ifdef CYGSEM_REDBOOT_FLASH_CONFIG
 #include <flash_config.h>
 #endif
 
 
-#define MII_REG_CR          0  /* Control Register                         */
-#define MII_REG_SR          1  /* Status Register                          */
-#define MII_REG_PHYIR1      2  /* PHY Identification Register 1            */
-#define MII_REG_PHYIR2      3  /* PHY Identification Register 2            */
+#define MII_REG_CR                     0  /* Control Register                                             */
+#define MII_REG_SR                     1  /* Status Register                                              */
+#define MII_REG_PHYIR1         2  /* PHY Identification Register 1                        */
+#define MII_REG_PHYIR2         3  /* PHY Identification Register 2                        */
 
 static void mxc_fec_phy_status(mxc_fec_priv_t *dev, unsigned short value, bool show);
 
@@ -127,13 +118,13 @@ static mxc_fec_priv_t  mxc_fec_private;
 
 /*!
  * Global variable which defines the buffer descriptors for receive frames
- *     comment:: it must aligned by 128-bits.
+ *     comment:: it must aligned by 128-bits.
  */
 static mxc_fec_bd_t mxc_fec_rx_bd[FEC_BD_RX_NUM] __attribute__ ((aligned(32)));
 
 /*!
  * Global variable which defines the buffer descriptors for transmit frames
- *     comment:: it must aligned by 128-bits.
+ *     comment:: it must aligned by 128-bits.
  */
 static mxc_fec_bd_t mxc_fec_tx_bd[FEC_BD_TX_NUM] __attribute__ ((aligned(32)));
 
@@ -147,8 +138,8 @@ static unsigned char mxc_fec_rx_buf[FEC_BD_RX_NUM][2048] __attribute__ ((aligned
  */
 static unsigned char mxc_fec_tx_buf[FEC_BD_TX_NUM][2048] __attribute__ ((aligned(32)));
 
-#if 0
-static void dump_packet (unsigned char *pkt, size_t len)
+#if 1
+static void dump_packet(const unsigned char *pkt, size_t len)
 {
        int i;
 
@@ -171,44 +162,49 @@ static void dump_packet (unsigned char *pkt, size_t len)
 }
 #endif
 
-#define mxc_fec_reg_read(hw_reg,reg) _mxc_fec_reg_read(&(hw_reg)->reg, #reg)
-static inline unsigned long _mxc_fec_reg_read(volatile unsigned long *addr,
-                                                                                         const char *reg)
+static inline volatile void *fec_reg_addr(volatile void *base, unsigned int reg)
+{
+       return (volatile void *)((unsigned long)base + reg);
+}
+
+#define mxc_fec_reg_read(hw_reg,reg) _mxc_fec_reg_read(hw_reg, reg, #reg)
+static inline unsigned long _mxc_fec_reg_read(volatile void *base, unsigned int reg,
+                                                                                       const char *name)
 {
-       unsigned long val = readl(addr);
+       unsigned long val = readl(fec_reg_addr(base, reg));
 
-       if (net_debug) diag_printf("Read %08lx from FEC reg %s[%p]\n",
-                                  val, reg, addr);
+       if (net_debug) diag_printf("Read %08lx from FEC reg %s[%03x]\n",
+                                  val, name, reg);
        return val;
 }
 
-#define mxc_fec_reg_write(hw_reg,reg,val) _mxc_fec_reg_write(&(hw_reg)->reg, val, #reg)
-static inline void _mxc_fec_reg_write(volatile unsigned long *addr,
-                                                                         unsigned long val, const char *reg)
+#define mxc_fec_reg_write(hw_reg,reg,val) _mxc_fec_reg_write(hw_reg, reg, val, #reg)
+static inline void _mxc_fec_reg_write(volatile void *base, unsigned int reg,
+                                                                         unsigned long val, const char *name)
 {
-       if (net_debug) diag_printf("Writing %08lx to FEC reg %s[%p]\n",
-                                  val, reg, addr);
-       writel(val, addr);
+       if (net_debug) diag_printf("Writing %08lx to FEC reg %s[%03x]\n",
+                                                       val, name, reg);
+       writel(val, fec_reg_addr(base, reg));
 }
 
-#define mxc_fec_reg_read16(hw_reg,reg) _mxc_fec_reg_read16(&(hw_reg)->reg, #reg)
-static inline unsigned short _mxc_fec_reg_read16(volatile unsigned short *addr,
-                                                                                               const char *reg)
+#define mxc_fec_reg_read16(hw_reg,reg) _mxc_fec_reg_read16(hw_reg, reg, #reg)
+static inline unsigned short _mxc_fec_reg_read16(volatile void *base, unsigned int reg,
+                                                                                               const char *name)
 {
-       unsigned short val = readw(addr);
+       unsigned short val = readw(fec_reg_addr(base, reg));
 
-       if (net_debug) diag_printf("Read %04x from FEC reg %s[%p]\n",
-                                  val, reg, addr);
+       if (net_debug) diag_printf("Read %04x from FEC reg %s[%03x]\n",
+                                                       val, name, reg);
        return val;
 }
 
-#define mxc_fec_reg_write16(hw_reg,reg,val) _mxc_fec_reg_write16(&(hw_reg)->reg, val, #reg)
-static inline void _mxc_fec_reg_write16(volatile unsigned short *addr,
-                                                                               unsigned short val, const char *reg)
+#define mxc_fec_reg_write16(hw_reg,reg,val) _mxc_fec_reg_write16(hw_reg, reg, val, #reg)
+static inline void _mxc_fec_reg_write16(volatile void *base, unsigned int reg,
+                                                                               unsigned short val, const char *name)
 {
-       if (net_debug) diag_printf("Writing %04x to FEC reg %s[%p]\n",
-                                  val, reg, addr);
-       writew(val, addr);
+       if (net_debug) diag_printf("Writing %04x to FEC reg %s[%03x]\n",
+                                                       val, name, reg);
+       writew(val, fec_reg_addr(base, reg));
 }
 
 /*!
@@ -221,7 +217,7 @@ mxc_fec_mii_read(volatile mxc_fec_reg_t *hw_reg, unsigned char phy_addr, unsigne
        unsigned long waiting = FEC_MII_TIMEOUT;
 
        if (net_debug) diag_printf("%s: Trying to read phy[%02x] reg %04x\n",
-                                  __FUNCTION__, phy_addr, reg_addr);
+                                                       __FUNCTION__, phy_addr, reg_addr);
        if (mxc_fec_reg_read(hw_reg, eir) & FEC_EVENT_MII) {
                if (net_debug) diag_printf("%s: Clearing EIR_EVENT_MII\n", __FUNCTION__);
                mxc_fec_reg_write(hw_reg, eir, FEC_EVENT_MII);
@@ -237,15 +233,15 @@ mxc_fec_mii_read(volatile mxc_fec_reg_t *hw_reg, unsigned char phy_addr, unsigne
                }
                if (--waiting == 0) {
                        diag_printf("%s: Read from PHY at addr %d reg 0x%02x timed out: EIR=%08lx\n",
-                                   __FUNCTION__, phy_addr, reg_addr,
-                                   mxc_fec_reg_read(hw_reg, eir));
+                                               __FUNCTION__, phy_addr, reg_addr,
+                                               mxc_fec_reg_read(hw_reg, eir));
                        return -1;
                }
                hal_delay_us(FEC_MII_TICK);
        }
        *value = FEC_MII_GET_DATA(mxc_fec_reg_read(hw_reg, mmfr));
        if (net_debug) diag_printf("%s: Read %04x from phy[%02x] reg %04x\n", __FUNCTION__,
-                                  *value, phy_addr, reg_addr);
+                                                       *value, phy_addr, reg_addr);
        return 0;
 }
 
@@ -277,8 +273,8 @@ mxc_fec_mii_write(volatile mxc_fec_reg_t *hw_reg, unsigned char phy_addr, unsign
                }
                if (--waiting == 0) {
                        diag_printf("%s: Write to PHY at addr %d reg 0x%02x timed out: EIR=%08lx\n",
-                                   __FUNCTION__, phy_addr, reg_addr,
-                                   mxc_fec_reg_read(hw_reg, eir));
+                                               __FUNCTION__, phy_addr, reg_addr,
+                                               mxc_fec_reg_read(hw_reg, eir));
                        return -1;
                }
                hal_delay_us(FEC_MII_TICK);
@@ -375,7 +371,7 @@ mxc_fec_control(struct eth_drv_sc *sc, unsigned long key, void *data, int data_l
 {
        /*TODO:: Add support */
        diag_printf("mxc_fec_control: key=0x%08lx, data=%p, data_len=0x%08x\n",
-                   key, data, data_length);
+                               key, data, data_length);
        return 0;
 }
 
@@ -439,7 +435,7 @@ mxc_fec_can_send(struct eth_drv_sc *sc)
  */
 static void
 mxc_fec_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int total,
-                        unsigned long key)
+                       unsigned long key)
 {
        mxc_fec_priv_t *dev = sc ? sc->driver_private : NULL;
        volatile mxc_fec_reg_t *hw_reg = dev ? dev->hw_reg : NULL;
@@ -478,7 +474,6 @@ mxc_fec_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int
                return;
        }
        p->length = off;
-       //p->status &= ~(BD_TX_ST_LAST | BD_TX_ST_RDY | BD_TX_ST_TC | BD_TX_ST_ABC);
        p->status &= ~BD_TX_ST_ABC;
        p->status |= BD_TX_ST_LAST | BD_TX_ST_RDY | BD_TX_ST_TC;
        if (p->status & BD_TX_ST_WRAP) {
@@ -498,7 +493,7 @@ mxc_fec_send(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len, int
 static void
 mxc_fec_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
 {
-        mxc_fec_priv_t *priv = sc ? sc->driver_private : NULL;
+       mxc_fec_priv_t *priv = sc ? sc->driver_private : NULL;
        mxc_fec_bd_t *p;
        unsigned long vaddr;
 
@@ -526,8 +521,9 @@ mxc_fec_recv(struct eth_drv_sc *sc, struct eth_drv_sg *sg_list, int sg_len)
                return;
        }
        vaddr = hal_ioremap_nocache((unsigned long)p->data);
-       /*TODO::D_CACHE invalid this data buffer*/
+       /*TODO::D_CACHE invalidate this data buffer*/
        memcpy((void *)sg_list->buf, (void *)vaddr, p->length - 4);
+       if (net_debug) dump_packet((void *)sg_list->buf, p->length - 4);
 }
 
 static void
@@ -571,7 +567,7 @@ mxc_fec_check_rx_bd(struct eth_drv_sc *sc)
                } else {
                        sc->funs->eth_drv->recv(sc, p->length - 4);
                }
-skip_next:
+       skip_next:
                p->status = (p->status & BD_RX_ST_WRAP) | BD_RX_ST_EMPTY;
 
                if (p->status & BD_RX_ST_WRAP) {
@@ -636,8 +632,8 @@ mxc_fec_int_vector(struct eth_drv_sc *sc)
 {
        /*TODO::
         *      get FEC interrupt number
-        */
-       return -1;
+        */
+       return -1;
 }
 
 /*!
@@ -680,6 +676,7 @@ mxc_fec_chip_init(mxc_fec_priv_t *dev)
 {
        volatile mxc_fec_reg_t *hw_reg = dev->hw_reg;
        unsigned long ipg_clk;
+       unsigned long clkdiv;
 
        mxc_fec_reg_write(hw_reg, ecr, mxc_fec_reg_read(hw_reg, ecr) | FEC_RESET);
        while (mxc_fec_reg_read(hw_reg, ecr) & FEC_RESET) {
@@ -690,8 +687,8 @@ mxc_fec_chip_init(mxc_fec_priv_t *dev)
        mxc_fec_reg_write(hw_reg, eir, ~0);
 
        mxc_fec_reg_write(hw_reg, rcr,
-                                         (mxc_fec_reg_read(hw_reg, rcr) & ~0x3F) |
-                                         FEC_RCR_FCE | FEC_RCR_MII_MODE);
+                                       (mxc_fec_reg_read(hw_reg, rcr) & ~0x3F) |
+                                       FEC_RCR_FCE | FEC_RCR_MII_MODE);
 
        mxc_fec_reg_write(hw_reg, tcr, mxc_fec_reg_read(hw_reg, tcr) | FEC_TCR_FDEN);
        mxc_fec_reg_write(hw_reg, mibc, mxc_fec_reg_read(hw_reg, mibc) | FEC_MIB_DISABLE);
@@ -702,12 +699,13 @@ mxc_fec_chip_init(mxc_fec_priv_t *dev)
        mxc_fec_reg_write(hw_reg, galr, 0);
 
        ipg_clk = get_main_clock(IPG_CLK);
-
-       mxc_fec_reg_write(hw_reg, mscr,
-                                         (mxc_fec_reg_read(hw_reg, mscr) & ~0x7e) |
-                                         (((ipg_clk + 499999) / 2500000 / 2) << 1));
-       if (net_debug) diag_printf("mscr set to %08lx for ipg_clk %ld\n",
-                                  mxc_fec_reg_read(hw_reg, mscr), ipg_clk);
+       clkdiv = ((ipg_clk + 499999) / 2500000 / 2) << 1;
+#if 1
+       mxc_fec_reg_write(hw_reg, mscr, (mxc_fec_reg_read(hw_reg, mscr) & ~0x7e) |
+                                       clkdiv);
+#endif
+       if (net_debug) diag_printf("mscr set to %08lx(%08lx) for ipg_clk %ld\n",
+                                                       clkdiv, mxc_fec_reg_read(hw_reg, mscr), ipg_clk);
 
        mxc_fec_reg_write(hw_reg, emrbr, 2048 - 16);
        mxc_fec_reg_write(hw_reg, erdsr, hal_virt_to_phy((unsigned long)dev->rx_bd));
@@ -752,18 +750,18 @@ static void mxc_fec_phy_status(mxc_fec_priv_t *dev, unsigned short value, bool s
                dev->status &= ~FEC_STATUS_FULL_DPLX;
        }
        if (value & PHY_DIAG_RATE) {
-                dev->status |= FEC_STATUS_100M;
-        } else {
-                dev->status &= ~FEC_STATUS_100M;
-        }
+               dev->status |= FEC_STATUS_100M;
+       } else {
+               dev->status &= ~FEC_STATUS_100M;
+       }
 #endif
        if (!show) {
                return;
        }
        if (dev->status & FEC_STATUS_LINK_ON) {
                diag_printf("FEC: [ %s ] [ %s ]:\n",
-                           (dev->status & FEC_STATUS_FULL_DPLX) ? "FULL_DUPLEX" : "HALF_DUPLEX",
-                           (dev->status & FEC_STATUS_100M) ? "100 Mbps" : "10 Mbps");
+                                       (dev->status & FEC_STATUS_FULL_DPLX) ? "FULL_DUPLEX" : "HALF_DUPLEX",
+                                       (dev->status & FEC_STATUS_100M) ? "100 Mbps" : "10 Mbps");
        } else {
                diag_printf("FEC: no cable\n");
        }
@@ -814,7 +812,7 @@ mxc_fec_phy_init(mxc_fec_priv_t *dev)
 
        timeout = FEC_COMMON_TIMEOUT;
        while (timeout-- &&
-              mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_STATUS_REG, &value) == 0) {
+               mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_STATUS_REG, &value) == 0) {
                if (value & PHY_STATUS_LINK_ST) {
                        if (net_debug) diag_printf("PHY Status: %04x\n", value);
                        break;
@@ -842,7 +840,8 @@ mxc_fec_phy_init(mxc_fec_priv_t *dev)
                diag_printf("[Warning] FEC not connect right PHY: ID=%lx\n", id);
        }
 
-       mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG|PHY_CTRL_FULL_DPLX);
+       mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_CTRL_REG,
+                                       PHY_CTRL_AUTO_NEG | PHY_CTRL_FULL_DPLX);
 
 #ifdef CYGPKG_HAL_ARM_MX27ADS
        mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, &value);
@@ -850,7 +849,8 @@ mxc_fec_phy_init(mxc_fec_priv_t *dev)
        mxc_fec_mii_write(dev->hw_reg, dev->phy_addr, PHY_MODE_REG, value);
 #endif
 
-#if defined(CYGPKG_HAL_ARM_MX51) || defined (CYGPKG_HAL_ARM_MX25_3STACK) || defined (CYGPKG_HAL_ARM_MX35_3STACK) || defined (CYGPKG_HAL_ARM_MX27_3STACK)
+#if defined(CYGPKG_HAL_ARM_MX51) || defined(CYGPKG_HAL_ARM_MX25_3STACK) || \
+       defined(CYGPKG_HAL_ARM_MX35_3STACK) || defined(CYGPKG_HAL_ARM_MX27_3STACK)
        mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_EXP_REG, &value);
        /* Wait for packet to arrive */
        while (((value & PHY_AUTO_NEG_NEW_PAGE) == 0) && (timeout != 0)) {
@@ -886,12 +886,13 @@ mxc_fec_phy_init(mxc_fec_priv_t *dev)
        }
        if (value & PHY_DIAG_DPLX) {
                dev->status |= FEC_STATUS_100M;
-        } else {
+       } else {
                dev->status &= ~FEC_STATUS_100M;
        }
 #endif
 
-#if defined(CYGPKG_HAL_ARM_MX51) || defined (CYGPKG_HAL_ARM_MX25_3STACK) || defined (CYGPKG_HAL_ARM_MX35_3STACK)
+#if defined(CYGPKG_HAL_ARM_MX51) || defined(CYGPKG_HAL_ARM_MX25_3STACK) || \
+       defined(CYGPKG_HAL_ARM_MX35_3STACK)
        mxc_fec_mii_read(dev->hw_reg, dev->phy_addr, PHY_AUTO_NEG_REG, &value);
        if (value & PHY_AUTO_10BASET) {
                dev->status &= ~FEC_STATUS_100M;
@@ -925,6 +926,7 @@ static int mxc_fec_discover_phy(mxc_fec_priv_t *fep, unsigned char def_addr)
        unsigned char phy_addr = def_addr;
        unsigned long id = 0;
        int i;
+
        for (i = 0; i < 32; i++) {
                unsigned short mii_reg;
 
@@ -1057,7 +1059,7 @@ mxc_fec_init(struct cyg_netdevtab_entry *tab)
                return false;
        }
 
-       private->hw_reg = (void *)SOC_FEC_BASE;
+       private->hw_reg = (volatile void *)SOC_FEC_BASE;
        private->tx_busy = 0;
        private->status = 0;
 
@@ -1092,24 +1094,24 @@ mxc_fec_init(struct cyg_netdevtab_entry *tab)
  * Global variable which defines the FEC driver,
  */
 ETH_DRV_SC(mxc_fec_sc,
-           &mxc_fec_private, // Driver specific data
-           mxc_fec_name,
-           mxc_fec_start,
-           mxc_fec_stop,
-           mxc_fec_control,
-           mxc_fec_can_send,
-           mxc_fec_send,
-           mxc_fec_recv,
-           mxc_fec_deliver,     // "pseudoDSR" called from fast net thread
-           mxc_fec_poll,        // poll function, encapsulates ISR and DSR
-           mxc_fec_int_vector);
+               &mxc_fec_private,       // Driver specific data
+               mxc_fec_name,
+               mxc_fec_start,
+               mxc_fec_stop,
+               mxc_fec_control,
+               mxc_fec_can_send,
+               mxc_fec_send,
+               mxc_fec_recv,
+               mxc_fec_deliver,         // "pseudoDSR" called from fast net thread
+               mxc_fec_poll,            // poll function, encapsulates ISR and DSR
+               mxc_fec_int_vector);
 
 /*!
  * Global variable which defines the FEC device
  */
 NETDEVTAB_ENTRY(mxc_fec_netdev,
-                mxc_fec_name,
-                mxc_fec_init,
-                &mxc_fec_sc);
+                               mxc_fec_name,
+                               mxc_fec_init,
+                               &mxc_fec_sc);
 
 #endif // CYGPKG_DEVS_ETH_PHY
index fa24d6230731ed55e55566448b9d720e5d33678c..a2d9df605c3532f982eb947cb281ffafe3aa1edd 100644 (file)
 // -------------------------------------------
 //####ECOSGPLCOPYRIGHTEND####
 //==========================================================================
-
+#include <pkgconf/system.h>
+#ifdef CYGPKG_REDBOOT
 #include <redboot.h>
+#endif
 #include <stdlib.h>
 #include <pkgconf/hal.h>
 #include <cyg/hal/hal_arch.h>
 #include <cyg/hal/hal_cache.h>
 #include <cyg/hal/hal_io.h>
 
+#ifdef CYGBLD_HAL_PLF_DEFS_H
+#include CYGBLD_HAL_PLF_DEFS_H
+#else
 #include <cyg/hal/fsl_board.h>
+#endif
 #include <cyg/io/mxc_i2c.h>
 
 extern void mxc_i2c_init(unsigned int module_base);
@@ -55,7 +61,7 @@ extern void mxc_i2c_init(unsigned int module_base);
 #undef MXC_I2C_DEBUG
 
 #ifdef MXC_I2C_DEBUG
-#define diag_printf1    diag_printf
+#define diag_printf1   diag_printf
 #else
 #define diag_printf1(fmt,args...)
 #endif
@@ -85,29 +91,29 @@ static const struct clk_div_table i2c_clk_table[] = {
        {0, 0}
 };
 
-#define ERR_TX             -1
-#define ERR_RX             -2
-#define ERR_ARB_LOST   -3
-#define ERR_NO_ACK         -4
-#define ERR_XFER           -5
-#define ERR_RX_ACK      -6
+#define ERR_TX                 (-1)
+#define ERR_RX                 (-2)
+#define ERR_ARB_LOST   (-3)
+#define ERR_NO_ACK             (-4)
+#define ERR_XFER               (-5)
+#define ERR_RX_ACK             (-6)
 
 static inline int wait_till_busy(unsigned int base)
 {
-    int i = 10000;
+       int i = 10000;
 
-    while(((readw(base + I2C_I2SR) & I2C_I2SR_IBB) == 0) && (--i > 0)) {
-        if (readw(base + I2C_I2SR) & I2C_I2SR_IAL) {
-            diag_printf1("Error: arbitration lost!\n");
-            return ERR_ARB_LOST;
-        }
-    }
+       while(((readw(base + I2C_I2SR) & I2C_I2SR_IBB) == 0) && (--i > 0)) {
+               if (readw(base + I2C_I2SR) & I2C_I2SR_IAL) {
+                       diag_printf1("Error: arbitration lost!\n");
+                       return ERR_ARB_LOST;
+               }
+       }
 
-    if (i <= 0) {
-        return -1;
-    }
+       if (i <= 0) {
+               return -1;
+       }
 
-    return 0;
+       return 0;
 }
 
 static unsigned int g_dev_addr_width, g_dev_data_width;
@@ -116,205 +122,201 @@ static unsigned int g_i2c_nr = -1;
 
 static inline int is_bus_free(unsigned int base)
 {
-    return ((readw(base + I2C_I2SR) & I2C_I2SR_IBB) == 0);
+       return ((readw(base + I2C_I2SR) & I2C_I2SR_IBB) == 0);
 }
 
-#define ASSERT_NO_ARBITRATION_LOST(stat)  \
-{ \
-       if (stat & I2C_I2SR_IAL) { \
-               diag_printf("Error %d: Arbitration lost\n", __LINE__); \
-               return ERR_ARB_LOST; \
-       } \
-}
+#define ASSERT_NO_ARBITRATION_LOST(stat)                                                       \
+       {                                                                                                                               \
+               if (stat & I2C_I2SR_IAL) {                                                                      \
+                       diag_printf("Error %d: Arbitration lost\n", __LINE__);  \
+                       return ERR_ARB_LOST;                                                                    \
+               }                                                                                                                       \
+       }
 
-#define WAIT_RXAK_LOOPS     1000000
+#define WAIT_RXAK_LOOPS                1000000
 
 static inline unsigned short wait_op_done(unsigned int base, int is_tx)
 {
-    volatile unsigned short v;
-    int i = WAIT_RXAK_LOOPS;
-
-    while ((((v = readw(base + I2C_I2SR)) & I2C_I2SR_IIF) == 0 ||
-           (v & I2C_I2SR_ICF) == 0) && --i > 0) {
-        if (v & I2C_I2SR_IAL) {
-            diag_printf1("Error %d: Arbitration lost\n", __LINE__);
-            return ERR_ARB_LOST;
-        }
-
-    }
-    if (i <= 0) {
-        diag_printf1("I2C Error: timeout unexpected\n");
-        return -1;
-    }
-    if (is_tx) {
-        if (v & I2C_I2SR_IAL) {
-            diag_printf1("Error %d: Arbitration lost\n", __LINE__);
-            return ERR_ARB_LOST;
-        }
-       if (v & I2C_I2SR_RXAK) {
-            diag_printf1("Error %d: no ack received\n", __LINE__);
-            return -1;
+       volatile unsigned short v;
+       int i = WAIT_RXAK_LOOPS;
+
+       while ((((v = readw(base + I2C_I2SR)) & I2C_I2SR_IIF) == 0) && (--i > 0));
+
+       if (i <= 0) {
+               diag_printf1("I2C Error: timeout unexpected\n");
+               return -1;
+       }
+
+       writew(0x0, base + I2C_I2SR);
+       if (v & I2C_I2SR_IAL) {
+               diag_printf1("Error %d: Arbitration lost\n", __LINE__);
+               return ERR_ARB_LOST;
        }
-    }
-    return 0;
+
+       if (is_tx) {
+               if (v & I2C_I2SR_RXAK) {
+                       diag_printf1("Error %d: no ack received\n", __LINE__);
+                       return -1;
+               }
+       }
+       return 0;
 }
 
 //
 // For master TX, always expect a RXAK signal to be set!
 static int tx_byte(unsigned char *data, unsigned int base)
 {
-    diag_printf1("%s(data=0x%02x, base=0x%x)\n", __FUNCTION__, *data, base);
+       diag_printf1("%s(data=0x%02x, base=0x%x)\n", __FUNCTION__, *data, base);
 
-    // clear both IAL and IIF bits
-    writew(0, base + I2C_I2SR);
+       // clear both IAL and IIF bits
+       writew(0, base + I2C_I2SR);
 
-    writew(*data, base + I2C_I2DR);
-    
-    if (wait_op_done(base, 1) != 0)
-        return -1;
+       writew(*data, base + I2C_I2DR);
 
-    return 0;
+       if (wait_op_done(base, 1) != 0)
+               return -1;
+
+       return 0;
 }
 
 // For master RX
 static int rx_bytes(unsigned char *data, unsigned int base, int sz)
 {
-    unsigned short i2cr;
-    int i;
-
-    for (i = 0; sz > 0; sz--, i++) {
-        if (wait_op_done(base, 0) != 0)
-            return -1;
-
-        // clear both IAL and IIF bits
-        writew(0, base + I2C_I2SR);
-
-        // the next two if-statements setup for the next read control register value
-        if (sz == 1) {
-            // last byte --> generate STOP
-            i2cr = readw(base + I2C_I2CR);
-            writew(i2cr & ~(I2C_I2CR_MSTA | I2C_I2CR_MTX), base + I2C_I2CR);
-        }
-        if (sz == 2) {
-            // 2nd last byte --> set TXAK bit to NOT generate ACK
-            i2cr = readw(base + I2C_I2CR);
-            writew(i2cr | I2C_I2CR_TXAK, base + I2C_I2CR);
-        }
-
-        // read the true data
-        data[i] = readw(base + I2C_I2DR);
-        diag_printf1("OK 0x%02x\n", data[i]);
-    }
-    return 0;
+       unsigned short i2cr;
+       int i;
+
+       for (i = 0; sz > 0; sz--, i++) {
+               if (wait_op_done(base, 0) != 0)
+                       return -1;
+
+               // the next two if-statements setup for the next read control register value
+               if (sz == 1) {
+                       // last byte --> generate STOP
+                       i2cr = readw(base + I2C_I2CR);
+                       writew(i2cr & ~(I2C_I2CR_MSTA | I2C_I2CR_MTX), base + I2C_I2CR);
+               }
+               if (sz == 2) {
+                       // 2nd last byte --> set TXAK bit to NOT generate ACK
+                       i2cr = readw(base + I2C_I2CR);
+                       writew(i2cr | I2C_I2CR_TXAK, base + I2C_I2CR);
+               }
+
+               // read the true data
+               data[i] = readw(base + I2C_I2DR);
+               diag_printf1("OK 0x%02x\n", data[i]);
+       }
+       return 0;
 }
 
 int i2c_xfer(unsigned int i2c_nr, struct mxc_i2c_request *rq, int dir)
 {
-    unsigned int base, reg;
-    unsigned char i, data;
-    unsigned short i2cr;
-    int ret = 0;
-    
-    if ( rq == NULL || i2c_nr >= i2c_num) {
-       diag_printf("Invalid request or invalid i2c port number\n");
-       return -1;
-    } 
-
-    base = i2c_base_addr[i2c_nr];
-    if (rq->reg_addr_sz == 0 || rq->buffer_sz == 0 || rq->buffer == NULL) {
-        diag_printf("Invalid register address size=%x, buffer size=%x, buffer=%x\n",
-                    rq->reg_addr_sz, rq->buffer_sz, (unsigned int)rq->buffer);
-        return -1;
-    }
-
-    // reset and enable I2C
-    writew(0, base + I2C_I2CR);
-
-    writew(I2C_I2CR_IEN, base + I2C_I2CR);
-
-    /* Need wait at least 2 cycles of per_clk*/
-    for (i = 0; i < 16; i++) {
-        asm("nop");
-    }
-    // Step 1: generate START signal
-    // 1.1 make sure bus is free
-    if (!is_bus_free(base)) {
-        return -1;
-    }
-    // 1.2 clear both IAL and IIF bits
-    writew(0, base + I2C_I2SR);
-
-    // 1.3 assert START signal and also indicate TX mode
-    i2cr = I2C_I2CR_IEN | I2C_I2CR_MSTA | I2C_I2CR_MTX;
-    writew(i2cr, base + I2C_I2CR);
-
-    // 1.4 make sure bus is busy after the START signal
-    if (wait_till_busy(base) != 0) {
-        return ERR_TX;
-    }
-
-    // Step 2: send slave address + read/write at the LSB
-    data = (rq->dev_addr << 1) | I2C_WRITE;
-    if (tx_byte(&data, base) != 0) {
-        return -1;
-    }
-
-    // Step 3: send I2C device register address
-    if (rq->reg_addr_sz > 4) {
-        diag_printf("Warning register address size %d should less than 4\n",
-                            rq->reg_addr_sz);
-        rq->reg_addr_sz = 4;
-    }
-    reg = rq->reg_addr;
-
-    for (i = 0; i <  rq->reg_addr_sz; i++, reg>>=8) {
-        data = reg & 0xFF;
-        diag_printf1("sending I2C=0x%x device register: data=0x%x, byte %d\n",
-                     base, data, i);
-        if (tx_byte(&data, base) != 0) {
-            return -1;
-        }
-    }
-    // Step 4: read/write data
-    if (dir == I2C_READ) {
-        // do repeat-start
-        i2cr = readw(base + I2C_I2CR);
-        writew(i2cr | I2C_I2CR_RSTA, base + I2C_I2CR);
-
-        // send slave address again, but indicate read operation
-        data = (rq->dev_addr << 1) | I2C_READ;
-        if (tx_byte(&data, base) != 0) {
-            return -1;
-        }
-
-        // change to receive mode
-        i2cr = readw(base + I2C_I2CR);
-        if (rq->buffer_sz == 1) {
-            // if only one byte to read, make sure don't send ack
-            i2cr |= I2C_I2CR_TXAK;
-        }
-        writew(i2cr & ~I2C_I2CR_MTX, base + I2C_I2CR);
-        // dummy read
-        readw(base + I2C_I2DR);
-
-        // now reading ...
-        if (rx_bytes(rq->buffer, base, rq->buffer_sz) != 0) {
-            return -1;
-        }
-    } else {
-        // I2C_WRITE
-        for (i = 0; i < rq->buffer_sz; i++) {
-            // send device register value
-            data = rq->buffer[i];
-            if ((ret = tx_byte(&data, base)) != 0) {
-                break;
-            }
-        }
-        // generate STOP by clearing MSTA bit
-        writew(I2C_I2CR_IEN | I2C_I2CR_MTX, base + I2C_I2CR);
-    }
-
-    return ret;
+       unsigned int base, reg;
+       unsigned char i, data;
+       unsigned short i2cr;
+       int ret = 0;
+
+       if ( rq == NULL || i2c_nr >= i2c_num) {
+               diag_printf("Invalid request or invalid i2c port number\n");
+               return -1;
+       }
+
+       base = i2c_base_addr[i2c_nr];
+       if (rq->reg_addr_sz == 0 || rq->buffer_sz == 0 || rq->buffer == NULL) {
+               diag_printf("Invalid register address size=%x, buffer size=%x, buffer=%x\n",
+                                       rq->reg_addr_sz, rq->buffer_sz, (unsigned int)rq->buffer);
+               return -1;
+       }
+
+       // reset and enable I2C
+       writew(0, base + I2C_I2CR);
+
+       writew(I2C_I2CR_IEN, base + I2C_I2CR);
+
+       /* Need wait at least 2 cycles of per_clk*/
+       hal_delay_us(5000);
+       // Step 1: generate START signal
+       // 1.1 make sure bus is free
+       if (!is_bus_free(base)) {
+               return -1;
+       }
+       // 1.2 clear both IAL and IIF bits
+       writew(0, base + I2C_I2SR);
+
+       // 1.3 assert START signal and also indicate TX mode
+       i2cr = I2C_I2CR_IEN | I2C_I2CR_MSTA | I2C_I2CR_MTX;
+       writew(i2cr, base + I2C_I2CR);
+
+       // 1.4 make sure bus is busy after the START signal
+       if (wait_till_busy(base) != 0) {
+               return ERR_TX;
+       }
+
+       // Step 2: send slave address + read/write at the LSB
+       data = (rq->dev_addr << 1) | I2C_WRITE;
+       if (tx_byte(&data, base) != 0) {
+               return -1;
+       }
+
+       // Step 3: send I2C device register address
+       if (rq->reg_addr_sz > 4) {
+               diag_printf("Warning register address size %d should less than 4\n",
+                                       rq->reg_addr_sz);
+               rq->reg_addr_sz = 4;
+       }
+       reg = rq->reg_addr;
+
+       for (i = 0; i <  rq->reg_addr_sz; i++, reg>>=8) {
+               data = reg & 0xFF;
+               diag_printf1("sending I2C=0x%x device register: data=0x%x, byte %d\n",
+                                       base, data, i);
+               if (tx_byte(&data, base) != 0) {
+                       return -1;
+               }
+       }
+       // Step 4: read/write data
+       if (dir == I2C_READ) {
+               // do repeat-start
+               i2cr = readw(base + I2C_I2CR);
+               writew(i2cr | I2C_I2CR_RSTA, base + I2C_I2CR);
+
+               // make sure bus is busy after the repeat-start signal
+               if (wait_till_busy(base) != 0) {
+                       return ERR_TX;
+               }
+               // send slave address again, but indicate read operation
+               data = (rq->dev_addr << 1) | I2C_READ;
+               if (tx_byte(&data, base) != 0) {
+                       return -1;
+               }
+
+               // change to receive mode
+               i2cr = readw(base + I2C_I2CR);
+               if (rq->buffer_sz == 1) {
+                       // if only one byte to read, make sure don't send ack
+                       i2cr |= I2C_I2CR_TXAK;
+               }
+               writew(i2cr & ~I2C_I2CR_MTX, base + I2C_I2CR);
+               // dummy read
+               readw(base + I2C_I2DR);
+
+               // now reading ...
+               if (rx_bytes(rq->buffer, base, rq->buffer_sz) != 0) {
+                       return -1;
+               }
+       } else {
+               // I2C_WRITE
+               for (i = 0; i < rq->buffer_sz; i++) {
+                       // send device register value
+                       data = rq->buffer[i];
+                       if ((ret = tx_byte(&data, base)) != 0) {
+                               break;
+                       }
+               }
+               // generate STOP by clearing MSTA bit
+               writew(I2C_I2CR_IEN | I2C_I2CR_MTX, base + I2C_I2CR);
+       }
+
+       return ret;
 }
 
 /*!
@@ -328,153 +330,155 @@ int i2c_xfer(unsigned int i2c_nr, struct mxc_i2c_request *rq, int dir)
  */
 int i2c_init(unsigned int base, unsigned int baud)
 {
-    unsigned int clock = get_main_clock(IPG_PER_CLK);
-    int div = clock / baud;
-    struct clk_div_table *p = (struct clk_div_table *)&i2c_clk_table[0];
+       unsigned int clock = get_main_clock(IPG_PER_CLK);
+       int div = clock / baud;
+       struct clk_div_table *p = (struct clk_div_table *)&i2c_clk_table[0];
 
-    mxc_i2c_init(base);
+       mxc_i2c_init(base);
 
-    // reset and enable I2C
-    writew(0, base + I2C_I2CR);
-    writew(I2C_I2CR_IEN, base + I2C_I2CR);
+       // reset and enable I2C
+       writew(0, base + I2C_I2CR);
+       writew(I2C_I2CR_IEN, base + I2C_I2CR);
+
+       while (p->div != 0) {
+               if (div <= p->div)
+                       break;
+               p++;
+       }
 
-    while (p->div != 0) {
-        if (div <= p->div)
-            break;
-        p++;
-    }
-    
-    if (p->div == 0) {
-        diag_printf("Error: can't meet I2C baud rate request (%d) for 0x%x)\n",
-                    baud, base);
-        return -1;
-    }
+       if (p->div == 0) {
+               diag_printf("Error: can't meet I2C baud rate request (%d) for 0x%x)\n",
+                                       baud, base);
+               return -1;
+       }
 
-    diag_printf1("baud=%d, div=%d, reg_val=%d\n", baud, p->div, p->reg_value);
+       diag_printf1("baud=%d, div=%d, reg_val=%d\n", baud, p->div, p->reg_value);
 
-    writew(p->reg_value, base + I2C_IFDR);
+       writew(p->reg_value, base + I2C_IFDR);
 
-    diag_printf1("requested data rate is: %d, actual rate is: %d\n",
-                 baud, clock / p->div);
+       diag_printf1("requested data rate is: %d, actual rate is: %d\n",
+                               baud, clock / p->div);
 
-    return 0;
+       return 0;
 }
 
+#ifdef CYGPKG_REDBOOT
 static void do_i2c(int argc, char *argv[]);
 RedBoot_cmd("i2c",
-            "i2c R/W operations as master",
-            "<i2c slave addr> <register index> [<regisetr val>]]",
-            do_i2c
-           );
+                       "i2c R/W operations as master",
+                       "<i2c slave addr> <register index> [<regisetr val>]]",
+                       do_i2c
+       );
 
 
 static void do_i2c(int argc,char *argv[])
 {
-    int dir = I2C_READ, i;
-    unsigned long v;
-    unsigned long dev_addr, dev_reg;
-    struct mxc_i2c_request rq;
-    if (g_i2c_nr == -1) {
-        diag_printf("I2C module [%d] not initialized. Issue i2c_init first\n\n", g_i2c_nr);
-        return;
-    }
-    if (argc == 1) {
-        diag_printf("\tRead:  i2c <i2c_dev_addr> <dev_reg_addr>\n");
-        diag_printf("\tWrite: i2c <i2c_dev_addr> <dev_reg_addr> <dev_reg_val>\n");
-        return;
-    }
-
-    if (!parse_num(argv[1], &dev_addr, &argv[1], ":")) {
-        diag_printf("Error: Invalid parameter %d\n", __LINE__);
-        return;
-    }
-
-    if (!parse_num(argv[2], &dev_reg, &argv[2], ":")) {
-        diag_printf("Error: Invalid parameter %d\n", __LINE__);
-        return;
-    }
-
-    if (argc == 4) {
-        if (!parse_num(argv[3], &v, &argv[3], ":")) {
-            diag_printf("Error: Invalid parameter\n");
-            return;
-        }
-        dir = I2C_WRITE;
-        diag_printf("Writing I2C[%d] for addr 0x%x register 0x%x with value 0x%08lx\n",
-                    g_i2c_nr, dev_addr, dev_reg, v);
-        for (i = 0; i < g_dev_data_width; i++) {
-            g_dev_value[i] = v >> (8 * (g_dev_data_width - i - 1)) & 0xff;
-        }
-        diag_printf1("testing reversed data: 0x%08x\n", *(unsigned int*)g_dev_value);
-
-    } else {
-        diag_printf("Reading I2C [%d] from slave addr [0x%x] register [0x%x]\n",
-                    g_i2c_nr, dev_addr,  dev_reg);
-    }
-
-    rq.dev_addr = dev_addr;
-    rq.reg_addr = dev_reg;
-    rq.reg_addr_sz = g_dev_addr_width;
-    rq.buffer = g_dev_value;
-    rq.buffer_sz = g_dev_data_width;
-
-    if (i2c_xfer(g_i2c_nr, &rq, dir) != 0) {
-        diag_printf("Error I2C transfer 1\n\n");
-        return;
-    }
-
-    if (dir == I2C_READ) {
-        diag_printf("--->  ");
-        for (i = 0; i < g_dev_data_width; i++) {
-            diag_printf("0x%02x ", g_dev_value[i]);
-        }
-        diag_printf("\n\n");
-    }
+       int dir = I2C_READ, i;
+       unsigned long v;
+       unsigned int dev_addr, dev_reg;
+       struct mxc_i2c_request rq;
+
+       if (g_i2c_nr == -1) {
+               diag_printf("I2C module [%d] not initialized. Issue i2c_init first\n\n", g_i2c_nr);
+               return;
+       }
+       if (argc == 1) {
+               diag_printf("\tRead:  i2c <i2c_dev_addr> <dev_reg_addr>\n");
+               diag_printf("\tWrite: i2c <i2c_dev_addr> <dev_reg_addr> <dev_reg_val>\n");
+               return;
+       }
+
+       if (!parse_num(*(&argv[1]), (unsigned long *)&dev_addr, &argv[1], ":")) {
+               diag_printf("Error: Invalid parameter %d\n", __LINE__);
+               return;
+       }
+
+       if (!parse_num(*(&argv[2]), (unsigned long *)&dev_reg, &argv[2], ":")) {
+               diag_printf("Error: Invalid parameter %d\n", __LINE__);
+               return;
+       }
+
+       if (argc == 4) {
+               if (!parse_num(*(&argv[3]), &v, &argv[3], ":")) {
+                       diag_printf("Error: Invalid parameter\n");
+                       return;
+               }
+               dir = I2C_WRITE;
+               diag_printf("Writing I2C[%d] for addr 0x%x register 0x%x with value 0x%08lx\n",
+                                       g_i2c_nr, dev_addr, dev_reg, v);
+               for (i = 0; i < g_dev_data_width; i++) {
+                       g_dev_value[i] = v >> (8 * (g_dev_data_width - i - 1)) & 0xff;
+               }
+               diag_printf1("testing reversed data: 0x%08x\n", *(unsigned int*)g_dev_value);
+
+       } else {
+               diag_printf("Reading I2C [%d] from slave addr [0x%x] register [0x%x]\n",
+                                       g_i2c_nr, dev_addr,  dev_reg);
+       }
+
+       rq.dev_addr = dev_addr;
+       rq.reg_addr = dev_reg;
+       rq.reg_addr_sz = g_dev_addr_width;
+       rq.buffer = g_dev_value;
+       rq.buffer_sz = g_dev_data_width;
+
+       if (i2c_xfer(g_i2c_nr, &rq, dir) != 0) {
+               diag_printf("Error I2C transfer 1\n\n");
+               return;
+       }
+
+       if (dir == I2C_READ) {
+               diag_printf("--->  ");
+               for (i = 0; i < g_dev_data_width; i++) {
+                       diag_printf("0x%02x ", g_dev_value[i]);
+               }
+               diag_printf("\n\n");
+       }
 }
 
 static void do_i2c_init(int argc, char *argv[]);
 RedBoot_cmd("i2c_init",
-            "Initialize i2c (i2c_num is 0-indexed)",
-            "<i2c_num> <frequency> <device addr width> <device reg width>",
-            do_i2c_init
-           );
+                       "Initialize i2c (i2c_num is 0-indexed)",
+                       "<i2c_num> <frequency> <device addr width> <device reg width>",
+                       do_i2c_init
+       );
 
-static void do_i2c_init(int argc, char *argv[])
+static void do_i2c_init(int argc,char *argv[])
 {
-    unsigned freq;
-
-    if (argc == 1 || argc != 5) {
-        diag_printf("\ni2c_init <i2c_num> <frequency> <device addr width> <device data width>\n\n");
-        return;
-    }
-
-    if (!parse_num(argv[1], (unsigned long *)&g_i2c_nr, &argv[1], ":")) {
-        diag_printf("Error: Invalid parameter\n");
-        return;
-    }
-    
-    if (g_i2c_nr > i2c_num - 1) {
-        diag_printf("invalide i2c number: %d, max number is: %d\n", g_i2c_nr, i2c_num - 1);
-        return;
-    }
-    diag_printf1("i2c max number is: %d\n", i2c_num - 1);
-
-    if (!parse_num(argv[2], (unsigned long *)&freq, &argv[2], ":")) {
-        diag_printf("Error: Invalid parameter\n");
-        return;
-    }
-    if (!parse_num(argv[3], (unsigned long *)&g_dev_addr_width, &argv[3], ":")) {
-        diag_printf("Error: Invalid parameter\n");
-        return;
-    }
-    if (!parse_num(argv[4], (unsigned long *)&g_dev_data_width, &argv[4], ":")) {
-        diag_printf("Error: Invalid parameter\n");
-        return;
-    }
-
-    i2c_init(i2c_base_addr[g_i2c_nr], freq);
-    
-    diag_printf("initializing i2c:%d, addr-width:%d, data-width:%d\n\n",
-                g_i2c_nr, g_dev_addr_width, g_dev_data_width);
+       unsigned freq;
+
+       if (argc == 1 || argc != 5) {
+               diag_printf("\ni2c_init <i2c_num> <frequency> <device addr width> <device data width>\n\n");
+               return;
+       }
+
+       if (!parse_num(*(&argv[1]), (unsigned long *)&g_i2c_nr, &argv[1], ":")) {
+               diag_printf("Error: Invalid parameter\n");
+               return;
+       }
+
+       if (g_i2c_nr > i2c_num - 1) {
+               diag_printf("invalide i2c number: %d, max number is: %d\n", g_i2c_nr, i2c_num - 1);
+               return;
+       }
+       diag_printf1("i2c max number is: %d\n", i2c_num - 1);
+
+       if (!parse_num(*(&argv[2]), (unsigned long *)&freq, &argv[2], ":")) {
+               diag_printf("Error: Invalid parameter\n");
+               return;
+       }
+       if (!parse_num(*(&argv[3]), (unsigned long *)&g_dev_addr_width, &argv[3], ":")) {
+               diag_printf("Error: Invalid parameter\n");
+               return;
+       }
+       if (!parse_num(*(&argv[4]), (unsigned long *)&g_dev_data_width, &argv[4], ":")) {
+               diag_printf("Error: Invalid parameter\n");
+               return;
+       }
+
+       i2c_init(i2c_base_addr[g_i2c_nr], freq);
+
+       diag_printf("initializing i2c:%d, addr-width:%d, data-width:%d\n\n",
+                               g_i2c_nr, g_dev_addr_width, g_dev_data_width);
 }
+#endif
diff --git a/packages/devs/ipu/arm/imx/v1_0/cdl/imx_ipu.cdl b/packages/devs/ipu/arm/imx/v1_0/cdl/imx_ipu.cdl
new file mode 100644 (file)
index 0000000..22fe58f
--- /dev/null
@@ -0,0 +1,76 @@
+# ====================================================================
+#
+#      ipu.cdl
+#
+#      A Freescale MXC-3stack ipu package.
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002, 2004 Red Hat, Inc.
+## Copyright (C) 2004 eCosCentric, Ltd
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      Ray Sun
+# Contributors:
+# Date:           2009-05-20
+#
+#####DESCRIPTIONEND####
+# ====================================================================
+
+cdl_package CYGPKG_DEVS_IMX_IPU {
+    display     "ipu driver for mxc"
+
+    compile     -library=libextras.a ipu_common.c ipu_dma.c ipu_proc.c ipu_display.c
+
+    include_dir   cyg/io
+
+    cdl_option CYGHWR_DEVS_IPU_3_EX {
+        display       "IPU version 3EX support"
+        default_value 0
+        description   "
+            When this option is enabled, it indicates the IPU version
+            is 3EX"
+        define_proc {
+            puts $::cdl_system_header "#define IMX_IPU_VER_3_EX"
+        }
+    }
+    cdl_option CYGHWR_DEVS_IPU_3_D {
+        display       "IPU version 3D support"
+        default_value 0
+        description   "
+            When this option is enabled, it indicates the IPU version
+            is 3D"
+        define_proc {
+            puts $::cdl_system_header "#define IMX_IPU_VER_3_D"
+        }
+    }
+}
diff --git a/packages/devs/ipu/arm/imx/v1_0/include/ipu_common.h b/packages/devs/ipu/arm/imx/v1_0/include/ipu_common.h
new file mode 100644 (file)
index 0000000..8f655ca
--- /dev/null
@@ -0,0 +1,406 @@
+//==========================================================================
+//
+//      IPU_COMMON.h
+//
+//      common functions declaration and macro definitions for IPUv3d
+//
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       Ray Sun <Yanfei.Sun@freescale.com>
+// Create Date: 2008-07-31
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef IPU_COMMON_H_
+#define IPU_COMMON_H_
+
+// System-wide configuration info
+#include <pkgconf/system.h>
+#include <cyg/infra/cyg_type.h>
+#ifdef CYGBLD_HAL_PLF_DEFS_H
+#include CYGBLD_HAL_PLF_DEFS_H
+#else
+#include <cyg/hal/fsl_board.h>
+#endif
+
+#ifdef IMX_IPU_VER_3_EX
+#include "ipuv3ex_reg_def.h"
+#endif
+
+#ifdef IMX_IPU_VER_3_D
+#include "ipuv3d_reg_def.h"
+#endif
+
+#define IPU_DEBUG
+#undef IPU_DEBUG
+#ifdef IPU_DEBUG
+#define DP(fmt,args...) diag_printf(fmt, ## args)
+#else
+#define DP(fmt,args...)
+#endif
+#define ERRDP(fmt, arg...) diag_printf("[ERR] " fmt, ## arg)
+#define WARNDP(fmt, arg...) diag_printf("[WARN] " fmt, ## arg)
+#define INFODP(fmt, arg...) diag_printf("[INFO] " fmt, ## arg)
+
+
+#define TIMEOUT_VALUE 0x1000
+
+#define T_VALUE 2
+
+/* Epson LCD command definitions */
+#define DISON 0x29
+#define DISOFF 0x28
+#define GAMSET 0x26
+#define SLPIN 0x10
+#define SLPOUT 0x11
+#define PASET 0x2b
+#define CASET 0x2a
+#define MADCTL 0x36
+#define COLMOD 0x3a
+#define RAMWR 0x2c
+#define PTLON 0x12
+#define PTLAR 0x30
+#define NORON 0x13
+
+/* DI counter definitions */
+#define DI_COUNTER_BASECLK             0
+#define DI_COUNTER_IHSYNC              1
+#define DI_COUNTER_OHSYNC              2
+#define DI_COUNTER_OVSYNC              3
+#define DI_COUNTER_ALINE               4
+#define DI_COUNTER_ACLOCK              5
+
+/* IDMAC defines */
+#define INTERLEAVED_MODE 0
+#define NON_INTERLEAVED_MODE 1
+
+#define SHIFT_DISABLE 0
+#define SHIFT_ENABLE  1
+
+#define GET_LSB(bit, val)  (((unsigned int)(val)) & ((0x1<<(bit)) - 1))
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+/* Display buffer starts at the end of DDR */
+#define DISPLAY_BUFFER_ADDR (void *)(SDRAM_BASE_ADDR + CYGMEM_REGION_ram_SIZE - 0x400000)
+
+typedef struct {
+       unsigned int lowmask;           // low mask inorder to find the correct masking in case of splitted data
+       unsigned int ID_mask;           // ID mask of the current field
+       unsigned int ID_addrs;          // ID address of the current channel
+       unsigned int data_high_sh;      // High data shift if needed
+} idmac_bpp_STC;
+
+typedef struct display_buffer_info {
+       CYG_ADDRESS startAddr;
+       unsigned int width;
+       unsigned int height;
+       int dataFormat;
+       int bpp;
+       int channel;
+} display_buffer_info_t;
+
+typedef struct {
+       unsigned int channel;
+       unsigned int xv;
+       unsigned int yv;
+       unsigned int xb;
+       unsigned int yb;
+       unsigned int nsb_b;
+       unsigned int cf;
+       unsigned int sx;
+       unsigned int sy;
+       unsigned int ns;
+       unsigned int sdx;
+       unsigned int sm;
+       unsigned int scc;
+       unsigned int sce;
+       unsigned int sdy;
+       unsigned int sdrx;
+       unsigned int sdry;
+       unsigned int bpp;
+       unsigned int dec_sel;
+       unsigned int dim;
+       unsigned int so;
+       unsigned int bndm;
+       unsigned int bm;
+       unsigned int rot;
+       unsigned int hf;
+       unsigned int vf;
+       unsigned int the;
+       unsigned int cap;
+       unsigned int cae;
+       unsigned int fw;
+       unsigned int fh;
+       unsigned int eba0;
+       unsigned int eba1;
+       unsigned int ilo;
+       unsigned int npb;
+       unsigned int pfs;
+       unsigned int alu;
+       unsigned int albm;
+       unsigned int id;
+       unsigned int th;
+       unsigned int sl;
+       unsigned int wid0;
+       unsigned int wid1;
+       unsigned int wid2;
+       unsigned int wid3;
+       unsigned int ofs0;
+       unsigned int ofs1;
+       unsigned int ofs2;
+       unsigned int ofs3;
+       unsigned int cre;
+       unsigned int ubo;
+       unsigned int vbo;
+       unsigned int sly;
+       unsigned int sluv;
+} ipu_channel_parameter_t;
+
+typedef struct ipu_res_info {
+       int taskType;
+       unsigned int inAddr0;
+       unsigned int inAddr1;
+       unsigned int outAddr0;
+       unsigned int outAddr1;
+       int inWidth;
+       int inHeight;
+       int outWidth;
+       int outHeight;
+       int xSplitParts;
+       int ySplitParts;
+       int stridelineIn;
+       int stridelineOut;
+       int uOffsetIn;
+       int uOffsetOut;
+       int inDataFormat;
+       int outDataFormat;
+} ipu_res_info_t;
+
+typedef struct ipu_rot_info {
+       int taskType;
+       unsigned int inAddr0;
+       unsigned int inAddr1;
+       unsigned int outAddr0;
+       unsigned int outAddr1;
+       int inWidth;
+       int inHeight;
+       int outWidth;
+       int outHeight;
+       int stridelineIn;
+       int stridelineOut;
+       int uOffsetIn;
+       int uOffsetOut;
+       int inDataFormat;
+       int outDataFormat;
+       int HorizFlip;
+       int VertFlip;
+       int rotation;
+} ipu_rot_info_t;
+
+typedef struct display_device {
+       unsigned int type;
+       int width;
+       int height;
+} display_device_t;
+
+enum icTaskType {
+       PrP_ENC_TASK = 0,
+       PrP_VF_TASK,
+       PP_TASK,
+       IC_CMB,
+       IC_CSC1,
+       IC_CSC2,
+       IC_PP,
+       IC_PRPENC,
+       IC_PRPVF,
+};
+
+enum colorSpace {
+       RGB = 0,
+       YCbCr,
+       RGB565,
+       RGB666,
+       RGB888,
+       RGBA8888,
+       YUV888,
+       YUVA8888,
+       GRAY,
+};
+
+enum dest {
+       DMA_CH0 = 0,
+       DMA_CH22,
+       DMA_CH23,
+       DMA_CH28,
+};
+
+enum tv_display_mode {
+       TVNTSC = 0,
+       TVPALM,
+       TVPALN,
+       TVPAL,
+       TV720P60,
+       TV720P50,
+       TV720P30,
+       TV720P25,
+       TV720P24,
+       TV1080I60,
+       TV1080I50,
+       TV1035I60,
+       TV1080P30,
+       TV1080P25,
+       TV1080P24,
+       TVNONE
+};
+
+typedef struct alpha_chan_params {
+       unsigned int alphaChanBaseAddr;
+       int alphaWidth;
+       int alphaHeight;
+       int alphaStrideline;
+} alpha_chan_params_t;
+
+typedef struct ic_comb_params {
+       int taskType;
+       unsigned int baseAddr;
+       int width;
+       int height;
+       int alpha;
+       int inDataformat;
+       alpha_chan_params_t alphaChan;
+} ic_comb_params_t;
+
+typedef struct ic_csc_params {
+       int taskType;
+       int inFormat;
+       int outFormat;
+} ic_csc_params_t;
+
+typedef struct ipu_task_params {
+       int taskType;
+       int resEnable;
+       int rotEnable;
+       ipu_res_info_t resInfo;
+       ipu_rot_info_t rotInfo;
+} ipu_task_params_t;
+
+typedef struct dp_csc_param {
+       int mode;
+       int **coeff;
+} dp_csc_param_t;
+
+typedef struct dp_fg_param {
+       int fgEnable;
+       int opaque;
+       int offsetVert;
+       int offsetHoriz;
+       int cursorEnable;
+       int colorKeyEnable;
+       int graphicSelect;
+       int alphaMode;
+} dp_fg_param_t;
+
+typedef struct cam_caputure_params {
+       int camMode;
+       int camRate;
+       int camInWidth;
+       int camInHeight;
+       int camOutWidth;
+       int camOutHeight;
+} cam_capture_params_t;
+
+typedef struct dc_microcode {
+       int addr;
+       int stop;
+       char *opcode;
+       int lf;
+       int af;
+       int operand;
+       int mapping;
+       int waveform;
+       int gluelogic;
+       int sync;
+} dc_microcode_t;
+
+typedef struct di_sync_wave_gen {
+       int runValue;
+       int runResolution;
+       int offsetValue;
+       int offsetResolution;
+       int cntAutoReload;
+       int stepRepeat;
+       int cntClrSel;
+       int cntPolarityGenEn;
+       int cntPolarityTrigSel;
+       int cntPolarityClrSel;
+       int cntUp;
+       int cntDown;
+} di_sync_wave_gen_t;
+
+//common API functions for IPU
+void ipu_write_field(unsigned int id_addr, unsigned int id_mask, unsigned int data);
+void ipu_enable_display(void);
+void ipu_disable_display(void);
+void ipu_csi_config(int width, int height);
+
+//dma API functions for IPU
+void ipu_idmac_params_init(ipu_channel_parameter_t * ipu_channel_params_ptr);
+void ipu_idmac_cpmem_param_update(int ch_number, int int_mode, char field_name[10], int data);
+void ipu_idmac_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params);
+void ipu_idmac_non_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params);
+void ipu_idmac_cpmem_param_set(int ch_number, unsigned int id_addr,
+                                                       unsigned int id_mask, int sh_en, idmac_bpp_STC * idmac_bpp);
+void ipu_idmac_channel_buf_ready(int channel, int buf);
+void ipu_idmac_channel_buf_not_ready(int channel, int buf);
+void ipu_idmac_channel_mode_sel(int channel, int double_buf_en);
+void ipu_idmac_channel_enable(int channel, int enable);
+int ipu_idmac_channel_busy(int channel);
+int ipu_idmac_chan_cur_buff(int channel);
+int ipu_idamc_chan_eof_int(int channel);
+int ipu_idmac_chan_till_idle(int channel, int timeout);
+int ipu_dmfc_fifo_allocate(int channel, int fifo_size, int burst_size, int offset_addr);
+int ipu_smfc_fifo_allocate(int channel, int map, int burst_size);
+
+/* processing API functions for IPU */
+void ipu_ic_enable(int ic_enable, int irt_enable);
+void ipu_ic_task_config(ipu_task_params_t task_params);
+void ipu_ic_calc_resize_coeffs(unsigned int in_size, unsigned int out_size,
+                                                       unsigned int *resize_coeff, unsigned int *downsize_coeff);
+int ipu_ic_config_resize_rate(char *task_type, unsigned int res_vert,
+                                                       unsigned int down_vert, unsigned int res_horiz,
+                                                       unsigned int down_horiz);
+void ipu_ic_calc_vout_size(ipu_res_info_t * info, display_device_t disp_dev, int rotation,
+                                               int full_screen_enable);
+int ipu_ic_combine_config(ic_comb_params_t comb_params);
+int ipu_ic_csc_config(int csc_index, ic_csc_params_t csc_params);
+int ipu_ic_task_enable(int task_type, int task, int enable);
+void ipu_dp_csc_config(int dp, dp_csc_param_t dp_csc_params, bool srm_mode_update);
+void ipu_dp_fg_config(dp_fg_param_t foreground_params);
+void ipu_dp_fg_config(dp_fg_param_t foreground_params);
+void ipu_dc_microcode_config(dc_microcode_t microcode);
+void ipu_dc_microcode_event(int channel, char event[8], int priority, int address);
+int ipu_dc_map(int map, int format);
+int ipu_dc_display_config(int disp_port, int type, int increment, int strideline);
+int ipu_dc_write_channel_config(int dma_channel, int disp_port, int link_di_index,
+                                                               int field_mode_enable);
+
+/* display API functions for IPU */
+void ipu_di_sync_config(int di, int pointer, di_sync_wave_gen_t sync_wave_gen);
+void ipu_di_pointer_config(int di, int pointer, int access, int component, int cst,
+                                               int pt0, int pt1, int pt2, int pt3, int pt4, int pt5, int pt6);
+void ipu_di_waveform_config(int di, int pointer, int set, int up, int down);
+int ipu_di_bsclk_gen(int di, int division, int up, int down);
+int ipu_di_screen_set(int di, int screen_height);
+int ipu_di_general_set(int di, int line_prediction, int vsync_sel, int hsync_sel, int clk_sel);
+
+void fastlogo_init(display_buffer_info_t *di);
+void fastlogo_dma(void);
+void fastlogo_dmfc(void);
+void fastlogo_dc(void);
+void fastlogo_di(void);
+
+#endif
diff --git a/packages/devs/ipu/arm/imx/v1_0/include/ipuv3d_reg_def.h b/packages/devs/ipu/arm/imx/v1_0/include/ipuv3d_reg_def.h
new file mode 100644 (file)
index 0000000..7586adf
--- /dev/null
@@ -0,0 +1,10047 @@
+//==========================================================================
+//
+//      IPUV3D_REG_DEF.h
+//
+//      regs definitions of IPUv3d 
+//
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       Ray Sun <Yanfei.Sun@freescale.com> 
+// Create Date: 2008-07-31
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef _IPUV3D_REG_DEF_H_
+#define _IPUV3D_REG_DEF_H_
+
+// part before __ means register name, while part after __ 
+//means the property or bit fields of this reg.
+#define IPU_IPU_CONF__ADDR             0x1E000000
+#define IPU_IPU_CONF__EMPTY            0x1E000000,0x00000000
+#define IPU_IPU_CONF__FULL             0x1E000000,0xffffffff
+#define IPU_IPU_CONF__IC_DMFC_SYNC     0x1E000000,0x04000000
+#define IPU_IPU_CONF__IC_DMFC_SEL      0x1E000000,0x02000000
+#define IPU_IPU_CONF__IDMAC_DISABLE    0x1E000000,0x00400000
+#define IPU_IPU_CONF__IPU_DIAGBUS_ON   0x1E000000,0x00200000
+#define IPU_IPU_CONF__IPU_DIAGBUS_MODE 0x1E000000,0x001F0000
+#define IPU_IPU_CONF__DMFC_EN          0x1E000000,0x00000400
+#define IPU_IPU_CONF__DC_EN            0x1E000000,0x00000200
+#define IPU_IPU_CONF__DI1_EN           0x1E000000,0x00000080
+#define IPU_IPU_CONF__DI0_EN           0x1E000000,0x00000040
+#define IPU_IPU_CONF__DP_EN            0x1E000000,0x00000020
+#define IPU_IPU_CONF__IRT_EN           0x1E000000,0x00000008
+#define IPU_IPU_CONF__IC_EN            0x1E000000,0x00000004
+
+#define IPU_IPU_INT_CTRL_1__ADDR            0x1E00003C
+#define IPU_IPU_INT_CTRL_1__EMPTY           0x1E00003C,0x00000000
+#define IPU_IPU_INT_CTRL_1__FULL            0x1E00003C,0xffffffff
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_31 0x1E00003C,0x80000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_29 0x1E00003C,0x20000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_28 0x1E00003C,0x10000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_27 0x1E00003C,0x08000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_24 0x1E00003C,0x01000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_23 0x1E00003C,0x00800000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_22 0x1E00003C,0x00400000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_21 0x1E00003C,0x00200000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_20 0x1E00003C,0x00100000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_18 0x1E00003C,0x00040000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_17 0x1E00003C,0x00020000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_15 0x1E00003C,0x00008000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_14 0x1E00003C,0x00004000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_12 0x1E00003C,0x00001000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_11 0x1E00003C,0x00000800
+
+#define IPU_IPU_INT_CTRL_2__ADDR            0x1E000040
+#define IPU_IPU_INT_CTRL_2__EMPTY           0x1E000040,0x00000000
+#define IPU_IPU_INT_CTRL_2__FULL            0x1E000040,0xffffffff
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_52 0x1E000040,0x00100000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_51 0x1E000040,0x00080000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_50 0x1E000040,0x00040000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_49 0x1E000040,0x00020000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_48 0x1E000040,0x00010000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_47 0x1E000040,0x00008000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_46 0x1E000040,0x00004000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_45 0x1E000040,0x00002000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_44 0x1E000040,0x00001000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_43 0x1E000040,0x00000800
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_42 0x1E000040,0x00000400
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_41 0x1E000040,0x00000200
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_40 0x1E000040,0x00000100
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_33 0x1E000040,0x00000002
+
+#define IPU_IPU_INT_CTRL_3__ADDR              0x1E000044
+#define IPU_IPU_INT_CTRL_3__EMPTY             0x1E000044,0x00000000
+#define IPU_IPU_INT_CTRL_3__FULL              0x1E000044,0xffffffff
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31 0x1E000044,0x80000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29 0x1E000044,0x20000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28 0x1E000044,0x10000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27 0x1E000044,0x08000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24 0x1E000044,0x01000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23 0x1E000044,0x00800000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22 0x1E000044,0x00400000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21 0x1E000044,0x00200000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20 0x1E000044,0x00100000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18 0x1E000044,0x00040000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17 0x1E000044,0x00020000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15 0x1E000044,0x00008000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14 0x1E000044,0x00004000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12 0x1E000044,0x00001000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11 0x1E000044,0x00000800
+
+#define IPU_IPU_INT_CTRL_4__ADDR              0x1E000048
+#define IPU_IPU_INT_CTRL_4__EMPTY             0x1E000048,0x00000000
+#define IPU_IPU_INT_CTRL_4__FULL              0x1E000048,0xffffffff
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52 0x1E000048,0x00100000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51 0x1E000048,0x00080000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50 0x1E000048,0x00040000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49 0x1E000048,0x00020000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48 0x1E000048,0x00010000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47 0x1E000048,0x00008000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46 0x1E000048,0x00004000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45 0x1E000048,0x00002000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44 0x1E000048,0x00001000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43 0x1E000048,0x00000800
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42 0x1E000048,0x00000400
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41 0x1E000048,0x00000200
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40 0x1E000048,0x00000100
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33 0x1E000048,0x00000002
+
+#define IPU_IPU_INT_CTRL_5__ADDR                0x1E00004C
+#define IPU_IPU_INT_CTRL_5__EMPTY               0x1E00004C,0x00000000
+#define IPU_IPU_INT_CTRL_5__FULL                0x1E00004C,0xffffffff
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31 0x1E00004C,0x80000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29 0x1E00004C,0x20000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28 0x1E00004C,0x10000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27 0x1E00004C,0x08000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24 0x1E00004C,0x01000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23 0x1E00004C,0x00800000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22 0x1E00004C,0x00400000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21 0x1E00004C,0x00200000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20 0x1E00004C,0x00100000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18 0x1E00004C,0x00040000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17 0x1E00004C,0x00020000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15 0x1E00004C,0x00008000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14 0x1E00004C,0x00004000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12 0x1E00004C,0x00001000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11 0x1E00004C,0x00000800
+
+#define IPU_IPU_INT_CTRL_6__ADDR                0x1E000050
+#define IPU_IPU_INT_CTRL_6__EMPTY               0x1E000050,0x00000000
+#define IPU_IPU_INT_CTRL_6__FULL                0x1E000050,0xffffffff
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52 0x1E000050,0x00100000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51 0x1E000050,0x00080000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50 0x1E000050,0x00040000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49 0x1E000050,0x00020000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48 0x1E000050,0x00010000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47 0x1E000050,0x00008000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46 0x1E000050,0x00004000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45 0x1E000050,0x00002000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44 0x1E000050,0x00001000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43 0x1E000050,0x00000800
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42 0x1E000050,0x00000400
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41 0x1E000050,0x00000200
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40 0x1E000050,0x00000100
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33 0x1E000050,0x00000002
+
+#define IPU_IPU_INT_CTRL_7__ADDR            0x1E000054
+#define IPU_IPU_INT_CTRL_7__EMPTY           0x1E000054,0x00000000
+#define IPU_IPU_INT_CTRL_7__FULL            0x1E000054,0xffffffff
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1E000054,0x80000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1E000054,0x20000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1E000054,0x10000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1E000054,0x08000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1E000054,0x01000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1E000054,0x00800000
+
+#define IPU_IPU_INT_CTRL_8__ADDR            0x1E000058
+#define IPU_IPU_INT_CTRL_8__EMPTY           0x1E000058,0x00000000
+#define IPU_IPU_INT_CTRL_8__FULL            0x1E000058,0xffffffff
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1E000058,0x00100000
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1E000058,0x00080000
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1E000058,0x00001000
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1E000058,0x00000800
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1E000058,0x00000400
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1E000058,0x00000200
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1E000058,0x00000002
+
+#define IPU_IPU_INT_CTRL_10__ADDR                      0x1E000060
+#define IPU_IPU_INT_CTRL_10__EMPTY                     0x1E000060,0x00000000
+#define IPU_IPU_INT_CTRL_10__FULL                      0x1E000060,0xffffffff
+#define IPU_IPU_INT_CTRL_10__AXIR_ERR_EN               0x1E000060,0x40000000
+#define IPU_IPU_INT_CTRL_10__AXIW_ERR_EN               0x1E000060,0x20000000
+#define IPU_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN 0x1E000060,0x10000000
+#define IPU_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN  0x1E000060,0x04000000
+#define IPU_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN    0x1E000060,0x02000000
+#define IPU_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN     0x1E000060,0x01000000
+#define IPU_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN       0x1E000060,0x00400000
+#define IPU_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN       0x1E000060,0x00200000
+#define IPU_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN      0x1E000060,0x00100000
+#define IPU_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN      0x1E000060,0x00080000
+#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN       0x1E000060,0x00040000
+#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN       0x1E000060,0x00020000
+#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN       0x1E000060,0x00010000
+
+#define IPU_IPU_INT_CTRL_11__ADDR              0x1E000064
+#define IPU_IPU_INT_CTRL_11__EMPTY             0x1E000064,0x00000000
+#define IPU_IPU_INT_CTRL_11__FULL              0x1E000064,0xffffffff
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22 0x1E000064,0x00400000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21 0x1E000064,0x00200000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20 0x1E000064,0x00100000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12 0x1E000064,0x00001000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11 0x1E000064,0x00000800
+
+#define IPU_IPU_INT_CTRL_12__ADDR              0x1E000068
+#define IPU_IPU_INT_CTRL_12__EMPTY             0x1E000068,0x00000000
+#define IPU_IPU_INT_CTRL_12__FULL              0x1E000068,0xffffffff
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50 0x1E000068,0x00040000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49 0x1E000068,0x00020000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48 0x1E000068,0x00010000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47 0x1E000068,0x00008000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46 0x1E000068,0x00004000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45 0x1E000068,0x00002000
+
+#define IPU_IPU_INT_CTRL_13__ADDR           0x1E00006C
+#define IPU_IPU_INT_CTRL_13__EMPTY          0x1E00006C,0x00000000
+#define IPU_IPU_INT_CTRL_13__FULL           0x1E00006C,0xffffffff
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_31 0x1E00006C,0x80000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_29 0x1E00006C,0x20000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_28 0x1E00006C,0x10000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_27 0x1E00006C,0x08000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_24 0x1E00006C,0x01000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_23 0x1E00006C,0x00800000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_22 0x1E00006C,0x00400000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_21 0x1E00006C,0x00200000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_20 0x1E00006C,0x00100000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_18 0x1E00006C,0x00040000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_17 0x1E00006C,0x00020000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_15 0x1E00006C,0x00008000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_14 0x1E00006C,0x00004000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_12 0x1E00006C,0x00001000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_11 0x1E00006C,0x00000800
+
+#define IPU_IPU_INT_CTRL_14__ADDR           0x1E000070
+#define IPU_IPU_INT_CTRL_14__EMPTY          0x1E000070,0x00000000
+#define IPU_IPU_INT_CTRL_14__FULL           0x1E000070,0xffffffff
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_52 0x1E000070,0x00100000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_51 0x1E000070,0x00080000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_50 0x1E000070,0x00040000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_49 0x1E000070,0x00020000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_48 0x1E000070,0x00010000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_47 0x1E000070,0x00008000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_46 0x1E000070,0x00004000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_45 0x1E000070,0x00002000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_44 0x1E000070,0x00001000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_43 0x1E000070,0x00000800
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_42 0x1E000070,0x00000400
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_41 0x1E000070,0x00000200
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_40 0x1E000070,0x00000100
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_33 0x1E000070,0x00000002
+
+#define IPU_IPU_INT_CTRL_15__ADDR                   0x1E000074
+#define IPU_IPU_INT_CTRL_15__EMPTY                  0x1E000074,0x00000000
+#define IPU_IPU_INT_CTRL_15__FULL                   0x1E000074,0xffffffff
+#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN    0x1E000074,0x80000000
+#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN    0x1E000074,0x40000000
+#define IPU_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN 0x1E000074,0x20000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN   0x1E000074,0x10000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN    0x1E000074,0x08000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN    0x1E000074,0x04000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN    0x1E000074,0x02000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN    0x1E000074,0x01000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN    0x1E000074,0x00800000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN    0x1E000074,0x00400000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN    0x1E000074,0x00200000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN    0x1E000074,0x00100000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN    0x1E000074,0x00080000
+#define IPU_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN 0x1E000074,0x00040000
+#define IPU_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN       0x1E000074,0x00020000
+#define IPU_IPU_INT_CTRL_15__DC_DP_START_EN         0x1E000074,0x00010000
+#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN      0x1E000074,0x00008000
+#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN      0x1E000074,0x00004000
+#define IPU_IPU_INT_CTRL_15__DC_FC_6_EN             0x1E000074,0x00002000
+#define IPU_IPU_INT_CTRL_15__DC_FC_4_EN             0x1E000074,0x00001000
+#define IPU_IPU_INT_CTRL_15__DC_FC_3_EN             0x1E000074,0x00000800
+#define IPU_IPU_INT_CTRL_15__DC_FC_2_EN             0x1E000074,0x00000400
+#define IPU_IPU_INT_CTRL_15__DC_FC_1_EN             0x1E000074,0x00000200
+#define IPU_IPU_INT_CTRL_15__DC_FC_0_EN             0x1E000074,0x00000100
+#define IPU_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN        0x1E000074,0x00000080
+#define IPU_IPU_INT_CTRL_15__DP_SF_BRAKE_EN         0x1E000074,0x00000040
+#define IPU_IPU_INT_CTRL_15__DP_ASF_END_EN          0x1E000074,0x00000020
+#define IPU_IPU_INT_CTRL_15__DP_ASF_START_EN        0x1E000074,0x00000010
+#define IPU_IPU_INT_CTRL_15__DP_SF_END_EN           0x1E000074,0x00000008
+#define IPU_IPU_INT_CTRL_15__DP_SF_START_EN         0x1E000074,0x00000004
+#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN   0x1E000074,0x00000002
+#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN   0x1E000074,0x00000001
+
+#define IPU_IPU_SDMA_EVENT_1__ADDR                 0x1E000078
+#define IPU_IPU_SDMA_EVENT_1__EMPTY                0x1E000078,0x00000000
+#define IPU_IPU_SDMA_EVENT_1__FULL                 0x1E000078,0xffffffff
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31 0x1E000078,0x80000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29 0x1E000078,0x20000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28 0x1E000078,0x10000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27 0x1E000078,0x08000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24 0x1E000078,0x01000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23 0x1E000078,0x00800000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22 0x1E000078,0x00400000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21 0x1E000078,0x00200000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20 0x1E000078,0x00100000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18 0x1E000078,0x00040000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17 0x1E000078,0x00020000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15 0x1E000078,0x00008000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14 0x1E000078,0x00004000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12 0x1E000078,0x00001000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11 0x1E000078,0x00000800
+
+#define IPU_IPU_SDMA_EVENT_2__ADDR                 0x1E00007C
+#define IPU_IPU_SDMA_EVENT_2__EMPTY                0x1E00007C,0x00000000
+#define IPU_IPU_SDMA_EVENT_2__FULL                 0x1E00007C,0xffffffff
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52 0x1E00007C,0x00100000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51 0x1E00007C,0x00080000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50 0x1E00007C,0x00040000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49 0x1E00007C,0x00020000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48 0x1E00007C,0x00010000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47 0x1E00007C,0x00008000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46 0x1E00007C,0x00004000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45 0x1E00007C,0x00002000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44 0x1E00007C,0x00001000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43 0x1E00007C,0x00000800
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42 0x1E00007C,0x00000400
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41 0x1E00007C,0x00000200
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40 0x1E00007C,0x00000100
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33 0x1E00007C,0x00000002
+
+#define IPU_IPU_SDMA_EVENT_3__ADDR                   0x1E000080
+#define IPU_IPU_SDMA_EVENT_3__EMPTY                  0x1E000080,0x00000000
+#define IPU_IPU_SDMA_EVENT_3__FULL                   0x1E000080,0xffffffff
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31 0x1E000080,0x80000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29 0x1E000080,0x20000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28 0x1E000080,0x10000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27 0x1E000080,0x08000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24 0x1E000080,0x01000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23 0x1E000080,0x00800000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22 0x1E000080,0x00400000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21 0x1E000080,0x00200000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20 0x1E000080,0x00100000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18 0x1E000080,0x00040000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17 0x1E000080,0x00020000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15 0x1E000080,0x00008000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14 0x1E000080,0x00004000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12 0x1E000080,0x00001000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11 0x1E000080,0x00000800
+
+#define IPU_IPU_SDMA_EVENT_4__ADDR                   0x1E000084
+#define IPU_IPU_SDMA_EVENT_4__EMPTY                  0x1E000084,0x00000000
+#define IPU_IPU_SDMA_EVENT_4__FULL                   0x1E000084,0xffffffff
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52 0x1E000084,0x00100000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51 0x1E000084,0x00080000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50 0x1E000084,0x00040000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49 0x1E000084,0x00020000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48 0x1E000084,0x00010000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47 0x1E000084,0x00008000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46 0x1E000084,0x00004000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45 0x1E000084,0x00002000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44 0x1E000084,0x00001000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43 0x1E000084,0x00000800
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42 0x1E000084,0x00000400
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41 0x1E000084,0x00000200
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40 0x1E000084,0x00000100
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33 0x1E000084,0x00000002
+
+#define IPU_IPU_SDMA_EVENT_7__ADDR                 0x1E000088
+#define IPU_IPU_SDMA_EVENT_7__EMPTY                0x1E000088,0x00000000
+#define IPU_IPU_SDMA_EVENT_7__FULL                 0x1E000088,0xffffffff
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1E000088,0x80000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1E000088,0x20000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1E000088,0x10000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1E000088,0x08000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1E000088,0x01000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1E000088,0x00800000
+
+#define IPU_IPU_SDMA_EVENT_8__ADDR                 0x1E00008C
+#define IPU_IPU_SDMA_EVENT_8__EMPTY                0x1E00008C,0x00000000
+#define IPU_IPU_SDMA_EVENT_8__FULL                 0x1E00008C,0xffffffff
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1E00008C,0x00100000
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1E00008C,0x00080000
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1E00008C,0x00001000
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1E00008C,0x00000800
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1E00008C,0x00000400
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1E00008C,0x00000200
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1E00008C,0x00000002
+
+#define IPU_IPU_SDMA_EVENT_11__ADDR                   0x1E000090
+#define IPU_IPU_SDMA_EVENT_11__EMPTY                  0x1E000090,0x00000000
+#define IPU_IPU_SDMA_EVENT_11__FULL                   0x1E000090,0xffffffff
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22 0x1E000090,0x00400000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21 0x1E000090,0x00200000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20 0x1E000090,0x00100000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12 0x1E000090,0x00001000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11 0x1E000090,0x00000800
+
+#define IPU_IPU_SDMA_EVENT_12__ADDR                   0x1E000094
+#define IPU_IPU_SDMA_EVENT_12__EMPTY                  0x1E000094,0x00000000
+#define IPU_IPU_SDMA_EVENT_12__FULL                   0x1E000094,0xffffffff
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50 0x1E000094,0x00040000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49 0x1E000094,0x00020000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48 0x1E000094,0x00010000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47 0x1E000094,0x00008000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46 0x1E000094,0x00004000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45 0x1E000094,0x00002000
+
+#define IPU_IPU_SDMA_EVENT_13__ADDR                0x1E000098
+#define IPU_IPU_SDMA_EVENT_13__EMPTY               0x1E000098,0x00000000
+#define IPU_IPU_SDMA_EVENT_13__FULL                0x1E000098,0xffffffff
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31 0x1E000098,0x80000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29 0x1E000098,0x20000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28 0x1E000098,0x10000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27 0x1E000098,0x08000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24 0x1E000098,0x01000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23 0x1E000098,0x00800000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22 0x1E000098,0x00400000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21 0x1E000098,0x00200000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20 0x1E000098,0x00100000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18 0x1E000098,0x00040000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17 0x1E000098,0x00020000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15 0x1E000098,0x00008000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14 0x1E000098,0x00004000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12 0x1E000098,0x00001000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11 0x1E000098,0x00000800
+
+#define IPU_IPU_SDMA_EVENT_14__ADDR                0x1E00009C
+#define IPU_IPU_SDMA_EVENT_14__EMPTY               0x1E00009C,0x00000000
+#define IPU_IPU_SDMA_EVENT_14__FULL                0x1E00009C,0xffffffff
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52 0x1E00009C,0x00100000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51 0x1E00009C,0x00080000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50 0x1E00009C,0x00040000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49 0x1E00009C,0x00020000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48 0x1E00009C,0x00010000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47 0x1E00009C,0x00008000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46 0x1E00009C,0x00004000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45 0x1E00009C,0x00002000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44 0x1E00009C,0x00001000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43 0x1E00009C,0x00000800
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42 0x1E00009C,0x00000400
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41 0x1E00009C,0x00000200
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40 0x1E00009C,0x00000100
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33 0x1E00009C,0x00000002
+
+#define IPU_IPU_SRM_PRI2__ADDR           0x1E0000A4
+#define IPU_IPU_SRM_PRI2__EMPTY          0x1E0000A4,0x00000000
+#define IPU_IPU_SRM_PRI2__FULL           0x1E0000A4,0xffffffff
+#define IPU_IPU_SRM_PRI2__DI1_SRM_MODE   0x1E0000A4,0x18000000
+#define IPU_IPU_SRM_PRI2__DI1_SRM_PRI    0x1E0000A4,0x07000000
+#define IPU_IPU_SRM_PRI2__DI0_SRM_MODE   0x1E0000A4,0x00180000
+#define IPU_IPU_SRM_PRI2__DI0_SRM_PRI    0x1E0000A4,0x00070000
+#define IPU_IPU_SRM_PRI2__DC_6_SRM_MODE  0x1E0000A4,0x0000C000
+#define IPU_IPU_SRM_PRI2__DC_2_SRM_MODE  0x1E0000A4,0x00003000
+#define IPU_IPU_SRM_PRI2__DC_SRM_PRI     0x1E0000A4,0x00000E00
+#define IPU_IPU_SRM_PRI2__DP_A1_SRM_MODE 0x1E0000A4,0x00000180
+#define IPU_IPU_SRM_PRI2__DP_A0_SRM_MODE 0x1E0000A4,0x00000060
+#define IPU_IPU_SRM_PRI2__DP_S_SRM_MODE  0x1E0000A4,0x00000018
+#define IPU_IPU_SRM_PRI2__DP_SRM_PRI     0x1E0000A4,0x00000007
+
+#define IPU_IPU_FS_PROC_FLOW1__ADDR               0x1E0000A8
+#define IPU_IPU_FS_PROC_FLOW1__EMPTY              0x1E0000A8,0x00000000
+#define IPU_IPU_FS_PROC_FLOW1__FULL               0x1E0000A8,0xffffffff
+#define IPU_IPU_FS_PROC_FLOW1__VF_IN_VALID        0x1E0000A8,0x80000000
+#define IPU_IPU_FS_PROC_FLOW1__ENC_IN_VALID       0x1E0000A8,0x40000000
+#define IPU_IPU_FS_PROC_FLOW1__PRP_SRC_SEL        0x1E0000A8,0x0F000000
+#define IPU_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL     0x1E0000A8,0x000F0000
+#define IPU_IPU_FS_PROC_FLOW1__PP_SRC_SEL         0x1E0000A8,0x0000F000
+#define IPU_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL  0x1E0000A8,0x00000F00
+#define IPU_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL 0x1E0000A8,0x0000000F
+
+#define IPU_IPU_FS_PROC_FLOW2__ADDR                0x1E0000AC
+#define IPU_IPU_FS_PROC_FLOW2__EMPTY               0x1E0000AC,0x00000000
+#define IPU_IPU_FS_PROC_FLOW2__FULL                0x1E0000AC,0xffffffff
+#define IPU_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL 0x1E0000AC,0x00F00000
+#define IPU_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL     0x1E0000AC,0x000F0000
+#define IPU_IPU_FS_PROC_FLOW2__PP_DEST_SEL         0x1E0000AC,0x0000F000
+#define IPU_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL  0x1E0000AC,0x00000F00
+#define IPU_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL      0x1E0000AC,0x000000F0
+#define IPU_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL    0x1E0000AC,0x0000000F
+
+#define IPU_IPU_FS_DISP_FLOW1__ADDR              0x1E0000B4
+#define IPU_IPU_FS_DISP_FLOW1__EMPTY             0x1E0000B4,0x00000000
+#define IPU_IPU_FS_DISP_FLOW1__FULL              0x1E0000B4,0xffffffff
+#define IPU_IPU_FS_DISP_FLOW1__DC1_SRC_SEL       0x1E0000B4,0x00F00000
+#define IPU_IPU_FS_DISP_FLOW1__DC2_SRC_SEL       0x1E0000B4,0x000F0000
+#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL 0x1E0000B4,0x0000F000
+#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL 0x1E0000B4,0x00000F00
+#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL  0x1E0000B4,0x000000F0
+#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL  0x1E0000B4,0x0000000F
+
+#define IPU_IPU_FS_DISP_FLOW2__ADDR                  0x1E0000B8
+#define IPU_IPU_FS_DISP_FLOW2__EMPTY                 0x1E0000B8,0x00000000
+#define IPU_IPU_FS_DISP_FLOW2__FULL                  0x1E0000B8,0xffffffff
+#define IPU_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL       0x1E0000B8,0x000F0000
+#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL 0x1E0000B8,0x000000F0
+#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL 0x1E0000B8,0x0000000F
+
+#define IPU_IPU_DISP_GEN__ADDR                 0x1E0000C4
+#define IPU_IPU_DISP_GEN__EMPTY                0x1E0000C4,0x00000000
+#define IPU_IPU_DISP_GEN__FULL                 0x1E0000C4,0xffffffff
+#define IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE  0x1E0000C4,0x02000000
+#define IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE  0x1E0000C4,0x01000000
+#define IPU_IPU_DISP_GEN__MCU_MAX_BURST_STOP   0x1E0000C4,0x00400000
+#define IPU_IPU_DISP_GEN__MCU_T                0x1E0000C4,0x003C0000
+#define IPU_IPU_DISP_GEN__MCU_DI_ID_9          0x1E0000C4,0x00020000
+#define IPU_IPU_DISP_GEN__MCU_DI_ID_8          0x1E0000C4,0x00010000
+#define IPU_IPU_DISP_GEN__DP_PIPE_CLR          0x1E0000C4,0x00000040
+#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC1      0x1E0000C4,0x00000020
+#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC0      0x1E0000C4,0x00000010
+#define IPU_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW 0x1E0000C4,0x00000008
+#define IPU_IPU_DISP_GEN__DC2_DOUBLE_FLOW      0x1E0000C4,0x00000004
+#define IPU_IPU_DISP_GEN__DI1_DUAL_MODE        0x1E0000C4,0x00000002
+#define IPU_IPU_DISP_GEN__DI0_DUAL_MODE        0x1E0000C4,0x00000001
+
+#define IPU_IPU_DISP_ALT1__ADDR                  0x1E0000C8
+#define IPU_IPU_DISP_ALT1__EMPTY                 0x1E0000C8,0x00000000
+#define IPU_IPU_DISP_ALT1__FULL                  0x1E0000C8,0xffffffff
+#define IPU_IPU_DISP_ALT1__SEL_ALT_0             0x1E0000C8,0xF0000000
+#define IPU_IPU_DISP_ALT1__STEP_REPEAT_ALT_0     0x1E0000C8,0x0FFF0000
+#define IPU_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0 0x1E0000C8,0x00008000
+#define IPU_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0     0x1E0000C8,0x00007000
+#define IPU_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0    0x1E0000C8,0x00000FFF
+
+#define IPU_IPU_DISP_ALT2__ADDR                    0x1E0000CC
+#define IPU_IPU_DISP_ALT2__EMPTY                   0x1E0000CC,0x00000000
+#define IPU_IPU_DISP_ALT2__FULL                    0x1E0000CC,0xffffffff
+#define IPU_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0    0x1E0000CC,0x00070000
+#define IPU_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0 0x1E0000CC,0x00007000
+#define IPU_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0      0x1E0000CC,0x00000FFF
+
+#define IPU_IPU_DISP_ALT3__ADDR                  0x1E0000D0
+#define IPU_IPU_DISP_ALT3__EMPTY                 0x1E0000D0,0x00000000
+#define IPU_IPU_DISP_ALT3__FULL                  0x1E0000D0,0xffffffff
+#define IPU_IPU_DISP_ALT3__SEL_ALT_1             0x1E0000D0,0xF0000000
+#define IPU_IPU_DISP_ALT3__STEP_REPEAT_ALT_1     0x1E0000D0,0x0FFF0000
+#define IPU_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1 0x1E0000D0,0x00008000
+#define IPU_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1     0x1E0000D0,0x00007000
+#define IPU_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1    0x1E0000D0,0x00000FFF
+
+#define IPU_IPU_DISP_ALT4__ADDR                    0x1E0000D4
+#define IPU_IPU_DISP_ALT4__EMPTY                   0x1E0000D4,0x00000000
+#define IPU_IPU_DISP_ALT4__FULL                    0x1E0000D4,0xffffffff
+#define IPU_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1    0x1E0000D4,0x00070000
+#define IPU_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1 0x1E0000D4,0x00007000
+#define IPU_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1      0x1E0000D4,0x00000FFF
+
+#define IPU_IPU_SNOOP__ADDR            0x1E0000D8
+#define IPU_IPU_SNOOP__EMPTY           0x1E0000D8,0x00000000
+#define IPU_IPU_SNOOP__FULL            0x1E0000D8,0xffffffff
+#define IPU_IPU_SNOOP__SNOOP2_SYNC_BYP 0x1E0000D8,0x00010000
+#define IPU_IPU_SNOOP__AUTOREF_PER     0x1E0000D8,0x000003FF
+
+#define IPU_IPU_MEM_RST__ADDR          0x1E0000DC
+#define IPU_IPU_MEM_RST__EMPTY         0x1E0000DC,0x00000000
+#define IPU_IPU_MEM_RST__FULL          0x1E0000DC,0xffffffff
+#define IPU_IPU_MEM_RST__RST_MEM_START 0x1E0000DC,0x80000000
+#define IPU_IPU_MEM_RST__RST_MEM_EN    0x1E0000DC,0x007FFFFF
+
+#define IPU_IPU_PM__ADDR                      0x1E0000E0
+#define IPU_IPU_PM__EMPTY                     0x1E0000E0,0x00000000
+#define IPU_IPU_PM__FULL                      0x1E0000E0,0xffffffff
+#define IPU_IPU_PM__LPSR_MODE                 0x1E0000E0,0x80000000
+#define IPU_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x40000000
+#define IPU_IPU_PM__DI1_CLK_PERIOD_1          0x1E0000E0,0x3F800000
+#define IPU_IPU_PM__DI1_CLK_PERIOD_0          0x1E0000E0,0x007F0000
+#define IPU_IPU_PM__CLOCK_MODE_STAT           0x1E0000E0,0x00008000
+#define IPU_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x00004000
+#define IPU_IPU_PM__DI0_CLK_PERIOD_1          0x1E0000E0,0x00003F80
+#define IPU_IPU_PM__DI0_CLK_PERIOD_0          0x1E0000E0,0x0000007F
+
+#define IPU_IPU_GPR__ADDR                     0x1E0000E4
+#define IPU_IPU_GPR__EMPTY                    0x1E0000E4,0x00000000
+#define IPU_IPU_GPR__FULL                     0x1E0000E4,0xffffffff
+#define IPU_IPU_GPR__IPU_CH_BUF1_RDY1_CLR     0x1E0000E4,0x80000000
+#define IPU_IPU_GPR__IPU_CH_BUF1_RDY0_CLR     0x1E0000E4,0x40000000
+#define IPU_IPU_GPR__IPU_CH_BUF0_RDY1_CLR     0x1E0000E4,0x20000000
+#define IPU_IPU_GPR__IPU_CH_BUF0_RDY0_CLR     0x1E0000E4,0x10000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR 0x1E0000E4,0x08000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR 0x1E0000E4,0x04000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR 0x1E0000E4,0x02000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR 0x1E0000E4,0x01000000
+#define IPU_IPU_GPR__IPU_DI1_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00800000
+#define IPU_IPU_GPR__IPU_DI0_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00400000
+#define IPU_IPU_GPR__IPU_GP21                 0x1E0000E4,0x00200000
+#define IPU_IPU_GPR__IPU_GP20                 0x1E0000E4,0x00100000
+#define IPU_IPU_GPR__IPU_GP19                 0x1E0000E4,0x00080000
+#define IPU_IPU_GPR__IPU_GP18                 0x1E0000E4,0x00040000
+#define IPU_IPU_GPR__IPU_GP17                 0x1E0000E4,0x00020000
+#define IPU_IPU_GPR__IPU_GP16                 0x1E0000E4,0x00010000
+#define IPU_IPU_GPR__IPU_GP15                 0x1E0000E4,0x00008000
+#define IPU_IPU_GPR__IPU_GP14                 0x1E0000E4,0x00004000
+#define IPU_IPU_GPR__IPU_GP13                 0x1E0000E4,0x00002000
+#define IPU_IPU_GPR__IPU_GP12                 0x1E0000E4,0x00001000
+#define IPU_IPU_GPR__IPU_GP11                 0x1E0000E4,0x00000800
+#define IPU_IPU_GPR__IPU_GP10                 0x1E0000E4,0x00000400
+#define IPU_IPU_GPR__IPU_GP9                  0x1E0000E4,0x00000200
+#define IPU_IPU_GPR__IPU_GP8                  0x1E0000E4,0x00000100
+#define IPU_IPU_GPR__IPU_GP7                  0x1E0000E4,0x00000080
+#define IPU_IPU_GPR__IPU_GP6                  0x1E0000E4,0x00000040
+#define IPU_IPU_GPR__IPU_GP5                  0x1E0000E4,0x00000020
+#define IPU_IPU_GPR__IPU_GP4                  0x1E0000E4,0x00000010
+#define IPU_IPU_GPR__IPU_GP3                  0x1E0000E4,0x00000008
+#define IPU_IPU_GPR__IPU_GP2                  0x1E0000E4,0x00000004
+#define IPU_IPU_GPR__IPU_GP1                  0x1E0000E4,0x00000002
+#define IPU_IPU_GPR__IPU_GP0                  0x1E0000E4,0x00000001
+
+#define IPU_IPU_INT_STAT_1__ADDR         0x1E0000E8
+#define IPU_IPU_INT_STAT_1__EMPTY        0x1E0000E8,0x00000000
+#define IPU_IPU_INT_STAT_1__FULL         0x1E0000E8,0xffffffff
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_31 0x1E0000E8,0x80000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_29 0x1E0000E8,0x20000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_28 0x1E0000E8,0x10000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_27 0x1E0000E8,0x08000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_24 0x1E0000E8,0x01000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_23 0x1E0000E8,0x00800000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_22 0x1E0000E8,0x00400000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_21 0x1E0000E8,0x00200000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_20 0x1E0000E8,0x00100000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_18 0x1E0000E8,0x00040000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_17 0x1E0000E8,0x00020000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_15 0x1E0000E8,0x00008000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_14 0x1E0000E8,0x00004000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_12 0x1E0000E8,0x00001000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_11 0x1E0000E8,0x00000800
+
+#define IPU_IPU_INT_STAT_2__ADDR         0x1E0000EC
+#define IPU_IPU_INT_STAT_2__EMPTY        0x1E0000EC,0x00000000
+#define IPU_IPU_INT_STAT_2__FULL         0x1E0000EC,0xffffffff
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_52 0x1E0000EC,0x00100000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_51 0x1E0000EC,0x00080000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_50 0x1E0000EC,0x00040000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_49 0x1E0000EC,0x00020000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_48 0x1E0000EC,0x00010000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_47 0x1E0000EC,0x00008000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_46 0x1E0000EC,0x00004000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_45 0x1E0000EC,0x00002000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_44 0x1E0000EC,0x00001000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_43 0x1E0000EC,0x00000800
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_42 0x1E0000EC,0x00000400
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_41 0x1E0000EC,0x00000200
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_40 0x1E0000EC,0x00000100
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_33 0x1E0000EC,0x00000002
+
+#define IPU_IPU_INT_STAT_3__ADDR           0x1E0000F0
+#define IPU_IPU_INT_STAT_3__EMPTY          0x1E0000F0,0x00000000
+#define IPU_IPU_INT_STAT_3__FULL           0x1E0000F0,0xffffffff
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_31 0x1E0000F0,0x80000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_29 0x1E0000F0,0x20000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_28 0x1E0000F0,0x10000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_27 0x1E0000F0,0x08000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_24 0x1E0000F0,0x01000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_23 0x1E0000F0,0x00800000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_22 0x1E0000F0,0x00400000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_21 0x1E0000F0,0x00200000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_20 0x1E0000F0,0x00100000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_18 0x1E0000F0,0x00040000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_17 0x1E0000F0,0x00020000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_15 0x1E0000F0,0x00008000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_14 0x1E0000F0,0x00004000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_12 0x1E0000F0,0x00001000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_11 0x1E0000F0,0x00000800
+
+#define IPU_IPU_INT_STAT_4__ADDR           0x1E0000F4
+#define IPU_IPU_INT_STAT_4__EMPTY          0x1E0000F4,0x00000000
+#define IPU_IPU_INT_STAT_4__FULL           0x1E0000F4,0xffffffff
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_52 0x1E0000F4,0x00100000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_51 0x1E0000F4,0x00080000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_50 0x1E0000F4,0x00040000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_49 0x1E0000F4,0x00020000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_48 0x1E0000F4,0x00010000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_47 0x1E0000F4,0x00008000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_46 0x1E0000F4,0x00004000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_45 0x1E0000F4,0x00002000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_44 0x1E0000F4,0x00001000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_43 0x1E0000F4,0x00000800
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_42 0x1E0000F4,0x00000400
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_41 0x1E0000F4,0x00000200
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_40 0x1E0000F4,0x00000100
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_33 0x1E0000F4,0x00000002
+
+#define IPU_IPU_INT_STAT_5__ADDR                 0x1E0000F8
+#define IPU_IPU_INT_STAT_5__EMPTY                0x1E0000F8,0x00000000
+#define IPU_IPU_INT_STAT_5__FULL                 0x1E0000F8,0xffffffff
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_31 0x1E0000F8,0x80000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_29 0x1E0000F8,0x20000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_28 0x1E0000F8,0x10000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_27 0x1E0000F8,0x08000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_24 0x1E0000F8,0x01000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_23 0x1E0000F8,0x00800000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_22 0x1E0000F8,0x00400000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_21 0x1E0000F8,0x00200000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_20 0x1E0000F8,0x00100000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_18 0x1E0000F8,0x00040000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_17 0x1E0000F8,0x00020000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_15 0x1E0000F8,0x00008000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_14 0x1E0000F8,0x00004000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_12 0x1E0000F8,0x00001000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_11 0x1E0000F8,0x00000800
+
+#define IPU_IPU_INT_STAT_6__ADDR                 0x1E0000FC
+#define IPU_IPU_INT_STAT_6__EMPTY                0x1E0000FC,0x00000000
+#define IPU_IPU_INT_STAT_6__FULL                 0x1E0000FC,0xffffffff
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_52 0x1E0000FC,0x00100000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_51 0x1E0000FC,0x00080000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_50 0x1E0000FC,0x00040000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_49 0x1E0000FC,0x00020000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_48 0x1E0000FC,0x00010000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_47 0x1E0000FC,0x00008000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_46 0x1E0000FC,0x00004000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_45 0x1E0000FC,0x00002000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_44 0x1E0000FC,0x00001000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_43 0x1E0000FC,0x00000800
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_42 0x1E0000FC,0x00000400
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_41 0x1E0000FC,0x00000200
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_40 0x1E0000FC,0x00000100
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_33 0x1E0000FC,0x00000002
+
+#define IPU_IPU_INT_STAT_7__ADDR         0x1E000100
+#define IPU_IPU_INT_STAT_7__EMPTY        0x1E000100,0x00000000
+#define IPU_IPU_INT_STAT_7__FULL         0x1E000100,0xffffffff
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_31 0x1E000100,0x80000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_29 0x1E000100,0x20000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_28 0x1E000100,0x10000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_27 0x1E000100,0x08000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_24 0x1E000100,0x01000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_23 0x1E000100,0x00800000
+
+#define IPU_IPU_INT_STAT_8__ADDR         0x1E000104
+#define IPU_IPU_INT_STAT_8__EMPTY        0x1E000104,0x00000000
+#define IPU_IPU_INT_STAT_8__FULL         0x1E000104,0xffffffff
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_52 0x1E000104,0x00100000
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_51 0x1E000104,0x00080000
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_44 0x1E000104,0x00001000
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_43 0x1E000104,0x00000800
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_42 0x1E000104,0x00000400
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_41 0x1E000104,0x00000200
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_32 0x1E000104,0x00000002
+
+#define IPU_IPU_INT_STAT_10__ADDR                   0x1E00010C
+#define IPU_IPU_INT_STAT_10__EMPTY                  0x1E00010C,0x00000000
+#define IPU_IPU_INT_STAT_10__FULL                   0x1E00010C,0xffffffff
+#define IPU_IPU_INT_STAT_10__AXIR_ERR               0x1E00010C,0x40000000
+#define IPU_IPU_INT_STAT_10__AXIW_ERR               0x1E00010C,0x20000000
+#define IPU_IPU_INT_STAT_10__NON_PRIVILEGED_ACC_ERR 0x1E00010C,0x10000000
+#define IPU_IPU_INT_STAT_10__IC_BAYER_FRM_LOST_ERR  0x1E00010C,0x04000000
+#define IPU_IPU_INT_STAT_10__IC_ENC_FRM_LOST_ERR    0x1E00010C,0x02000000
+#define IPU_IPU_INT_STAT_10__IC_VF_FRM_LOST_ERR     0x1E00010C,0x01000000
+#define IPU_IPU_INT_STAT_10__DI1_TIME_OUT_ERR       0x1E00010C,0x00400000
+#define IPU_IPU_INT_STAT_10__DI0_TIME_OUT_ERR       0x1E00010C,0x00200000
+#define IPU_IPU_INT_STAT_10__DI1_SYNC_DISP_ERR      0x1E00010C,0x00100000
+#define IPU_IPU_INT_STAT_10__DI0_SYNC_DISP_ERR      0x1E00010C,0x00080000
+#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_6       0x1E00010C,0x00040000
+#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_2       0x1E00010C,0x00020000
+#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_1       0x1E00010C,0x00010000
+
+#define IPU_IPU_INT_STAT_11__ADDR           0x1E000110
+#define IPU_IPU_INT_STAT_11__EMPTY          0x1E000110,0x00000000
+#define IPU_IPU_INT_STAT_11__FULL           0x1E000110,0xffffffff
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_22 0x1E000110,0x00400000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_21 0x1E000110,0x00200000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_20 0x1E000110,0x00100000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_12 0x1E000110,0x00001000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_11 0x1E000110,0x00000800
+
+#define IPU_IPU_INT_STAT_12__ADDR           0x1E000114
+#define IPU_IPU_INT_STAT_12__EMPTY          0x1E000114,0x00000000
+#define IPU_IPU_INT_STAT_12__FULL           0x1E000114,0xffffffff
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_50 0x1E000114,0x00040000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_49 0x1E000114,0x00020000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_48 0x1E000114,0x00010000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_47 0x1E000114,0x00008000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_46 0x1E000114,0x00004000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_45 0x1E000114,0x00002000
+
+#define IPU_IPU_INT_STAT_13__ADDR        0x1E000118
+#define IPU_IPU_INT_STAT_13__EMPTY       0x1E000118,0x00000000
+#define IPU_IPU_INT_STAT_13__FULL        0x1E000118,0xffffffff
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_31 0x1E000118,0x80000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_29 0x1E000118,0x20000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_28 0x1E000118,0x10000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_27 0x1E000118,0x08000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_24 0x1E000118,0x01000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_23 0x1E000118,0x00800000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_22 0x1E000118,0x00400000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_21 0x1E000118,0x00200000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_20 0x1E000118,0x00100000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_18 0x1E000118,0x00040000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_17 0x1E000118,0x00020000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_15 0x1E000118,0x00008000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_14 0x1E000118,0x00004000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_12 0x1E000118,0x00001000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_11 0x1E000118,0x00000800
+
+#define IPU_IPU_INT_STAT_14__ADDR        0x1E00011C
+#define IPU_IPU_INT_STAT_14__EMPTY       0x1E00011C,0x00000000
+#define IPU_IPU_INT_STAT_14__FULL        0x1E00011C,0xffffffff
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_52 0x1E00011C,0x00100000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_51 0x1E00011C,0x00080000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_50 0x1E00011C,0x00040000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_49 0x1E00011C,0x00020000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_48 0x1E00011C,0x00010000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_47 0x1E00011C,0x00008000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_46 0x1E00011C,0x00004000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_45 0x1E00011C,0x00002000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_44 0x1E00011C,0x00001000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_43 0x1E00011C,0x00000800
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_42 0x1E00011C,0x00000400
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_41 0x1E00011C,0x00000200
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_40 0x1E00011C,0x00000100
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_33 0x1E00011C,0x00000002
+
+#define IPU_IPU_INT_STAT_15__ADDR                0x1E000120
+#define IPU_IPU_INT_STAT_15__EMPTY               0x1E000120,0x00000000
+#define IPU_IPU_INT_STAT_15__FULL                0x1E000120,0xffffffff
+#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_8    0x1E000120,0x80000000
+#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_3    0x1E000120,0x40000000
+#define IPU_IPU_INT_STAT_15__DI1_DISP_CLK_EN_PRE 0x1E000120,0x20000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_10   0x1E000120,0x10000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_9    0x1E000120,0x08000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_8    0x1E000120,0x04000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_7    0x1E000120,0x02000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_6    0x1E000120,0x01000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_5    0x1E000120,0x00800000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_4    0x1E000120,0x00400000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_3    0x1E000120,0x00200000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_2    0x1E000120,0x00100000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_1    0x1E000120,0x00080000
+#define IPU_IPU_INT_STAT_15__DI0_DISP_CLK_EN_PRE 0x1E000120,0x00040000
+#define IPU_IPU_INT_STAT_15__DC_ASYNC_STOP       0x1E000120,0x00020000
+#define IPU_IPU_INT_STAT_15__DC_DP_START         0x1E000120,0x00010000
+#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_1      0x1E000120,0x00008000
+#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_0      0x1E000120,0x00004000
+#define IPU_IPU_INT_STAT_15__DC_FC_6             0x1E000120,0x00002000
+#define IPU_IPU_INT_STAT_15__DC_FC_4             0x1E000120,0x00001000
+#define IPU_IPU_INT_STAT_15__DC_FC_3             0x1E000120,0x00000800
+#define IPU_IPU_INT_STAT_15__DC_FC_2             0x1E000120,0x00000400
+#define IPU_IPU_INT_STAT_15__DC_FC_1             0x1E000120,0x00000200
+#define IPU_IPU_INT_STAT_15__DC_FC_0             0x1E000120,0x00000100
+#define IPU_IPU_INT_STAT_15__DP_ASF_BRAKE        0x1E000120,0x00000080
+#define IPU_IPU_INT_STAT_15__DP_SF_BRAKE         0x1E000120,0x00000040
+#define IPU_IPU_INT_STAT_15__DP_ASF_END          0x1E000120,0x00000020
+#define IPU_IPU_INT_STAT_15__DP_ASF_START        0x1E000120,0x00000010
+#define IPU_IPU_INT_STAT_15__DP_SF_END           0x1E000120,0x00000008
+#define IPU_IPU_INT_STAT_15__DP_SF_START         0x1E000120,0x00000004
+#define IPU_IPU_INT_STAT_15__IPU_SNOOPING2_INT   0x1E000120,0x00000002
+#define IPU_IPU_INT_STAT_15__IPU_SNOOPING1_INT   0x1E000120,0x00000001
+
+#define IPU_IPU_CUR_BUF_0__ADDR              0x1E000124
+#define IPU_IPU_CUR_BUF_0__EMPTY             0x1E000124,0x00000000
+#define IPU_IPU_CUR_BUF_0__FULL              0x1E000124,0xffffffff
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_31 0x1E000124,0x80000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_29 0x1E000124,0x20000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_28 0x1E000124,0x10000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_27 0x1E000124,0x08000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_24 0x1E000124,0x01000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_23 0x1E000124,0x00800000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_22 0x1E000124,0x00400000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_21 0x1E000124,0x00200000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_20 0x1E000124,0x00100000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_18 0x1E000124,0x00040000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_17 0x1E000124,0x00020000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_15 0x1E000124,0x00008000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_14 0x1E000124,0x00004000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_12 0x1E000124,0x00001000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_11 0x1E000124,0x00000800
+
+#define IPU_IPU_CUR_BUF_1__ADDR              0x1E000128
+#define IPU_IPU_CUR_BUF_1__EMPTY             0x1E000128,0x00000000
+#define IPU_IPU_CUR_BUF_1__FULL              0x1E000128,0xffffffff
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_52 0x1E000128,0x00100000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_51 0x1E000128,0x00080000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_50 0x1E000128,0x00040000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_49 0x1E000128,0x00020000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_48 0x1E000128,0x00010000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_47 0x1E000128,0x00008000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_46 0x1E000128,0x00004000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_45 0x1E000128,0x00002000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_44 0x1E000128,0x00001000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_43 0x1E000128,0x00000800
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_42 0x1E000128,0x00000400
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_41 0x1E000128,0x00000200
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_40 0x1E000128,0x00000100
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_33 0x1E000128,0x00000002
+
+#define IPU_IPU_ALT_CUR_BUF_0__ADDR                  0x1E00012C
+#define IPU_IPU_ALT_CUR_BUF_0__EMPTY                 0x1E00012C,0x00000000
+#define IPU_IPU_ALT_CUR_BUF_0__FULL                  0x1E00012C,0xffffffff
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_29 0x1E00012C,0x20000000
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_24 0x1E00012C,0x01000000
+
+#define IPU_IPU_ALT_CUR_BUF_1__ADDR                  0x1E000130
+#define IPU_IPU_ALT_CUR_BUF_1__EMPTY                 0x1E000130,0x00000000
+#define IPU_IPU_ALT_CUR_BUF_1__FULL                  0x1E000130,0xffffffff
+#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_52 0x1E000130,0x00100000
+#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_41 0x1E000130,0x00000200
+#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_33 0x1E000130,0x00000002
+
+#define IPU_IPU_SRM_STAT__ADDR           0x1E000134
+#define IPU_IPU_SRM_STAT__EMPTY          0x1E000134,0x00000000
+#define IPU_IPU_SRM_STAT__FULL           0x1E000134,0xffffffff
+#define IPU_IPU_SRM_STAT__DI1_SRM_STAT   0x1E000134,0x00000200
+#define IPU_IPU_SRM_STAT__DI0_SRM_STAT   0x1E000134,0x00000100
+#define IPU_IPU_SRM_STAT__DC_6_SRM_STAT  0x1E000134,0x00000020
+#define IPU_IPU_SRM_STAT__DC_2_SRM_STAT  0x1E000134,0x00000010
+#define IPU_IPU_SRM_STAT__DP_A1_SRM_STAT 0x1E000134,0x00000004
+#define IPU_IPU_SRM_STAT__DP_A0_SRM_STAT 0x1E000134,0x00000002
+#define IPU_IPU_SRM_STAT__DP_S_SRM_STAT  0x1E000134,0x00000001
+
+#define IPU_IPU_DISP_TASKS_STAT__ADDR               0x1E00013C
+#define IPU_IPU_DISP_TASKS_STAT__EMPTY              0x1E00013C,0x00000000
+#define IPU_IPU_DISP_TASKS_STAT__FULL               0x1E00013C,0xffffffff
+#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC1_CUR_FLOW 0x1E00013C,0x00000800
+#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC1_TSTAT    0x1E00013C,0x00000700
+#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC0_TSTAT    0x1E00013C,0x00000030
+#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_CUR_FLOW  0x1E00013C,0x00000008
+#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_TSTAT     0x1E00013C,0x00000007
+
+#define IPU_IPU_CH_BUF0_RDY0__ADDR               0x1E000140
+#define IPU_IPU_CH_BUF0_RDY0__EMPTY              0x1E000140,0x00000000
+#define IPU_IPU_CH_BUF0_RDY0__FULL               0x1E000140,0xffffffff
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_31 0x1E000140,0x80000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_29 0x1E000140,0x20000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_28 0x1E000140,0x10000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_27 0x1E000140,0x08000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_24 0x1E000140,0x01000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_23 0x1E000140,0x00800000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_22 0x1E000140,0x00400000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_21 0x1E000140,0x00200000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_20 0x1E000140,0x00100000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_18 0x1E000140,0x00040000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_17 0x1E000140,0x00020000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_15 0x1E000140,0x00008000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_14 0x1E000140,0x00004000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_12 0x1E000140,0x00001000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_11 0x1E000140,0x00000800
+
+#define IPU_IPU_CH_BUF0_RDY1__ADDR               0x1E000144
+#define IPU_IPU_CH_BUF0_RDY1__EMPTY              0x1E000144,0x00000000
+#define IPU_IPU_CH_BUF0_RDY1__FULL               0x1E000144,0xffffffff
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_52 0x1E000144,0x00100000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_51 0x1E000144,0x00080000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_50 0x1E000144,0x00040000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_49 0x1E000144,0x00020000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_48 0x1E000144,0x00010000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_47 0x1E000144,0x00008000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_46 0x1E000144,0x00004000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_45 0x1E000144,0x00002000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_44 0x1E000144,0x00001000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_43 0x1E000144,0x00000800
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_42 0x1E000144,0x00000400
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_41 0x1E000144,0x00000200
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_40 0x1E000144,0x00000100
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_33 0x1E000144,0x00000002
+
+#define IPU_IPU_CH_BUF1_RDY0__ADDR               0x1E000148
+#define IPU_IPU_CH_BUF1_RDY0__EMPTY              0x1E000148,0x00000000
+#define IPU_IPU_CH_BUF1_RDY0__FULL               0x1E000148,0xffffffff
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_31 0x1E000148,0x80000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_29 0x1E000148,0x20000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_28 0x1E000148,0x10000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_27 0x1E000148,0x08000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_24 0x1E000148,0x01000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_23 0x1E000148,0x00800000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_22 0x1E000148,0x00400000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_21 0x1E000148,0x00200000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_20 0x1E000148,0x00100000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_18 0x1E000148,0x00040000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_17 0x1E000148,0x00020000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_15 0x1E000148,0x00008000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_14 0x1E000148,0x00004000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_12 0x1E000148,0x00001000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_11 0x1E000148,0x00000800
+
+#define IPU_IPU_CH_BUF1_RDY1__ADDR               0x1E00014C
+#define IPU_IPU_CH_BUF1_RDY1__EMPTY              0x1E00014C,0x00000000
+#define IPU_IPU_CH_BUF1_RDY1__FULL               0x1E00014C,0xffffffff
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_52 0x1E00014C,0x00100000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_51 0x1E00014C,0x00080000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_50 0x1E00014C,0x00040000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_49 0x1E00014C,0x00020000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_48 0x1E00014C,0x00010000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_47 0x1E00014C,0x00008000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_46 0x1E00014C,0x00004000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_45 0x1E00014C,0x00002000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_44 0x1E00014C,0x00001000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_43 0x1E00014C,0x00000800
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_42 0x1E00014C,0x00000400
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_41 0x1E00014C,0x00000200
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_40 0x1E00014C,0x00000100
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_33 0x1E00014C,0x00000002
+
+#define IPU_IPU_CH_DB_MODE_SEL_0__ADDR                  0x1E000150
+#define IPU_IPU_CH_DB_MODE_SEL_0__EMPTY                 0x1E000150,0x00000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__FULL                  0x1E000150,0xffffffff
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_31 0x1E000150,0x80000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_29 0x1E000150,0x20000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_28 0x1E000150,0x10000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_27 0x1E000150,0x08000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_24 0x1E000150,0x01000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_23 0x1E000150,0x00800000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_22 0x1E000150,0x00400000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_21 0x1E000150,0x00200000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_20 0x1E000150,0x00100000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_18 0x1E000150,0x00040000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_17 0x1E000150,0x00020000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_15 0x1E000150,0x00008000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_14 0x1E000150,0x00004000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_12 0x1E000150,0x00001000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_11 0x1E000150,0x00000800
+
+#define IPU_IPU_CH_DB_MODE_SEL_1__ADDR                  0x1E000154
+#define IPU_IPU_CH_DB_MODE_SEL_1__EMPTY                 0x1E000154,0x00000000
+#define IPU_IPU_CH_DB_MODE_SEL_1__FULL                  0x1E000154,0xffffffff
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_52 0x1E000154,0x00100000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_51 0x1E000154,0x00080000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_50 0x1E000154,0x00040000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_49 0x1E000154,0x00020000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_48 0x1E000154,0x00010000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_47 0x1E000154,0x00008000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_46 0x1E000154,0x00004000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_45 0x1E000154,0x00002000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_44 0x1E000154,0x00001000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_43 0x1E000154,0x00000800
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_42 0x1E000154,0x00000400
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_41 0x1E000154,0x00000200
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_40 0x1E000154,0x00000100
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_33 0x1E000154,0x00000002
+
+#define IPU_IPU_ALT_CH_BUF0_RDY0__ADDR                   0x1E000158
+#define IPU_IPU_ALT_CH_BUF0_RDY0__EMPTY                  0x1E000158,0x00000000
+#define IPU_IPU_ALT_CH_BUF0_RDY0__FULL                   0x1E000158,0xffffffff
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_29 0x1E000158,0x20000000
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_24 0x1E000158,0x01000000
+
+#define IPU_IPU_ALT_CH_BUF0_RDY1__ADDR                   0x1E00015C
+#define IPU_IPU_ALT_CH_BUF0_RDY1__EMPTY                  0x1E00015C,0x00000000
+#define IPU_IPU_ALT_CH_BUF0_RDY1__FULL                   0x1E00015C,0xffffffff
+#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_52 0x1E00015C,0x00100000
+#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_41 0x1E00015C,0x00000200
+#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_33 0x1E00015C,0x00000002
+
+#define IPU_IPU_ALT_CH_BUF1_RDY0__ADDR                   0x1E000160
+#define IPU_IPU_ALT_CH_BUF1_RDY0__EMPTY                  0x1E000160,0x00000000
+#define IPU_IPU_ALT_CH_BUF1_RDY0__FULL                   0x1E000160,0xffffffff
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_29 0x1E000160,0x20000000
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_24 0x1E000160,0x01000000
+
+#define IPU_IPU_ALT_CH_BUF1_RDY1__ADDR                   0x1E000164
+#define IPU_IPU_ALT_CH_BUF1_RDY1__EMPTY                  0x1E000164,0x00000000
+#define IPU_IPU_ALT_CH_BUF1_RDY1__FULL                   0x1E000164,0xffffffff
+#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_52 0x1E000164,0x00100000
+#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_41 0x1E000164,0x00000200
+#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_33 0x1E000164,0x00000002
+
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__ADDR                      0x1E000168
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__EMPTY                     0x1E000168,0x00000000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__FULL                      0x1E000168,0xffffffff
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_29 0x1E000168,0x20000000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_24 0x1E000168,0x01000000
+
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__ADDR                      0x1E00016C
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__EMPTY                     0x1E00016C,0x00000000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__FULL                      0x1E00016C,0xffffffff
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_52 0x1E00016C,0x00100000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_41 0x1E00016C,0x00000200
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_33 0x1E00016C,0x00000002
+
+#define IPU_IDMAC_CONF__ADDR         0x1E008000
+#define IPU_IDMAC_CONF__EMPTY        0x1E008000,0x00000000
+#define IPU_IDMAC_CONF__FULL         0x1E008000,0xffffffff
+#define IPU_IDMAC_CONF__P_ENDIAN     0x1E008000,0x00010000
+#define IPU_IDMAC_CONF__WIDPT        0x1E008000,0x00000018
+#define IPU_IDMAC_CONF__MAX_REQ_READ 0x1E008000,0x00000007
+
+#define IPU_IDMAC_CH_EN_1__ADDR           0x1E008004
+#define IPU_IDMAC_CH_EN_1__EMPTY          0x1E008004,0x00000000
+#define IPU_IDMAC_CH_EN_1__FULL           0x1E008004,0xffffffff
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_31 0x1E008004,0x80000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_29 0x1E008004,0x20000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_28 0x1E008004,0x10000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_27 0x1E008004,0x08000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_24 0x1E008004,0x01000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_23 0x1E008004,0x00800000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_22 0x1E008004,0x00400000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_21 0x1E008004,0x00200000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_20 0x1E008004,0x00100000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_18 0x1E008004,0x00040000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_17 0x1E008004,0x00020000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_15 0x1E008004,0x00008000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_14 0x1E008004,0x00004000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_12 0x1E008004,0x00001000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_11 0x1E008004,0x00000800
+
+#define IPU_IDMAC_CH_EN_2__ADDR           0x1E008008
+#define IPU_IDMAC_CH_EN_2__EMPTY          0x1E008008,0x00000000
+#define IPU_IDMAC_CH_EN_2__FULL           0x1E008008,0xffffffff
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_52 0x1E008008,0x00100000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_51 0x1E008008,0x00080000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_50 0x1E008008,0x00040000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_49 0x1E008008,0x00020000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_48 0x1E008008,0x00010000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_47 0x1E008008,0x00008000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_46 0x1E008008,0x00004000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_45 0x1E008008,0x00002000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_44 0x1E008008,0x00001000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_43 0x1E008008,0x00000800
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_42 0x1E008008,0x00000400
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_41 0x1E008008,0x00000200
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_40 0x1E008008,0x00000100
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_33 0x1E008008,0x00000002
+
+#define IPU_IDMAC_SEP_ALPHA__ADDR            0x1E00800C
+#define IPU_IDMAC_SEP_ALPHA__EMPTY           0x1E00800C,0x00000000
+#define IPU_IDMAC_SEP_ALPHA__FULL            0x1E00800C,0xffffffff
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29 0x1E00800C,0x20000000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27 0x1E00800C,0x08000000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24 0x1E00800C,0x01000000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23 0x1E00800C,0x00800000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15 0x1E00800C,0x00008000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14 0x1E00800C,0x00004000
+
+#define IPU_IDMAC_ALT_SEP_ALPHA__ADDR                0x1E008010
+#define IPU_IDMAC_ALT_SEP_ALPHA__EMPTY               0x1E008010,0x00000000
+#define IPU_IDMAC_ALT_SEP_ALPHA__FULL                0x1E008010,0xffffffff
+#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29 0x1E008010,0x20000000
+#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24 0x1E008010,0x01000000
+#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23 0x1E008010,0x00800000
+
+#define IPU_IDMAC_CH_PRI_1__ADDR            0x1E008014
+#define IPU_IDMAC_CH_PRI_1__EMPTY           0x1E008014,0x00000000
+#define IPU_IDMAC_CH_PRI_1__FULL            0x1E008014,0xffffffff
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29 0x1E008014,0x20000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28 0x1E008014,0x10000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27 0x1E008014,0x08000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24 0x1E008014,0x01000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23 0x1E008014,0x00800000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22 0x1E008014,0x00400000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21 0x1E008014,0x00200000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20 0x1E008014,0x00100000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15 0x1E008014,0x00008000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14 0x1E008014,0x00004000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12 0x1E008014,0x00001000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11 0x1E008014,0x00000800
+
+#define IPU_IDMAC_CH_PRI_2__ADDR            0x1E008018
+#define IPU_IDMAC_CH_PRI_2__EMPTY           0x1E008018,0x00000000
+#define IPU_IDMAC_CH_PRI_2__FULL            0x1E008018,0xffffffff
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50 0x1E008018,0x00040000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49 0x1E008018,0x00020000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48 0x1E008018,0x00010000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47 0x1E008018,0x00008000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46 0x1E008018,0x00004000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45 0x1E008018,0x00002000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44 0x1E008018,0x00001000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43 0x1E008018,0x00000800
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42 0x1E008018,0x00000400
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41 0x1E008018,0x00000200
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40 0x1E008018,0x00000100
+
+#define IPU_IDMAC_WM_EN_1__ADDR           0x1E00801C
+#define IPU_IDMAC_WM_EN_1__EMPTY          0x1E00801C,0x00000000
+#define IPU_IDMAC_WM_EN_1__FULL           0x1E00801C,0xffffffff
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_29 0x1E00801C,0x20000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_28 0x1E00801C,0x10000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_27 0x1E00801C,0x08000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_24 0x1E00801C,0x01000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_23 0x1E00801C,0x00800000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_14 0x1E00801C,0x00004000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_12 0x1E00801C,0x00001000
+
+#define IPU_IDMAC_WM_EN_2__ADDR           0x1E008020
+#define IPU_IDMAC_WM_EN_2__EMPTY          0x1E008020,0x00000000
+#define IPU_IDMAC_WM_EN_2__FULL           0x1E008020,0xffffffff
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_44 0x1E008020,0x00001000
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_43 0x1E008020,0x00000800
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_42 0x1E008020,0x00000400
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_41 0x1E008020,0x00000200
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_40 0x1E008020,0x00000100
+
+#define IPU_IDMAC_LOCK_EN_2__ADDR             0x1E008024
+#define IPU_IDMAC_LOCK_EN_2__EMPTY            0x1E008024,0x00000000
+#define IPU_IDMAC_LOCK_EN_2__FULL             0x1E008024,0xffffffff
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50 0x1E008024,0x00040000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49 0x1E008024,0x00020000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48 0x1E008024,0x00010000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47 0x1E008024,0x00008000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46 0x1E008024,0x00004000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45 0x1E008024,0x00002000
+
+#define IPU_IDMAC_SUB_ADDR_1__ADDR              0x1E00802C
+#define IPU_IDMAC_SUB_ADDR_1__EMPTY             0x1E00802C,0x00000000
+#define IPU_IDMAC_SUB_ADDR_1__FULL              0x1E00802C,0xffffffff
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33 0x1E00802C,0x7F000000
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29 0x1E00802C,0x007F0000
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24 0x1E00802C,0x00007F00
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23 0x1E00802C,0x0000007F
+
+#define IPU_IDMAC_SUB_ADDR_2__ADDR              0x1E008030
+#define IPU_IDMAC_SUB_ADDR_2__EMPTY             0x1E008030,0x00000000
+#define IPU_IDMAC_SUB_ADDR_2__FULL              0x1E008030,0xffffffff
+#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52 0x1E008030,0x007F0000
+#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51 0x1E008030,0x00007F00
+#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41 0x1E008030,0x0000007F
+
+#define IPU_IDMAC_BNDM_EN_1__ADDR             0x1E008034
+#define IPU_IDMAC_BNDM_EN_1__EMPTY            0x1E008034,0x00000000
+#define IPU_IDMAC_BNDM_EN_1__FULL             0x1E008034,0xffffffff
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22 0x1E008034,0x00400000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21 0x1E008034,0x00200000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20 0x1E008034,0x00100000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12 0x1E008034,0x00001000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11 0x1E008034,0x00000800
+
+#define IPU_IDMAC_BNDM_EN_2__ADDR             0x1E008038
+#define IPU_IDMAC_BNDM_EN_2__EMPTY            0x1E008038,0x00000000
+#define IPU_IDMAC_BNDM_EN_2__FULL             0x1E008038,0xffffffff
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50 0x1E008038,0x00040000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49 0x1E008038,0x00020000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48 0x1E008038,0x00010000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47 0x1E008038,0x00008000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46 0x1E008038,0x00004000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45 0x1E008038,0x00002000
+
+#define IPU_IDMAC_SC_CORD__ADDR  0x1E00803C
+#define IPU_IDMAC_SC_CORD__EMPTY 0x1E00803C,0x00000000
+#define IPU_IDMAC_SC_CORD__FULL  0x1E00803C,0xffffffff
+#define IPU_IDMAC_SC_CORD__SX0   0x1E00803C,0x0FFF0000
+#define IPU_IDMAC_SC_CORD__SY0   0x1E00803C,0x000007FF
+
+#define IPU_IDMAC_CH_BUSY_1__ADDR             0x1E008040
+#define IPU_IDMAC_CH_BUSY_1__EMPTY            0x1E008040,0x00000000
+#define IPU_IDMAC_CH_BUSY_1__FULL             0x1E008040,0xffffffff
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_31 0x1E008040,0x80000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_29 0x1E008040,0x20000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_28 0x1E008040,0x10000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_27 0x1E008040,0x08000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_24 0x1E008040,0x01000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_23 0x1E008040,0x00800000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_22 0x1E008040,0x00400000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_21 0x1E008040,0x00200000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_20 0x1E008040,0x00100000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_18 0x1E008040,0x00040000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_17 0x1E008040,0x00020000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_15 0x1E008040,0x00008000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_14 0x1E008040,0x00004000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_12 0x1E008040,0x00001000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_11 0x1E008040,0x00000800
+
+#define IPU_IDMAC_CH_BUSY_2__ADDR             0x1E008044
+#define IPU_IDMAC_CH_BUSY_2__EMPTY            0x1E008044,0x00000000
+#define IPU_IDMAC_CH_BUSY_2__FULL             0x1E008044,0xffffffff
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_52 0x1E008044,0x00100000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_51 0x1E008044,0x00080000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_50 0x1E008044,0x00040000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_49 0x1E008044,0x00020000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_48 0x1E008044,0x00010000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_47 0x1E008044,0x00008000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_46 0x1E008044,0x00004000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_45 0x1E008044,0x00002000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_44 0x1E008044,0x00001000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_43 0x1E008044,0x00000800
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_42 0x1E008044,0x00000400
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_41 0x1E008044,0x00000200
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_40 0x1E008044,0x00000100
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_33 0x1E008044,0x00000002
+
+#define IPU_DP_COM_CONF_SYNC__ADDR                     0x1E018000
+#define IPU_DP_COM_CONF_SYNC__EMPTY                    0x1E018000,0x00000000
+#define IPU_DP_COM_CONF_SYNC__FULL                     0x1E018000,0xffffffff
+#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC     0x1E018000,0x00002000
+#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC         0x1E018000,0x00001000
+#define IPU_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1E018000,0x00000800
+#define IPU_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1E018000,0x00000400
+#define IPU_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC          0x1E018000,0x00000300
+#define IPU_DP_COM_CONF_SYNC__DP_COC_SYNC              0x1E018000,0x00000070
+#define IPU_DP_COM_CONF_SYNC__DP_GWCKE_SYNC            0x1E018000,0x00000008
+#define IPU_DP_COM_CONF_SYNC__DP_GWAM_SYNC             0x1E018000,0x00000004
+#define IPU_DP_COM_CONF_SYNC__DP_GWSEL_SYNC            0x1E018000,0x00000002
+#define IPU_DP_COM_CONF_SYNC__DP_FG_EN_SYNC            0x1E018000,0x00000001
+
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__ADDR          0x1E018004
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__EMPTY         0x1E018004,0x00000000
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__FULL          0x1E018004,0xffffffff
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC  0x1E018004,0xFF000000
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1E018004,0x00FF0000
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1E018004,0x0000FF00
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1E018004,0x000000FF
+
+#define IPU_DP_FG_POS_SYNC__ADDR         0x1E018008
+#define IPU_DP_FG_POS_SYNC__EMPTY        0x1E018008,0x00000000
+#define IPU_DP_FG_POS_SYNC__FULL         0x1E018008,0xffffffff
+#define IPU_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1E018008,0x07FF0000
+#define IPU_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1E018008,0x000007FF
+
+#define IPU_DP_CUR_POS_SYNC__ADDR        0x1E01800C
+#define IPU_DP_CUR_POS_SYNC__EMPTY       0x1E01800C,0x00000000
+#define IPU_DP_CUR_POS_SYNC__FULL        0x1E01800C,0xffffffff
+#define IPU_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1E01800C,0xF8000000
+#define IPU_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1E01800C,0x07FF0000
+#define IPU_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1E01800C,0x0000F800
+#define IPU_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1E01800C,0x000007FF
+
+#define IPU_DP_CUR_MAP_SYNC__ADDR              0x1E018010
+#define IPU_DP_CUR_MAP_SYNC__EMPTY             0x1E018010,0x00000000
+#define IPU_DP_CUR_MAP_SYNC__FULL              0x1E018010,0xffffffff
+#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1E018010,0x00FF0000
+#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1E018010,0x0000FF00
+#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1E018010,0x000000FF
+
+#define IPU_DP_GAMMA_C_SYNC_0__ADDR              0x1E018014
+#define IPU_DP_GAMMA_C_SYNC_0__EMPTY             0x1E018014,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_0__FULL              0x1E018014,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1E018014,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1E018014,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_1__ADDR              0x1E018018
+#define IPU_DP_GAMMA_C_SYNC_1__EMPTY             0x1E018018,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_1__FULL              0x1E018018,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1E018018,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1E018018,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_2__ADDR              0x1E01801C
+#define IPU_DP_GAMMA_C_SYNC_2__EMPTY             0x1E01801C,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_2__FULL              0x1E01801C,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1E01801C,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1E01801C,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_3__ADDR              0x1E018020
+#define IPU_DP_GAMMA_C_SYNC_3__EMPTY             0x1E018020,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_3__FULL              0x1E018020,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1E018020,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1E018020,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_4__ADDR              0x1E018024
+#define IPU_DP_GAMMA_C_SYNC_4__EMPTY             0x1E018024,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_4__FULL              0x1E018024,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1E018024,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1E018024,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_5__ADDR               0x1E018028
+#define IPU_DP_GAMMA_C_SYNC_5__EMPTY              0x1E018028,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_5__FULL               0x1E018028,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1E018028,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1E018028,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_6__ADDR               0x1E01802C
+#define IPU_DP_GAMMA_C_SYNC_6__EMPTY              0x1E01802C,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_6__FULL               0x1E01802C,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1E01802C,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1E01802C,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_7__ADDR               0x1E018030
+#define IPU_DP_GAMMA_C_SYNC_7__EMPTY              0x1E018030,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_7__FULL               0x1E018030,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1E018030,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1E018030,0x000001FF
+
+#define IPU_DP_GAMMA_S_SYNC_0__ADDR              0x1E018034
+#define IPU_DP_GAMMA_S_SYNC_0__EMPTY             0x1E018034,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_0__FULL              0x1E018034,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1E018034,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1E018034,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1E018034,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1E018034,0x000000FF
+
+#define IPU_DP_GAMMA_S_SYNC_1__ADDR              0x1E018038
+#define IPU_DP_GAMMA_S_SYNC_1__EMPTY             0x1E018038,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_1__FULL              0x1E018038,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1E018038,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1E018038,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1E018038,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1E018038,0x000000FF
+
+#define IPU_DP_GAMMA_S_SYNC_2__ADDR               0x1E01803C
+#define IPU_DP_GAMMA_S_SYNC_2__EMPTY              0x1E01803C,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_2__FULL               0x1E01803C,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1E01803C,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1E01803C,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9  0x1E01803C,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8  0x1E01803C,0x000000FF
+
+#define IPU_DP_GAMMA_S_SYNC_3__ADDR               0x1E018040
+#define IPU_DP_GAMMA_S_SYNC_3__EMPTY              0x1E018040,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_3__FULL               0x1E018040,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1E018040,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1E018040,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1E018040,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1E018040,0x000000FF
+
+#define IPU_DP_CSCA_SYNC_0__ADDR            0x1E018044
+#define IPU_DP_CSCA_SYNC_0__EMPTY           0x1E018044,0x00000000
+#define IPU_DP_CSCA_SYNC_0__FULL            0x1E018044,0xffffffff
+#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1E018044,0x03FF0000
+#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1E018044,0x000003FF
+
+#define IPU_DP_CSCA_SYNC_1__ADDR            0x1E018048
+#define IPU_DP_CSCA_SYNC_1__EMPTY           0x1E018048,0x00000000
+#define IPU_DP_CSCA_SYNC_1__FULL            0x1E018048,0xffffffff
+#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1E018048,0x03FF0000
+#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1E018048,0x000003FF
+
+#define IPU_DP_CSCA_SYNC_2__ADDR            0x1E01804C
+#define IPU_DP_CSCA_SYNC_2__EMPTY           0x1E01804C,0x00000000
+#define IPU_DP_CSCA_SYNC_2__FULL            0x1E01804C,0xffffffff
+#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1E01804C,0x03FF0000
+#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1E01804C,0x000003FF
+
+#define IPU_DP_CSCA_SYNC_3__ADDR            0x1E018050
+#define IPU_DP_CSCA_SYNC_3__EMPTY           0x1E018050,0x00000000
+#define IPU_DP_CSCA_SYNC_3__FULL            0x1E018050,0xffffffff
+#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1E018050,0x03FF0000
+#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1E018050,0x000003FF
+
+#define IPU_DP_CSC_SYNC_0__ADDR           0x1E018054
+#define IPU_DP_CSC_SYNC_0__EMPTY          0x1E018054,0x00000000
+#define IPU_DP_CSC_SYNC_0__FULL           0x1E018054,0xffffffff
+#define IPU_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1E018054,0xC0000000
+#define IPU_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1E018054,0x3FFF0000
+#define IPU_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1E018054,0x000003FF
+
+#define IPU_DP_CSC_SYNC_1__ADDR           0x1E018058
+#define IPU_DP_CSC_SYNC_1__EMPTY          0x1E018058,0x00000000
+#define IPU_DP_CSC_SYNC_1__FULL           0x1E018058,0xffffffff
+#define IPU_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1E018058,0xC0000000
+#define IPU_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1E018058,0x3FFF0000
+#define IPU_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1E018058,0x0000C000
+#define IPU_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1E018058,0x00003FFF
+
+#define IPU_DP_CUR_POS_ALT__ADDR            0x1E01805C
+#define IPU_DP_CUR_POS_ALT__EMPTY           0x1E01805C,0x00000000
+#define IPU_DP_CUR_POS_ALT__FULL            0x1E01805C,0xffffffff
+#define IPU_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1E01805C,0xF8000000
+#define IPU_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1E01805C,0x07FF0000
+#define IPU_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1E01805C,0x0000F800
+#define IPU_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1E01805C,0x000007FF
+
+#define IPU_DP_COM_CONF_ASYNC__ADDR                       0x1E018060
+#define IPU_DP_COM_CONF_ASYNC__EMPTY                      0x1E018060,0x00000000
+#define IPU_DP_COM_CONF_ASYNC__FULL                       0x1E018060,0xffffffff
+#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_YUV_EN_ASYNC      0x1E018060,0x00002000
+#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_EN_ASYNC         0x1E018060,0x00001000
+#define IPU_DP_COM_CONF_ASYNC__DP_CSC_YUV_SAT_MODE_ASYNC 0x1E018060,0x00000800
+#define IPU_DP_COM_CONF_ASYNC__DP_CSC_GAMUT_SAT_EN_ASYNC 0x1E018060,0x00000400
+#define IPU_DP_COM_CONF_ASYNC__DP_CSC_DEF_ASYNC          0x1E018060,0x00000300
+#define IPU_DP_COM_CONF_ASYNC__DP_COC_ASYNC              0x1E018060,0x00000070
+#define IPU_DP_COM_CONF_ASYNC__DP_GWCKE_ASYNC            0x1E018060,0x00000008
+#define IPU_DP_COM_CONF_ASYNC__DP_GWAM_ASYNC             0x1E018060,0x00000004
+#define IPU_DP_COM_CONF_ASYNC__DP_GWSEL_ASYNC            0x1E018060,0x00000002
+#define IPU_DP_COM_CONF_ASYNC__DP_FG_EN_ASYNC            0x1E018060,0x00000001
+
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__ADDR            0x1E018064
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__EMPTY           0x1E018064,0x00000000
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__FULL            0x1E018064,0xffffffff
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWAV_ASYNC  0x1E018064,0xFF000000
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKR_ASYNC 0x1E018064,0x00FF0000
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKG_ASYNC 0x1E018064,0x0000FF00
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKB_ASYNC 0x1E018064,0x000000FF
+
+#define IPU_DP_FG_POS_ASYNC__ADDR           0x1E018068
+#define IPU_DP_FG_POS_ASYNC__EMPTY          0x1E018068,0x00000000
+#define IPU_DP_FG_POS_ASYNC__FULL           0x1E018068,0xffffffff
+#define IPU_DP_FG_POS_ASYNC__DP_FGXP_ASYNC 0x1E018068,0x07FF0000
+#define IPU_DP_FG_POS_ASYNC__DP_FGYP_ASYNC 0x1E018068,0x000007FF
+
+#define IPU_DP_CUR_POS_ASYNC__ADDR          0x1E01806C
+#define IPU_DP_CUR_POS_ASYNC__EMPTY         0x1E01806C,0x00000000
+#define IPU_DP_CUR_POS_ASYNC__FULL          0x1E01806C,0xffffffff
+#define IPU_DP_CUR_POS_ASYNC__DP_CXW_ASYNC 0x1E01806C,0xF8000000
+#define IPU_DP_CUR_POS_ASYNC__DP_CXP_ASYNC 0x1E01806C,0x07FF0000
+#define IPU_DP_CUR_POS_ASYNC__DP_CYH_ASYNC 0x1E01806C,0x0000F800
+#define IPU_DP_CUR_POS_ASYNC__DP_CYP_ASYNC 0x1E01806C,0x000007FF
+
+#define IPU_DP_CUR_MAP_ASYNC__ADDR             0x1E018070
+#define IPU_DP_CUR_MAP_ASYNC__EMPTY            0x1E018070,0x00000000
+#define IPU_DP_CUR_MAP_ASYNC__FULL             0x1E018070,0xffffffff
+#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_R_ASYNC 0x1E018070,0x00FF0000
+#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_G_ASYNC 0x1E018070,0x0000FF00
+#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_B_ASYNC 0x1E018070,0x000000FF
+
+#define IPU_DP_GAMMA_C_ASYNC_0__ADDR                0x1E018074
+#define IPU_DP_GAMMA_C_ASYNC_0__EMPTY               0x1E018074,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_0__FULL                0x1E018074,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_1 0x1E018074,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_0 0x1E018074,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_1__ADDR                0x1E018078
+#define IPU_DP_GAMMA_C_ASYNC_1__EMPTY               0x1E018078,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_1__FULL                0x1E018078,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_3 0x1E018078,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_2 0x1E018078,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_2__ADDR                0x1E01807C
+#define IPU_DP_GAMMA_C_ASYNC_2__EMPTY               0x1E01807C,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_2__FULL                0x1E01807C,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_5 0x1E01807C,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_4 0x1E01807C,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_3__ADDR                0x1E018080
+#define IPU_DP_GAMMA_C_ASYNC_3__EMPTY               0x1E018080,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_3__FULL                0x1E018080,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_7 0x1E018080,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_6 0x1E018080,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_4__ADDR                0x1E018084
+#define IPU_DP_GAMMA_C_ASYNC_4__EMPTY               0x1E018084,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_4__FULL                0x1E018084,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_9 0x1E018084,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_8 0x1E018084,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_5__ADDR                 0x1E018088
+#define IPU_DP_GAMMA_C_ASYNC_5__EMPTY                0x1E018088,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_5__FULL                 0x1E018088,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_11 0x1E018088,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_10 0x1E018088,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_6__ADDR                 0x1E01808C
+#define IPU_DP_GAMMA_C_ASYNC_6__EMPTY                0x1E01808C,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_6__FULL                 0x1E01808C,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_13 0x1E01808C,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_12 0x1E01808C,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_7__ADDR                 0x1E018090
+#define IPU_DP_GAMMA_C_ASYNC_7__EMPTY                0x1E018090,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_7__FULL                 0x1E018090,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_15 0x1E018090,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_14 0x1E018090,0x000001FF
+
+#define IPU_DP_GAMMA_S_ASYNC_0__ADDR                0x1E018094
+#define IPU_DP_GAMMA_S_ASYNC_0__EMPTY               0x1E018094,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_0__FULL                0x1E018094,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_3 0x1E018094,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_2 0x1E018094,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_1 0x1E018094,0x0000FF04
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_0 0x1E018094,0x00000103
+
+#define IPU_DP_GAMMA_S_ASYNC_1__ADDR                0x1E018098
+#define IPU_DP_GAMMA_S_ASYNC_1__EMPTY               0x1E018098,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_1__FULL                0x1E018098,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_7 0x1E018098,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_6 0x1E018098,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_5 0x1E018098,0x0000FF00
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_4 0x1E018098,0x000000FF
+
+#define IPU_DP_GAMMA_S_ASYNC_2__ADDR                 0x1E01809C
+#define IPU_DP_GAMMA_S_ASYNC_2__EMPTY                0x1E01809C,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_2__FULL                 0x1E01809C,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_11 0x1E01809C,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_10 0x1E01809C,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_9  0x1E01809C,0x0000FF00
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_8  0x1E01809C,0x000000FF
+
+#define IPU_DP_GAMMA_S_ASYNC_3__ADDR                 0x1E0180A0
+#define IPU_DP_GAMMA_S_ASYNC_3__EMPTY                0x1E0180A0,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_3__FULL                 0x1E0180A0,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_15 0x1E0180A0,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_14 0x1E0180A0,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_13 0x1E0180A0,0x0000FF00
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_12 0x1E0180A0,0x000000FF
+
+#define IPU_DP_CSCA_ASYNC_0__ADDR              0x1E0180A4
+#define IPU_DP_CSCA_ASYNC_0__EMPTY             0x1E0180A4,0x00000000
+#define IPU_DP_CSCA_ASYNC_0__FULL              0x1E0180A4,0xffffffff
+#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_1 0x1E0180A4,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_0 0x1E0180A4,0x000003FF
+
+#define IPU_DP_CSCA_ASYNC_1__ADDR              0x1E0180A8
+#define IPU_DP_CSCA_ASYNC_1__EMPTY             0x1E0180A8,0x00000000
+#define IPU_DP_CSCA_ASYNC_1__FULL              0x1E0180A8,0xffffffff
+#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_3 0x1E0180A8,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_2 0x1E0180A8,0x000003FF
+
+#define IPU_DP_CSCA_ASYNC_2__ADDR              0x1E0180AC
+#define IPU_DP_CSCA_ASYNC_2__EMPTY             0x1E0180AC,0x00000000
+#define IPU_DP_CSCA_ASYNC_2__FULL              0x1E0180AC,0xffffffff
+#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_5 0x1E0180AC,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_4 0x1E0180AC,0x000003FF
+
+#define IPU_DP_CSCA_ASYNC_3__ADDR              0x1E0180B0
+#define IPU_DP_CSCA_ASYNC_3__EMPTY             0x1E0180B0,0x00000000
+#define IPU_DP_CSCA_ASYNC_3__FULL              0x1E0180B0,0xffffffff
+#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_7 0x1E0180B0,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_6 0x1E0180B0,0x000003FF
+
+#define IPU_DP_CSC_ASYNC_0__ADDR             0x1E0180B4
+#define IPU_DP_CSC_ASYNC_0__EMPTY            0x1E0180B4,0x00000000
+#define IPU_DP_CSC_ASYNC_0__FULL             0x1E0180B4,0xffffffff
+#define IPU_DP_CSC_ASYNC_0__DP_CSC_S0_ASYNC 0x1E0180B4,0xC0000000
+#define IPU_DP_CSC_ASYNC_0__DP_CSC_B0_ASYNC 0x1E0180B4,0x3FFF0000
+#define IPU_DP_CSC_ASYNC_0__DP_CSC_A8_ASYNC 0x1E0180B4,0x00000403
+
+#define IPU_DP_CSC_ASYNC_1__ADDR             0x1E0180B8
+#define IPU_DP_CSC_ASYNC_1__EMPTY            0x1E0180B8,0x00000000
+#define IPU_DP_CSC_ASYNC_1__FULL             0x1E0180B8,0xffffffff
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_S2_ASYNC 0x1E0180B8,0xC0000000
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_B2_ASYNC 0x1E0180B8,0x3FFF0000
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_S1_ASYNC 0x1E0180B8,0x0000C000
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_B1_ASYNC 0x1E0180B8,0x00003FFF
+
+#define IPU_DP_DEBUG_CNT__ADDR              0x1E0180BC
+#define IPU_DP_DEBUG_CNT__EMPTY             0x1E0180BC,0x00000000
+#define IPU_DP_DEBUG_CNT__FULL              0x1E0180BC,0xffffffff
+#define IPU_DP_DEBUG_CNT__BRAKE_CNT_1       0x1E0180BC,0x000000E0
+#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_1 0x1E0180BC,0x00000010
+#define IPU_DP_DEBUG_CNT__BRAKE_CNT_0       0x1E0180BC,0x0000000E
+#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_0 0x1E0180BC,0x00000001
+
+#define IPU_DP_DEBUG_STAT__ADDR            0x1E0180C0
+#define IPU_DP_DEBUG_STAT__EMPTY           0x1E0180C0,0x00000000
+#define IPU_DP_DEBUG_STAT__FULL            0x1E0180C0,0xffffffff
+#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_1    0x1E0180C0,0x20000000
+#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_1 0x1E0180C0,0x10000000
+#define IPU_DP_DEBUG_STAT__FG_ACTIVE_1     0x1E0180C0,0x08000000
+#define IPU_DP_DEBUG_STAT__V_CNT_OLD_1     0x1E0180C0,0x07FF0000
+#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_0    0x1E0180C0,0x00002000
+#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_0 0x1E0180C0,0x00001000
+#define IPU_DP_DEBUG_STAT__FG_ACTIVE_0     0x1E0180C0,0x00000800
+#define IPU_DP_DEBUG_STAT__V_CNT_OLD_0     0x1E0180C0,0x000007FF
+
+#define IPU_IC_CONF__ADDR            0x1E020000
+#define IPU_IC_CONF__EMPTY           0x1E020000,0x00000000
+#define IPU_IC_CONF__FULL            0x1E020000,0xffffffff
+#define IPU_IC_CONF__CSI_MEM_WR_EN   0x1E020000,0x80000000
+#define IPU_IC_CONF__RWS_EN          0x1E020000,0x40000000
+#define IPU_IC_CONF__IC_KEY_COLOR_EN 0x1E020000,0x20000000
+#define IPU_IC_CONF__IC_GLB_LOC_A    0x1E020000,0x10000000
+#define IPU_IC_CONF__PP_ROT_EN       0x1E020000,0x00100000
+#define IPU_IC_CONF__PP_CMB          0x1E020000,0x00080000
+#define IPU_IC_CONF__PP_CSC2         0x1E020000,0x00040000
+#define IPU_IC_CONF__PP_CSC1         0x1E020000,0x00020000
+#define IPU_IC_CONF__PP_EN           0x1E020000,0x00010000
+#define IPU_IC_CONF__PRPVF_ROT_EN    0x1E020000,0x00001000
+#define IPU_IC_CONF__PRPVF_CMB       0x1E020000,0x00000800
+#define IPU_IC_CONF__PRPVF_CSC2      0x1E020000,0x00000400
+#define IPU_IC_CONF__PRPVF_CSC1      0x1E020000,0x00000200
+#define IPU_IC_CONF__PRPVF_EN        0x1E020000,0x00000100
+#define IPU_IC_CONF__PRPENC_ROT_EN   0x1E020000,0x00000004
+#define IPU_IC_CONF__PRPENC_CSC1     0x1E020000,0x00000002
+#define IPU_IC_CONF__PRPENC_EN       0x1E020000,0x00000001
+
+#define IPU_IC_PRP_ENC_RSC__ADDR          0x1E020004
+#define IPU_IC_PRP_ENC_RSC__EMPTY         0x1E020004,0x00000000
+#define IPU_IC_PRP_ENC_RSC__FULL          0x1E020004,0xffffffff
+#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_V 0x1E020004,0xC0000000
+#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_V 0x1E020004,0x3FFF0000
+#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_H 0x1E020004,0x0000C000
+#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_H 0x1E020004,0x00003FFF
+
+#define IPU_IC_PRP_VF_RSC__ADDR         0x1E020008
+#define IPU_IC_PRP_VF_RSC__EMPTY        0x1E020008,0x00000000
+#define IPU_IC_PRP_VF_RSC__FULL         0x1E020008,0xffffffff
+#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_V 0x1E020008,0xC0000000
+#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_V 0x1E020008,0x3FFF0000
+#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_H 0x1E020008,0x0000C000
+#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_H 0x1E020008,0x00003FFF
+
+#define IPU_IC_PP_RSC__ADDR      0x1E02000C
+#define IPU_IC_PP_RSC__EMPTY     0x1E02000C,0x00000000
+#define IPU_IC_PP_RSC__FULL      0x1E02000C,0xffffffff
+#define IPU_IC_PP_RSC__PP_DS_R_V 0x1E02000C,0xC0000000
+#define IPU_IC_PP_RSC__PP_RS_R_V 0x1E02000C,0x3FFF0000
+#define IPU_IC_PP_RSC__PP_DS_R_H 0x1E02000C,0x0000C000
+#define IPU_IC_PP_RSC__PP_RS_R_H 0x1E02000C,0x00003FFF
+
+#define IPU_IC_CMBP_1__ADDR             0x1E020010
+#define IPU_IC_CMBP_1__EMPTY            0x1E020010,0x00000000
+#define IPU_IC_CMBP_1__FULL             0x1E020010,0xffffffff
+#define IPU_IC_CMBP_1__IC_PP_ALPHA_V    0x1E020010,0x0000FF00
+#define IPU_IC_CMBP_1__IC_PRPVF_ALPHA_V 0x1E020010,0x000000FF
+
+#define IPU_IC_CMBP_2__ADDR           0x1E020014
+#define IPU_IC_CMBP_2__EMPTY          0x1E020014,0x00000000
+#define IPU_IC_CMBP_2__FULL           0x1E020014,0xffffffff
+#define IPU_IC_CMBP_2__IC_KEY_COLOR_R 0x1E020014,0x00FF0000
+#define IPU_IC_CMBP_2__IC_KEY_COLOR_G 0x1E020014,0x0000FF00
+#define IPU_IC_CMBP_2__IC_KEY_COLOR_B 0x1E020014,0x000000FF
+
+#define IPU_IC_IDMAC_1__ADDR             0x1E020018
+#define IPU_IC_IDMAC_1__EMPTY            0x1E020018,0x00000000
+#define IPU_IC_IDMAC_1__FULL             0x1E020018,0xffffffff
+#define IPU_IC_IDMAC_1__ALT_CB7_BURST_16 0x1E020018,0x02000000
+#define IPU_IC_IDMAC_1__ALT_CB6_BURST_16 0x1E020018,0x01000000
+#define IPU_IC_IDMAC_1__T3_FLIP_UD       0x1E020018,0x00080000
+#define IPU_IC_IDMAC_1__T3_FLIP_LR       0x1E020018,0x00040000
+#define IPU_IC_IDMAC_1__T3_ROT           0x1E020018,0x00020000
+#define IPU_IC_IDMAC_1__T2_FLIP_UD       0x1E020018,0x00010000
+#define IPU_IC_IDMAC_1__T2_FLIP_LR       0x1E020018,0x00008000
+#define IPU_IC_IDMAC_1__T2_ROT           0x1E020018,0x00004000
+#define IPU_IC_IDMAC_1__T1_FLIP_UD       0x1E020018,0x00002000
+#define IPU_IC_IDMAC_1__T1_FLIP_LR       0x1E020018,0x00001000
+#define IPU_IC_IDMAC_1__T1_ROT           0x1E020018,0x00000800
+#define IPU_IC_IDMAC_1__CB7_BURST_16     0x1E020018,0x00000080
+#define IPU_IC_IDMAC_1__CB6_BURST_16     0x1E020018,0x00000040
+#define IPU_IC_IDMAC_1__CB5_BURST_16     0x1E020018,0x00000020
+#define IPU_IC_IDMAC_1__CB4_BURST_16     0x1E020018,0x00000010
+#define IPU_IC_IDMAC_1__CB3_BURST_16     0x1E020018,0x00000008
+#define IPU_IC_IDMAC_1__CB2_BURST_16     0x1E020018,0x00000004
+#define IPU_IC_IDMAC_1__CB1_BURST_16     0x1E020018,0x00000002
+#define IPU_IC_IDMAC_1__CB0_BURST_16     0x1E020018,0x00000001
+
+#define IPU_IC_IDMAC_2__ADDR         0x1E02001C
+#define IPU_IC_IDMAC_2__EMPTY        0x1E02001C,0x00000000
+#define IPU_IC_IDMAC_2__FULL         0x1E02001C,0xffffffff
+#define IPU_IC_IDMAC_2__T3_FR_HEIGHT 0x1E02001C,0x3FF00000
+#define IPU_IC_IDMAC_2__T2_FR_HEIGHT 0x1E02001C,0x000FFC00
+#define IPU_IC_IDMAC_2__T1_FR_HEIGHT 0x1E02001C,0x000003FF
+
+#define IPU_IC_IDMAC_3__ADDR        0x1E020020
+#define IPU_IC_IDMAC_3__EMPTY       0x1E020020,0x00000000
+#define IPU_IC_IDMAC_3__FULL        0x1E020020,0xffffffff
+#define IPU_IC_IDMAC_3__T3_FR_WIDTH 0x1E020020,0x3FF00000
+#define IPU_IC_IDMAC_3__T2_FR_WIDTH 0x1E020020,0x000FFC00
+#define IPU_IC_IDMAC_3__T1_FR_WIDTH 0x1E020020,0x000003FF
+
+#define IPU_IC_IDMAC_4__ADDR                 0x1E020024
+#define IPU_IC_IDMAC_4__EMPTY                0x1E020024,0x00000000
+#define IPU_IC_IDMAC_4__FULL                 0x1E020024,0xffffffff
+#define IPU_IC_IDMAC_4__RM_BRDG_MAX_RQ       0x1E020024,0x0000F000
+#define IPU_IC_IDMAC_4__IBM_BRDG_MAX_RQ      0x1E020024,0x00000F00
+#define IPU_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ 0x1E020024,0x000000F0
+#define IPU_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ   0x1E020024,0x0000000F
+
+#define IPU_DI0_GENERAL__ADDR                  0x1E040000
+#define IPU_DI0_GENERAL__EMPTY                 0x1E040000,0x00000000
+#define IPU_DI0_GENERAL__FULL                  0x1E040000,0xffffffff
+#define IPU_DI0_GENERAL__DI0_DISP_Y_SEL        0x1E040000,0x70000000
+#define IPU_DI0_GENERAL__DI0_CLOCK_STOP_MODE   0x1E040000,0x0F000000
+#define IPU_DI0_GENERAL__DI0_DISP_CLOCK_INIT   0x1E040000,0x00800000
+#define IPU_DI0_GENERAL__DI0_MASK_SEL          0x1E040000,0x00400000
+#define IPU_DI0_GENERAL__DI0_VSYNC_EXT         0x1E040000,0x00200000
+#define IPU_DI0_GENERAL__DI0_CLK_EXT           0x1E040000,0x00100000
+#define IPU_DI0_GENERAL__DI0_WATCHDOG_MODE     0x1E040000,0x000C0000
+#define IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1E040000,0x00020000
+#define IPU_DI0_GENERAL__DI0_SYNC_COUNT_SEL    0x1E040000,0x0000F000
+#define IPU_DI0_GENERAL__DI0_ERR_TREATMENT     0x1E040000,0x00000800
+#define IPU_DI0_GENERAL__DI0_ERM_VSYNC_SEL     0x1E040000,0x00000400
+#define IPU_DI0_GENERAL__DI0_POLARITY_CS1      0x1E040000,0x00000200
+#define IPU_DI0_GENERAL__DI0_POLARITY_CS0      0x1E040000,0x00000100
+#define IPU_DI0_GENERAL__DI0_POLARITY_8        0x1E040000,0x00000080
+#define IPU_DI0_GENERAL__DI0_POLARITY_7        0x1E040000,0x00000040
+#define IPU_DI0_GENERAL__DI0_POLARITY_6        0x1E040000,0x00000020
+#define IPU_DI0_GENERAL__DI0_POLARITY_5        0x1E040000,0x00000010
+#define IPU_DI0_GENERAL__DI0_POLARITY_4        0x1E040000,0x00000008
+#define IPU_DI0_GENERAL__DI0_POLARITY_3        0x1E040000,0x00000004
+#define IPU_DI0_GENERAL__DI0_POLARITY_2        0x1E040000,0x00000002
+#define IPU_DI0_GENERAL__DI0_POLARITY_1        0x1E040000,0x00000001
+
+#define IPU_DI0_BS_CLKGEN0__ADDR                0x1E040004
+#define IPU_DI0_BS_CLKGEN0__EMPTY               0x1E040004,0x00000000
+#define IPU_DI0_BS_CLKGEN0__FULL                0x1E040004,0xffffffff
+#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1E040004,0x01FF0000
+#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1E040004,0x00000FFF
+
+#define IPU_DI0_BS_CLKGEN1__ADDR              0x1E040008
+#define IPU_DI0_BS_CLKGEN1__EMPTY             0x1E040008,0x00000000
+#define IPU_DI0_BS_CLKGEN1__FULL              0x1E040008,0xffffffff
+#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1E040008,0x01FF0000
+#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP   0x1E040008,0x000001FF
+
+#define DI_SWGEN0_ADDR(di, pointer)                                                    (IPU_DI0_GENERAL__ADDR + \
+                                                                                                                                                                                       di *0x8000 + \
+                                                                                                                                                                                       (pointer-1) * 0x4 + 0x000C)
+#define DI_SWGEN0_EMPTY(di, pointer)                                           DI_SWGEN0_ADDR(di, pointer), 0x00000000
+#define DI_SWGEN0_FULL(di, pointer)                                                    DI_SWGEN0_ADDR(di, pointer), 0xFFFFFFFF
+
+#define DI_SWGEN0_RUN_VALUE_M1(di, pointer)            DI_SWGEN0_ADDR(di, pointer), 0x7FF80000
+#define DI_SWGEN0_RUN_RESOL(di, pointer)                               DI_SWGEN0_ADDR(di, pointer), 0x00070000
+#define DI_SWGEN0_OFFSET_VALUE(di, pointer)                    DI_SWGEN0_ADDR(di, pointer), 0x00007FF8
+#define DI_SWGEN0_OFFSET_RESOL(di, pointer)                    DI_SWGEN0_ADDR(di, pointer), 0x00000007
+
+#define DI_SWGEN1_ADDR(di, pointer)                                                    (IPU_DI0_GENERAL__ADDR + \
+                                                                                                                                                                                       di *0x8000 + \
+                                                                                                                                                                                       (pointer-1) * 0x4 + 0x0030)
+#define DI_SWGEN1_EMPTY(di, pointer)                                           DI_SWGEN1_ADDR(di, pointer), 0x00000000
+#define DI_SWGEN1_FULL(di, pointer)                                                    DI_SWGEN1_ADDR(di, pointer), 0xFFFFFFFF
+
+#define DI_SWGEN1_CNT_POL_GEN_EN(di, pointer)  DI_SWGEN1_ADDR(di, pointer), 0x60000000
+#define DI_SWGEN1_CNT_AUTOLOAD(di, pointer)            DI_SWGEN1_ADDR(di, pointer), 0x10000000
+#define DI_SWGEN1_CNT_CLR_SEL(di, pointer)                     DI_SWGEN1_ADDR(di, pointer), 0x0E000000
+#define DI_SWGEN1_CNT_DOW(di, pointer)                                         DI_SWGEN1_ADDR(di, pointer), 0x01FF0000
+#define DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00007000
+#define DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00000E00
+#define DI_SWGEN1_CNT_CNT_UP(di, pointer)                              DI_SWGEN1_ADDR(di, pointer), 0x000001FF
+
+/*sync waveform generator 9 is special*/
+#define IPU_DI0_SW_GEN0_9__ADDR                    0x1E04002C
+#define IPU_DI0_SW_GEN0_9__EMPTY                   0x1E04002C,0x00000000
+#define IPU_DI0_SW_GEN0_9__FULL                    0x1E04002C,0xffffffff
+#define IPU_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9      0x1E04002C,0x7FF80000
+#define IPU_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9    0x1E04002C,0x00070000
+#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9      0x1E04002C,0x00007FF8
+#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1E04002C,0x00000007
+
+#define IPU_DI0_SW_GEN1_9__ADDR                  0x1E040050
+#define IPU_DI0_SW_GEN1_9__EMPTY                 0x1E040050,0x00000000
+#define IPU_DI0_SW_GEN1_9__FULL                  0x1E040050,0xffffffff
+#define IPU_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9     0x1E040050,0xE0000000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1E040050,0x10000000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9     0x1E040050,0x0E000000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_DOWN_9        0x1E040050,0x01FF0000
+#define IPU_DI0_SW_GEN1_9__DI0_TAG_SEL_9         0x1E040050,0x00008000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_UP_9          0x1E040050,0x000001FF
+
+#define IPU_DI0_SYNC_AS_GEN__ADDR              0x1E040054
+#define IPU_DI0_SYNC_AS_GEN__EMPTY             0x1E040054,0x00000000
+#define IPU_DI0_SYNC_AS_GEN__FULL              0x1E040054,0xffffffff
+#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1E040054,0x10000000
+#define IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL     0x1E040054,0x0000E000
+#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START    0x1E040054,0x00000FFF
+
+#define IPU_DI0_DW_GEN_0__ADDR                  0x1E040058
+#define IPU_DI0_DW_GEN_0__EMPTY                 0x1E040058,0x00000000
+#define IPU_DI0_DW_GEN_0__FULL                  0x1E040058,0xffffffff
+#define IPU_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0     0x1E040058,0xFF000000
+#define IPU_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1E040058,0x00FF0000
+#define IPU_DI0_DW_GEN_0__DI0_CST_0             0x1E040058,0x0000C000
+#define IPU_DI0_DW_GEN_0__DI0_PT_6_0            0x1E040058,0x00003000
+#define IPU_DI0_DW_GEN_0__DI0_PT_5_0            0x1E040058,0x00000C00
+#define IPU_DI0_DW_GEN_0__DI0_PT_4_0            0x1E040058,0x00000300
+#define IPU_DI0_DW_GEN_0__DI0_PT_3_0            0x1E040058,0x000000C0
+#define IPU_DI0_DW_GEN_0__DI0_PT_2_0            0x1E040058,0x00000030
+#define IPU_DI0_DW_GEN_0__DI0_PT_1_0            0x1E040058,0x0000000C
+#define IPU_DI0_DW_GEN_0__DI0_PT_0_0            0x1E040058,0x00000003
+
+#define IPU_DI0_DW_GEN_0__ADDR                    0x1E040058
+#define IPU_DI0_DW_GEN_0__EMPTY                   0x1E040058,0x00000000
+#define IPU_DI0_DW_GEN_0__FULL                    0x1E040058,0xffffffff
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0     0x1E040058,0xFF000000
+#define IPU_DI0_DW_GEN_0__DI0_START_PERIOD_0      0x1E040058,0x00FF0000
+#define IPU_DI0_DW_GEN_0__DI0_CST_0               0x1E040058,0x0000C000
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1E040058,0x000001F0
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_RS_0         0x1E040058,0x0000000C
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_CLK_0        0x1E040058,0x00000003
+
+#define IPU_DI0_DW_GEN_1__ADDR                  0x1E04005C
+#define IPU_DI0_DW_GEN_1__EMPTY                 0x1E04005C,0x00000000
+#define IPU_DI0_DW_GEN_1__FULL                  0x1E04005C,0xffffffff
+#define IPU_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1     0x1E04005C,0xFF000000
+#define IPU_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1E04005C,0x00FF0000
+#define IPU_DI0_DW_GEN_1__DI0_CST_1             0x1E04005C,0x0000C000
+#define IPU_DI0_DW_GEN_1__DI0_PT_6_1            0x1E04005C,0x00003000
+#define IPU_DI0_DW_GEN_1__DI0_PT_5_1            0x1E04005C,0x00000C00
+#define IPU_DI0_DW_GEN_1__DI0_PT_4_1            0x1E04005C,0x00000300
+#define IPU_DI0_DW_GEN_1__DI0_PT_3_1            0x1E04005C,0x000000C0
+#define IPU_DI0_DW_GEN_1__DI0_PT_2_1            0x1E04005C,0x00000030
+#define IPU_DI0_DW_GEN_1__DI0_PT_1_1            0x1E04005C,0x0000000C
+#define IPU_DI0_DW_GEN_1__DI0_PT_0_1            0x1E04005C,0x00000003
+
+#define IPU_DI0_DW_GEN_1__ADDR                    0x1E04005C
+#define IPU_DI0_DW_GEN_1__EMPTY                   0x1E04005C,0x00000000
+#define IPU_DI0_DW_GEN_1__FULL                    0x1E04005C,0xffffffff
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1     0x1E04005C,0xFF000000
+#define IPU_DI0_DW_GEN_1__DI0_START_PERIOD_1      0x1E04005C,0x00FF0000
+#define IPU_DI0_DW_GEN_1__DI0_CST_1               0x1E04005C,0x0000C000
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1E04005C,0x000001F0
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_RS_1         0x1E04005C,0x0000000C
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_CLK_1        0x1E04005C,0x00000003
+
+#define IPU_DI0_DW_GEN_2__ADDR                  0x1E040060
+#define IPU_DI0_DW_GEN_2__EMPTY                 0x1E040060,0x00000000
+#define IPU_DI0_DW_GEN_2__FULL                  0x1E040060,0xffffffff
+#define IPU_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2     0x1E040060,0xFF000000
+#define IPU_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1E040060,0x00FF0000
+#define IPU_DI0_DW_GEN_2__DI0_CST_2             0x1E040060,0x0000C000
+#define IPU_DI0_DW_GEN_2__DI0_PT_6_2            0x1E040060,0x00003000
+#define IPU_DI0_DW_GEN_2__DI0_PT_5_2            0x1E040060,0x00000C00
+#define IPU_DI0_DW_GEN_2__DI0_PT_4_2            0x1E040060,0x00000300
+#define IPU_DI0_DW_GEN_2__DI0_PT_3_2            0x1E040060,0x000000C0
+#define IPU_DI0_DW_GEN_2__DI0_PT_2_2            0x1E040060,0x00000030
+#define IPU_DI0_DW_GEN_2__DI0_PT_1_2            0x1E040060,0x0000000C
+#define IPU_DI0_DW_GEN_2__DI0_PT_0_2            0x1E040060,0x00000003
+
+#define IPU_DI0_DW_GEN_2__ADDR                    0x1E040060
+#define IPU_DI0_DW_GEN_2__EMPTY                   0x1E040060,0x00000000
+#define IPU_DI0_DW_GEN_2__FULL                    0x1E040060,0xffffffff
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2     0x1E040060,0xFF000000
+#define IPU_DI0_DW_GEN_2__DI0_START_PERIOD_2      0x1E040060,0x00FF0000
+#define IPU_DI0_DW_GEN_2__DI0_CST_2               0x1E040060,0x0000C000
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1E040060,0x000001F0
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_RS_2         0x1E040060,0x0000000C
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_CLK_2        0x1E040060,0x00000003
+
+#define IPU_DI0_DW_GEN_3__ADDR                  0x1E040064
+#define IPU_DI0_DW_GEN_3__EMPTY                 0x1E040064,0x00000000
+#define IPU_DI0_DW_GEN_3__FULL                  0x1E040064,0xffffffff
+#define IPU_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3     0x1E040064,0xFF000000
+#define IPU_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1E040064,0x00FF0000
+#define IPU_DI0_DW_GEN_3__DI0_CST_3             0x1E040064,0x0000C000
+#define IPU_DI0_DW_GEN_3__DI0_PT_6_3            0x1E040064,0x00003000
+#define IPU_DI0_DW_GEN_3__DI0_PT_5_3            0x1E040064,0x00000C00
+#define IPU_DI0_DW_GEN_3__DI0_PT_4_3            0x1E040064,0x00000300
+#define IPU_DI0_DW_GEN_3__DI0_PT_3_3            0x1E040064,0x000000C0
+#define IPU_DI0_DW_GEN_3__DI0_PT_2_3            0x1E040064,0x00000030
+#define IPU_DI0_DW_GEN_3__DI0_PT_1_3            0x1E040064,0x0000000C
+#define IPU_DI0_DW_GEN_3__DI0_PT_0_3            0x1E040064,0x00000003
+
+#define IPU_DI0_DW_GEN_3__ADDR                    0x1E040064
+#define IPU_DI0_DW_GEN_3__EMPTY                   0x1E040064,0x00000000
+#define IPU_DI0_DW_GEN_3__FULL                    0x1E040064,0xffffffff
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3     0x1E040064,0xFF000000
+#define IPU_DI0_DW_GEN_3__DI0_START_PERIOD_3      0x1E040064,0x00FF0000
+#define IPU_DI0_DW_GEN_3__DI0_CST_3               0x1E040064,0x0000C000
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1E040064,0x000001F0
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_RS_3         0x1E040064,0x0000000C
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_CLK_3        0x1E040064,0x00000003
+
+#define IPU_DI0_DW_GEN_4__ADDR                  0x1E040068
+#define IPU_DI0_DW_GEN_4__EMPTY                 0x1E040068,0x00000000
+#define IPU_DI0_DW_GEN_4__FULL                  0x1E040068,0xffffffff
+#define IPU_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4     0x1E040068,0xFF000000
+#define IPU_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1E040068,0x00FF0000
+#define IPU_DI0_DW_GEN_4__DI0_CST_4             0x1E040068,0x0000C000
+#define IPU_DI0_DW_GEN_4__DI0_PT_6_4            0x1E040068,0x00003000
+#define IPU_DI0_DW_GEN_4__DI0_PT_5_4            0x1E040068,0x00000C00
+#define IPU_DI0_DW_GEN_4__DI0_PT_4_4            0x1E040068,0x00000300
+#define IPU_DI0_DW_GEN_4__DI0_PT_3_4            0x1E040068,0x000000C0
+#define IPU_DI0_DW_GEN_4__DI0_PT_2_4            0x1E040068,0x00000030
+#define IPU_DI0_DW_GEN_4__DI0_PT_1_4            0x1E040068,0x0000000C
+#define IPU_DI0_DW_GEN_4__DI0_PT_0_4            0x1E040068,0x00000003
+
+#define IPU_DI0_DW_GEN_4__ADDR                    0x1E040068
+#define IPU_DI0_DW_GEN_4__EMPTY                   0x1E040068,0x00000000
+#define IPU_DI0_DW_GEN_4__FULL                    0x1E040068,0xffffffff
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4     0x1E040068,0xFF000000
+#define IPU_DI0_DW_GEN_4__DI0_START_PERIOD_4      0x1E040068,0x00FF0000
+#define IPU_DI0_DW_GEN_4__DI0_CST_4               0x1E040068,0x0000C000
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1E040068,0x000001F0
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_RS_4         0x1E040068,0x0000000C
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_CLK_4        0x1E040068,0x00000003
+
+#define IPU_DI0_DW_GEN_5__ADDR                  0x1E04006C
+#define IPU_DI0_DW_GEN_5__EMPTY                 0x1E04006C,0x00000000
+#define IPU_DI0_DW_GEN_5__FULL                  0x1E04006C,0xffffffff
+#define IPU_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5     0x1E04006C,0xFF000000
+#define IPU_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1E04006C,0x00FF0000
+#define IPU_DI0_DW_GEN_5__DI0_CST_5             0x1E04006C,0x0000C000
+#define IPU_DI0_DW_GEN_5__DI0_PT_6_5            0x1E04006C,0x00003000
+#define IPU_DI0_DW_GEN_5__DI0_PT_5_5            0x1E04006C,0x00000C00
+#define IPU_DI0_DW_GEN_5__DI0_PT_4_5            0x1E04006C,0x00000300
+#define IPU_DI0_DW_GEN_5__DI0_PT_3_5            0x1E04006C,0x000000C0
+#define IPU_DI0_DW_GEN_5__DI0_PT_2_5            0x1E04006C,0x00000030
+#define IPU_DI0_DW_GEN_5__DI0_PT_1_5            0x1E04006C,0x0000000C
+#define IPU_DI0_DW_GEN_5__DI0_PT_0_5            0x1E04006C,0x00000003
+
+#define IPU_DI0_DW_GEN_5__ADDR                    0x1E04006C
+#define IPU_DI0_DW_GEN_5__EMPTY                   0x1E04006C,0x00000000
+#define IPU_DI0_DW_GEN_5__FULL                    0x1E04006C,0xffffffff
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5     0x1E04006C,0xFF000000
+#define IPU_DI0_DW_GEN_5__DI0_START_PERIOD_5      0x1E04006C,0x00FF0000
+#define IPU_DI0_DW_GEN_5__DI0_CST_5               0x1E04006C,0x0000C000
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1E04006C,0x000001F0
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_RS_5         0x1E04006C,0x0000000C
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_CLK_5        0x1E04006C,0x00000003
+
+#define IPU_DI0_DW_GEN_6__ADDR                  0x1E040070
+#define IPU_DI0_DW_GEN_6__EMPTY                 0x1E040070,0x00000000
+#define IPU_DI0_DW_GEN_6__FULL                  0x1E040070,0xffffffff
+#define IPU_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6     0x1E040070,0xFF000000
+#define IPU_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1E040070,0x00FF0000
+#define IPU_DI0_DW_GEN_6__DI0_CST_6             0x1E040070,0x0000C000
+#define IPU_DI0_DW_GEN_6__DI0_PT_6_6            0x1E040070,0x00003000
+#define IPU_DI0_DW_GEN_6__DI0_PT_5_6            0x1E040070,0x00000C00
+#define IPU_DI0_DW_GEN_6__DI0_PT_4_6            0x1E040070,0x00000300
+#define IPU_DI0_DW_GEN_6__DI0_PT_3_6            0x1E040070,0x000000C0
+#define IPU_DI0_DW_GEN_6__DI0_PT_2_6            0x1E040070,0x00000030
+#define IPU_DI0_DW_GEN_6__DI0_PT_1_6            0x1E040070,0x0000000C
+#define IPU_DI0_DW_GEN_6__DI0_PT_0_6            0x1E040070,0x00000003
+
+#define IPU_DI0_DW_GEN_6__ADDR                    0x1E040070
+#define IPU_DI0_DW_GEN_6__EMPTY                   0x1E040070,0x00000000
+#define IPU_DI0_DW_GEN_6__FULL                    0x1E040070,0xffffffff
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6     0x1E040070,0xFF000000
+#define IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6      0x1E040070,0x00FF0000
+#define IPU_DI0_DW_GEN_6__DI0_CST_6               0x1E040070,0x0000C000
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1E040070,0x000001F0
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6         0x1E040070,0x0000000C
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6        0x1E040070,0x00000003
+
+#define IPU_DI0_DW_GEN_7__ADDR                  0x1E040074
+#define IPU_DI0_DW_GEN_7__EMPTY                 0x1E040074,0x00000000
+#define IPU_DI0_DW_GEN_7__FULL                  0x1E040074,0xffffffff
+#define IPU_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7     0x1E040074,0xFF000000
+#define IPU_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1E040074,0x00FF0000
+#define IPU_DI0_DW_GEN_7__DI0_CST_7             0x1E040074,0x0000C000
+#define IPU_DI0_DW_GEN_7__DI0_PT_6_7            0x1E040074,0x00003000
+#define IPU_DI0_DW_GEN_7__DI0_PT_5_7            0x1E040074,0x00000C00
+#define IPU_DI0_DW_GEN_7__DI0_PT_4_7            0x1E040074,0x00000300
+#define IPU_DI0_DW_GEN_7__DI0_PT_3_7            0x1E040074,0x000000C0
+#define IPU_DI0_DW_GEN_7__DI0_PT_2_7            0x1E040074,0x00000030
+#define IPU_DI0_DW_GEN_7__DI0_PT_1_7            0x1E040074,0x0000000C
+#define IPU_DI0_DW_GEN_7__DI0_PT_0_7            0x1E040074,0x00000003
+
+#define IPU_DI0_DW_GEN_7__ADDR                    0x1E040074
+#define IPU_DI0_DW_GEN_7__EMPTY                   0x1E040074,0x00000000
+#define IPU_DI0_DW_GEN_7__FULL                    0x1E040074,0xffffffff
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7     0x1E040074,0xFF000000
+#define IPU_DI0_DW_GEN_7__DI0_START_PERIOD_7      0x1E040074,0x00FF0000
+#define IPU_DI0_DW_GEN_7__DI0_CST_7               0x1E040074,0x0000C000
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1E040074,0x000001F0
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_RS_7         0x1E040074,0x0000000C
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_CLK_7        0x1E040074,0x00000003
+
+#define IPU_DI0_DW_GEN_8__ADDR                  0x1E040078
+#define IPU_DI0_DW_GEN_8__EMPTY                 0x1E040078,0x00000000
+#define IPU_DI0_DW_GEN_8__FULL                  0x1E040078,0xffffffff
+#define IPU_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8     0x1E040078,0xFF000000
+#define IPU_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1E040078,0x00FF0000
+#define IPU_DI0_DW_GEN_8__DI0_CST_8             0x1E040078,0x0000C000
+#define IPU_DI0_DW_GEN_8__DI0_PT_6_8            0x1E040078,0x00003000
+#define IPU_DI0_DW_GEN_8__DI0_PT_5_8            0x1E040078,0x00000C00
+#define IPU_DI0_DW_GEN_8__DI0_PT_4_8            0x1E040078,0x00000300
+#define IPU_DI0_DW_GEN_8__DI0_PT_3_8            0x1E040078,0x000000C0
+#define IPU_DI0_DW_GEN_8__DI0_PT_2_8            0x1E040078,0x00000030
+#define IPU_DI0_DW_GEN_8__DI0_PT_1_8            0x1E040078,0x0000000C
+#define IPU_DI0_DW_GEN_8__DI0_PT_0_8            0x1E040078,0x00000003
+
+#define IPU_DI0_DW_GEN_8__ADDR                    0x1E040078
+#define IPU_DI0_DW_GEN_8__EMPTY                   0x1E040078,0x00000000
+#define IPU_DI0_DW_GEN_8__FULL                    0x1E040078,0xffffffff
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8     0x1E040078,0xFF000000
+#define IPU_DI0_DW_GEN_8__DI0_START_PERIOD_8      0x1E040078,0x00FF0000
+#define IPU_DI0_DW_GEN_8__DI0_CST_8               0x1E040078,0x0000C000
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1E040078,0x000001F0
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_RS_8         0x1E040078,0x0000000C
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_CLK_8        0x1E040078,0x00000003
+
+#define IPU_DI0_DW_GEN_9__ADDR                  0x1E04007C
+#define IPU_DI0_DW_GEN_9__EMPTY                 0x1E04007C,0x00000000
+#define IPU_DI0_DW_GEN_9__FULL                  0x1E04007C,0xffffffff
+#define IPU_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9     0x1E04007C,0xFF000000
+#define IPU_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1E04007C,0x00FF0000
+#define IPU_DI0_DW_GEN_9__DI0_CST_9             0x1E04007C,0x0000C000
+#define IPU_DI0_DW_GEN_9__DI0_PT_6_9            0x1E04007C,0x00003000
+#define IPU_DI0_DW_GEN_9__DI0_PT_5_9            0x1E04007C,0x00000C00
+#define IPU_DI0_DW_GEN_9__DI0_PT_4_9            0x1E04007C,0x00000300
+#define IPU_DI0_DW_GEN_9__DI0_PT_3_9            0x1E04007C,0x000000C0
+#define IPU_DI0_DW_GEN_9__DI0_PT_2_9            0x1E04007C,0x00000030
+#define IPU_DI0_DW_GEN_9__DI0_PT_1_9            0x1E04007C,0x0000000C
+#define IPU_DI0_DW_GEN_9__DI0_PT_0_9            0x1E04007C,0x00000003
+
+#define IPU_DI0_DW_GEN_9__ADDR                    0x1E04007C
+#define IPU_DI0_DW_GEN_9__EMPTY                   0x1E04007C,0x00000000
+#define IPU_DI0_DW_GEN_9__FULL                    0x1E04007C,0xffffffff
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9     0x1E04007C,0xFF000000
+#define IPU_DI0_DW_GEN_9__DI0_START_PERIOD_9      0x1E04007C,0x00FF0000
+#define IPU_DI0_DW_GEN_9__DI0_CST_9               0x1E04007C,0x0000C000
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1E04007C,0x000001F0
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_RS_9         0x1E04007C,0x0000000C
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_CLK_9        0x1E04007C,0x00000003
+
+#define IPU_DI0_DW_GEN_10__ADDR                   0x1E040080
+#define IPU_DI0_DW_GEN_10__EMPTY                  0x1E040080,0x00000000
+#define IPU_DI0_DW_GEN_10__FULL                   0x1E040080,0xffffffff
+#define IPU_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10     0x1E040080,0xFF000000
+#define IPU_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1E040080,0x00FF0000
+#define IPU_DI0_DW_GEN_10__DI0_CST_10             0x1E040080,0x0000C000
+#define IPU_DI0_DW_GEN_10__DI0_PT_6_10            0x1E040080,0x00003000
+#define IPU_DI0_DW_GEN_10__DI0_PT_5_10            0x1E040080,0x00000C00
+#define IPU_DI0_DW_GEN_10__DI0_PT_4_10            0x1E040080,0x00000300
+#define IPU_DI0_DW_GEN_10__DI0_PT_3_10            0x1E040080,0x000000C0
+#define IPU_DI0_DW_GEN_10__DI0_PT_2_10            0x1E040080,0x00000030
+#define IPU_DI0_DW_GEN_10__DI0_PT_1_10            0x1E040080,0x0000000C
+#define IPU_DI0_DW_GEN_10__DI0_PT_0_10            0x1E040080,0x00000003
+
+#define IPU_DI0_DW_GEN_10__ADDR                     0x1E040080
+#define IPU_DI0_DW_GEN_10__EMPTY                    0x1E040080,0x00000000
+#define IPU_DI0_DW_GEN_10__FULL                     0x1E040080,0xffffffff
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10     0x1E040080,0xFF000000
+#define IPU_DI0_DW_GEN_10__DI0_START_PERIOD_10      0x1E040080,0x00FF0000
+#define IPU_DI0_DW_GEN_10__DI0_CST_10               0x1E040080,0x0000C000
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E040080,0x000001F0
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_RS_10         0x1E040080,0x0000000C
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_CLK_10        0x1E040080,0x00000003
+
+#define IPU_DI0_DW_GEN_11__ADDR                   0x1E040084
+#define IPU_DI0_DW_GEN_11__EMPTY                  0x1E040084,0x00000000
+#define IPU_DI0_DW_GEN_11__FULL                   0x1E040084,0xffffffff
+#define IPU_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11     0x1E040084,0xFF000000
+#define IPU_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1E040084,0x00FF0000
+#define IPU_DI0_DW_GEN_11__DI0_CST_11             0x1E040084,0x0000C000
+#define IPU_DI0_DW_GEN_11__DI0_PT_6_11            0x1E040084,0x00003000
+#define IPU_DI0_DW_GEN_11__DI0_PT_5_11            0x1E040084,0x00000C00
+#define IPU_DI0_DW_GEN_11__DI0_PT_4_11            0x1E040084,0x00000300
+#define IPU_DI0_DW_GEN_11__DI0_PT_3_11            0x1E040084,0x000000C0
+#define IPU_DI0_DW_GEN_11__DI0_PT_2_11            0x1E040084,0x00000030
+#define IPU_DI0_DW_GEN_11__DI0_PT_1_11            0x1E040084,0x0000000C
+#define IPU_DI0_DW_GEN_11__DI0_PT_0_11            0x1E040084,0x00000003
+
+#define IPU_DI0_DW_GEN_11__ADDR                     0x1E040084
+#define IPU_DI0_DW_GEN_11__EMPTY                    0x1E040084,0x00000000
+#define IPU_DI0_DW_GEN_11__FULL                     0x1E040084,0xffffffff
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11     0x1E040084,0xFF000000
+#define IPU_DI0_DW_GEN_11__DI0_START_PERIOD_11      0x1E040084,0x00FF0000
+#define IPU_DI0_DW_GEN_11__DI0_CST_11               0x1E040084,0x0000C000
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E040084,0x000001F0
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_RS_11         0x1E040084,0x0000000C
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_CLK_11        0x1E040084,0x00000003
+
+#define IPU_DI_DW_OFFSET                                                               0x0088
+#define DI_WAVESET_ADDR(di, pointer, set)              (IPU_DI0_GENERAL__ADDR + \
+                                                                                                                                                               di*0x8000 + IPU_DI_DW_OFFSET + \
+                                                                                                                                                               pointer*0x4 + set * 0x30)
+#define DI_WAVESET_UP(di, pointer, set)                        DI_WAVESET_ADDR(di, pointer, set), 0x000001FF
+#define DI_WAVESET_DOWN(di, pointer, set)      DI_WAVESET_ADDR(di, pointer, set), 0x01FF0000
+
+#define IPU_DI_STEP_RPT_OFFSET                                         0x0148
+#define DI_STEP_RPT_ADDR(di, pointer)                          (IPU_DI0_GENERAL__ADDR + \
+                                                                                                                                                               di*0x8000 + IPU_DI_STEP_RPT_OFFSET + \
+                                                                                                                                                               ((pointer-1) / 2)*0x4 )
+#define DI_STEP_RPT(di, pointer)                                               DI_STEP_RPT_ADDR(di, pointer), 0x0FFF<<((pointer-1)%2)*16
+
+#define IPU_DI0_STP_REP_9__ADDR              0x1E040158
+#define IPU_DI0_STP_REP_9__EMPTY             0x1E040158,0x00000000
+#define IPU_DI0_STP_REP_9__FULL              0x1E040158,0xffffffff
+#define IPU_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1E040158,0x00000FFF
+
+#define IPU_DI0_SER_CONF__ADDR                        0x1E04015C
+#define IPU_DI0_SER_CONF__EMPTY                       0x1E04015C,0x00000000
+#define IPU_DI0_SER_CONF__FULL                        0x1E04015C,0xffffffff
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1  0x1E04015C,0xF0000000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0  0x1E04015C,0x0F000000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1E04015C,0x00F00000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0  0x1E04015C,0x000F0000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LATCH            0x1E04015C,0x0000FF00
+#define IPU_DI0_SER_CONF__DI0_LLA_SER_ACCESS          0x1E04015C,0x00000020
+#define IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY        0x1E04015C,0x00000010
+#define IPU_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY    0x1E04015C,0x00000008
+#define IPU_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY      0x1E04015C,0x00000004
+#define IPU_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY      0x1E04015C,0x00000002
+#define IPU_DI0_SER_CONF__DI0_WAIT4SERIAL             0x1E04015C,0x00000001
+
+#define IPU_DI0_SSC__ADDR              0x1E040160
+#define IPU_DI0_SSC__EMPTY             0x1E040160,0x00000000
+#define IPU_DI0_SSC__FULL              0x1E040160,0xffffffff
+#define IPU_DI0_SSC__DI0_PIN17_ERM     0x1E040160,0x00800000
+#define IPU_DI0_SSC__DI0_PIN16_ERM     0x1E040160,0x00400000
+#define IPU_DI0_SSC__DI0_PIN15_ERM     0x1E040160,0x00200000
+#define IPU_DI0_SSC__DI0_PIN14_ERM     0x1E040160,0x00100000
+#define IPU_DI0_SSC__DI0_PIN13_ERM     0x1E040160,0x00080000
+#define IPU_DI0_SSC__DI0_PIN12_ERM     0x1E040160,0x00040000
+#define IPU_DI0_SSC__DI0_PIN11_ERM     0x1E040160,0x00020000
+#define IPU_DI0_SSC__DI0_CS_ERM        0x1E040160,0x00010000
+#define IPU_DI0_SSC__DI0_WAIT_ON       0x1E040160,0x00000020
+#define IPU_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1E040160,0x00000008
+#define IPU_DI0_SSC__DI0_BYTE_EN_PNTR  0x1E040160,0x00000007
+
+#define IPU_DI0_POL__ADDR                     0x1E040164
+#define IPU_DI0_POL__EMPTY                    0x1E040164,0x00000000
+#define IPU_DI0_POL__FULL                     0x1E040164,0xffffffff
+#define IPU_DI0_POL__DI0_WAIT_POLARITY        0x1E040164,0x04000000
+#define IPU_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1E040164,0x02000000
+#define IPU_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1E040164,0x01000000
+#define IPU_DI0_POL__DI0_CS1_DATA_POLARITY    0x1E040164,0x00800000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_17      0x1E040164,0x00400000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_16      0x1E040164,0x00200000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_15      0x1E040164,0x00100000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_14      0x1E040164,0x00080000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_13      0x1E040164,0x00040000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_12      0x1E040164,0x00020000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_11      0x1E040164,0x00010000
+#define IPU_DI0_POL__DI0_CS0_DATA_POLARITY    0x1E040164,0x00008000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_17      0x1E040164,0x00004000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_16      0x1E040164,0x00002000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_15      0x1E040164,0x00001000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_14      0x1E040164,0x00000800
+#define IPU_DI0_POL__DI0_CS0_POLARITY_13      0x1E040164,0x00000400
+#define IPU_DI0_POL__DI0_CS0_POLARITY_12      0x1E040164,0x00000200
+#define IPU_DI0_POL__DI0_CS0_POLARITY_11      0x1E040164,0x00000100
+#define IPU_DI0_POL__DI0_DRDY_DATA_POLARITY   0x1E040164,0x00000080
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_17     0x1E040164,0x00000040
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_16     0x1E040164,0x00000020
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_15     0x1E040164,0x00000010
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_14     0x1E040164,0x00000008
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_13     0x1E040164,0x00000004
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_12     0x1E040164,0x00000002
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_11     0x1E040164,0x00000001
+
+#define IPU_DI0_AW0__ADDR              0x1E040168
+#define IPU_DI0_AW0__EMPTY             0x1E040168,0x00000000
+#define IPU_DI0_AW0__FULL              0x1E040168,0xffffffff
+#define IPU_DI0_AW0__DI0_AW_TRIG_SEL   0x1E040168,0xF0000000
+#define IPU_DI0_AW0__DI0_AW_HEND       0x1E040168,0x0FFF0000
+#define IPU_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1E040168,0x0000F000
+#define IPU_DI0_AW0__DI0_AW_HSTART     0x1E040168,0x00000FFF
+
+#define IPU_DI0_AW1__ADDR              0x1E04016C
+#define IPU_DI0_AW1__EMPTY             0x1E04016C,0x00000000
+#define IPU_DI0_AW1__FULL              0x1E04016C,0xffffffff
+#define IPU_DI0_AW1__DI0_AW_VEND       0x1E04016C,0x0FFF0000
+#define IPU_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1E04016C,0x0000F000
+#define IPU_DI0_AW1__DI0_AW_VSTART     0x1E04016C,0x00000FFF
+
+#define IPU_DI0_SCR_CONF__ADDR              0x1E040170
+#define IPU_DI0_SCR_CONF__EMPTY             0x1E040170,0x00000000
+#define IPU_DI0_SCR_CONF__FULL              0x1E040170,0xffffffff
+#define IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1E040170,0x00000FFF
+
+#define IPU_DI0_STAT__ADDR                0x1E040174
+#define IPU_DI0_STAT__EMPTY               0x1E040174,0x00000000
+#define IPU_DI0_STAT__FULL                0x1E040174,0xffffffff
+#define IPU_DI0_STAT__DI0_CNTR_FIFO_FULL  0x1E040174,0x00000008
+#define IPU_DI0_STAT__DI0_CNTR_FIFO_EMPTY 0x1E040174,0x00000004
+#define IPU_DI0_STAT__DI0_READ_FIFO_FULL  0x1E040174,0x00000002
+#define IPU_DI0_STAT__DI0_READ_FIFO_EMPTY 0x1E040174,0x00000001
+
+#define IPU_DI1_GENERAL__ADDR                  0x1E048000
+#define IPU_DI1_GENERAL__EMPTY                 0x1E048000,0x00000000
+#define IPU_DI1_GENERAL__FULL                  0x1E048000,0xffffffff
+#define IPU_DI1_GENERAL__DI1_DISP_Y_SEL        0x1E048000,0x70000000
+#define IPU_DI1_GENERAL__DI1_CLOCK_STOP_MODE   0x1E048000,0x0F000000
+#define IPU_DI1_GENERAL__DI1_DISP_CLOCK_INIT   0x1E048000,0x00800000
+#define IPU_DI1_GENERAL__DI1_MASK_SEL          0x1E048000,0x00400000
+#define IPU_DI1_GENERAL__DI1_VSYNC_EXT         0x1E048000,0x00200000
+#define IPU_DI1_GENERAL__DI1_CLK_EXT           0x1E048000,0x00100000
+#define IPU_DI1_GENERAL__DI1_WATCHDOG_MODE     0x1E048000,0x000C0000
+#define IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1E048000,0x00020000
+#define IPU_DI1_GENERAL__DI1_SYNC_COUNT_SEL    0x1E048000,0x0000F000
+#define IPU_DI1_GENERAL__DI1_ERR_TREATMENT     0x1E048000,0x00000800
+#define IPU_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1E048000,0x00000400
+#define IPU_DI1_GENERAL__DI1_POLARITY_CS1      0x1E048000,0x00000200
+#define IPU_DI1_GENERAL__DI1_POLARITY_CS0      0x1E048000,0x00000100
+#define IPU_DI1_GENERAL__DI1_POLARITY_8        0x1E048000,0x00000080
+#define IPU_DI1_GENERAL__DI1_POLARITY_7        0x1E048000,0x00000040
+#define IPU_DI1_GENERAL__DI1_POLARITY_6        0x1E048000,0x00000020
+#define IPU_DI1_GENERAL__DI1_POLARITY_5        0x1E048000,0x00000010
+#define IPU_DI1_GENERAL__DI1_POLARITY_4        0x1E048000,0x00000008
+#define IPU_DI1_GENERAL__DI1_POLARITY_3        0x1E048000,0x00000004
+#define IPU_DI1_GENERAL__DI1_POLARITY_2        0x1E048000,0x00000002
+#define IPU_DI1_GENERAL__DI1_POLARITY_1        0x1E048000,0x00000001
+
+#define IPU_DI1_BS_CLKGEN0__ADDR                0x1E048004
+#define IPU_DI1_BS_CLKGEN0__EMPTY               0x1E048004,0x00000000
+#define IPU_DI1_BS_CLKGEN0__FULL                0x1E048004,0xffffffff
+#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1E048004,0x01FF0000
+#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1E048004,0x00000FFF
+
+#define IPU_DI1_BS_CLKGEN1__ADDR              0x1E048008
+#define IPU_DI1_BS_CLKGEN1__EMPTY             0x1E048008,0x00000000
+#define IPU_DI1_BS_CLKGEN1__FULL              0x1E048008,0xffffffff
+#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1E048008,0x01FF0000
+#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP   0x1E048008,0x000001FF
+
+#define IPU_DI1_SW_GEN0_9__ADDR                    0x1E04802C
+#define IPU_DI1_SW_GEN0_9__EMPTY                   0x1E04802C,0x00000000
+#define IPU_DI1_SW_GEN0_9__FULL                    0x1E04802C,0xffffffff
+#define IPU_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9      0x1E04802C,0x7FF80000
+#define IPU_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9    0x1E04802C,0x00070000
+#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9      0x1E04802C,0x00007FF8
+#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1E04802C,0x00000007
+
+#define IPU_DI1_SW_GEN1_9__ADDR                  0x1E048050
+#define IPU_DI1_SW_GEN1_9__EMPTY                 0x1E048050,0x00000000
+#define IPU_DI1_SW_GEN1_9__FULL                  0x1E048050,0xffffffff
+#define IPU_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9     0x1E048050,0xE0000000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1E048050,0x10000000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9     0x1E048050,0x0E000000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_DOWN_9        0x1E048050,0x01FF0000
+#define IPU_DI1_SW_GEN1_9__DI1_TAG_SEL_9         0x1E048050,0x00008000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_UP_9          0x1E048050,0x000001FF
+
+#define IPU_DI1_SYNC_AS_GEN__ADDR              0x1E048054
+#define IPU_DI1_SYNC_AS_GEN__EMPTY             0x1E048054,0x00000000
+#define IPU_DI1_SYNC_AS_GEN__FULL              0x1E048054,0xffffffff
+#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1E048054,0x10000000
+#define IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL     0x1E048054,0x0000E000
+#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START    0x1E048054,0x00000FFF
+
+#define IPU_DI1_DW_GEN_0__ADDR                  0x1E048058
+#define IPU_DI1_DW_GEN_0__EMPTY                 0x1E048058,0x00000000
+#define IPU_DI1_DW_GEN_0__FULL                  0x1E048058,0xffffffff
+#define IPU_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0     0x1E048058,0xFF000000
+#define IPU_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1E048058,0x00FF0000
+#define IPU_DI1_DW_GEN_0__DI1_CST_0             0x1E048058,0x0000C000
+#define IPU_DI1_DW_GEN_0__DI1_PT_6_0            0x1E048058,0x00003000
+#define IPU_DI1_DW_GEN_0__DI1_PT_5_0            0x1E048058,0x00000C00
+#define IPU_DI1_DW_GEN_0__DI1_PT_4_0            0x1E048058,0x00000300
+#define IPU_DI1_DW_GEN_0__DI1_PT_3_0            0x1E048058,0x000000C0
+#define IPU_DI1_DW_GEN_0__DI1_PT_2_0            0x1E048058,0x00000030
+#define IPU_DI1_DW_GEN_0__DI1_PT_1_0            0x1E048058,0x0000000C
+#define IPU_DI1_DW_GEN_0__DI1_PT_0_0            0x1E048058,0x00000003
+
+#define IPU_DI1_DW_GEN_0__ADDR                    0x1E048058
+#define IPU_DI1_DW_GEN_0__EMPTY                   0x1E048058,0x00000000
+#define IPU_DI1_DW_GEN_0__FULL                    0x1E048058,0xffffffff
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0     0x1E048058,0xFF000000
+#define IPU_DI1_DW_GEN_0__DI1_START_PERIOD_0      0x1E048058,0x00FF0000
+#define IPU_DI1_DW_GEN_0__DI1_CST_0               0x1E048058,0x0000C000
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1E048058,0x000001F0
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_RS_0         0x1E048058,0x0000000C
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_CLK_0        0x1E048058,0x00000003
+
+#define IPU_DI1_DW_GEN_1__ADDR                  0x1E04805C
+#define IPU_DI1_DW_GEN_1__EMPTY                 0x1E04805C,0x00000000
+#define IPU_DI1_DW_GEN_1__FULL                  0x1E04805C,0xffffffff
+#define IPU_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1     0x1E04805C,0xFF000000
+#define IPU_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1E04805C,0x00FF0000
+#define IPU_DI1_DW_GEN_1__DI1_CST_1             0x1E04805C,0x0000C000
+#define IPU_DI1_DW_GEN_1__DI1_PT_6_1            0x1E04805C,0x00003000
+#define IPU_DI1_DW_GEN_1__DI1_PT_5_1            0x1E04805C,0x00000C00
+#define IPU_DI1_DW_GEN_1__DI1_PT_4_1            0x1E04805C,0x00000300
+#define IPU_DI1_DW_GEN_1__DI1_PT_3_1            0x1E04805C,0x000000C0
+#define IPU_DI1_DW_GEN_1__DI1_PT_2_1            0x1E04805C,0x00000030
+#define IPU_DI1_DW_GEN_1__DI1_PT_1_1            0x1E04805C,0x0000000C
+#define IPU_DI1_DW_GEN_1__DI1_PT_0_1            0x1E04805C,0x00000003
+
+#define IPU_DI1_DW_GEN_1__ADDR                    0x1E04805C
+#define IPU_DI1_DW_GEN_1__EMPTY                   0x1E04805C,0x00000000
+#define IPU_DI1_DW_GEN_1__FULL                    0x1E04805C,0xffffffff
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1     0x1E04805C,0xFF000000
+#define IPU_DI1_DW_GEN_1__DI1_START_PERIOD_1      0x1E04805C,0x00FF0000
+#define IPU_DI1_DW_GEN_1__DI1_CST_1               0x1E04805C,0x0000C000
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1E04805C,0x000001F0
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_RS_1         0x1E04805C,0x0000000C
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_CLK_1        0x1E04805C,0x00000003
+
+#define IPU_DI1_DW_GEN_2__ADDR                  0x1E048060
+#define IPU_DI1_DW_GEN_2__EMPTY                 0x1E048060,0x00000000
+#define IPU_DI1_DW_GEN_2__FULL                  0x1E048060,0xffffffff
+#define IPU_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2     0x1E048060,0xFF000000
+#define IPU_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1E048060,0x00FF0000
+#define IPU_DI1_DW_GEN_2__DI1_CST_2             0x1E048060,0x0000C000
+#define IPU_DI1_DW_GEN_2__DI1_PT_6_2            0x1E048060,0x00003000
+#define IPU_DI1_DW_GEN_2__DI1_PT_5_2            0x1E048060,0x00000C00
+#define IPU_DI1_DW_GEN_2__DI1_PT_4_2            0x1E048060,0x00000300
+#define IPU_DI1_DW_GEN_2__DI1_PT_3_2            0x1E048060,0x000000C0
+#define IPU_DI1_DW_GEN_2__DI1_PT_2_2            0x1E048060,0x00000030
+#define IPU_DI1_DW_GEN_2__DI1_PT_1_2            0x1E048060,0x0000000C
+#define IPU_DI1_DW_GEN_2__DI1_PT_0_2            0x1E048060,0x00000003
+
+#define IPU_DI1_DW_GEN_2__ADDR                    0x1E048060
+#define IPU_DI1_DW_GEN_2__EMPTY                   0x1E048060,0x00000000
+#define IPU_DI1_DW_GEN_2__FULL                    0x1E048060,0xffffffff
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2     0x1E048060,0xFF000000
+#define IPU_DI1_DW_GEN_2__DI1_START_PERIOD_2      0x1E048060,0x00FF0000
+#define IPU_DI1_DW_GEN_2__DI1_CST_2               0x1E048060,0x0000C000
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1E048060,0x000001F0
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_RS_2         0x1E048060,0x0000000C
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_CLK_2        0x1E048060,0x00000003
+
+#define IPU_DI1_DW_GEN_3__ADDR                  0x1E048064
+#define IPU_DI1_DW_GEN_3__EMPTY                 0x1E048064,0x00000000
+#define IPU_DI1_DW_GEN_3__FULL                  0x1E048064,0xffffffff
+#define IPU_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3     0x1E048064,0xFF000000
+#define IPU_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1E048064,0x00FF0000
+#define IPU_DI1_DW_GEN_3__DI1_CST_3             0x1E048064,0x0000C000
+#define IPU_DI1_DW_GEN_3__DI1_PT_6_3            0x1E048064,0x00003000
+#define IPU_DI1_DW_GEN_3__DI1_PT_5_3            0x1E048064,0x00000C00
+#define IPU_DI1_DW_GEN_3__DI1_PT_4_3            0x1E048064,0x00000300
+#define IPU_DI1_DW_GEN_3__DI1_PT_3_3            0x1E048064,0x000000C0
+#define IPU_DI1_DW_GEN_3__DI1_PT_2_3            0x1E048064,0x00000030
+#define IPU_DI1_DW_GEN_3__DI1_PT_1_3            0x1E048064,0x0000000C
+#define IPU_DI1_DW_GEN_3__DI1_PT_0_3            0x1E048064,0x00000003
+
+#define IPU_DI1_DW_GEN_3__ADDR                    0x1E048064
+#define IPU_DI1_DW_GEN_3__EMPTY                   0x1E048064,0x00000000
+#define IPU_DI1_DW_GEN_3__FULL                    0x1E048064,0xffffffff
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3     0x1E048064,0xFF000000
+#define IPU_DI1_DW_GEN_3__DI1_START_PERIOD_3      0x1E048064,0x00FF0000
+#define IPU_DI1_DW_GEN_3__DI1_CST_3               0x1E048064,0x0000C000
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1E048064,0x000001F0
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_RS_3         0x1E048064,0x0000000C
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_CLK_3        0x1E048064,0x00000003
+
+#define IPU_DI1_DW_GEN_4__ADDR                  0x1E048068
+#define IPU_DI1_DW_GEN_4__EMPTY                 0x1E048068,0x00000000
+#define IPU_DI1_DW_GEN_4__FULL                  0x1E048068,0xffffffff
+#define IPU_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4     0x1E048068,0xFF000000
+#define IPU_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1E048068,0x00FF0000
+#define IPU_DI1_DW_GEN_4__DI1_CST_4             0x1E048068,0x0000C000
+#define IPU_DI1_DW_GEN_4__DI1_PT_6_4            0x1E048068,0x00003000
+#define IPU_DI1_DW_GEN_4__DI1_PT_5_4            0x1E048068,0x00000C00
+#define IPU_DI1_DW_GEN_4__DI1_PT_4_4            0x1E048068,0x00000300
+#define IPU_DI1_DW_GEN_4__DI1_PT_3_4            0x1E048068,0x000000C0
+#define IPU_DI1_DW_GEN_4__DI1_PT_2_4            0x1E048068,0x00000030
+#define IPU_DI1_DW_GEN_4__DI1_PT_1_4            0x1E048068,0x0000000C
+#define IPU_DI1_DW_GEN_4__DI1_PT_0_4            0x1E048068,0x00000003
+
+#define IPU_DI1_DW_GEN_4__ADDR                    0x1E048068
+#define IPU_DI1_DW_GEN_4__EMPTY                   0x1E048068,0x00000000
+#define IPU_DI1_DW_GEN_4__FULL                    0x1E048068,0xffffffff
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4     0x1E048068,0xFF000000
+#define IPU_DI1_DW_GEN_4__DI1_START_PERIOD_4      0x1E048068,0x00FF0000
+#define IPU_DI1_DW_GEN_4__DI1_CST_4               0x1E048068,0x0000C000
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1E048068,0x000001F0
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_RS_4         0x1E048068,0x0000000C
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_CLK_4        0x1E048068,0x00000003
+
+#define IPU_DI1_DW_GEN_5__ADDR                  0x1E04806C
+#define IPU_DI1_DW_GEN_5__EMPTY                 0x1E04806C,0x00000000
+#define IPU_DI1_DW_GEN_5__FULL                  0x1E04806C,0xffffffff
+#define IPU_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5     0x1E04806C,0xFF000000
+#define IPU_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1E04806C,0x00FF0000
+#define IPU_DI1_DW_GEN_5__DI1_CST_5             0x1E04806C,0x0000C000
+#define IPU_DI1_DW_GEN_5__DI1_PT_6_5            0x1E04806C,0x00003000
+#define IPU_DI1_DW_GEN_5__DI1_PT_5_5            0x1E04806C,0x00000C00
+#define IPU_DI1_DW_GEN_5__DI1_PT_4_5            0x1E04806C,0x00000300
+#define IPU_DI1_DW_GEN_5__DI1_PT_3_5            0x1E04806C,0x000000C0
+#define IPU_DI1_DW_GEN_5__DI1_PT_2_5            0x1E04806C,0x00000030
+#define IPU_DI1_DW_GEN_5__DI1_PT_1_5            0x1E04806C,0x0000000C
+#define IPU_DI1_DW_GEN_5__DI1_PT_0_5            0x1E04806C,0x00000003
+
+#define IPU_DI1_DW_GEN_5__ADDR                    0x1E04806C
+#define IPU_DI1_DW_GEN_5__EMPTY                   0x1E04806C,0x00000000
+#define IPU_DI1_DW_GEN_5__FULL                    0x1E04806C,0xffffffff
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5     0x1E04806C,0xFF000000
+#define IPU_DI1_DW_GEN_5__DI1_START_PERIOD_5      0x1E04806C,0x00FF0000
+#define IPU_DI1_DW_GEN_5__DI1_CST_5               0x1E04806C,0x0000C000
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1E04806C,0x000001F0
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_RS_5         0x1E04806C,0x0000000C
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_CLK_5        0x1E04806C,0x00000003
+
+#define IPU_DI1_DW_GEN_6__ADDR                  0x1E048070
+#define IPU_DI1_DW_GEN_6__EMPTY                 0x1E048070,0x00000000
+#define IPU_DI1_DW_GEN_6__FULL                  0x1E048070,0xffffffff
+#define IPU_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6     0x1E048070,0xFF000000
+#define IPU_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1E048070,0x00FF0000
+#define IPU_DI1_DW_GEN_6__DI1_CST_6             0x1E048070,0x0000C000
+#define IPU_DI1_DW_GEN_6__DI1_PT_6_6            0x1E048070,0x00003000
+#define IPU_DI1_DW_GEN_6__DI1_PT_5_6            0x1E048070,0x00000C00
+#define IPU_DI1_DW_GEN_6__DI1_PT_4_6            0x1E048070,0x00000300
+#define IPU_DI1_DW_GEN_6__DI1_PT_3_6            0x1E048070,0x000000C0
+#define IPU_DI1_DW_GEN_6__DI1_PT_2_6            0x1E048070,0x00000030
+#define IPU_DI1_DW_GEN_6__DI1_PT_1_6            0x1E048070,0x0000000C
+#define IPU_DI1_DW_GEN_6__DI1_PT_0_6            0x1E048070,0x00000003
+
+#define IPU_DI1_DW_GEN_6__ADDR                    0x1E048070
+#define IPU_DI1_DW_GEN_6__EMPTY                   0x1E048070,0x00000000
+#define IPU_DI1_DW_GEN_6__FULL                    0x1E048070,0xffffffff
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6     0x1E048070,0xFF000000
+#define IPU_DI1_DW_GEN_6__DI1_START_PERIOD_6      0x1E048070,0x00FF0000
+#define IPU_DI1_DW_GEN_6__DI1_CST_6               0x1E048070,0x0000C000
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1E048070,0x000001F0
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_RS_6         0x1E048070,0x0000000C
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_CLK_6        0x1E048070,0x00000003
+
+#define IPU_DI1_DW_GEN_7__ADDR                  0x1E048074
+#define IPU_DI1_DW_GEN_7__EMPTY                 0x1E048074,0x00000000
+#define IPU_DI1_DW_GEN_7__FULL                  0x1E048074,0xffffffff
+#define IPU_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7     0x1E048074,0xFF000000
+#define IPU_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1E048074,0x00FF0000
+#define IPU_DI1_DW_GEN_7__DI1_CST_7             0x1E048074,0x0000C000
+#define IPU_DI1_DW_GEN_7__DI1_PT_6_7            0x1E048074,0x00003000
+#define IPU_DI1_DW_GEN_7__DI1_PT_5_7            0x1E048074,0x00000C00
+#define IPU_DI1_DW_GEN_7__DI1_PT_4_7            0x1E048074,0x00000300
+#define IPU_DI1_DW_GEN_7__DI1_PT_3_7            0x1E048074,0x000000C0
+#define IPU_DI1_DW_GEN_7__DI1_PT_2_7            0x1E048074,0x00000030
+#define IPU_DI1_DW_GEN_7__DI1_PT_1_7            0x1E048074,0x0000000C
+#define IPU_DI1_DW_GEN_7__DI1_PT_0_7            0x1E048074,0x00000003
+
+#define IPU_DI1_DW_GEN_7__ADDR                    0x1E048074
+#define IPU_DI1_DW_GEN_7__EMPTY                   0x1E048074,0x00000000
+#define IPU_DI1_DW_GEN_7__FULL                    0x1E048074,0xffffffff
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7     0x1E048074,0xFF000000
+#define IPU_DI1_DW_GEN_7__DI1_START_PERIOD_7      0x1E048074,0x00FF0000
+#define IPU_DI1_DW_GEN_7__DI1_CST_7               0x1E048074,0x0000C000
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1E048074,0x000001F0
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_RS_7         0x1E048074,0x0000000C
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_CLK_7        0x1E048074,0x00000003
+
+#define IPU_DI1_DW_GEN_8__ADDR                  0x1E048078
+#define IPU_DI1_DW_GEN_8__EMPTY                 0x1E048078,0x00000000
+#define IPU_DI1_DW_GEN_8__FULL                  0x1E048078,0xffffffff
+#define IPU_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8     0x1E048078,0xFF000000
+#define IPU_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1E048078,0x00FF0000
+#define IPU_DI1_DW_GEN_8__DI1_CST_8             0x1E048078,0x0000C000
+#define IPU_DI1_DW_GEN_8__DI1_PT_6_8            0x1E048078,0x00003000
+#define IPU_DI1_DW_GEN_8__DI1_PT_5_8            0x1E048078,0x00000C00
+#define IPU_DI1_DW_GEN_8__DI1_PT_4_8            0x1E048078,0x00000300
+#define IPU_DI1_DW_GEN_8__DI1_PT_3_8            0x1E048078,0x000000C0
+#define IPU_DI1_DW_GEN_8__DI1_PT_2_8            0x1E048078,0x00000030
+#define IPU_DI1_DW_GEN_8__DI1_PT_1_8            0x1E048078,0x0000000C
+#define IPU_DI1_DW_GEN_8__DI1_PT_0_8            0x1E048078,0x00000003
+
+#define IPU_DI1_DW_GEN_8__ADDR                    0x1E048078
+#define IPU_DI1_DW_GEN_8__EMPTY                   0x1E048078,0x00000000
+#define IPU_DI1_DW_GEN_8__FULL                    0x1E048078,0xffffffff
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8     0x1E048078,0xFF000000
+#define IPU_DI1_DW_GEN_8__DI1_START_PERIOD_8      0x1E048078,0x00FF0000
+#define IPU_DI1_DW_GEN_8__DI1_CST_8               0x1E048078,0x0000C000
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1E048078,0x000001F0
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_RS_8         0x1E048078,0x0000000C
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_CLK_8        0x1E048078,0x00000003
+
+#define IPU_DI1_DW_GEN_9__ADDR                  0x1E04807C
+#define IPU_DI1_DW_GEN_9__EMPTY                 0x1E04807C,0x00000000
+#define IPU_DI1_DW_GEN_9__FULL                  0x1E04807C,0xffffffff
+#define IPU_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9     0x1E04807C,0xFF000000
+#define IPU_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1E04807C,0x00FF0000
+#define IPU_DI1_DW_GEN_9__DI1_CST_9             0x1E04807C,0x0000C000
+#define IPU_DI1_DW_GEN_9__DI1_PT_6_9            0x1E04807C,0x00003000
+#define IPU_DI1_DW_GEN_9__DI1_PT_5_9            0x1E04807C,0x00000C00
+#define IPU_DI1_DW_GEN_9__DI1_PT_4_9            0x1E04807C,0x00000300
+#define IPU_DI1_DW_GEN_9__DI1_PT_3_9            0x1E04807C,0x000000C0
+#define IPU_DI1_DW_GEN_9__DI1_PT_2_9            0x1E04807C,0x00000030
+#define IPU_DI1_DW_GEN_9__DI1_PT_1_9            0x1E04807C,0x0000000C
+#define IPU_DI1_DW_GEN_9__DI1_PT_0_9            0x1E04807C,0x00000003
+
+#define IPU_DI1_DW_GEN_9__ADDR                    0x1E04807C
+#define IPU_DI1_DW_GEN_9__EMPTY                   0x1E04807C,0x00000000
+#define IPU_DI1_DW_GEN_9__FULL                    0x1E04807C,0xffffffff
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9     0x1E04807C,0xFF000000
+#define IPU_DI1_DW_GEN_9__DI1_START_PERIOD_9      0x1E04807C,0x00FF0000
+#define IPU_DI1_DW_GEN_9__DI1_CST_9               0x1E04807C,0x0000C000
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1E04807C,0x000001F0
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_RS_9         0x1E04807C,0x0000000C
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_CLK_9        0x1E04807C,0x00000003
+
+#define IPU_DI1_DW_GEN_10__ADDR                   0x1E048080
+#define IPU_DI1_DW_GEN_10__EMPTY                  0x1E048080,0x00000000
+#define IPU_DI1_DW_GEN_10__FULL                   0x1E048080,0xffffffff
+#define IPU_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10     0x1E048080,0xFF000000
+#define IPU_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1E048080,0x00FF0000
+#define IPU_DI1_DW_GEN_10__DI1_CST_10             0x1E048080,0x0000C000
+#define IPU_DI1_DW_GEN_10__DI1_PT_6_10            0x1E048080,0x00003000
+#define IPU_DI1_DW_GEN_10__DI1_PT_5_10            0x1E048080,0x00000C00
+#define IPU_DI1_DW_GEN_10__DI1_PT_4_10            0x1E048080,0x00000300
+#define IPU_DI1_DW_GEN_10__DI1_PT_3_10            0x1E048080,0x000000C0
+#define IPU_DI1_DW_GEN_10__DI1_PT_2_10            0x1E048080,0x00000030
+#define IPU_DI1_DW_GEN_10__DI1_PT_1_10            0x1E048080,0x0000000C
+#define IPU_DI1_DW_GEN_10__DI1_PT_0_10            0x1E048080,0x00000003
+
+#define IPU_DI1_DW_GEN_10__ADDR                     0x1E048080
+#define IPU_DI1_DW_GEN_10__EMPTY                    0x1E048080,0x00000000
+#define IPU_DI1_DW_GEN_10__FULL                     0x1E048080,0xffffffff
+#define IPU_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10     0x1E048080,0xFF000000
+#define IPU_DI1_DW_GEN_10__DI1_START_PERIOD_10      0x1E048080,0x00FF0000
+#define IPU_DI1_DW_GEN_10__DI1_CST_10               0x1E048080,0x0000C000
+#define IPU_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E048080,0x000001F0
+#define IPU_DI1_DW_GEN_10__DI1_SERIAL_RS_10         0x1E048080,0x0000000C
+#define IPU_DI1_DW_GEN_10__DI1_SERIAL_CLK_10        0x1E048080,0x00000003
+
+#define IPU_DI1_DW_GEN_11__ADDR                   0x1E048084
+#define IPU_DI1_DW_GEN_11__EMPTY                  0x1E048084,0x00000000
+#define IPU_DI1_DW_GEN_11__FULL                   0x1E048084,0xffffffff
+#define IPU_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11     0x1E048084,0xFF000000
+#define IPU_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1E048084,0x00FF0000
+#define IPU_DI1_DW_GEN_11__DI1_CST_11             0x1E048084,0x0000C000
+#define IPU_DI1_DW_GEN_11__DI1_PT_6_11            0x1E048084,0x00003000
+#define IPU_DI1_DW_GEN_11__DI1_PT_5_11            0x1E048084,0x00000C00
+#define IPU_DI1_DW_GEN_11__DI1_PT_4_11            0x1E048084,0x00000300
+#define IPU_DI1_DW_GEN_11__DI1_PT_3_11            0x1E048084,0x000000C0
+#define IPU_DI1_DW_GEN_11__DI1_PT_2_11            0x1E048084,0x00000030
+#define IPU_DI1_DW_GEN_11__DI1_PT_1_11            0x1E048084,0x0000000C
+#define IPU_DI1_DW_GEN_11__DI1_PT_0_11            0x1E048084,0x00000003
+
+#define IPU_DI1_DW_GEN_11__ADDR                     0x1E048084
+#define IPU_DI1_DW_GEN_11__EMPTY                    0x1E048084,0x00000000
+#define IPU_DI1_DW_GEN_11__FULL                     0x1E048084,0xffffffff
+#define IPU_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11     0x1E048084,0xFF000000
+#define IPU_DI1_DW_GEN_11__DI1_START_PERIOD_11      0x1E048084,0x00FF0000
+#define IPU_DI1_DW_GEN_11__DI1_CST_11               0x1E048084,0x0000C000
+#define IPU_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E048084,0x000001F0
+#define IPU_DI1_DW_GEN_11__DI1_SERIAL_RS_11         0x1E048084,0x0000000C
+#define IPU_DI1_DW_GEN_11__DI1_SERIAL_CLK_11        0x1E048084,0x00000003
+
+#define IPU_DI1_STP_REP_9__ADDR              0x1E048158
+#define IPU_DI1_STP_REP_9__EMPTY             0x1E048158,0x00000000
+#define IPU_DI1_STP_REP_9__FULL              0x1E048158,0xffffffff
+#define IPU_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1E048158,0x00000FFF
+
+#define IPU_DI1_SER_CONF__ADDR                       0x1E04815C
+#define IPU_DI1_SER_CONF__EMPTY                      0x1E04815C,0x00000000
+#define IPU_DI1_SER_CONF__FULL                       0x1E04815C,0xffffffff
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1E04815C,0xF0000000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1E04815C,0x0F000000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1E04815C,0x00F00000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1E04815C,0x000F0000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LATCH           0x1E04815C,0x0000FF00
+#define IPU_DI1_SER_CONF__DI1_LLA_SER_ACCESS         0x1E04815C,0x00000020
+#define IPU_DI1_SER_CONF__DI1_SER_CLK_POLARITY       0x1E04815C,0x00000010
+#define IPU_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY   0x1E04815C,0x00000008
+#define IPU_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY     0x1E04815C,0x00000004
+#define IPU_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY     0x1E04815C,0x00000002
+#define IPU_DI1_SER_CONF__DI1_WAIT4SERIAL            0x1E04815C,0x00000001
+
+#define IPU_DI1_SSC__ADDR              0x1E048160
+#define IPU_DI1_SSC__EMPTY             0x1E048160,0x00000000
+#define IPU_DI1_SSC__FULL              0x1E048160,0xffffffff
+#define IPU_DI1_SSC__DI1_PIN17_ERM     0x1E048160,0x00800000
+#define IPU_DI1_SSC__DI1_PIN16_ERM     0x1E048160,0x00400000
+#define IPU_DI1_SSC__DI1_PIN15_ERM     0x1E048160,0x00200000
+#define IPU_DI1_SSC__DI1_PIN14_ERM     0x1E048160,0x00100000
+#define IPU_DI1_SSC__DI1_PIN13_ERM     0x1E048160,0x00080000
+#define IPU_DI1_SSC__DI1_PIN12_ERM     0x1E048160,0x00040000
+#define IPU_DI1_SSC__DI1_PIN11_ERM     0x1E048160,0x00020000
+#define IPU_DI1_SSC__DI1_CS_ERM        0x1E048160,0x00010000
+#define IPU_DI1_SSC__DI1_WAIT_ON       0x1E048160,0x00000020
+#define IPU_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1E048160,0x00000008
+#define IPU_DI1_SSC__DI1_BYTE_EN_PNTR  0x1E048160,0x00000007
+
+#define IPU_DI1_POL__ADDR                     0x1E048164
+#define IPU_DI1_POL__EMPTY                    0x1E048164,0x00000000
+#define IPU_DI1_POL__FULL                     0x1E048164,0xffffffff
+#define IPU_DI1_POL__DI1_WAIT_POLARITY        0x1E048164,0x04000000
+#define IPU_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1E048164,0x02000000
+#define IPU_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1E048164,0x01000000
+#define IPU_DI1_POL__DI1_CS1_DATA_POLARITY    0x1E048164,0x00800000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_17      0x1E048164,0x00400000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_16      0x1E048164,0x00200000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_15      0x1E048164,0x00100000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_14      0x1E048164,0x00080000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_13      0x1E048164,0x00040000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_12      0x1E048164,0x00020000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_11      0x1E048164,0x00010000
+#define IPU_DI1_POL__DI1_CS0_DATA_POLARITY    0x1E048164,0x00008000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_17      0x1E048164,0x00004000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_16      0x1E048164,0x00002000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_15      0x1E048164,0x00001000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_14      0x1E048164,0x00000800
+#define IPU_DI1_POL__DI1_CS0_POLARITY_13      0x1E048164,0x00000400
+#define IPU_DI1_POL__DI1_CS0_POLARITY_12      0x1E048164,0x00000200
+#define IPU_DI1_POL__DI1_CS0_POLARITY_11      0x1E048164,0x00000100
+#define IPU_DI1_POL__DI1_DRDY_DATA_POLARITY   0x1E048164,0x00000080
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_17     0x1E048164,0x00000040
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_16     0x1E048164,0x00000020
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_15     0x1E048164,0x00000010
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_14     0x1E048164,0x00000008
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_13     0x1E048164,0x00000004
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_12     0x1E048164,0x00000002
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_11     0x1E048164,0x00000001
+
+#define IPU_DI1_AW0__ADDR              0x1E048168
+#define IPU_DI1_AW0__EMPTY             0x1E048168,0x00000000
+#define IPU_DI1_AW0__FULL              0x1E048168,0xffffffff
+#define IPU_DI1_AW0__DI1_AW_TRIG_SEL   0x1E048168,0xF0000000
+#define IPU_DI1_AW0__DI1_AW_HEND       0x1E048168,0x0FFF0000
+#define IPU_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1E048168,0x0000F000
+#define IPU_DI1_AW0__DI1_AW_HSTART     0x1E048168,0x00000FFF
+
+#define IPU_DI1_AW1__ADDR              0x1E04816C
+#define IPU_DI1_AW1__EMPTY             0x1E04816C,0x00000000
+#define IPU_DI1_AW1__FULL              0x1E04816C,0xffffffff
+#define IPU_DI1_AW1__DI1_AW_VEND       0x1E04816C,0x0FFF0000
+#define IPU_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1E04816C,0x0000F000
+#define IPU_DI1_AW1__DI1_AW_VSTART     0x1E04816C,0x00000FFF
+
+#define IPU_DI1_SCR_CONF__ADDR              0x1E048170
+#define IPU_DI1_SCR_CONF__EMPTY             0x1E048170,0x00000000
+#define IPU_DI1_SCR_CONF__FULL              0x1E048170,0xffffffff
+#define IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1E048170,0x00000FFF
+
+#define IPU_DI1_STAT__ADDR                0x1E048174
+#define IPU_DI1_STAT__EMPTY               0x1E048174,0x00000000
+#define IPU_DI1_STAT__FULL                0x1E048174,0xffffffff
+#define IPU_DI1_STAT__DI1_CNTR_FIFO_FULL  0x1E048174,0x00000008
+#define IPU_DI1_STAT__DI1_CNTR_FIFO_EMPTY 0x1E048174,0x00000004
+#define IPU_DI1_STAT__DI1_READ_FIFO_FULL  0x1E048174,0x00000002
+#define IPU_DI1_STAT__DI1_READ_FIFO_EMPTY 0x1E048174,0x00000001
+
+#define IPU_DC_READ_CH_CONF__ADDR                0x1E058000
+#define IPU_DC_READ_CH_CONF__EMPTY               0x1E058000,0x00000000
+#define IPU_DC_READ_CH_CONF__FULL                0x1E058000,0xffffffff
+#define IPU_DC_READ_CH_CONF__TIME_OUT_VALUE      0x1E058000,0xFFFF0000
+#define IPU_DC_READ_CH_CONF__CS_ID_3             0x1E058000,0x00000800
+#define IPU_DC_READ_CH_CONF__CS_ID_2             0x1E058000,0x00000400
+#define IPU_DC_READ_CH_CONF__CS_ID_1             0x1E058000,0x00000200
+#define IPU_DC_READ_CH_CONF__CS_ID_0             0x1E058000,0x00000100
+#define IPU_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0 0x1E058000,0x00000040
+#define IPU_DC_READ_CH_CONF__W_SIZE_0            0x1E058000,0x00000030
+#define IPU_DC_READ_CH_CONF__PROG_DISP_ID_0      0x1E058000,0x0000000C
+#define IPU_DC_READ_CH_CONF__PROG_DI_ID_0        0x1E058000,0x00000002
+#define IPU_DC_READ_CH_CONF__RD_CHANNEL_EN       0x1E058000,0x00000001
+
+#define IPU_DC_READ_CH_ADDR__ADDR      0x1E058004
+#define IPU_DC_READ_CH_ADDR__EMPTY     0x1E058004,0x00000000
+#define IPU_DC_READ_CH_ADDR__FULL      0x1E058004,0xffffffff
+#define IPU_DC_READ_CH_ADDR__ST_ADDR_0 0x1E058004,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_0__ADDR                   0x1E058008
+#define IPU_DC_RL0_CH_0__EMPTY                  0x1E058008,0x00000000
+#define IPU_DC_RL0_CH_0__FULL                   0x1E058008,0xffffffff
+#define IPU_DC_RL0_CH_0__COD_NL_START_CHAN_0    0x1E058008,0xFF000000
+#define IPU_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0 0x1E058008,0x000F0000
+#define IPU_DC_RL0_CH_0__COD_NF_START_CHAN_0    0x1E058008,0x0000FF00
+#define IPU_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0 0x1E058008,0x0000000F
+
+#define IPU_DC_RL1_CH_0__ADDR                       0x1E05800C
+#define IPU_DC_RL1_CH_0__EMPTY                      0x1E05800C,0x00000000
+#define IPU_DC_RL1_CH_0__FULL                       0x1E05800C,0xffffffff
+#define IPU_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0    0x1E05800C,0xFF000000
+#define IPU_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0 0x1E05800C,0x000F0000
+#define IPU_DC_RL1_CH_0__COD_EOF_START_CHAN_0       0x1E05800C,0x0000FF00
+#define IPU_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0    0x1E05800C,0x0000000F
+
+#define IPU_DC_RL2_CH_0__ADDR                        0x1E058010
+#define IPU_DC_RL2_CH_0__EMPTY                       0x1E058010,0x00000000
+#define IPU_DC_RL2_CH_0__FULL                        0x1E058010,0xffffffff
+#define IPU_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0    0x1E058010,0xFF000000
+#define IPU_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0 0x1E058010,0x000F0000
+#define IPU_DC_RL2_CH_0__COD_EOL_START_CHAN_0        0x1E058010,0x0000FF00
+#define IPU_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0     0x1E058010,0x0000000F
+
+#define IPU_DC_RL3_CH_0__ADDR                         0x1E058014
+#define IPU_DC_RL3_CH_0__EMPTY                        0x1E058014,0x00000000
+#define IPU_DC_RL3_CH_0__FULL                         0x1E058014,0xffffffff
+#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0    0x1E058014,0xFF000000
+#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0 0x1E058014,0x000F0000
+#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0    0x1E058014,0x0000FF00
+#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0 0x1E058014,0x0000000F
+
+#define IPU_DC_RL4_CH_0__ADDR                         0x1E058018
+#define IPU_DC_RL4_CH_0__EMPTY                        0x1E058018,0x00000000
+#define IPU_DC_RL4_CH_0__FULL                         0x1E058018,0xffffffff
+#define IPU_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0    0x1E058018,0x0000FF00
+#define IPU_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0 0x1E058018,0x0000000F
+
+#define IPU_DC_WR_CH_CONF_1__ADDR                0x1E05801C
+#define IPU_DC_WR_CH_CONF_1__EMPTY               0x1E05801C,0x00000000
+#define IPU_DC_WR_CH_CONF_1__FULL                0x1E05801C,0xffffffff
+#define IPU_DC_WR_CH_CONF_1__PROG_START_TIME_1   0x1E05801C,0x07FF0000
+#define IPU_DC_WR_CH_CONF_1__FIELD_MODE_1        0x1E05801C,0x00000200
+#define IPU_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1 0x1E05801C,0x00000100
+#define IPU_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1     0x1E05801C,0x000000E0
+#define IPU_DC_WR_CH_CONF_1__PROG_DISP_ID_1      0x1E05801C,0x00000018
+#define IPU_DC_WR_CH_CONF_1__PROG_DI_ID_1        0x1E05801C,0x00000004
+#define IPU_DC_WR_CH_CONF_1__W_SIZE_1            0x1E05801C,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_1__ADDR      0x1E058020
+#define IPU_DC_WR_CH_ADDR_1__EMPTY     0x1E058020,0x00000000
+#define IPU_DC_WR_CH_ADDR_1__FULL      0x1E058020,0xffffffff
+#define IPU_DC_WR_CH_ADDR_1__ST_ADDR_1 0x1E058020,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_1__ADDR                   0x1E058024
+#define IPU_DC_RL0_CH_1__EMPTY                  0x1E058024,0x00000000
+#define IPU_DC_RL0_CH_1__FULL                   0x1E058024,0xffffffff
+#define IPU_DC_RL0_CH_1__COD_NL_START_CHAN_1    0x1E058024,0xFF000000
+#define IPU_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1 0x1E058024,0x000F0000
+#define IPU_DC_RL0_CH_1__COD_NF_START_CHAN_1    0x1E058024,0x0000FF00
+#define IPU_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1 0x1E058024,0x0000000F
+
+#define IPU_DC_RL1_CH_1__ADDR                       0x1E058028
+#define IPU_DC_RL1_CH_1__EMPTY                      0x1E058028,0x00000000
+#define IPU_DC_RL1_CH_1__FULL                       0x1E058028,0xffffffff
+#define IPU_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1    0x1E058028,0xFF000000
+#define IPU_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1 0x1E058028,0x000F0000
+#define IPU_DC_RL1_CH_1__COD_EOF_START_CHAN_1       0x1E058028,0x0000FF00
+#define IPU_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1    0x1E058028,0x0000000F
+
+#define IPU_DC_RL2_CH_1__ADDR                        0x1E05802C
+#define IPU_DC_RL2_CH_1__EMPTY                       0x1E05802C,0x00000000
+#define IPU_DC_RL2_CH_1__FULL                        0x1E05802C,0xffffffff
+#define IPU_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1    0x1E05802C,0xFF000000
+#define IPU_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1 0x1E05802C,0x000F0000
+#define IPU_DC_RL2_CH_1__COD_EOL_START_CHAN_1        0x1E05802C,0x0000FF00
+#define IPU_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1     0x1E05802C,0x0000000F
+
+#define IPU_DC_RL3_CH_1__ADDR                         0x1E058030
+#define IPU_DC_RL3_CH_1__EMPTY                        0x1E058030,0x00000000
+#define IPU_DC_RL3_CH_1__FULL                         0x1E058030,0xffffffff
+#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1    0x1E058030,0xFF000000
+#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1 0x1E058030,0x000F0000
+#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1    0x1E058030,0x0000FF00
+#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1 0x1E058030,0x0000000F
+
+#define IPU_DC_RL4_CH_1__ADDR                         0x1E058034
+#define IPU_DC_RL4_CH_1__EMPTY                        0x1E058034,0x00000000
+#define IPU_DC_RL4_CH_1__FULL                         0x1E058034,0xffffffff
+#define IPU_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1    0x1E058034,0x0000FF00
+#define IPU_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1 0x1E058034,0x0000000F
+
+#define IPU_DC_WR_CH_CONF_2__ADDR                0x1E058038
+#define IPU_DC_WR_CH_CONF_2__EMPTY               0x1E058038,0x00000000
+#define IPU_DC_WR_CH_CONF_2__FULL                0x1E058038,0xffffffff
+#define IPU_DC_WR_CH_CONF_2__PROG_START_TIME_2   0x1E058038,0x07FF0000
+#define IPU_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1E058038,0x00000100
+#define IPU_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2     0x1E058038,0x000000E0
+#define IPU_DC_WR_CH_CONF_2__PROG_DISP_ID_2      0x1E058038,0x00000018
+#define IPU_DC_WR_CH_CONF_2__PROG_DI_ID_2        0x1E058038,0x00000004
+#define IPU_DC_WR_CH_CONF_2__W_SIZE_2            0x1E058038,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_2__ADDR      0x1E05803C
+#define IPU_DC_WR_CH_ADDR_2__EMPTY     0x1E05803C,0x00000000
+#define IPU_DC_WR_CH_ADDR_2__FULL      0x1E05803C,0xffffffff
+#define IPU_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1E05803C,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_2__ADDR                   0x1E058040
+#define IPU_DC_RL0_CH_2__EMPTY                  0x1E058040,0x00000000
+#define IPU_DC_RL0_CH_2__FULL                   0x1E058040,0xffffffff
+#define IPU_DC_RL0_CH_2__COD_NL_START_CHAN_2    0x1E058040,0xFF000000
+#define IPU_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1E058040,0x000F0000
+#define IPU_DC_RL0_CH_2__COD_NF_START_CHAN_2    0x1E058040,0x0000FF00
+#define IPU_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1E058040,0x0000000F
+
+#define IPU_DC_RL1_CH_2__ADDR                       0x1E058044
+#define IPU_DC_RL1_CH_2__EMPTY                      0x1E058044,0x00000000
+#define IPU_DC_RL1_CH_2__FULL                       0x1E058044,0xffffffff
+#define IPU_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2    0x1E058044,0xFF000000
+#define IPU_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1E058044,0x000F0000
+#define IPU_DC_RL1_CH_2__COD_EOF_START_CHAN_2       0x1E058044,0x0000FF00
+#define IPU_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2    0x1E058044,0x0000000F
+
+#define IPU_DC_RL2_CH_2__ADDR                        0x1E058048
+#define IPU_DC_RL2_CH_2__EMPTY                       0x1E058048,0x00000000
+#define IPU_DC_RL2_CH_2__FULL                        0x1E058048,0xffffffff
+#define IPU_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2    0x1E058048,0xFF000000
+#define IPU_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1E058048,0x000F0000
+#define IPU_DC_RL2_CH_2__COD_EOL_START_CHAN_2        0x1E058048,0x0000FF00
+#define IPU_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2     0x1E058048,0x0000000F
+
+#define IPU_DC_RL3_CH_2__ADDR                         0x1E05804C
+#define IPU_DC_RL3_CH_2__EMPTY                        0x1E05804C,0x00000000
+#define IPU_DC_RL3_CH_2__FULL                         0x1E05804C,0xffffffff
+#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2    0x1E05804C,0xFF000000
+#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1E05804C,0x000F0000
+#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2    0x1E05804C,0x0000FF00
+#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1E05804C,0x0000000F
+
+#define IPU_DC_RL4_CH_2__ADDR                         0x1E058050
+#define IPU_DC_RL4_CH_2__EMPTY                        0x1E058050,0x00000000
+#define IPU_DC_RL4_CH_2__FULL                         0x1E058050,0xffffffff
+#define IPU_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2    0x1E058050,0x0000FF00
+#define IPU_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1E058050,0x0000000F
+
+#define IPU_DC_CMD_CH_CONF_3__ADDR                      0x1E058054
+#define IPU_DC_CMD_CH_CONF_3__EMPTY                     0x1E058054,0x00000000
+#define IPU_DC_CMD_CH_CONF_3__FULL                      0x1E058054,0xffffffff
+#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3 0x1E058054,0xFF000000
+#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3 0x1E058054,0x0000FF00
+#define IPU_DC_CMD_CH_CONF_3__W_SIZE_3                  0x1E058054,0x00000003
+
+#define IPU_DC_CMD_CH_CONF_4__ADDR                      0x1E058058
+#define IPU_DC_CMD_CH_CONF_4__EMPTY                     0x1E058058,0x00000000
+#define IPU_DC_CMD_CH_CONF_4__FULL                      0x1E058058,0xffffffff
+#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4 0x1E058058,0xFF000000
+#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4 0x1E058058,0x0000FF00
+#define IPU_DC_CMD_CH_CONF_4__W_SIZE_4                  0x1E058058,0x00000003
+
+#define IPU_DC_WR_CH_CONF_5__ADDR                0x1E05805C
+#define IPU_DC_WR_CH_CONF_5__EMPTY               0x1E05805C,0x00000000
+#define IPU_DC_WR_CH_CONF_5__FULL                0x1E05805C,0xffffffff
+#define IPU_DC_WR_CH_CONF_5__PROG_START_TIME_5   0x1E05805C,0x07FF0000
+#define IPU_DC_WR_CH_CONF_5__FIELD_MODE_5        0x1E05805C,0x00000200
+#define IPU_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5 0x1E05805C,0x00000100
+#define IPU_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5     0x1E05805C,0x000000E0
+#define IPU_DC_WR_CH_CONF_5__PROG_DISP_ID_5      0x1E05805C,0x00000018
+#define IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5        0x1E05805C,0x00000004
+#define IPU_DC_WR_CH_CONF_5__W_SIZE_5            0x1E05805C,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_5__ADDR      0x1E058060
+#define IPU_DC_WR_CH_ADDR_5__EMPTY     0x1E058060,0x00000000
+#define IPU_DC_WR_CH_ADDR_5__FULL      0x1E058060,0xffffffff
+#define IPU_DC_WR_CH_ADDR_5__ST_ADDR_5 0x1E058060,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_5__ADDR                   0x1E058064
+#define IPU_DC_RL0_CH_5__EMPTY                  0x1E058064,0x00000000
+#define IPU_DC_RL0_CH_5__FULL                   0x1E058064,0xffffffff
+#define IPU_DC_RL0_CH_5__COD_NL_START_CHAN_5    0x1E058064,0xFF000000
+#define IPU_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5 0x1E058064,0x000F0000
+#define IPU_DC_RL0_CH_5__COD_NF_START_CHAN_5    0x1E058064,0x0000FF00
+#define IPU_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5 0x1E058064,0x0000000F
+
+#define IPU_DC_RL1_CH_5__ADDR                       0x1E058068
+#define IPU_DC_RL1_CH_5__EMPTY                      0x1E058068,0x00000000
+#define IPU_DC_RL1_CH_5__FULL                       0x1E058068,0xffffffff
+#define IPU_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5    0x1E058068,0xFF000000
+#define IPU_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5 0x1E058068,0x000F0000
+#define IPU_DC_RL1_CH_5__COD_EOF_START_CHAN_5       0x1E058068,0x0000FF00
+#define IPU_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5    0x1E058068,0x0000000F
+
+#define IPU_DC_RL2_CH_5__ADDR                        0x1E05806C
+#define IPU_DC_RL2_CH_5__EMPTY                       0x1E05806C,0x00000000
+#define IPU_DC_RL2_CH_5__FULL                        0x1E05806C,0xffffffff
+#define IPU_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5    0x1E05806C,0xFF000000
+#define IPU_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5 0x1E05806C,0x000F0000
+#define IPU_DC_RL2_CH_5__COD_EOL_START_CHAN_5        0x1E05806C,0x0000FF00
+#define IPU_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5     0x1E05806C,0x0000000F
+
+#define IPU_DC_RL3_CH_5__ADDR                         0x1E058070
+#define IPU_DC_RL3_CH_5__EMPTY                        0x1E058070,0x00000000
+#define IPU_DC_RL3_CH_5__FULL                         0x1E058070,0xffffffff
+#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5    0x1E058070,0xFF000000
+#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5 0x1E058070,0x000F0000
+#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5    0x1E058070,0x0000FF00
+#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5 0x1E058070,0x0000000F
+
+#define IPU_DC_RL4_CH_5__ADDR                         0x1E058074
+#define IPU_DC_RL4_CH_5__EMPTY                        0x1E058074,0x00000000
+#define IPU_DC_RL4_CH_5__FULL                         0x1E058074,0xffffffff
+#define IPU_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5    0x1E058074,0x0000FF00
+#define IPU_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5 0x1E058074,0x0000000F
+
+#define IPU_DC_WR_CH_CONF_6__ADDR                0x1E058078
+#define IPU_DC_WR_CH_CONF_6__EMPTY               0x1E058078,0x00000000
+#define IPU_DC_WR_CH_CONF_6__FULL                0x1E058078,0xffffffff
+#define IPU_DC_WR_CH_CONF_6__PROG_START_TIME_6   0x1E058078,0x07FF0000
+#define IPU_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1E058078,0x00000100
+#define IPU_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6     0x1E058078,0x000000E0
+#define IPU_DC_WR_CH_CONF_6__PROG_DISP_ID_6      0x1E058078,0x00000018
+#define IPU_DC_WR_CH_CONF_6__PROG_DI_ID_6        0x1E058078,0x00000004
+#define IPU_DC_WR_CH_CONF_6__W_SIZE_6            0x1E058078,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_6__ADDR      0x1E05807C
+#define IPU_DC_WR_CH_ADDR_6__EMPTY     0x1E05807C,0x00000000
+#define IPU_DC_WR_CH_ADDR_6__FULL      0x1E05807C,0xffffffff
+#define IPU_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1E05807C,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_6__ADDR                   0x1E058080
+#define IPU_DC_RL0_CH_6__EMPTY                  0x1E058080,0x00000000
+#define IPU_DC_RL0_CH_6__FULL                   0x1E058080,0xffffffff
+#define IPU_DC_RL0_CH_6__COD_NL_START_CHAN_6    0x1E058080,0xFF000000
+#define IPU_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1E058080,0x000F0000
+#define IPU_DC_RL0_CH_6__COD_NF_START_CHAN_6    0x1E058080,0x0000FF00
+#define IPU_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1E058080,0x0000000F
+
+#define IPU_DC_RL1_CH_6__ADDR                       0x1E058084
+#define IPU_DC_RL1_CH_6__EMPTY                      0x1E058084,0x00000000
+#define IPU_DC_RL1_CH_6__FULL                       0x1E058084,0xffffffff
+#define IPU_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6    0x1E058084,0xFF000000
+#define IPU_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1E058084,0x000F0000
+#define IPU_DC_RL1_CH_6__COD_EOF_START_CHAN_6       0x1E058084,0x0000FF00
+#define IPU_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6    0x1E058084,0x0000000F
+
+#define IPU_DC_RL2_CH_6__ADDR                        0x1E058088
+#define IPU_DC_RL2_CH_6__EMPTY                       0x1E058088,0x00000000
+#define IPU_DC_RL2_CH_6__FULL                        0x1E058088,0xffffffff
+#define IPU_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6    0x1E058088,0xFF000000
+#define IPU_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1E058088,0x000F0000
+#define IPU_DC_RL2_CH_6__COD_EOL_START_CHAN_6        0x1E058088,0x0000FF00
+#define IPU_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6     0x1E058088,0x0000000F
+
+#define IPU_DC_RL3_CH_6__ADDR                         0x1E05808C
+#define IPU_DC_RL3_CH_6__EMPTY                        0x1E05808C,0x00000000
+#define IPU_DC_RL3_CH_6__FULL                         0x1E05808C,0xffffffff
+#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6    0x1E05808C,0xFF000000
+#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1E05808C,0x000F0000
+#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6    0x1E05808C,0x0000FF00
+#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1E05808C,0x0000000F
+
+#define IPU_DC_RL4_CH_6__ADDR                         0x1E058090
+#define IPU_DC_RL4_CH_6__EMPTY                        0x1E058090,0x00000000
+#define IPU_DC_RL4_CH_6__FULL                         0x1E058090,0xffffffff
+#define IPU_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6    0x1E058090,0x0000FF00
+#define IPU_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1E058090,0x0000000F
+
+#define IPU_DC_WR_CH_CONF1_8__ADDR                0x1E058094
+#define IPU_DC_WR_CH_CONF1_8__EMPTY               0x1E058094,0x00000000
+#define IPU_DC_WR_CH_CONF1_8__FULL                0x1E058094,0xffffffff
+#define IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8       0x1E058094,0x00000018
+#define IPU_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8 0x1E058094,0x00000004
+#define IPU_DC_WR_CH_CONF1_8__W_SIZE_8            0x1E058094,0x00000003
+
+#define IPU_DC_WR_CH_CONF2_8__ADDR                0x1E058098
+#define IPU_DC_WR_CH_CONF2_8__EMPTY               0x1E058098,0x00000000
+#define IPU_DC_WR_CH_CONF2_8__FULL                0x1E058098,0xffffffff
+#define IPU_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8 0x1E058098,0x1FFFFFFF
+
+#define IPU_DC_RL1_CH_8__ADDR                          0x1E05809C
+#define IPU_DC_RL1_CH_8__EMPTY                         0x1E05809C,0x00000000
+#define IPU_DC_RL1_CH_8__FULL                          0x1E05809C,0xffffffff
+#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1 0x1E05809C,0xFF000000
+#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0 0x1E05809C,0x0000FF00
+#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8  0x1E05809C,0x0000000F
+
+#define IPU_DC_RL2_CH_8__ADDR                          0x1E0580A0
+#define IPU_DC_RL2_CH_8__EMPTY                         0x1E0580A0,0x00000000
+#define IPU_DC_RL2_CH_8__FULL                          0x1E0580A0,0xffffffff
+#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1 0x1E0580A0,0xFF000000
+#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0 0x1E0580A0,0x0000FF00
+#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8  0x1E0580A0,0x0000000F
+
+#define IPU_DC_RL3_CH_8__ADDR                          0x1E0580A4
+#define IPU_DC_RL3_CH_8__EMPTY                         0x1E0580A4,0x00000000
+#define IPU_DC_RL3_CH_8__FULL                          0x1E0580A4,0xffffffff
+#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1 0x1E0580A4,0xFF000000
+#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0 0x1E0580A4,0x0000FF00
+#define IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8  0x1E0580A4,0x0000000F
+
+#define IPU_DC_RL4_CH_8__ADDR                          0x1E0580A8
+#define IPU_DC_RL4_CH_8__EMPTY                         0x1E0580A8,0x00000000
+#define IPU_DC_RL4_CH_8__FULL                          0x1E0580A8,0xffffffff
+#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1 0x1E0580A8,0xFF000000
+#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0 0x1E0580A8,0x0000FF00
+
+#define IPU_DC_RL5_CH_8__ADDR                          0x1E0580AC
+#define IPU_DC_RL5_CH_8__EMPTY                         0x1E0580AC,0x00000000
+#define IPU_DC_RL5_CH_8__FULL                          0x1E0580AC,0xffffffff
+#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1 0x1E0580AC,0xFF000000
+#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0 0x1E0580AC,0x0000FF00
+
+#define IPU_DC_RL6_CH_8__ADDR                          0x1E0580B0
+#define IPU_DC_RL6_CH_8__EMPTY                         0x1E0580B0,0x00000000
+#define IPU_DC_RL6_CH_8__FULL                          0x1E0580B0,0xffffffff
+#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1 0x1E0580B0,0xFF000000
+#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0 0x1E0580B0,0x0000FF00
+
+#define IPU_DC_WR_CH_CONF1_9__ADDR                0x1E0580B4
+#define IPU_DC_WR_CH_CONF1_9__EMPTY               0x1E0580B4,0x00000000
+#define IPU_DC_WR_CH_CONF1_9__FULL                0x1E0580B4,0xffffffff
+#define IPU_DC_WR_CH_CONF1_9__MCU_DISP_ID_9       0x1E0580B4,0x00000018
+#define IPU_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9 0x1E0580B4,0x00000004
+#define IPU_DC_WR_CH_CONF1_9__W_SIZE_9            0x1E0580B4,0x00000003
+
+#define IPU_DC_WR_CH_CONF2_9__ADDR                0x1E0580B8
+#define IPU_DC_WR_CH_CONF2_9__EMPTY               0x1E0580B8,0x00000000
+#define IPU_DC_WR_CH_CONF2_9__FULL                0x1E0580B8,0xffffffff
+#define IPU_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9 0x1E0580B8,0x1FFFFFFF
+
+#define IPU_DC_RL1_CH_9__ADDR                          0x1E0580BC
+#define IPU_DC_RL1_CH_9__EMPTY                         0x1E0580BC,0x00000000
+#define IPU_DC_RL1_CH_9__FULL                          0x1E0580BC,0xffffffff
+#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1 0x1E0580BC,0xFF000000
+#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0 0x1E0580BC,0x0000FF00
+#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9  0x1E0580BC,0x0000000F
+
+#define IPU_DC_RL2_CH_9__ADDR                          0x1E0580C0
+#define IPU_DC_RL2_CH_9__EMPTY                         0x1E0580C0,0x00000000
+#define IPU_DC_RL2_CH_9__FULL                          0x1E0580C0,0xffffffff
+#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1 0x1E0580C0,0xFF000000
+#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0 0x1E0580C0,0x0000FF00
+#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9  0x1E0580C0,0x0000000F
+
+#define IPU_DC_RL3_CH_9__ADDR                          0x1E0580C4
+#define IPU_DC_RL3_CH_9__EMPTY                         0x1E0580C4,0x00000000
+#define IPU_DC_RL3_CH_9__FULL                          0x1E0580C4,0xffffffff
+#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1 0x1E0580C4,0xFF000000
+#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0 0x1E0580C4,0x0000FF00
+#define IPU_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9  0x1E0580C4,0x0000000F
+
+#define IPU_DC_RL4_CH_9__ADDR                          0x1E0580C8
+#define IPU_DC_RL4_CH_9__EMPTY                         0x1E0580C8,0x00000000
+#define IPU_DC_RL4_CH_9__FULL                          0x1E0580C8,0xffffffff
+#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1 0x1E0580C8,0xFF000000
+#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0 0x1E0580C8,0x0000FF00
+
+#define IPU_DC_RL5_CH_9__ADDR                          0x1E0580CC
+#define IPU_DC_RL5_CH_9__EMPTY                         0x1E0580CC,0x00000000
+#define IPU_DC_RL5_CH_9__FULL                          0x1E0580CC,0xffffffff
+#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1 0x1E0580CC,0xFF000000
+#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0 0x1E0580CC,0x0000FF00
+
+#define IPU_DC_RL6_CH_9__ADDR                          0x1E0580D0
+#define IPU_DC_RL6_CH_9__EMPTY                         0x1E0580D0,0x00000000
+#define IPU_DC_RL6_CH_9__FULL                          0x1E0580D0,0xffffffff
+#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1 0x1E0580D0,0xFF000000
+#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0 0x1E0580D0,0x0000FF00
+
+#define IPU_DC_GEN__ADDR            0x1E0580D4
+#define IPU_DC_GEN__EMPTY           0x1E0580D4,0x00000000
+#define IPU_DC_GEN__FULL            0x1E0580D4,0xffffffff
+#define IPU_DC_GEN__DC_BK_EN        0x1E0580D4,0x01000000
+#define IPU_DC_GEN__DC_BKDIV        0x1E0580D4,0x00FF0000
+#define IPU_DC_GEN__DC_CH5_TYPE     0x1E0580D4,0x00000100
+#define IPU_DC_GEN__SYNC_PRIORITY_1 0x1E0580D4,0x00000080
+#define IPU_DC_GEN__SYNC_PRIORITY_5 0x1E0580D4,0x00000040
+#define IPU_DC_GEN__MASK4CHAN_5     0x1E0580D4,0x00000020
+#define IPU_DC_GEN__MASK_EN         0x1E0580D4,0x00000010
+#define IPU_DC_GEN__SYNC_1_6        0x1E0580D4,0x00000006
+
+#define IPU_DC_DISP_CONF1_0__ADDR                0x1E0580D8
+#define IPU_DC_DISP_CONF1_0__EMPTY               0x1E0580D8,0x00000000
+#define IPU_DC_DISP_CONF1_0__FULL                0x1E0580D8,0xffffffff
+#define IPU_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1E0580D8,0x00000080
+#define IPU_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0   0x1E0580D8,0x00000040
+#define IPU_DC_DISP_CONF1_0__ADDR_BE_L_INC_0     0x1E0580D8,0x00000030
+#define IPU_DC_DISP_CONF1_0__ADDR_INCREMENT_0    0x1E0580D8,0x0000000C
+#define IPU_DC_DISP_CONF1_0__DISP_TYP_0          0x1E0580D8,0x00000003
+
+#define IPU_DC_DISP_CONF1_1__ADDR                0x1E0580DC
+#define IPU_DC_DISP_CONF1_1__EMPTY               0x1E0580DC,0x00000000
+#define IPU_DC_DISP_CONF1_1__FULL                0x1E0580DC,0xffffffff
+#define IPU_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1E0580DC,0x00000080
+#define IPU_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1   0x1E0580DC,0x00000040
+#define IPU_DC_DISP_CONF1_1__ADDR_BE_L_INC_1     0x1E0580DC,0x00000030
+#define IPU_DC_DISP_CONF1_1__ADDR_INCREMENT_1    0x1E0580DC,0x0000000C
+#define IPU_DC_DISP_CONF1_1__DISP_TYP_1          0x1E0580DC,0x00000003
+
+#define IPU_DC_DISP_CONF1_2__ADDR                0x1E0580E0
+#define IPU_DC_DISP_CONF1_2__EMPTY               0x1E0580E0,0x00000000
+#define IPU_DC_DISP_CONF1_2__FULL                0x1E0580E0,0xffffffff
+#define IPU_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1E0580E0,0x00000080
+#define IPU_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2   0x1E0580E0,0x00000040
+#define IPU_DC_DISP_CONF1_2__ADDR_BE_L_INC_2     0x1E0580E0,0x00000030
+#define IPU_DC_DISP_CONF1_2__ADDR_INCREMENT_2    0x1E0580E0,0x0000000C
+#define IPU_DC_DISP_CONF1_2__DISP_TYP_2          0x1E0580E0,0x00000003
+
+#define IPU_DC_DISP_CONF1_3__ADDR                0x1E0580E4
+#define IPU_DC_DISP_CONF1_3__EMPTY               0x1E0580E4,0x00000000
+#define IPU_DC_DISP_CONF1_3__FULL                0x1E0580E4,0xffffffff
+#define IPU_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1E0580E4,0x00000080
+#define IPU_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3   0x1E0580E4,0x00000040
+#define IPU_DC_DISP_CONF1_3__ADDR_BE_L_INC_3     0x1E0580E4,0x00000030
+#define IPU_DC_DISP_CONF1_3__ADDR_INCREMENT_3    0x1E0580E4,0x0000000C
+#define IPU_DC_DISP_CONF1_3__DISP_TYP_3          0x1E0580E4,0x00000003
+
+#define IPU_DC_DISP_CONF2_0__ADDR  0x1E0580E8
+#define IPU_DC_DISP_CONF2_0__EMPTY 0x1E0580E8,0x00000000
+#define IPU_DC_DISP_CONF2_0__FULL  0x1E0580E8,0xffffffff
+#define IPU_DC_DISP_CONF2_0__SL_0  0x1E0580E8,0x1FFFFFFF
+
+#define IPU_DC_DISP_CONF2_1__ADDR  0x1E0580EC
+#define IPU_DC_DISP_CONF2_1__EMPTY 0x1E0580EC,0x00000000
+#define IPU_DC_DISP_CONF2_1__FULL  0x1E0580EC,0xffffffff
+#define IPU_DC_DISP_CONF2_1__SL_1  0x1E0580EC,0x1FFFFFFF
+
+#define IPU_DC_DISP_CONF2_2__ADDR  0x1E0580F0
+#define IPU_DC_DISP_CONF2_2__EMPTY 0x1E0580F0,0x00000000
+#define IPU_DC_DISP_CONF2_2__FULL  0x1E0580F0,0xffffffff
+#define IPU_DC_DISP_CONF2_2__SL_2  0x1E0580F0,0x1FFFFFFF
+
+#define IPU_DC_DISP_CONF2_3__ADDR  0x1E0580F4
+#define IPU_DC_DISP_CONF2_3__EMPTY 0x1E0580F4,0x00000000
+#define IPU_DC_DISP_CONF2_3__FULL  0x1E0580F4,0xffffffff
+#define IPU_DC_DISP_CONF2_3__SL_3  0x1E0580F4,0x1FFFFFFF
+
+#define IPU_DC_DI0_CONF_1__ADDR                0x1E0580F8
+#define IPU_DC_DI0_CONF_1__EMPTY               0x1E0580F8,0x00000000
+#define IPU_DC_DI0_CONF_1__FULL                0x1E0580F8,0xffffffff
+#define IPU_DC_DI0_CONF_1__DI_READ_DATA_MASK_0 0x1E0580F8,0xFFFFFFFF
+
+#define IPU_DC_DI0_CONF_2__ADDR                     0x1E0580FC
+#define IPU_DC_DI0_CONF_2__EMPTY                    0x1E0580FC,0x00000000
+#define IPU_DC_DI0_CONF_2__FULL                     0x1E0580FC,0xffffffff
+#define IPU_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0 0x1E0580FC,0xFFFFFFFF
+
+#define IPU_DC_DI1_CONF_1__ADDR                0x1E058100
+#define IPU_DC_DI1_CONF_1__EMPTY               0x1E058100,0x00000000
+#define IPU_DC_DI1_CONF_1__FULL                0x1E058100,0xffffffff
+#define IPU_DC_DI1_CONF_1__DI_READ_DATA_MASK_1 0x1E058100,0xFFFFFFFF
+
+#define IPU_DC_DI1_CONF_2__ADDR                     0x1E058104
+#define IPU_DC_DI1_CONF_2__EMPTY                    0x1E058104,0x00000000
+#define IPU_DC_DI1_CONF_2__FULL                     0x1E058104,0xffffffff
+#define IPU_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1 0x1E058104,0xFFFFFFFF
+
+#define IPU_DC_MAP_CONF_0__ADDR                 0x1E058108
+#define IPU_DC_MAP_CONF_0__EMPTY                0x1E058108,0x00000000
+#define IPU_DC_MAP_CONF_0__FULL                 0x1E058108,0xffffffff
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1 0x1E058108,0x7C000000
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1 0x1E058108,0x03E00000
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1 0x1E058108,0x001F0000
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0 0x1E058108,0x00007C00
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0 0x1E058108,0x000003E0
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0 0x1E058108,0x0000001F
+
+#define IPU_DC_MAP_CONF_1__ADDR                 0x1E05810C
+#define IPU_DC_MAP_CONF_1__EMPTY                0x1E05810C,0x00000000
+#define IPU_DC_MAP_CONF_1__FULL                 0x1E05810C,0xffffffff
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3 0x1E05810C,0x7C000000
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3 0x1E05810C,0x03E00000
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3 0x1E05810C,0x001F0000
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2 0x1E05810C,0x00007C00
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2 0x1E05810C,0x000003E0
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2 0x1E05810C,0x0000001F
+
+#define IPU_DC_MAP_CONF_2__ADDR                 0x1E058110
+#define IPU_DC_MAP_CONF_2__EMPTY                0x1E058110,0x00000000
+#define IPU_DC_MAP_CONF_2__FULL                 0x1E058110,0xffffffff
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5 0x1E058110,0x7C000000
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5 0x1E058110,0x03E00000
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5 0x1E058110,0x001F0000
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4 0x1E058110,0x00007C00
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4 0x1E058110,0x000003E0
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4 0x1E058110,0x0000001F
+
+#define IPU_DC_MAP_CONF_3__ADDR                 0x1E058114
+#define IPU_DC_MAP_CONF_3__EMPTY                0x1E058114,0x00000000
+#define IPU_DC_MAP_CONF_3__FULL                 0x1E058114,0xffffffff
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7 0x1E058114,0x7C000000
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7 0x1E058114,0x03E00000
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7 0x1E058114,0x001F0000
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6 0x1E058114,0x00007C00
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6 0x1E058114,0x000003E0
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6 0x1E058114,0x0000001F
+
+#define IPU_DC_MAP_CONF_4__ADDR                 0x1E058118
+#define IPU_DC_MAP_CONF_4__EMPTY                0x1E058118,0x00000000
+#define IPU_DC_MAP_CONF_4__FULL                 0x1E058118,0xffffffff
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9 0x1E058118,0x7C000000
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9 0x1E058118,0x03E00000
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9 0x1E058118,0x001F0000
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8 0x1E058118,0x00007C00
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8 0x1E058118,0x000003E0
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8 0x1E058118,0x0000001F
+
+#define IPU_DC_MAP_CONF_5__ADDR                  0x1E05811C
+#define IPU_DC_MAP_CONF_5__EMPTY                 0x1E05811C,0x00000000
+#define IPU_DC_MAP_CONF_5__FULL                  0x1E05811C,0xffffffff
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11 0x1E05811C,0x7C000000
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11 0x1E05811C,0x03E00000
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11 0x1E05811C,0x001F0000
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10 0x1E05811C,0x00007C00
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10 0x1E05811C,0x000003E0
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10 0x1E05811C,0x0000001F
+
+#define IPU_DC_MAP_CONF_6__ADDR                  0x1E058120
+#define IPU_DC_MAP_CONF_6__EMPTY                 0x1E058120,0x00000000
+#define IPU_DC_MAP_CONF_6__FULL                  0x1E058120,0xffffffff
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13 0x1E058120,0x7C000000
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13 0x1E058120,0x03E00000
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13 0x1E058120,0x001F0000
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12 0x1E058120,0x00007C00
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12 0x1E058120,0x000003E0
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12 0x1E058120,0x0000001F
+
+#define IPU_DC_MAP_CONF_7__ADDR                  0x1E058124
+#define IPU_DC_MAP_CONF_7__EMPTY                 0x1E058124,0x00000000
+#define IPU_DC_MAP_CONF_7__FULL                  0x1E058124,0xffffffff
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15 0x1E058124,0x7C000000
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15 0x1E058124,0x03E00000
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15 0x1E058124,0x001F0000
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14 0x1E058124,0x00007C00
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14 0x1E058124,0x000003E0
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14 0x1E058124,0x0000001F
+
+#define IPU_DC_MAP_CONF_8__ADDR                  0x1E058128
+#define IPU_DC_MAP_CONF_8__EMPTY                 0x1E058128,0x00000000
+#define IPU_DC_MAP_CONF_8__FULL                  0x1E058128,0xffffffff
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17 0x1E058128,0x7C000000
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17 0x1E058128,0x03E00000
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17 0x1E058128,0x001F0000
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16 0x1E058128,0x00007C00
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16 0x1E058128,0x000003E0
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16 0x1E058128,0x0000001F
+
+#define IPU_DC_MAP_CONF_9__ADDR                  0x1E05812C
+#define IPU_DC_MAP_CONF_9__EMPTY                 0x1E05812C,0x00000000
+#define IPU_DC_MAP_CONF_9__FULL                  0x1E05812C,0xffffffff
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19 0x1E05812C,0x7C000000
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19 0x1E05812C,0x03E00000
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19 0x1E05812C,0x001F0000
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18 0x1E05812C,0x00007C00
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18 0x1E05812C,0x000003E0
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18 0x1E05812C,0x0000001F
+
+#define IPU_DC_MAP_CONF_10__ADDR                  0x1E058130
+#define IPU_DC_MAP_CONF_10__EMPTY                 0x1E058130,0x00000000
+#define IPU_DC_MAP_CONF_10__FULL                  0x1E058130,0xffffffff
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21 0x1E058130,0x7C000000
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21 0x1E058130,0x03E00000
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21 0x1E058130,0x001F0000
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20 0x1E058130,0x00007C00
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20 0x1E058130,0x000003E0
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20 0x1E058130,0x0000001F
+
+#define IPU_DC_MAP_CONF_11__ADDR                  0x1E058134
+#define IPU_DC_MAP_CONF_11__EMPTY                 0x1E058134,0x00000000
+#define IPU_DC_MAP_CONF_11__FULL                  0x1E058134,0xffffffff
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23 0x1E058134,0x7C000000
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23 0x1E058134,0x03E00000
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23 0x1E058134,0x001F0000
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22 0x1E058134,0x00007C00
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22 0x1E058134,0x000003E0
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22 0x1E058134,0x0000001F
+
+#define IPU_DC_MAP_CONF_12__ADDR                  0x1E058138
+#define IPU_DC_MAP_CONF_12__EMPTY                 0x1E058138,0x00000000
+#define IPU_DC_MAP_CONF_12__FULL                  0x1E058138,0xffffffff
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25 0x1E058138,0x7C000000
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25 0x1E058138,0x03E00000
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25 0x1E058138,0x001F0000
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24 0x1E058138,0x00007C00
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24 0x1E058138,0x000003E0
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24 0x1E058138,0x0000001F
+
+#define IPU_DC_MAP_CONF_13__ADDR                  0x1E05813C
+#define IPU_DC_MAP_CONF_13__EMPTY                 0x1E05813C,0x00000000
+#define IPU_DC_MAP_CONF_13__FULL                  0x1E05813C,0xffffffff
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27 0x1E05813C,0x7C000000
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27 0x1E05813C,0x03E00000
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27 0x1E05813C,0x001F0000
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26 0x1E05813C,0x00007C00
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26 0x1E05813C,0x000003E0
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26 0x1E05813C,0x0000001F
+
+#define IPU_DC_MAP_CONF_14__ADDR                  0x1E058140
+#define IPU_DC_MAP_CONF_14__EMPTY                 0x1E058140,0x00000000
+#define IPU_DC_MAP_CONF_14__FULL                  0x1E058140,0xffffffff
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29 0x1E058140,0x7C000000
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29 0x1E058140,0x03E00000
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29 0x1E058140,0x001F0000
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28 0x1E058140,0x00007C00
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28 0x1E058140,0x000003E0
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28 0x1E058140,0x0000001F
+
+#define IPU_DC_MAP_CONF_15__ADDR        0x1E058144
+#define IPU_DC_MAP_CONF_15__EMPTY       0x1E058144,0x00000000
+#define IPU_DC_MAP_CONF_15__FULL        0x1E058144,0xffffffff
+#define IPU_DC_MAP_CONF_15__MD_OFFSET_1 0x1E058144,0x1F000000
+#define IPU_DC_MAP_CONF_15__MD_MASK_1   0x1E058144,0x00FF0000
+#define IPU_DC_MAP_CONF_15__MD_OFFSET_0 0x1E058144,0x00001F00
+#define IPU_DC_MAP_CONF_15__MD_MASK_0   0x1E058144,0x000000FF
+
+#define IPU_DC_MAP_CONF_16__ADDR        0x1E058148
+#define IPU_DC_MAP_CONF_16__EMPTY       0x1E058148,0x00000000
+#define IPU_DC_MAP_CONF_16__FULL        0x1E058148,0xffffffff
+#define IPU_DC_MAP_CONF_16__MD_OFFSET_3 0x1E058148,0x1F000000
+#define IPU_DC_MAP_CONF_16__MD_MASK_3   0x1E058148,0x00FF0000
+#define IPU_DC_MAP_CONF_16__MD_OFFSET_2 0x1E058148,0x00001F00
+#define IPU_DC_MAP_CONF_16__MD_MASK_2   0x1E058148,0x000000FF
+
+#define IPU_DC_MAP_CONF_17__ADDR        0x1E05814C
+#define IPU_DC_MAP_CONF_17__EMPTY       0x1E05814C,0x00000000
+#define IPU_DC_MAP_CONF_17__FULL        0x1E05814C,0xffffffff
+#define IPU_DC_MAP_CONF_17__MD_OFFSET_5 0x1E05814C,0x1F000000
+#define IPU_DC_MAP_CONF_17__MD_MASK_5   0x1E05814C,0x00FF0000
+#define IPU_DC_MAP_CONF_17__MD_OFFSET_4 0x1E05814C,0x00001F00
+#define IPU_DC_MAP_CONF_17__MD_MASK_4   0x1E05814C,0x000000FF
+
+#define IPU_DC_MAP_CONF_18__ADDR        0x1E058150
+#define IPU_DC_MAP_CONF_18__EMPTY       0x1E058150,0x00000000
+#define IPU_DC_MAP_CONF_18__FULL        0x1E058150,0xffffffff
+#define IPU_DC_MAP_CONF_18__MD_OFFSET_7 0x1E058150,0x1F000000
+#define IPU_DC_MAP_CONF_18__MD_MASK_7   0x1E058150,0x00FF0000
+#define IPU_DC_MAP_CONF_18__MD_OFFSET_6 0x1E058150,0x00001F00
+#define IPU_DC_MAP_CONF_18__MD_MASK_6   0x1E058150,0x000000FF
+
+#define IPU_DC_MAP_CONF_19__ADDR        0x1E058154
+#define IPU_DC_MAP_CONF_19__EMPTY       0x1E058154,0x00000000
+#define IPU_DC_MAP_CONF_19__FULL        0x1E058154,0xffffffff
+#define IPU_DC_MAP_CONF_19__MD_OFFSET_9 0x1E058154,0x1F000000
+#define IPU_DC_MAP_CONF_19__MD_MASK_9   0x1E058154,0x00FF0000
+#define IPU_DC_MAP_CONF_19__MD_OFFSET_8 0x1E058154,0x00001F00
+#define IPU_DC_MAP_CONF_19__MD_MASK_8   0x1E058154,0x000000FF
+
+#define IPU_DC_MAP_CONF_20__ADDR         0x1E058158
+#define IPU_DC_MAP_CONF_20__EMPTY        0x1E058158,0x00000000
+#define IPU_DC_MAP_CONF_20__FULL         0x1E058158,0xffffffff
+#define IPU_DC_MAP_CONF_20__MD_OFFSET_11 0x1E058158,0x1F000000
+#define IPU_DC_MAP_CONF_20__MD_MASK_11   0x1E058158,0x00FF0000
+#define IPU_DC_MAP_CONF_20__MD_OFFSET_10 0x1E058158,0x00001F00
+#define IPU_DC_MAP_CONF_20__MD_MASK_10   0x1E058158,0x000000FF
+
+#define IPU_DC_MAP_CONF_21__ADDR         0x1E05815C
+#define IPU_DC_MAP_CONF_21__EMPTY        0x1E05815C,0x00000000
+#define IPU_DC_MAP_CONF_21__FULL         0x1E05815C,0xffffffff
+#define IPU_DC_MAP_CONF_21__MD_OFFSET_13 0x1E05815C,0x1F000000
+#define IPU_DC_MAP_CONF_21__MD_MASK_13   0x1E05815C,0x00FF0000
+#define IPU_DC_MAP_CONF_21__MD_OFFSET_12 0x1E05815C,0x00001F00
+#define IPU_DC_MAP_CONF_21__MD_MASK_12   0x1E05815C,0x000000FF
+
+#define IPU_DC_MAP_CONF_22__ADDR         0x1E058160
+#define IPU_DC_MAP_CONF_22__EMPTY        0x1E058160,0x00000000
+#define IPU_DC_MAP_CONF_22__FULL         0x1E058160,0xffffffff
+#define IPU_DC_MAP_CONF_22__MD_OFFSET_15 0x1E058160,0x1F000000
+#define IPU_DC_MAP_CONF_22__MD_MASK_15   0x1E058160,0x00FF0000
+#define IPU_DC_MAP_CONF_22__MD_OFFSET_14 0x1E058160,0x00001F00
+#define IPU_DC_MAP_CONF_22__MD_MASK_14   0x1E058160,0x000000FF
+
+#define IPU_DC_MAP_CONF_23__ADDR         0x1E058164
+#define IPU_DC_MAP_CONF_23__EMPTY        0x1E058164,0x00000000
+#define IPU_DC_MAP_CONF_23__FULL         0x1E058164,0xffffffff
+#define IPU_DC_MAP_CONF_23__MD_OFFSET_17 0x1E058164,0x1F000000
+#define IPU_DC_MAP_CONF_23__MD_MASK_17   0x1E058164,0x00FF0000
+#define IPU_DC_MAP_CONF_23__MD_OFFSET_16 0x1E058164,0x00001F00
+#define IPU_DC_MAP_CONF_23__MD_MASK_16   0x1E058164,0x000000FF
+
+#define IPU_DC_MAP_CONF_24__ADDR         0x1E058168
+#define IPU_DC_MAP_CONF_24__EMPTY        0x1E058168,0x00000000
+#define IPU_DC_MAP_CONF_24__FULL         0x1E058168,0xffffffff
+#define IPU_DC_MAP_CONF_24__MD_OFFSET_19 0x1E058168,0x1F000000
+#define IPU_DC_MAP_CONF_24__MD_MASK_19   0x1E058168,0x00FF0000
+#define IPU_DC_MAP_CONF_24__MD_OFFSET_18 0x1E058168,0x00001F00
+#define IPU_DC_MAP_CONF_24__MD_MASK_18   0x1E058168,0x000000FF
+
+#define IPU_DC_MAP_CONF_25__ADDR         0x1E05816C
+#define IPU_DC_MAP_CONF_25__EMPTY        0x1E05816C,0x00000000
+#define IPU_DC_MAP_CONF_25__FULL         0x1E05816C,0xffffffff
+#define IPU_DC_MAP_CONF_25__MD_OFFSET_21 0x1E05816C,0x1F000000
+#define IPU_DC_MAP_CONF_25__MD_MASK_21   0x1E05816C,0x00FF0000
+#define IPU_DC_MAP_CONF_25__MD_OFFSET_20 0x1E05816C,0x00001F00
+#define IPU_DC_MAP_CONF_25__MD_MASK_20   0x1E05816C,0x000000FF
+
+#define IPU_DC_MAP_CONF_26__ADDR         0x1E058170
+#define IPU_DC_MAP_CONF_26__EMPTY        0x1E058170,0x00000000
+#define IPU_DC_MAP_CONF_26__FULL         0x1E058170,0xffffffff
+#define IPU_DC_MAP_CONF_26__MD_OFFSET_23 0x1E058170,0x1F000000
+#define IPU_DC_MAP_CONF_26__MD_MASK_23   0x1E058170,0x00FF0000
+#define IPU_DC_MAP_CONF_26__MD_OFFSET_22 0x1E058170,0x00001F00
+#define IPU_DC_MAP_CONF_26__MD_MASK_22   0x1E058170,0x000000FF
+
+#define IPU_DC_UGDE0_0__ADDR              0x1E058174
+#define IPU_DC_UGDE0_0__EMPTY             0x1E058174,0x00000000
+#define IPU_DC_UGDE0_0__FULL              0x1E058174,0xffffffff
+#define IPU_DC_UGDE0_0__NF_NL_0           0x1E058174,0x18000000
+#define IPU_DC_UGDE0_0__AUTORESTART_0     0x1E058174,0x04000000
+#define IPU_DC_UGDE0_0__ODD_EN_0          0x1E058174,0x02000000
+#define IPU_DC_UGDE0_0__COD_ODD_START_0   0x1E058174,0x00FF0000
+#define IPU_DC_UGDE0_0__COD_EV_START_0    0x1E058174,0x0000FF00
+#define IPU_DC_UGDE0_0__COD_EV_PRIORITY_0 0x1E058174,0x00000078
+#define IPU_DC_UGDE0_0__ID_CODED_0        0x1E058174,0x00000007
+
+#define IPU_DC_UGDE0_1__ADDR   0x1E058178
+#define IPU_DC_UGDE0_1__EMPTY  0x1E058178,0x00000000
+#define IPU_DC_UGDE0_1__FULL   0x1E058178,0xffffffff
+#define IPU_DC_UGDE0_1__STEP_0 0x1E058178,0x1FFFFFFF
+
+#define IPU_DC_UGDE0_2__ADDR        0x1E05817C
+#define IPU_DC_UGDE0_2__EMPTY       0x1E05817C,0x00000000
+#define IPU_DC_UGDE0_2__FULL        0x1E05817C,0xffffffff
+#define IPU_DC_UGDE0_2__OFFSET_DT_0 0x1E05817C,0x1FFFFFFF
+
+#define IPU_DC_UGDE0_3__ADDR          0x1E058180
+#define IPU_DC_UGDE0_3__EMPTY         0x1E058180,0x00000000
+#define IPU_DC_UGDE0_3__FULL          0x1E058180,0xffffffff
+#define IPU_DC_UGDE0_3__STEP_REPEAT_0 0x1E058180,0x1FFFFFFF
+
+#define IPU_DC_UGDE1_0__ADDR              0x1E058184
+#define IPU_DC_UGDE1_0__EMPTY             0x1E058184,0x00000000
+#define IPU_DC_UGDE1_0__FULL              0x1E058184,0xffffffff
+#define IPU_DC_UGDE1_0__NF_NL_1           0x1E058184,0x18000000
+#define IPU_DC_UGDE1_0__AUTORESTART_1     0x1E058184,0x04000000
+#define IPU_DC_UGDE1_0__ODD_EN_1          0x1E058184,0x02000000
+#define IPU_DC_UGDE1_0__COD_ODD_START_1   0x1E058184,0x00FF0000
+#define IPU_DC_UGDE1_0__COD_EV_START_1    0x1E058184,0x00007F80
+#define IPU_DC_UGDE1_0__COD_EV_PRIORITY_1 0x1E058184,0x00000078
+#define IPU_DC_UGDE1_0__ID_CODED_1        0x1E058184,0x00000007
+
+#define IPU_DC_UGDE1_1__ADDR   0x1E058188
+#define IPU_DC_UGDE1_1__EMPTY  0x1E058188,0x00000000
+#define IPU_DC_UGDE1_1__FULL   0x1E058188,0xffffffff
+#define IPU_DC_UGDE1_1__STEP_1 0x1E058188,0x1FFFFFFF
+
+#define IPU_DC_UGDE1_2__ADDR        0x1E05818C
+#define IPU_DC_UGDE1_2__EMPTY       0x1E05818C,0x00000000
+#define IPU_DC_UGDE1_2__FULL        0x1E05818C,0xffffffff
+#define IPU_DC_UGDE1_2__OFFSET_DT_1 0x1E05818C,0x1FFFFFFF
+
+#define IPU_DC_UGDE1_3__ADDR          0x1E058190
+#define IPU_DC_UGDE1_3__EMPTY         0x1E058190,0x00000000
+#define IPU_DC_UGDE1_3__FULL          0x1E058190,0xffffffff
+#define IPU_DC_UGDE1_3__STEP_REPEAT_1 0x1E058190,0x1FFFFFFF
+
+#define IPU_DC_UGDE2_0__ADDR              0x1E058194
+#define IPU_DC_UGDE2_0__EMPTY             0x1E058194,0x00000000
+#define IPU_DC_UGDE2_0__FULL              0x1E058194,0xffffffff
+#define IPU_DC_UGDE2_0__NF_NL_2           0x1E058194,0x18000000
+#define IPU_DC_UGDE2_0__AUTORESTART_2     0x1E058194,0x04000000
+#define IPU_DC_UGDE2_0__ODD_EN_2          0x1E058194,0x02000000
+#define IPU_DC_UGDE2_0__COD_ODD_START_2   0x1E058194,0x00FF0000
+#define IPU_DC_UGDE2_0__COD_EV_START_2    0x1E058194,0x00007F80
+#define IPU_DC_UGDE2_0__COD_EV_PRIORITY_2 0x1E058194,0x00000078
+#define IPU_DC_UGDE2_0__ID_CODED_2        0x1E058194,0x00000007
+
+#define IPU_DC_UGDE2_1__ADDR   0x1E058198
+#define IPU_DC_UGDE2_1__EMPTY  0x1E058198,0x00000000
+#define IPU_DC_UGDE2_1__FULL   0x1E058198,0xffffffff
+#define IPU_DC_UGDE2_1__STEP_2 0x1E058198,0x1FFFFFFF
+
+#define IPU_DC_UGDE2_2__ADDR        0x1E05819C
+#define IPU_DC_UGDE2_2__EMPTY       0x1E05819C,0x00000000
+#define IPU_DC_UGDE2_2__FULL        0x1E05819C,0xffffffff
+#define IPU_DC_UGDE2_2__OFFSET_DT_2 0x1E05819C,0x1FFFFFFF
+
+#define IPU_DC_UGDE2_3__ADDR          0x1E0581A0
+#define IPU_DC_UGDE2_3__EMPTY         0x1E0581A0,0x00000000
+#define IPU_DC_UGDE2_3__FULL          0x1E0581A0,0xffffffff
+#define IPU_DC_UGDE2_3__STEP_REPEAT_2 0x1E0581A0,0x1FFFFFFF
+
+#define IPU_DC_UGDE3_0__ADDR              0x1E0581A4
+#define IPU_DC_UGDE3_0__EMPTY             0x1E0581A4,0x00000000
+#define IPU_DC_UGDE3_0__FULL              0x1E0581A4,0xffffffff
+#define IPU_DC_UGDE3_0__NF_NL_3           0x1E0581A4,0x18000000
+#define IPU_DC_UGDE3_0__AUTORESTART_3     0x1E0581A4,0x04000000
+#define IPU_DC_UGDE3_0__ODD_EN_3          0x1E0581A4,0x02000000
+#define IPU_DC_UGDE3_0__COD_ODD_START_3   0x1E0581A4,0x00FF0000
+#define IPU_DC_UGDE3_0__COD_EV_START_3    0x1E0581A4,0x00007F80
+#define IPU_DC_UGDE3_0__COD_EV_PRIORITY_3 0x1E0581A4,0x00000078
+#define IPU_DC_UGDE3_0__ID_CODED_3        0x1E0581A4,0x00000007
+
+#define IPU_DC_UGDE3_1__ADDR   0x1E0581A8
+#define IPU_DC_UGDE3_1__EMPTY  0x1E0581A8,0x00000000
+#define IPU_DC_UGDE3_1__FULL   0x1E0581A8,0xffffffff
+#define IPU_DC_UGDE3_1__STEP_3 0x1E0581A8,0x1FFFFFFF
+
+#define IPU_DC_UGDE3_2__ADDR        0x1E0581AC
+#define IPU_DC_UGDE3_2__EMPTY       0x1E0581AC,0x00000000
+#define IPU_DC_UGDE3_2__FULL        0x1E0581AC,0xffffffff
+#define IPU_DC_UGDE3_2__OFFSET_DT_3 0x1E0581AC,0x1FFFFFFF
+
+#define IPU_DC_UGDE3_3__ADDR          0x1E0581B0
+#define IPU_DC_UGDE3_3__EMPTY         0x1E0581B0,0x00000000
+#define IPU_DC_UGDE3_3__FULL          0x1E0581B0,0xffffffff
+#define IPU_DC_UGDE3_3__STEP_REPEAT_3 0x1E0581B0,0x1FFFFFFF
+
+#define IPU_DC_LLA0__ADDR       0x1E0581B4
+#define IPU_DC_LLA0__EMPTY      0x1E0581B4,0x00000000
+#define IPU_DC_LLA0__FULL       0x1E0581B4,0xffffffff
+#define IPU_DC_LLA0__MCU_RS_3_0 0x1E0581B4,0xFF000000
+#define IPU_DC_LLA0__MCU_RS_2_0 0x1E0581B4,0x00FF0000
+#define IPU_DC_LLA0__MCU_RS_1_0 0x1E0581B4,0x0000FF00
+#define IPU_DC_LLA0__MCU_RS_0_0 0x1E0581B4,0x000000FF
+
+#define IPU_DC_LLA1__ADDR       0x1E0581B8
+#define IPU_DC_LLA1__EMPTY      0x1E0581B8,0x00000000
+#define IPU_DC_LLA1__FULL       0x1E0581B8,0xffffffff
+#define IPU_DC_LLA1__MCU_RS_3_1 0x1E0581B8,0xFF000000
+#define IPU_DC_LLA1__MCU_RS_2_1 0x1E0581B8,0x00FF0000
+#define IPU_DC_LLA1__MCU_RS_1_1 0x1E0581B8,0x0000FF00
+#define IPU_DC_LLA1__MCU_RS_0_1 0x1E0581B8,0x000000FF
+
+#define IPU_DC_R_LLA0__ADDR         0x1E0581BC
+#define IPU_DC_R_LLA0__EMPTY        0x1E0581BC,0x00000000
+#define IPU_DC_R_LLA0__FULL         0x1E0581BC,0xffffffff
+#define IPU_DC_R_LLA0__MCU_RS_R_3_0 0x1E0581BC,0xFF000000
+#define IPU_DC_R_LLA0__MCU_RS_R_2_0 0x1E0581BC,0x00FF0000
+#define IPU_DC_R_LLA0__MCU_RS_R_1_0 0x1E0581BC,0x0000FF00
+#define IPU_DC_R_LLA0__MCU_RS_R_0_0 0x1E0581BC,0x000000FF
+
+#define IPU_DC_R_LLA1__ADDR         0x1E0581C0
+#define IPU_DC_R_LLA1__EMPTY        0x1E0581C0,0x00000000
+#define IPU_DC_R_LLA1__FULL         0x1E0581C0,0xffffffff
+#define IPU_DC_R_LLA1__MCU_RS_R_3_1 0x1E0581C0,0xFF000000
+#define IPU_DC_R_LLA1__MCU_RS_R_2_1 0x1E0581C0,0x00FF0000
+#define IPU_DC_R_LLA1__MCU_RS_R_1_1 0x1E0581C0,0x0000FF00
+#define IPU_DC_R_LLA1__MCU_RS_R_0_1 0x1E0581C0,0x000000FF
+
+#define IPU_DC_WR_CH_ADDR_5_ALT__ADDR          0x1E0581C4
+#define IPU_DC_WR_CH_ADDR_5_ALT__EMPTY         0x1E0581C4,0x00000000
+#define IPU_DC_WR_CH_ADDR_5_ALT__FULL          0x1E0581C4,0xffffffff
+#define IPU_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT 0x1E0581C4,0x1FFFFFFF
+
+#define IPU_DC_STAT__ADDR                       0x1E0581C8
+#define IPU_DC_STAT__EMPTY                      0x1E0581C8,0x00000000
+#define IPU_DC_STAT__FULL                       0x1E0581C8,0xffffffff
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_1 0x1E0581C8,0x00000080
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_1  0x1E0581C8,0x00000040
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_1  0x1E0581C8,0x00000020
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_1   0x1E0581C8,0x00000010
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_0 0x1E0581C8,0x00000008
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_0  0x1E0581C8,0x00000004
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_0  0x1E0581C8,0x00000002
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_0   0x1E0581C8,0x00000001
+
+#define IPU_DMFC_RD_CHAN__ADDR              0x1E060000
+#define IPU_DMFC_RD_CHAN__EMPTY             0x1E060000,0x00000000
+#define IPU_DMFC_RD_CHAN__FULL              0x1E060000,0xffffffff
+#define IPU_DMFC_RD_CHAN__DMFC_PPW_C        0x1E060000,0x03000000
+#define IPU_DMFC_RD_CHAN__DMFC_WM_CLR_0     0x1E060000,0x00E00000
+#define IPU_DMFC_RD_CHAN__DMFC_WM_SET_0     0x1E060000,0x001C0000
+#define IPU_DMFC_RD_CHAN__DMFC_WM_EN_0      0x1E060000,0x00020000
+#define IPU_DMFC_RD_CHAN__DMFC_BURST_SIZE_0 0x1E060000,0x000000C0
+
+#define IPU_DMFC_WR_CHAN__ADDR               0x1E060004
+#define IPU_DMFC_WR_CHAN__EMPTY              0x1E060004,0x00000000
+#define IPU_DMFC_WR_CHAN__FULL               0x1E060004,0xffffffff
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C 0x1E060004,0xC0000000
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C  0x1E060004,0x38000000
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2C    0x1E060004,0x07000000
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C 0x1E060004,0x00C00000
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C  0x1E060004,0x00380000
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1C    0x1E060004,0x00070000
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2  0x1E060004,0x0000C000
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2   0x1E060004,0x00003800
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2     0x1E060004,0x00000700
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1  0x1E060004,0x000000C0
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1   0x1E060004,0x00000038
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1     0x1E060004,0x00000007
+
+#define IPU_DMFC_WR_CHAN_DEF__ADDR           0x1E060008
+#define IPU_DMFC_WR_CHAN_DEF__EMPTY          0x1E060008,0x00000000
+#define IPU_DMFC_WR_CHAN_DEF__FULL           0x1E060008,0xffffffff
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C 0x1E060008,0xE0000000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C 0x1E060008,0x1C000000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C  0x1E060008,0x02000000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C 0x1E060008,0x00E00000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C 0x1E060008,0x001C0000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C  0x1E060008,0x00020000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2  0x1E060008,0x0000E000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2  0x1E060008,0x00001C00
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2   0x1E060008,0x00000200
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1  0x1E060008,0x000000E0
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1  0x1E060008,0x0000001C
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1   0x1E060008,0x00000002
+
+#define IPU_DMFC_DP_CHAN__ADDR               0x1E06000C
+#define IPU_DMFC_DP_CHAN__EMPTY              0x1E06000C,0x00000000
+#define IPU_DMFC_DP_CHAN__FULL               0x1E06000C,0xffffffff
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F 0x1E06000C,0xC0000000
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F  0x1E06000C,0x38000000
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6F    0x1E06000C,0x07000000
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B 0x1E06000C,0x00C00000
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B  0x1E06000C,0x00380000
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6B    0x1E06000C,0x00070000
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F 0x1E06000C,0x0000C000
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F  0x1E06000C,0x00003800
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5F    0x1E06000C,0x00000700
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B 0x1E06000C,0x000000C0
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B  0x1E06000C,0x00000038
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5B    0x1E06000C,0x00000007
+
+#define IPU_DMFC_DP_CHAN_DEF__ADDR           0x1E060010
+#define IPU_DMFC_DP_CHAN_DEF__EMPTY          0x1E060010,0x00000000
+#define IPU_DMFC_DP_CHAN_DEF__FULL           0x1E060010,0xffffffff
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F 0x1E060010,0xE0000000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F 0x1E060010,0x1C000000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F  0x1E060010,0x02000000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B 0x1E060010,0x00E00000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B 0x1E060010,0x001C0000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B  0x1E060010,0x00020000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F 0x1E060010,0x0000E000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F 0x1E060010,0x00001C00
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F  0x1E060010,0x00000200
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B 0x1E060010,0x000000E0
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B 0x1E060010,0x0000001C
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B  0x1E060010,0x00000002
+
+#define IPU_DMFC_GENERAL1__ADDR              0x1E060014
+#define IPU_DMFC_GENERAL1__EMPTY             0x1E060014,0x00000000
+#define IPU_DMFC_GENERAL1__FULL              0x1E060014,0xffffffff
+#define IPU_DMFC_GENERAL1__WAIT4EOT_9        0x1E060014,0x01000000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_6F       0x1E060014,0x00800000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_6B       0x1E060014,0x00400000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_5F       0x1E060014,0x00200000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_5B       0x1E060014,0x00100000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_4        0x1E060014,0x00080000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_3        0x1E060014,0x00040000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_2        0x1E060014,0x00020000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_1        0x1E060014,0x00010000
+#define IPU_DMFC_GENERAL1__DMFC_WM_CLR_9     0x1E060014,0x0000E000
+#define IPU_DMFC_GENERAL1__DMFC_WM_SET_9     0x1E060014,0x00001C00
+#define IPU_DMFC_GENERAL1__DMFC_WM_EN_9      0x1E060014,0x00000200
+#define IPU_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1E060014,0x00000060
+#define IPU_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1E060014,0x00000003
+
+#define IPU_DMFC_GENERAL2__ADDR                 0x1E060018
+#define IPU_DMFC_GENERAL2__EMPTY                0x1E060018,0x00000000
+#define IPU_DMFC_GENERAL2__FULL                 0x1E060018,0xffffffff
+#define IPU_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD 0x1E060018,0x1FFF0000
+#define IPU_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD  0x1E060018,0x00001FFF
+
+#define IPU_DMFC_IC_CTRL__ADDR                    0x1E06001C
+#define IPU_DMFC_IC_CTRL__EMPTY                   0x1E06001C,0x00000000
+#define IPU_DMFC_IC_CTRL__FULL                    0x1E06001C,0xffffffff
+#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD 0x1E06001C,0xFFF80000
+#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD  0x1E06001C,0x0007FFC0
+#define IPU_DMFC_IC_CTRL__DMFC_IC_PPW_C           0x1E06001C,0x00000030
+#define IPU_DMFC_IC_CTRL__DMFC_IC_IN_PORT         0x1E06001C,0x00000007
+
+#define IPU_DMFC_STAT__ADDR                 0x1E060020
+#define IPU_DMFC_STAT__EMPTY                0x1E060020,0x00000000
+#define IPU_DMFC_STAT__FULL                 0x1E060020,0xffffffff
+#define IPU_DMFC_STAT__DMFC_IC_BUFFER_EMPTY 0x1E060020,0x02000000
+#define IPU_DMFC_STAT__DMFC_IC_BUFFER_FULL  0x1E060020,0x01000000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_11   0x1E060020,0x00800000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_10   0x1E060020,0x00400000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_9    0x1E060020,0x00200000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_8    0x1E060020,0x00100000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_7    0x1E060020,0x00080000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_6    0x1E060020,0x00040000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_5    0x1E060020,0x00020000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_4    0x1E060020,0x00010000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_3    0x1E060020,0x00008000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_2    0x1E060020,0x00004000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_1    0x1E060020,0x00002000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_0    0x1E060020,0x00001000
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_11    0x1E060020,0x00000800
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_10    0x1E060020,0x00000400
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_9     0x1E060020,0x00000200
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_8     0x1E060020,0x00000100
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_7     0x1E060020,0x00000080
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_6     0x1E060020,0x00000040
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_5     0x1E060020,0x00000020
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_4     0x1E060020,0x00000010
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_3     0x1E060020,0x00000008
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_2     0x1E060020,0x00000004
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_1     0x1E060020,0x00000002
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_0     0x1E060020,0x00000001
+
+#define CPMEM_WORD0_DATA0_INT__ADDR  0x1F000000
+#define CPMEM_WORD0_DATA0_INT__EMPTY 0x1F000000,0x00000000
+#define CPMEM_WORD0_DATA0_INT__FULL  0x1F000000,0xffffffff
+#define CPMEM_WORD0_DATA0_INT__XB    0x1F000000,0xFFF80000
+#define CPMEM_WORD0_DATA0_INT__YV    0x1F000000,0x0007FC00
+#define CPMEM_WORD0_DATA0_INT__XV    0x1F000000,0x000003FF
+
+#define CPMEM_WORD0_DATA1_INT__ADDR   0x1F000004
+#define CPMEM_WORD0_DATA1_INT__EMPTY  0x1F000004,0x00000000
+#define CPMEM_WORD0_DATA1_INT__FULL   0x1F000004,0xffffffff
+#define CPMEM_WORD0_DATA1_INT__SY_LOW 0x1F000004,0xFC000000
+#define CPMEM_WORD0_DATA1_INT__SX     0x1F000004,0x03FFC000
+#define CPMEM_WORD0_DATA1_INT__CF     0x1F000004,0x00002000
+#define CPMEM_WORD0_DATA1_INT__NSB_B  0x1F000004,0x00001000
+#define CPMEM_WORD0_DATA1_INT__YB     0x1F000004,0x00000FFF
+
+#define CPMEM_WORD0_DATA2_INT__ADDR    0x1F000008
+#define CPMEM_WORD0_DATA2_INT__EMPTY   0x1F000008,0x00000000
+#define CPMEM_WORD0_DATA2_INT__FULL    0x1F000008,0xffffffff
+#define CPMEM_WORD0_DATA2_INT__SM      0x1F000008,0xFFC00000
+#define CPMEM_WORD0_DATA2_INT__SDX     0x1F000008,0x003F8000
+#define CPMEM_WORD0_DATA2_INT__NS      0x1F000008,0x00007FE0
+#define CPMEM_WORD0_DATA2_INT__SY_HIGH 0x1F000008,0x0000001F
+
+#define CPMEM_WORD0_DATA3_INT__ADDR    0x1F00000C
+#define CPMEM_WORD0_DATA3_INT__EMPTY   0x1F00000C,0x00000000
+#define CPMEM_WORD0_DATA3_INT__FULL    0x1F00000C,0xffffffff
+#define CPMEM_WORD0_DATA3_INT__FW_LOW  0x1F00000C,0xE0000000
+#define CPMEM_WORD0_DATA3_INT__CAE     0x1F00000C,0x10000000
+#define CPMEM_WORD0_DATA3_INT__CAP     0x1F00000C,0x08000000
+#define CPMEM_WORD0_DATA3_INT__THE     0x1F00000C,0x04000000
+#define CPMEM_WORD0_DATA3_INT__VF      0x1F00000C,0x02000000
+#define CPMEM_WORD0_DATA3_INT__HF      0x1F00000C,0x01000000
+#define CPMEM_WORD0_DATA3_INT__ROT     0x1F00000C,0x00800000
+#define CPMEM_WORD0_DATA3_INT__BM      0x1F00000C,0x00600000
+#define CPMEM_WORD0_DATA3_INT__BNDM    0x1F00000C,0x001C0000
+#define CPMEM_WORD0_DATA3_INT__SO      0x1F00000C,0x00020000
+#define CPMEM_WORD0_DATA3_INT__DIM     0x1F00000C,0x00010000
+#define CPMEM_WORD0_DATA3_INT__DEC_SEL 0x1F00000C,0x0000C000
+#define CPMEM_WORD0_DATA3_INT__BPP     0x1F00000C,0x00003800
+#define CPMEM_WORD0_DATA3_INT__SDRY    0x1F00000C,0x00000400
+#define CPMEM_WORD0_DATA3_INT__SDRX    0x1F00000C,0x00000200
+#define CPMEM_WORD0_DATA3_INT__SDY     0x1F00000C,0x000001FC
+#define CPMEM_WORD0_DATA3_INT__SCE     0x1F00000C,0x00000002
+#define CPMEM_WORD0_DATA3_INT__SCC     0x1F00000C,0x00000001
+
+#define CPMEM_WORD0_DATA4_INT__ADDR     0x1F000010
+#define CPMEM_WORD0_DATA4_INT__EMPTY    0x1F000010,0x00000000
+#define CPMEM_WORD0_DATA4_INT__FULL     0x1F000010,0xffffffff
+#define CPMEM_WORD0_DATA4_INT__RESERVED 0x1F000010,0xFFC00000
+#define CPMEM_WORD0_DATA4_INT__FH       0x1F000010,0x003FFC00
+#define CPMEM_WORD0_DATA4_INT__FW_HIGH  0x1F000010,0x000003FF
+
+#define CPMEM_WORD0_DATA0_N_INT__ADDR  0x1F000000
+#define CPMEM_WORD0_DATA0_N_INT__EMPTY 0x1F000000,0x00000000
+#define CPMEM_WORD0_DATA0_N_INT__FULL  0x1F000000,0xffffffff
+#define CPMEM_WORD0_DATA0_N_INT__XB    0x1F000000,0xFFF80000
+#define CPMEM_WORD0_DATA0_N_INT__YV    0x1F000000,0x0007FC00
+#define CPMEM_WORD0_DATA0_N_INT__XV    0x1F000000,0x000003FF
+
+#define CPMEM_WORD0_DATA1_N_INT__ADDR    0x1F000004
+#define CPMEM_WORD0_DATA1_N_INT__EMPTY   0x1F000004,0x00000000
+#define CPMEM_WORD0_DATA1_N_INT__FULL    0x1F000004,0xffffffff
+#define CPMEM_WORD0_DATA1_N_INT__UBO_LOW 0x1F000004,0xFFFFC000
+#define CPMEM_WORD0_DATA1_N_INT__CF      0x1F000004,0x00002000
+#define CPMEM_WORD0_DATA1_N_INT__NSB_B   0x1F000004,0x00001000
+#define CPMEM_WORD0_DATA1_N_INT__YB      0x1F000004,0x00000FFF
+
+#define CPMEM_WORD0_DATA2_N_INT__ADDR     0x1F000008
+#define CPMEM_WORD0_DATA2_N_INT__EMPTY    0x1F000008,0x00000000
+#define CPMEM_WORD0_DATA2_N_INT__FULL     0x1F000008,0xffffffff
+#define CPMEM_WORD0_DATA2_N_INT__RESERVED 0x1F000008,0xFC000000
+#define CPMEM_WORD0_DATA2_N_INT__VBO      0x1F000008,0x03FFFFF0
+#define CPMEM_WORD0_DATA2_N_INT__UBO_HIGH 0x1F000008,0x0000000F
+
+#define CPMEM_WORD0_DATA3_N_INT__ADDR     0x1F00000C
+#define CPMEM_WORD0_DATA3_N_INT__EMPTY    0x1F00000C,0x00000000
+#define CPMEM_WORD0_DATA3_N_INT__FULL     0x1F00000C,0xffffffff
+#define CPMEM_WORD0_DATA3_N_INT__FW_LOW   0x1F00000C,0xE0000000
+#define CPMEM_WORD0_DATA3_N_INT__CAE      0x1F00000C,0x10000000
+#define CPMEM_WORD0_DATA3_N_INT__CAP      0x1F00000C,0x08000000
+#define CPMEM_WORD0_DATA3_N_INT__THE      0x1F00000C,0x04000000
+#define CPMEM_WORD0_DATA3_N_INT__VF       0x1F00000C,0x02000000
+#define CPMEM_WORD0_DATA3_N_INT__HF       0x1F00000C,0x01000000
+#define CPMEM_WORD0_DATA3_N_INT__ROT      0x1F00000C,0x00800000
+#define CPMEM_WORD0_DATA3_N_INT__BM       0x1F00000C,0x00600000
+#define CPMEM_WORD0_DATA3_N_INT__BNDM     0x1F00000C,0x001C0000
+#define CPMEM_WORD0_DATA3_N_INT__SO       0x1F00000C,0x00020000
+#define CPMEM_WORD0_DATA3_N_INT__RESERVED 0x1F00000C,0x0001FFFF
+
+#define CPMEM_WORD0_DATA4_N_INT__ADDR     0x1F000010
+#define CPMEM_WORD0_DATA4_N_INT__EMPTY    0x1F000010,0x00000000
+#define CPMEM_WORD0_DATA4_N_INT__FULL     0x1F000010,0xffffffff
+#define CPMEM_WORD0_DATA4_N_INT__RESERVED 0x1F000010,0xFFC00000
+#define CPMEM_WORD0_DATA4_N_INT__FH       0x1F000010,0x003FFC00
+#define CPMEM_WORD0_DATA4_N_INT__FW_HIGH  0x1F000010,0x000003FF
+
+#define CPMEM_WORD1_DATA0_INT__ADDR     0x1F000020
+#define CPMEM_WORD1_DATA0_INT__EMPTY    0x1F000020,0x00000000
+#define CPMEM_WORD1_DATA0_INT__FULL     0x1F000020,0xffffffff
+#define CPMEM_WORD1_DATA0_INT__EBA1_LOW 0x1F000020,0xE0000000
+#define CPMEM_WORD1_DATA0_INT__EBA0     0x1F000020,0x1FFFFFFF
+
+#define CPMEM_WORD1_DATA1_INT__ADDR      0x1F000024
+#define CPMEM_WORD1_DATA1_INT__EMPTY     0x1F000024,0x00000000
+#define CPMEM_WORD1_DATA1_INT__FULL      0x1F000024,0xffffffff
+#define CPMEM_WORD1_DATA1_INT__ILO_LOW   0x1F000024,0xFC000000
+#define CPMEM_WORD1_DATA1_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF
+
+#define CPMEM_WORD1_DATA2_INT__ADDR     0x1F000028
+#define CPMEM_WORD1_DATA2_INT__EMPTY    0x1F000028,0x00000000
+#define CPMEM_WORD1_DATA2_INT__FULL     0x1F000028,0xffffffff
+#define CPMEM_WORD1_DATA2_INT__TH_LOW   0x1F000028,0x80000000
+#define CPMEM_WORD1_DATA2_INT__ID       0x1F000028,0x60000000
+#define CPMEM_WORD1_DATA2_INT__ALBM     0x1F000028,0x1C000000
+#define CPMEM_WORD1_DATA2_INT__ALU      0x1F000028,0x02000000
+#define CPMEM_WORD1_DATA2_INT__PFS      0x1F000028,0x01E00000
+#define CPMEM_WORD1_DATA2_INT__NPB      0x1F000028,0x001FC000
+#define CPMEM_WORD1_DATA2_INT__ILO_HIGH 0x1F000028,0x00003FFF
+
+#define CPMEM_WORD1_DATA3_INT__ADDR    0x1F00002C
+#define CPMEM_WORD1_DATA3_INT__EMPTY   0x1F00002C,0x00000000
+#define CPMEM_WORD1_DATA3_INT__FULL    0x1F00002C,0xffffffff
+#define CPMEM_WORD1_DATA3_INT__WID3    0x1F00002C,0xE0000000
+#define CPMEM_WORD1_DATA3_INT__WID2    0x1F00002C,0x1C000000
+#define CPMEM_WORD1_DATA3_INT__WID1    0x1F00002C,0x03800000
+#define CPMEM_WORD1_DATA3_INT__WID0    0x1F00002C,0x00700000
+#define CPMEM_WORD1_DATA3_INT__SL      0x1F00002C,0x000FFFC0
+#define CPMEM_WORD1_DATA3_INT__TH_HIGH 0x1F00002C,0x0000003F
+
+#define CPMEM_WORD1_DATA4_INT__ADDR     0x1F000030
+#define CPMEM_WORD1_DATA4_INT__EMPTY    0x1F000030,0x00000000
+#define CPMEM_WORD1_DATA4_INT__FULL     0x1F000030,0xffffffff
+#define CPMEM_WORD1_DATA4_INT__RESERVED 0x1F000030,0xFFF00000
+#define CPMEM_WORD1_DATA4_INT__OFS3     0x1F000030,0x000F8000
+#define CPMEM_WORD1_DATA4_INT__OFS2     0x1F000030,0x00007C00
+#define CPMEM_WORD1_DATA4_INT__OFS1     0x1F000030,0x000003E0
+#define CPMEM_WORD1_DATA4_INT__OFS0     0x1F000030,0x0000001F
+
+#define CPMEM_WORD1_DATA0_N_INT__ADDR     0x1F000020
+#define CPMEM_WORD1_DATA0_N_INT__EMPTY    0x1F000020,0x00000000
+#define CPMEM_WORD1_DATA0_N_INT__FULL     0x1F000020,0xffffffff
+#define CPMEM_WORD1_DATA0_N_INT__EBA1_LOW 0x1F000020,0xE0000000
+#define CPMEM_WORD1_DATA0_N_INT__EBA0     0x1F000020,0x1FFFFFFF
+
+#define CPMEM_WORD1_DATA1_N_INT__ADDR      0x1F000024
+#define CPMEM_WORD1_DATA1_N_INT__EMPTY     0x1F000024,0x00000000
+#define CPMEM_WORD1_DATA1_N_INT__FULL      0x1F000024,0xffffffff
+#define CPMEM_WORD1_DATA1_N_INT__ILO_LOW   0x1F000024,0xFC000000
+#define CPMEM_WORD1_DATA1_N_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF
+
+#define CPMEM_WORD1_DATA2_N_INT__ADDR     0x1F000028
+#define CPMEM_WORD1_DATA2_N_INT__EMPTY    0x1F000028,0x00000000
+#define CPMEM_WORD1_DATA2_N_INT__FULL     0x1F000028,0xffffffff
+#define CPMEM_WORD1_DATA2_N_INT__TH_LOW   0x1F000028,0x80000000
+#define CPMEM_WORD1_DATA2_N_INT__ID       0x1F000028,0x60000000
+#define CPMEM_WORD1_DATA2_N_INT__ALBM     0x1F000028,0x1C000000
+#define CPMEM_WORD1_DATA2_N_INT__ALU      0x1F000028,0x02000000
+#define CPMEM_WORD1_DATA2_N_INT__PFS      0x1F000028,0x01E00000
+#define CPMEM_WORD1_DATA2_N_INT__NPB      0x1F000028,0x001FC000
+#define CPMEM_WORD1_DATA2_N_INT__ILO_HIGH 0x1F000028,0x00003FFF
+
+#define CPMEM_WORD1_DATA3_N_INT__ADDR     0x1F00002C
+#define CPMEM_WORD1_DATA3_N_INT__EMPTY    0x1F00002C,0x00000000
+#define CPMEM_WORD1_DATA3_N_INT__FULL     0x1F00002C,0xffffffff
+#define CPMEM_WORD1_DATA3_N_INT__SLY      0x1F00002C,0x000FFFC0
+#define CPMEM_WORD1_DATA3_N_INT__WID3     0x1F00002C,0xE0000000
+#define CPMEM_WORD1_DATA3_N_INT__TH_HIGH  0x1F00002C,0x0000003F
+
+#define CPMEM_WORD1_DATA4_N_INT__ADDR      0x1F000030
+#define CPMEM_WORD1_DATA4_N_INT__EMPTY     0x1F000030,0x00000000
+#define CPMEM_WORD1_DATA4_N_INT__FULL      0x1F000030,0xffffffff
+#define CPMEM_WORD1_DATA4_N_INT__RESERVED  0x1F000030,0xFFFFC000
+#define CPMEM_WORD1_DATA4_N_INT__SLUV      0x1F000030,0x00003FFF
+
+#define IC_INTERNAL_MEM_FW 0x400
+#define TASK1_TMP_COEF IC_INTERNAL_MEM_FW
+#define TASK1_CSC1_W0    (TASK1_TMP_COEF+1)
+#define TASK1_CSC1_W1    (TASK1_CSC1_W0+1)
+#define TASK1_CSC1_W2    (TASK1_CSC1_W1+1 )
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR   (0x1F060000 + (TASK1_CSC1_W0 << 3))
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C00    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C11    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C22    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR     0x1F060000 + (TASK1_CSC1_W0 << 3) + 4
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__FULL     IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SCALE    IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR   0x1F060000 + (TASK1_CSC1_W1 << 3)
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C01    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C10    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C20    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR    0x1F060000 + (TASK1_CSC1_W1 << 3) + 4
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__FULL    IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR   0x1F060000 + (TASK1_CSC1_W2 << 3)
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C02    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C12    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C21    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR    0x1F060000 + (TASK1_CSC1_W2 << 3) + 4
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__FULL    IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x000000FF
+
+#define TASK2_TMP_COEF   (TASK1_CSC1_W2+IC_INTERNAL_MEM_FW+1)
+#define TASK2_CSC1_W0    (TASK2_TMP_COEF+1)
+#define TASK2_CSC1_W1    (TASK2_CSC1_W0+1)
+#define TASK2_CSC1_W2    (TASK2_CSC1_W1+1)
+#define TASK2_CSC2_W0    (TASK2_CSC1_W2+1)
+#define TASK2_CSC2_W1    (TASK2_CSC2_W0+1)
+#define TASK2_CSC2_W2    (TASK2_CSC2_W1+1)
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR   (0x1F060000 + (TASK2_CSC1_W0 << 3))
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C00    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C11    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C22    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR     0x1F060000 + (TASK2_CSC1_W0 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__FULL     IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SCALE    IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR   0x1F060000 + (TASK2_CSC1_W1 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C01    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C10    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C20    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR    0x1F060000 + (TASK2_CSC1_W1 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__FULL    IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR   0x1F060000 + (TASK2_CSC1_W2 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C02    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C12    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C21    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR    0x1F060000 + (TASK2_CSC1_W2 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__FULL    IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR   0x1F060000 + (TASK2_CSC2_W0 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C00    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C11    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C22    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR     0x1F060000 + (TASK2_CSC2_W0 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__EMPTY    IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__FULL     IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SCALE    IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__A0_HIGH  IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR   0x1F060000 + (TASK2_CSC2_W1 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C01    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C10    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C20    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR    0x1F060000 + (TASK2_CSC2_W1 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__EMPTY   IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__FULL    IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR   0x1F060000 + (TASK2_CSC2_W2 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C02    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C12    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C21    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR    0x1F060000 + (TASK2_CSC2_W2 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__EMPTY   IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__FULL    IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x000000FF
+
+#define TASK3_TMP_COEF   (TASK2_CSC2_W2+IC_INTERNAL_MEM_FW+1)
+#define TASK3_CSC1_W0    (TASK3_TMP_COEF+1)
+#define TASK3_CSC1_W1    (TASK3_CSC1_W0+1)
+#define TASK3_CSC1_W2    (TASK3_CSC1_W1+1)
+#define TASK3_CSC2_W0    (TASK3_CSC1_W2+1)
+#define TASK3_CSC2_W1    (TASK3_CSC2_W0+1)
+#define TASK3_CSC2_W2    (TASK3_CSC2_W1+1)
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR   (0x1F060000 + (TASK3_CSC1_W0 << 3))
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__FULL   IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__C00    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__C11    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__C22    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR     0x1F060000 + (TASK3_CSC1_W0 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__FULL     IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__SCALE    IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR   0x1F060000 + (TASK3_CSC1_W1 << 3)
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__FULL   IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__C01    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__C10    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__C20    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR    0x1F060000 + (TASK3_CSC1_W1 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__FULL    IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR   0x1F060000 + (TASK3_CSC1_W2 << 3)
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__FULL   IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__C02    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__C12    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__C21    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR    0x1F060000 + (TASK3_CSC1_W2 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__FULL    IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR   0x1F060000 + (TASK3_CSC2_W0 << 3)
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__FULL   IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__C00    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__C11    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__C22    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR     0x1F060000 + (TASK3_CSC2_W0 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__EMPTY    IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__FULL     IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__SCALE    IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__A0_HIGH  IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR   0x1F060000 + (TASK3_CSC2_W1 << 3)
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__FULL   IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__C01    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__C10    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__C20    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR    0x1F060000 + (TASK3_CSC2_W1 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__EMPTY   IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__FULL    IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR   0x1F060000 + (TASK3_CSC2_W2 << 3)
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__FULL   IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__C02    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__C12    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__C21    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR    0x1F060000 + (TASK3_CSC2_W2 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__EMPTY   IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__FULL    IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x000000FF
+
+#define SRM_DP_COM_CONF_SYNC__ADDR                     0x1F040000
+#define SRM_DP_COM_CONF_SYNC__EMPTY                    0x1F040000,0x00000000
+#define SRM_DP_COM_CONF_SYNC__FULL                     0x1F040000,0xffffffff
+#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC     0x1F040000,0x00002000
+#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC         0x1F040000,0x00001000
+#define SRM_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1F040000,0x00000800
+#define SRM_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1F040000,0x00000400
+#define SRM_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC          0x1F040000,0x00000300
+#define SRM_DP_COM_CONF_SYNC__DP_COC_SYNC              0x1F040000,0x00000070
+#define SRM_DP_COM_CONF_SYNC__DP_GWCKE_SYNC            0x1F040000,0x00000008
+#define SRM_DP_COM_CONF_SYNC__DP_GWAM_SYNC             0x1F040000,0x00000004
+#define SRM_DP_COM_CONF_SYNC__DP_GWSEL_SYNC            0x1F040000,0x00000002
+#define SRM_DP_COM_CONF_SYNC__DP_FG_EN_SYNC            0x1F040000,0x00000001
+
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__ADDR          0x1F040004
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__EMPTY         0x1F040004,0x00000000
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__FULL          0x1F040004,0xffffffff
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC  0x1F040004,0xFF000000
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1F040004,0x00FF0000
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1F040004,0x0000FF00
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1F040004,0x000000FF
+
+#define SRM_DP_FG_POS_SYNC__ADDR         0x1F040008
+#define SRM_DP_FG_POS_SYNC__EMPTY        0x1F040008,0x00000000
+#define SRM_DP_FG_POS_SYNC__FULL         0x1F040008,0xffffffff
+#define SRM_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1F040008,0x07FF0000
+#define SRM_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1F040008,0x000007FF
+
+#define SRM_DP_CUR_POS_SYNC__ADDR        0x1F04000C
+#define SRM_DP_CUR_POS_SYNC__EMPTY       0x1F04000C,0x00000000
+#define SRM_DP_CUR_POS_SYNC__FULL        0x1F04000C,0xffffffff
+#define SRM_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1F04000C,0xF8000000
+#define SRM_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1F04000C,0x07FF0000
+#define SRM_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1F04000C,0x0000F800
+#define SRM_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1F04000C,0x000007FF
+
+#define SRM_DP_CUR_MAP_SYNC__ADDR              0x1F040010
+#define SRM_DP_CUR_MAP_SYNC__EMPTY             0x1F040010,0x00000000
+#define SRM_DP_CUR_MAP_SYNC__FULL              0x1F040010,0xffffffff
+#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1F040010,0x00FF0000
+#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1F040010,0x0000FF00
+#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1F040010,0x000000FF
+
+#define SRM_DP_GAMMA_C_SYNC_0__ADDR              0x1F040014
+#define SRM_DP_GAMMA_C_SYNC_0__EMPTY             0x1F040014,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_0__FULL              0x1F040014,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1F040014,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1F040014,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_1__ADDR              0x1F040018
+#define SRM_DP_GAMMA_C_SYNC_1__EMPTY             0x1F040018,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_1__FULL              0x1F040018,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1F040018,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1F040018,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_2__ADDR              0x1F04001C
+#define SRM_DP_GAMMA_C_SYNC_2__EMPTY             0x1F04001C,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_2__FULL              0x1F04001C,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1F04001C,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1F04001C,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_3__ADDR              0x1F040020
+#define SRM_DP_GAMMA_C_SYNC_3__EMPTY             0x1F040020,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_3__FULL              0x1F040020,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1F040020,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1F040020,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_4__ADDR              0x1F040024
+#define SRM_DP_GAMMA_C_SYNC_4__EMPTY             0x1F040024,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_4__FULL              0x1F040024,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1F040024,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1F040024,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_5__ADDR               0x1F040028
+#define SRM_DP_GAMMA_C_SYNC_5__EMPTY              0x1F040028,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_5__FULL               0x1F040028,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1F040028,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1F040028,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_6__ADDR               0x1F04002C
+#define SRM_DP_GAMMA_C_SYNC_6__EMPTY              0x1F04002C,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_6__FULL               0x1F04002C,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1F04002C,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1F04002C,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_7__ADDR               0x1F040030
+#define SRM_DP_GAMMA_C_SYNC_7__EMPTY              0x1F040030,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_7__FULL               0x1F040030,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1F040030,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1F040030,0x000001FF
+
+#define SRM_DP_GAMMA_S_SYNC_0__ADDR              0x1F040034
+#define SRM_DP_GAMMA_S_SYNC_0__EMPTY             0x1F040034,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_0__FULL              0x1F040034,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1F040034,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1F040034,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1F040034,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1F040034,0x000000FF
+
+#define SRM_DP_GAMMA_S_SYNC_1__ADDR              0x1F040038
+#define SRM_DP_GAMMA_S_SYNC_1__EMPTY             0x1F040038,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_1__FULL              0x1F040038,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1F040038,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1F040038,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1F040038,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1F040038,0x000000FF
+
+#define SRM_DP_GAMMA_S_SYNC_2__ADDR               0x1F04003C
+#define SRM_DP_GAMMA_S_SYNC_2__EMPTY              0x1F04003C,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_2__FULL               0x1F04003C,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1F04003C,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1F04003C,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9  0x1F04003C,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8  0x1F04003C,0x000000FF
+
+#define SRM_DP_GAMMA_S_SYNC_3__ADDR               0x1F040040
+#define SRM_DP_GAMMA_S_SYNC_3__EMPTY              0x1F040040,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_3__FULL               0x1F040040,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1F040040,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1F040040,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1F040040,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1F040040,0x000000FF
+
+#define SRM_DP_CSCA_SYNC_0__ADDR            0x1F040044
+#define SRM_DP_CSCA_SYNC_0__EMPTY           0x1F040044,0x00000000
+#define SRM_DP_CSCA_SYNC_0__FULL            0x1F040044,0xffffffff
+#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1F040044,0x03FF0000
+#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1F040044,0x000003FF
+
+#define SRM_DP_CSCA_SYNC_1__ADDR            0x1F040048
+#define SRM_DP_CSCA_SYNC_1__EMPTY           0x1F040048,0x00000000
+#define SRM_DP_CSCA_SYNC_1__FULL            0x1F040048,0xffffffff
+#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1F040048,0x03FF0000
+#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1F040048,0x000003FF
+
+#define SRM_DP_CSCA_SYNC_2__ADDR            0x1F04004C
+#define SRM_DP_CSCA_SYNC_2__EMPTY           0x1F04004C,0x00000000
+#define SRM_DP_CSCA_SYNC_2__FULL            0x1F04004C,0xffffffff
+#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1F04004C,0x03FF0000
+#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1F04004C,0x000003FF
+
+#define SRM_DP_CSCA_SYNC_3__ADDR            0x1F040050
+#define SRM_DP_CSCA_SYNC_3__EMPTY           0x1F040050,0x00000000
+#define SRM_DP_CSCA_SYNC_3__FULL            0x1F040050,0xffffffff
+#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1F040050,0x03FF0000
+#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1F040050,0x000003FF
+
+#define SRM_DP_CSC_SYNC_0__ADDR           0x1F040054
+#define SRM_DP_CSC_SYNC_0__EMPTY          0x1F040054,0x00000000
+#define SRM_DP_CSC_SYNC_0__FULL           0x1F040054,0xffffffff
+#define SRM_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1F040054,0xC0000000
+#define SRM_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1F040054,0x3FFF0000
+#define SRM_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1F040054,0x000003FF
+
+#define SRM_DP_CSC_SYNC_1__ADDR           0x1F040058
+#define SRM_DP_CSC_SYNC_1__EMPTY          0x1F040058,0x00000000
+#define SRM_DP_CSC_SYNC_1__FULL           0x1F040058,0xffffffff
+#define SRM_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1F040058,0xC0000000
+#define SRM_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1F040058,0x3FFF0000
+#define SRM_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1F040058,0x0000C000
+#define SRM_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1F040058,0x00003FFF
+
+#define SRM_DP_CUR_POS_ALT__ADDR            0x1F04005C
+#define SRM_DP_CUR_POS_ALT__EMPTY           0x1F04005C,0x00000000
+#define SRM_DP_CUR_POS_ALT__FULL            0x1F04005C,0xffffffff
+#define SRM_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1F04005C,0xF8000000
+#define SRM_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1F04005C,0x07FF0000
+#define SRM_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1F04005C,0x0000F800
+#define SRM_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1F04005C,0x000007FF
+
+#define SRM_DP_COM_CONF_ASYNC0__ADDR                       0x1F040060
+#define SRM_DP_COM_CONF_ASYNC0__EMPTY                      0x1F040060,0x00000000
+#define SRM_DP_COM_CONF_ASYNC0__FULL                       0x1F040060,0xffffffff
+#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_YUV_EN_ASYNC0     0x1F040060,0x00002000
+#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_EN_ASYNC0         0x1F040060,0x00001000
+#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_YUV_SAT_MODE_ASYNC0 0x1F040060,0x00000800
+#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_GAMUT_SAT_EN_ASYNC0 0x1F040060,0x00000400
+#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_DEF_ASYNC0          0x1F040060,0x00000300
+#define SRM_DP_COM_CONF_ASYNC0__DP_COC_ASYNC0              0x1F040060,0x00000070
+#define SRM_DP_COM_CONF_ASYNC0__DP_GWCKE_ASYNC0            0x1F040060,0x00000008
+#define SRM_DP_COM_CONF_ASYNC0__DP_GWAM_ASYNC0             0x1F040060,0x00000004
+#define SRM_DP_COM_CONF_ASYNC0__DP_GWSEL_ASYNC0            0x1F040060,0x00000002
+
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__ADDR            0x1F040064
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__EMPTY           0x1F040064,0x00000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__FULL            0x1F040064,0xffffffff
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWAV_ASYNC0  0x1F040064,0xFF000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKR_ASYNC0 0x1F040064,0x00FF0000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKG_ASYNC0 0x1F040064,0x0000FF00
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKB_ASYNC0 0x1F040064,0x000000FF
+
+#define SRM_DP_FG_POS_ASYNC0__ADDR           0x1F040068
+#define SRM_DP_FG_POS_ASYNC0__EMPTY          0x1F040068,0x00000000
+#define SRM_DP_FG_POS_ASYNC0__FULL           0x1F040068,0xffffffff
+#define SRM_DP_FG_POS_ASYNC0__DP_FGXP_ASYNC0 0x1F040068,0x07FF0000
+#define SRM_DP_FG_POS_ASYNC0__DP_FGYP_ASYNC0 0x1F040068,0x000007FF
+
+#define SRM_DP_CUR_POS_ASYNC0__ADDR          0x1F04006C
+#define SRM_DP_CUR_POS_ASYNC0__EMPTY         0x1F04006C,0x00000000
+#define SRM_DP_CUR_POS_ASYNC0__FULL          0x1F04006C,0xffffffff
+#define SRM_DP_CUR_POS_ASYNC0__DP_CXW_ASYNC0 0x1F04006C,0xF8000000
+#define SRM_DP_CUR_POS_ASYNC0__DP_CXP_ASYNC0 0x1F04006C,0x07FF0000
+#define SRM_DP_CUR_POS_ASYNC0__DP_CYH_ASYNC0 0x1F04006C,0x0000F800
+#define SRM_DP_CUR_POS_ASYNC0__DP_CYP_ASYNC0 0x1F04006C,0x000007FF
+
+#define SRM_DP_CUR_MAP_ASYNC0__ADDR             0x1F040070
+#define SRM_DP_CUR_MAP_ASYNC0__EMPTY            0x1F040070,0x00000000
+#define SRM_DP_CUR_MAP_ASYNC0__FULL             0x1F040070,0xffffffff
+#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_R_ASYNC0 0x1F040070,0x00FF0000
+#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_G_ASYNC0 0x1F040070,0x0000FF00
+#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_B_ASYNC0 0x1F040070,0x000000FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_0__ADDR                0x1F040074
+#define SRM_DP_GAMMA_C_ASYNC0_0__EMPTY               0x1F040074,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_0__FULL                0x1F040074,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_1 0x1F040074,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_0 0x1F040074,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_1__ADDR                0x1F040078
+#define SRM_DP_GAMMA_C_ASYNC0_1__EMPTY               0x1F040078,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_1__FULL                0x1F040078,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_3 0x1F040078,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_2 0x1F040078,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_2__ADDR                0x1F04007C
+#define SRM_DP_GAMMA_C_ASYNC0_2__EMPTY               0x1F04007C,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_2__FULL                0x1F04007C,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_5 0x1F04007C,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_4 0x1F04007C,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_3__ADDR                0x1F040080
+#define SRM_DP_GAMMA_C_ASYNC0_3__EMPTY               0x1F040080,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_3__FULL                0x1F040080,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_7 0x1F040080,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_6 0x1F040080,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_4__ADDR                0x1F040084
+#define SRM_DP_GAMMA_C_ASYNC0_4__EMPTY               0x1F040084,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_4__FULL                0x1F040084,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_9 0x1F040084,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_8 0x1F040084,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_5__ADDR                 0x1F040088
+#define SRM_DP_GAMMA_C_ASYNC0_5__EMPTY                0x1F040088,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_5__FULL                 0x1F040088,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_11 0x1F040088,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_10 0x1F040088,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_6__ADDR                 0x1F04008C
+#define SRM_DP_GAMMA_C_ASYNC0_6__EMPTY                0x1F04008C,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_6__FULL                 0x1F04008C,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_13 0x1F04008C,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_12 0x1F04008C,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_7__ADDR                 0x1F040090
+#define SRM_DP_GAMMA_C_ASYNC0_7__EMPTY                0x1F040090,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_7__FULL                 0x1F040090,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_15 0x1F040090,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_14 0x1F040090,0x000001FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_0__ADDR                0x1F040094
+#define SRM_DP_GAMMA_S_ASYNC0_0__EMPTY               0x1F040094,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_0__FULL                0x1F040094,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_3 0x1F040094,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_2 0x1F040094,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_1 0x1F040094,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_0 0x1F040094,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_1__ADDR                0x1F040098
+#define SRM_DP_GAMMA_S_ASYNC0_1__EMPTY               0x1F040098,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_1__FULL                0x1F040098,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_7 0x1F040098,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_6 0x1F040098,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_5 0x1F040098,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_4 0x1F040098,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_2__ADDR                 0x1F04009C
+#define SRM_DP_GAMMA_S_ASYNC0_2__EMPTY                0x1F04009C,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_2__FULL                 0x1F04009C,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_11 0x1F04009C,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_10 0x1F04009C,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_9  0x1F04009C,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_8  0x1F04009C,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_3__ADDR                 0x1F0400A0
+#define SRM_DP_GAMMA_S_ASYNC0_3__EMPTY                0x1F0400A0,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_3__FULL                 0x1F0400A0,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_15 0x1F0400A0,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_14 0x1F0400A0,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_13 0x1F0400A0,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_12 0x1F0400A0,0x000000FF
+
+#define SRM_DP_CSCA_ASYNC0_0__ADDR              0x1F0400A4
+#define SRM_DP_CSCA_ASYNC0_0__EMPTY             0x1F0400A4,0x00000000
+#define SRM_DP_CSCA_ASYNC0_0__FULL              0x1F0400A4,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_1 0x1F0400A4,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_0 0x1F0400A4,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC0_1__ADDR              0x1F0400A8
+#define SRM_DP_CSCA_ASYNC0_1__EMPTY             0x1F0400A8,0x00000000
+#define SRM_DP_CSCA_ASYNC0_1__FULL              0x1F0400A8,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_3 0x1F0400A8,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_2 0x1F0400A8,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC0_2__ADDR              0x1F0400AC
+#define SRM_DP_CSCA_ASYNC0_2__EMPTY             0x1F0400AC,0x00000000
+#define SRM_DP_CSCA_ASYNC0_2__FULL              0x1F0400AC,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_5 0x1F0400AC,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_4 0x1F0400AC,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC0_3__ADDR              0x1F0400B0
+#define SRM_DP_CSCA_ASYNC0_3__EMPTY             0x1F0400B0,0x00000000
+#define SRM_DP_CSCA_ASYNC0_3__FULL              0x1F0400B0,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_7 0x1F0400B0,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_6 0x1F0400B0,0x000003FF
+
+#define SRM_DP_CSC_ASYNC0_0__ADDR             0x1F0400B4
+#define SRM_DP_CSC_ASYNC0_0__EMPTY            0x1F0400B4,0x00000000
+#define SRM_DP_CSC_ASYNC0_0__FULL             0x1F0400B4,0xffffffff
+#define SRM_DP_CSC_ASYNC0_0__DP_CSC_S0_ASYNC0 0x1F0400B4,0xC0000000
+#define SRM_DP_CSC_ASYNC0_0__DP_CSC_B0_ASYNC0 0x1F0400B4,0x3FFF0000
+#define SRM_DP_CSC_ASYNC0_0__DP_CSC_A8_ASYNC0 0x1F0400B4,0x000003FF
+
+#define SRM_DP_CSC_ASYNC0_1__ADDR             0x1F0400B8
+#define SRM_DP_CSC_ASYNC0_1__EMPTY            0x1F0400B8,0x00000000
+#define SRM_DP_CSC_ASYNC0_1__FULL             0x1F0400B8,0xffffffff
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S2_ASYNC0 0x1F0400B8,0xC0000000
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B2_ASYNC0 0x1F0400B8,0x3FFF0000
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S1_ASYNC0 0x1F0400B8,0x0000C000
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B1_ASYNC0 0x1F0400B8,0x00003FFF
+
+#define SRM_DP_COM_CONF_ASYNC1__ADDR                       0x1F0400BC
+#define SRM_DP_COM_CONF_ASYNC1__EMPTY                      0x1F0400BC,0x00000000
+#define SRM_DP_COM_CONF_ASYNC1__FULL                       0x1F0400BC,0xffffffff
+#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_YUV_EN_ASYNC1     0x1F0400BC,0x00002000
+#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_EN_ASYNC1         0x1F0400BC,0x00001000
+#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_YUV_SAT_MODE_ASYNC1 0x1F0400BC,0x00000800
+#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_GAMUT_SAT_EN_ASYNC1 0x1F0400BC,0x00000400
+#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_DEF_ASYNC1          0x1F0400BC,0x00000300
+#define SRM_DP_COM_CONF_ASYNC1__DP_COC_ASYNC1              0x1F0400BC,0x00000070
+#define SRM_DP_COM_CONF_ASYNC1__DP_GWCKE_ASYNC1            0x1F0400BC,0x00000008
+#define SRM_DP_COM_CONF_ASYNC1__DP_GWAM_ASYNC1             0x1F0400BC,0x00000004
+#define SRM_DP_COM_CONF_ASYNC1__DP_GWSEL_ASYNC1            0x1F0400BC,0x00000002
+
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__ADDR            0x1F0400C0
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__EMPTY           0x1F0400C0,0x00000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__FULL            0x1F0400C0,0xffffffff
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWAV_ASYNC1  0x1F0400C0,0xFF000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKR_ASYNC1 0x1F0400C0,0x00FF0000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKG_ASYNC1 0x1F0400C0,0x0000FF00
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKB_ASYNC1 0x1F0400C0,0x000000FF
+
+#define SRM_DP_FG_POS_ASYNC1__ADDR           0x1F0400C4
+#define SRM_DP_FG_POS_ASYNC1__EMPTY          0x1F0400C4,0x00000000
+#define SRM_DP_FG_POS_ASYNC1__FULL           0x1F0400C4,0xffffffff
+#define SRM_DP_FG_POS_ASYNC1__DP_FGXP_ASYNC1 0x1F0400C4,0x07FF0000
+#define SRM_DP_FG_POS_ASYNC1__DP_FGYP_ASYNC1 0x1F0400C4,0x000007FF
+
+#define SRM_DP_CUR_POS_ASYNC1__ADDR          0x1F0400C8
+#define SRM_DP_CUR_POS_ASYNC1__EMPTY         0x1F0400C8,0x00000000
+#define SRM_DP_CUR_POS_ASYNC1__FULL          0x1F0400C8,0xffffffff
+#define SRM_DP_CUR_POS_ASYNC1__DP_CXW_ASYNC1 0x1F0400C8,0xF8000000
+#define SRM_DP_CUR_POS_ASYNC1__DP_CXP_ASYNC1 0x1F0400C8,0x07FF0000
+#define SRM_DP_CUR_POS_ASYNC1__DP_CYH_ASYNC1 0x1F0400C8,0x0000F800
+#define SRM_DP_CUR_POS_ASYNC1__DP_CYP_ASYNC1 0x1F0400C8,0x000007FF
+
+#define SRM_DP_CUR_MAP_ASYNC1__ADDR             0x1F0400CC
+#define SRM_DP_CUR_MAP_ASYNC1__EMPTY            0x1F0400CC,0x00000000
+#define SRM_DP_CUR_MAP_ASYNC1__FULL             0x1F0400CC,0xffffffff
+#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_R_ASYNC1 0x1F0400CC,0x00FF0000
+#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_G_ASYNC1 0x1F0400CC,0x0000FF00
+#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_B_ASYNC1 0x1F0400CC,0x000000FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_0__ADDR                0x1F0400D0
+#define SRM_DP_GAMMA_C_ASYNC1_0__EMPTY               0x1F0400D0,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_0__FULL                0x1F0400D0,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_1 0x1F0400D0,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_0 0x1F0400D0,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_1__ADDR                0x1F0400D4
+#define SRM_DP_GAMMA_C_ASYNC1_1__EMPTY               0x1F0400D4,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_1__FULL                0x1F0400D4,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_3 0x1F0400D4,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_2 0x1F0400D4,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_2__ADDR                0x1F0400D8
+#define SRM_DP_GAMMA_C_ASYNC1_2__EMPTY               0x1F0400D8,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_2__FULL                0x1F0400D8,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_5 0x1F0400D8,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_4 0x1F0400D8,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_3__ADDR                0x1F0400DC
+#define SRM_DP_GAMMA_C_ASYNC1_3__EMPTY               0x1F0400DC,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_3__FULL                0x1F0400DC,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_7 0x1F0400DC,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_6 0x1F0400DC,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_4__ADDR                0x1F0400E0
+#define SRM_DP_GAMMA_C_ASYNC1_4__EMPTY               0x1F0400E0,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_4__FULL                0x1F0400E0,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_9 0x1F0400E0,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_8 0x1F0400E0,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_5__ADDR                 0x1F0400E4
+#define SRM_DP_GAMMA_C_ASYNC1_5__EMPTY                0x1F0400E4,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_5__FULL                 0x1F0400E4,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_11 0x1F0400E4,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_10 0x1F0400E4,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_6__ADDR                 0x1F0400E8
+#define SRM_DP_GAMMA_C_ASYNC1_6__EMPTY                0x1F0400E8,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_6__FULL                 0x1F0400E8,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_13 0x1F0400E8,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_12 0x1F0400E8,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_7__ADDR                 0x1F0400EC
+#define SRM_DP_GAMMA_C_ASYNC1_7__EMPTY                0x1F0400EC,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_7__FULL                 0x1F0400EC,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_15 0x1F0400EC,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_14 0x1F0400EC,0x000001FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_0__ADDR                0x1F0400F0
+#define SRM_DP_GAMMA_S_ASYNC1_0__EMPTY               0x1F0400F0,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_0__FULL                0x1F0400F0,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_3 0x1F0400F0,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_2 0x1F0400F0,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_1 0x1F0400F0,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_0 0x1F0400F0,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_1__ADDR                0x1F0400F4
+#define SRM_DP_GAMMA_S_ASYNC1_1__EMPTY               0x1F0400F4,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_1__FULL                0x1F0400F4,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_7 0x1F0400F4,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_6 0x1F0400F4,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_5 0x1F0400F4,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_4 0x1F0400F4,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_2__ADDR                 0x1F0400F8
+#define SRM_DP_GAMMA_S_ASYNC1_2__EMPTY                0x1F0400F8,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_2__FULL                 0x1F0400F8,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_11 0x1F0400F8,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_10 0x1F0400F8,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_9  0x1F0400F8,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_8  0x1F0400F8,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_3__ADDR                 0x1F0400FC
+#define SRM_DP_GAMMA_S_ASYNC1_3__EMPTY                0x1F0400FC,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_3__FULL                 0x1F0400FC,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_15 0x1F0400FC,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_14 0x1F0400FC,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_13 0x1F0400FC,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_12 0x1F0400FC,0x000000FF
+
+#define SRM_DP_CSCA_ASYNC1_0__ADDR              0x1F040100
+#define SRM_DP_CSCA_ASYNC1_0__EMPTY             0x1F040100,0x00000000
+#define SRM_DP_CSCA_ASYNC1_0__FULL              0x1F040100,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_1 0x1F040100,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_0 0x1F040100,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC1_1__ADDR              0x1F040104
+#define SRM_DP_CSCA_ASYNC1_1__EMPTY             0x1F040104,0x00000000
+#define SRM_DP_CSCA_ASYNC1_1__FULL              0x1F040104,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_3 0x1F040104,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_2 0x1F040104,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC1_2__ADDR              0x1F040108
+#define SRM_DP_CSCA_ASYNC1_2__EMPTY             0x1F040108,0x00000000
+#define SRM_DP_CSCA_ASYNC1_2__FULL              0x1F040108,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_5 0x1F040108,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_4 0x1F040108,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC1_3__ADDR              0x1F04010C
+#define SRM_DP_CSCA_ASYNC1_3__EMPTY             0x1F04010C,0x00000000
+#define SRM_DP_CSCA_ASYNC1_3__FULL              0x1F04010C,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_7 0x1F04010C,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_6 0x1F04010C,0x000003FF
+
+#define SRM_DP_CSC_ASYNC1_0__ADDR             0x1F040110
+#define SRM_DP_CSC_ASYNC1_0__EMPTY            0x1F040110,0x00000000
+#define SRM_DP_CSC_ASYNC1_0__FULL             0x1F040110,0xffffffff
+#define SRM_DP_CSC_ASYNC1_0__DP_CSC_S0_ASYNC1 0x1F040110,0xC0000000
+#define SRM_DP_CSC_ASYNC1_0__DP_CSC_B0_ASYNC1 0x1F040110,0x3FFF0000
+#define SRM_DP_CSC_ASYNC1_0__DP_CSC_A8_ASYNC1 0x1F040110,0x000003FF
+
+#define SRM_DP_CSC_ASYNC1_1__ADDR             0x1F040114
+#define SRM_DP_CSC_ASYNC1_1__EMPTY            0x1F040114,0x00000000
+#define SRM_DP_CSC_ASYNC1_1__FULL             0x1F040114,0xffffffff
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S2_ASYNC1 0x1F040114,0xC0000000
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B2_ASYNC1 0x1F040114,0x3FFF0000
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S1_ASYNC1 0x1F040114,0x0000C000
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B1_ASYNC1 0x1F040114,0x00003FFF
+
+#define SRM_DI0_GENERAL__ADDR                   0x1F040448
+#define SRM_DI0_GENERAL__EMPTY       0x1F040448,0x00000000
+#define SRM_DI0_GENERAL__FULL       0x1F040448,0xffffffff
+#define SRM_DI0_GENERAL__DI0_DISP_Y_SEL       0x1F040448,0x70000000
+#define SRM_DI0_GENERAL__DI0_CLOCK_STOP_MODE       0x1F040448,0x0F000000
+#define SRM_DI0_GENERAL__DI0_DISP_CLOCK_INIT   0x1F040448,0x00800000
+#define SRM_DI0_GENERAL__DI0_MASK_SEL       0x1F040448,0x00400000
+#define SRM_DI0_GENERAL__DI0_VSYNC_EXT       0x1F040448,0x00200000
+#define SRM_DI0_GENERAL__DI0_CLK_EXT       0x1F040448,0x00100000
+#define SRM_DI0_GENERAL__DI0_WATCHDOG_MODE     0x1F040448,0x000C0000
+#define SRM_DI0_GENERAL__DI0_POLARITY_DISP_CLK       0x1F040448,0x00020000
+#define SRM_DI0_GENERAL__DI0_SYNC_COUNT_SEL       0x1F040448,0x0000F000
+#define SRM_DI0_GENERAL__DI0_ERR_TREATMENT       0x1F040448,0x00000800
+#define SRM_DI0_GENERAL__DI0_ERM_VSYNC_SEL     0x1F040448,0x00000400
+#define SRM_DI0_GENERAL__DI0_POLARITY_CS1       0x1F040448,0x00000200
+#define SRM_DI0_GENERAL__DI0_POLARITY_CS0       0x1F040448,0x00000100
+#define SRM_DI0_GENERAL__DI0_POLARITY_8       0x1F040448,0x00000080
+#define SRM_DI0_GENERAL__DI0_POLARITY_7       0x1F040448,0x00000040
+#define SRM_DI0_GENERAL__DI0_POLARITY_6       0x1F040448,0x00000020
+#define SRM_DI0_GENERAL__DI0_POLARITY_5       0x1F040448,0x00000010
+#define SRM_DI0_GENERAL__DI0_POLARITY_4       0x1F040448,0x00000008
+#define SRM_DI0_GENERAL__DI0_POLARITY_3       0x1F040448,0x00000004
+#define SRM_DI0_GENERAL__DI0_POLARITY_2       0x1F040448,0x00000002
+#define SRM_DI0_GENERAL__DI0_POLARITY_1       0x1F040448,0x00000001
+
+#define SRM_DI0_BS_CLKGEN0__ADDR                   0x1F04044C
+#define SRM_DI0_BS_CLKGEN0__EMPTY       0x1F04044C,0x00000000
+#define SRM_DI0_BS_CLKGEN0__FULL       0x1F04044C,0xffffffff
+#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET       0x1F04044C,0x01FF0000
+#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD       0x1F04044C,0x00000FFF
+
+#define SRM_DI0_BS_CLKGEN1__ADDR                   0x1F040450
+#define SRM_DI0_BS_CLKGEN1__EMPTY       0x1F040450,0x00000000
+#define SRM_DI0_BS_CLKGEN1__FULL       0x1F040450,0xffffffff
+#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN       0x1F040450,0x01FF0000
+#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP       0x1F040450,0x000001FF
+
+#define SRM_DI0_SW_GEN0_1__ADDR                   0x1F040454
+#define SRM_DI0_SW_GEN0_1__EMPTY       0x1F040454,0x00000000
+#define SRM_DI0_SW_GEN0_1__FULL       0x1F040454,0xffffffff
+#define SRM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1       0x1F040454,0x7FF80000
+#define SRM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1       0x1F040454,0x00070000
+#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1       0x1F040454,0x00007FF8
+#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1       0x1F040454,0x00000007
+
+#define SRM_DI0_SW_GEN0_2__ADDR                   0x1F040458
+#define SRM_DI0_SW_GEN0_2__EMPTY       0x1F040458,0x00000000
+#define SRM_DI0_SW_GEN0_2__FULL       0x1F040458,0xffffffff
+#define SRM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2       0x1F040458,0x7FF80000
+#define SRM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2       0x1F040458,0x00070000
+#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2       0x1F040458,0x00007FF8
+#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2       0x1F040458,0x00000007
+
+#define SRM_DI0_SW_GEN0_3__ADDR                   0x1F04045C
+#define SRM_DI0_SW_GEN0_3__EMPTY       0x1F04045C,0x00000000
+#define SRM_DI0_SW_GEN0_3__FULL       0x1F04045C,0xffffffff
+#define SRM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3       0x1F04045C,0x7FF80000
+#define SRM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3       0x1F04045C,0x00070000
+#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3       0x1F04045C,0x00007FF8
+#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3       0x1F04045C,0x00000007
+
+#define SRM_DI0_SW_GEN0_4__ADDR                   0x1F040460
+#define SRM_DI0_SW_GEN0_4__EMPTY       0x1F040460,0x00000000
+#define SRM_DI0_SW_GEN0_4__FULL       0x1F040460,0xffffffff
+#define SRM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4       0x1F040460,0x7FF80000
+#define SRM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4       0x1F040460,0x00070000
+#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4       0x1F040460,0x00007FF8
+#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4       0x1F040460,0x00000007
+
+#define SRM_DI0_SW_GEN0_5__ADDR                   0x1F040464
+#define SRM_DI0_SW_GEN0_5__EMPTY       0x1F040464,0x00000000
+#define SRM_DI0_SW_GEN0_5__FULL       0x1F040464,0xffffffff
+#define SRM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5       0x1F040464,0x7FF80000
+#define SRM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5       0x1F040464,0x00070000
+#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5       0x1F040464,0x00007FF8
+#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5       0x1F040464,0x00000007
+
+#define SRM_DI0_SW_GEN0_6__ADDR                   0x1F040468
+#define SRM_DI0_SW_GEN0_6__EMPTY       0x1F040468,0x00000000
+#define SRM_DI0_SW_GEN0_6__FULL       0x1F040468,0xffffffff
+#define SRM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6       0x1F040468,0x7FF80000
+#define SRM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6       0x1F040468,0x00070000
+#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6       0x1F040468,0x00007FF8
+#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6       0x1F040468,0x00000007
+
+#define SRM_DI0_SW_GEN0_7__ADDR                   0x1F04046C
+#define SRM_DI0_SW_GEN0_7__EMPTY       0x1F04046C,0x00000000
+#define SRM_DI0_SW_GEN0_7__FULL       0x1F04046C,0xffffffff
+#define SRM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7       0x1F04046C,0x7FF80000
+#define SRM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7       0x1F04046C,0x00070000
+#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7       0x1F04046C,0x00007FF8
+#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7       0x1F04046C,0x00000007
+
+#define SRM_DI0_SW_GEN0_8__ADDR                   0x1F040470
+#define SRM_DI0_SW_GEN0_8__EMPTY       0x1F040470,0x00000000
+#define SRM_DI0_SW_GEN0_8__FULL       0x1F040470,0xffffffff
+#define SRM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8       0x1F040470,0x7FF80000
+#define SRM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8       0x1F040470,0x00070000
+#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8       0x1F040470,0x00007FF8
+#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8       0x1F040470,0x00000007
+
+#define SRM_DI0_SW_GEN0_9__ADDR                   0x1F040474
+#define SRM_DI0_SW_GEN0_9__EMPTY       0x1F040474,0x00000000
+#define SRM_DI0_SW_GEN0_9__FULL       0x1F040474,0xffffffff
+#define SRM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9       0x1F040474,0x7FF80000
+#define SRM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9       0x1F040474,0x00070000
+#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9       0x1F040474,0x00007FF8
+#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9       0x1F040474,0x00000007
+
+#define SRM_DI0_SW_GEN1_1__ADDR                   0x1F040478
+#define SRM_DI0_SW_GEN1_1__EMPTY       0x1F040478,0x00000000
+#define SRM_DI0_SW_GEN1_1__FULL       0x1F040478,0xffffffff
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1       0x1F040478,0x60000000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1       0x1F040478,0x10000000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1       0x1F040478,0x0E000000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1       0x1F040478,0x01FF0000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1       0x1F040478,0x00007000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1       0x1F040478,0x00000E00
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_UP_1       0x1F040478,0x000001FF
+
+#define SRM_DI0_SW_GEN1_2__ADDR                   0x1F04047C
+#define SRM_DI0_SW_GEN1_2__EMPTY       0x1F04047C,0x00000000
+#define SRM_DI0_SW_GEN1_2__FULL       0x1F04047C,0xffffffff
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2       0x1F04047C,0x60000000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2       0x1F04047C,0x10000000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2       0x1F04047C,0x0E000000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2       0x1F04047C,0x01FF0000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2       0x1F04047C,0x00007000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2       0x1F04047C,0x00000E00
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_UP_2       0x1F04047C,0x000001FF
+
+#define SRM_DI0_SW_GEN1_3__ADDR                   0x1F040480
+#define SRM_DI0_SW_GEN1_3__EMPTY       0x1F040480,0x00000000
+#define SRM_DI0_SW_GEN1_3__FULL       0x1F040480,0xffffffff
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3       0x1F040480,0x60000000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3       0x1F040480,0x10000000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3       0x1F040480,0x0E000000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3       0x1F040480,0x01FF0000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3       0x1F040480,0x00007000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3       0x1F040480,0x00000E00
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_UP_3       0x1F040480,0x000001FF
+
+#define SRM_DI0_SW_GEN1_4__ADDR                   0x1F040484
+#define SRM_DI0_SW_GEN1_4__EMPTY       0x1F040484,0x00000000
+#define SRM_DI0_SW_GEN1_4__FULL       0x1F040484,0xffffffff
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4       0x1F040484,0x60000000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4       0x1F040484,0x10000000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4       0x1F040484,0x0E000000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4       0x1F040484,0x01FF0000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4       0x1F040484,0x00007000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4       0x1F040484,0x00000E00
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_UP_4       0x1F040484,0x000001FF
+
+#define SRM_DI0_SW_GEN1_5__ADDR                   0x1F040488
+#define SRM_DI0_SW_GEN1_5__EMPTY       0x1F040488,0x00000000
+#define SRM_DI0_SW_GEN1_5__FULL       0x1F040488,0xffffffff
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5       0x1F040488,0x60000000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5       0x1F040488,0x10000000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5       0x1F040488,0x0E000000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5       0x1F040488,0x01FF0000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5       0x1F040488,0x00007000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5       0x1F040488,0x00000E00
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_UP_5       0x1F040488,0x000001FF
+
+#define SRM_DI0_SW_GEN1_6__ADDR                   0x1F04048C
+#define SRM_DI0_SW_GEN1_6__EMPTY       0x1F04048C,0x00000000
+#define SRM_DI0_SW_GEN1_6__FULL       0x1F04048C,0xffffffff
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6       0x1F04048C,0x60000000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6       0x1F04048C,0x10000000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6       0x1F04048C,0x0E000000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6       0x1F04048C,0x01FF0000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6       0x1F04048C,0x00007000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6       0x1F04048C,0x00000E00
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_UP_6       0x1F04048C,0x000001FF
+
+#define SRM_DI0_SW_GEN1_7__ADDR                   0x1F040490
+#define SRM_DI0_SW_GEN1_7__EMPTY       0x1F040490,0x00000000
+#define SRM_DI0_SW_GEN1_7__FULL       0x1F040490,0xffffffff
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7       0x1F040490,0x60000000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7       0x1F040490,0x10000000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7       0x1F040490,0x0E000000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7       0x1F040490,0x01FF0000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7       0x1F040490,0x00007000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7       0x1F040490,0x00000E00
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_UP_7       0x1F040490,0x000001FF
+
+#define SRM_DI0_SW_GEN1_8__ADDR                   0x1F040494
+#define SRM_DI0_SW_GEN1_8__EMPTY       0x1F040494,0x00000000
+#define SRM_DI0_SW_GEN1_8__FULL       0x1F040494,0xffffffff
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8       0x1F040494,0x60000000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8       0x1F040494,0x10000000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8       0x1F040494,0x0E000000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8       0x1F040494,0x01FF0000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8       0x1F040494,0x00007000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8       0x1F040494,0x00000E00
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_UP_8       0x1F040494,0x000001FF
+
+#define SRM_DI0_SW_GEN1_9__ADDR                   0x1F040498
+#define SRM_DI0_SW_GEN1_9__EMPTY       0x1F040498,0x00000000
+#define SRM_DI0_SW_GEN1_9__FULL       0x1F040498,0xffffffff
+#define SRM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9       0x1F040498,0xE0000000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9       0x1F040498,0x10000000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9       0x1F040498,0x0E000000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9       0x1F040498,0x01FF0000
+#define SRM_DI0_SW_GEN1_9__DI0_TAG_SEL_9       0x1F040498,0x00008000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_UP_9       0x1F040498,0x000001FF
+
+#define SRM_DI0_SYNC_AS_GEN__ADDR                   0x1F04049C
+#define SRM_DI0_SYNC_AS_GEN__EMPTY       0x1F04049C,0x00000000
+#define SRM_DI0_SYNC_AS_GEN__FULL       0x1F04049C,0xffffffff
+#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN       0x1F04049C,0x10000000
+#define SRM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL       0x1F04049C,0x0000E000
+#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START       0x1F04049C,0x00000FFF
+
+#define SRM_DI0_DW_GEN_0__ADDR                  0x1F0404A0
+#define SRM_DI0_DW_GEN_0__EMPTY                 0x1F0404A0,0x00000000
+#define SRM_DI0_DW_GEN_0__FULL                  0x1F0404A0,0xffffffff
+#define SRM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0     0x1F0404A0,0xFF000000
+#define SRM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1F0404A0,0x00FF0000
+#define SRM_DI0_DW_GEN_0__DI0_CST_0             0x1F0404A0,0x0000C000
+#define SRM_DI0_DW_GEN_0__DI0_PT_6_0            0x1F0404A0,0x00003000
+#define SRM_DI0_DW_GEN_0__DI0_PT_5_0            0x1F0404A0,0x00000C00
+#define SRM_DI0_DW_GEN_0__DI0_PT_4_0            0x1F0404A0,0x00000300
+#define SRM_DI0_DW_GEN_0__DI0_PT_3_0            0x1F0404A0,0x000000C0
+#define SRM_DI0_DW_GEN_0__DI0_PT_2_0            0x1F0404A0,0x00000030
+#define SRM_DI0_DW_GEN_0__DI0_PT_1_0            0x1F0404A0,0x0000000C
+#define SRM_DI0_DW_GEN_0__DI0_PT_0_0            0x1F0404A0,0x00000003
+
+#define SRM_DI0_DW_GEN_0__ADDR                    0x1F0404A0
+#define SRM_DI0_DW_GEN_0__EMPTY                   0x1F0404A0,0x00000000
+#define SRM_DI0_DW_GEN_0__FULL                    0x1F0404A0,0xffffffff
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0     0x1F0404A0,0xFF000000
+#define SRM_DI0_DW_GEN_0__DI0_START_PERIOD_0      0x1F0404A0,0x00FF0000
+#define SRM_DI0_DW_GEN_0__DI0_CST_0               0x1F0404A0,0x0000C000
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1F0404A0,0x000001F0
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_RS_0         0x1F0404A0,0x0000000C
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0        0x1F0404A0,0x00000003
+
+#define SRM_DI0_DW_GEN_1__ADDR                  0x1F0404A4
+#define SRM_DI0_DW_GEN_1__EMPTY                 0x1F0404A4,0x00000000
+#define SRM_DI0_DW_GEN_1__FULL                  0x1F0404A4,0xffffffff
+#define SRM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1     0x1F0404A4,0xFF000000
+#define SRM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1F0404A4,0x00FF0000
+#define SRM_DI0_DW_GEN_1__DI0_CST_1             0x1F0404A4,0x0000C000
+#define SRM_DI0_DW_GEN_1__DI0_PT_6_1            0x1F0404A4,0x00003000
+#define SRM_DI0_DW_GEN_1__DI0_PT_5_1            0x1F0404A4,0x00000C00
+#define SRM_DI0_DW_GEN_1__DI0_PT_4_1            0x1F0404A4,0x00000300
+#define SRM_DI0_DW_GEN_1__DI0_PT_3_1            0x1F0404A4,0x000000C0
+#define SRM_DI0_DW_GEN_1__DI0_PT_2_1            0x1F0404A4,0x00000030
+#define SRM_DI0_DW_GEN_1__DI0_PT_1_1            0x1F0404A4,0x0000000C
+#define SRM_DI0_DW_GEN_1__DI0_PT_0_1            0x1F0404A4,0x00000003
+
+#define SRM_DI0_DW_GEN_1__ADDR                    0x1F0404A4
+#define SRM_DI0_DW_GEN_1__EMPTY                   0x1F0404A4,0x00000000
+#define SRM_DI0_DW_GEN_1__FULL                    0x1F0404A4,0xffffffff
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1     0x1F0404A4,0xFF000000
+#define SRM_DI0_DW_GEN_1__DI0_START_PERIOD_1      0x1F0404A4,0x00FF0000
+#define SRM_DI0_DW_GEN_1__DI0_CST_1               0x1F0404A4,0x0000C000
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1F0404A4,0x000001F0
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_RS_1         0x1F0404A4,0x0000000C
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1        0x1F0404A4,0x00000003
+
+#define SRM_DI0_DW_GEN_2__ADDR                  0x1F0404A8
+#define SRM_DI0_DW_GEN_2__EMPTY                 0x1F0404A8,0x00000000
+#define SRM_DI0_DW_GEN_2__FULL                  0x1F0404A8,0xffffffff
+#define SRM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2     0x1F0404A8,0xFF000000
+#define SRM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1F0404A8,0x00FF0000
+#define SRM_DI0_DW_GEN_2__DI0_CST_2             0x1F0404A8,0x0000C000
+#define SRM_DI0_DW_GEN_2__DI0_PT_6_2            0x1F0404A8,0x00003000
+#define SRM_DI0_DW_GEN_2__DI0_PT_5_2            0x1F0404A8,0x00000C00
+#define SRM_DI0_DW_GEN_2__DI0_PT_4_2            0x1F0404A8,0x00000300
+#define SRM_DI0_DW_GEN_2__DI0_PT_3_2            0x1F0404A8,0x000000C0
+#define SRM_DI0_DW_GEN_2__DI0_PT_2_2            0x1F0404A8,0x00000030
+#define SRM_DI0_DW_GEN_2__DI0_PT_1_2            0x1F0404A8,0x0000000C
+#define SRM_DI0_DW_GEN_2__DI0_PT_0_2            0x1F0404A8,0x00000003
+
+#define SRM_DI0_DW_GEN_2__ADDR                    0x1F0404A8
+#define SRM_DI0_DW_GEN_2__EMPTY                   0x1F0404A8,0x00000000
+#define SRM_DI0_DW_GEN_2__FULL                    0x1F0404A8,0xffffffff
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2     0x1F0404A8,0xFF000000
+#define SRM_DI0_DW_GEN_2__DI0_START_PERIOD_2      0x1F0404A8,0x00FF0000
+#define SRM_DI0_DW_GEN_2__DI0_CST_2               0x1F0404A8,0x0000C000
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1F0404A8,0x000001F0
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_RS_2         0x1F0404A8,0x0000000C
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2        0x1F0404A8,0x00000003
+
+#define SRM_DI0_DW_GEN_3__ADDR                  0x1F0404AC
+#define SRM_DI0_DW_GEN_3__EMPTY                 0x1F0404AC,0x00000000
+#define SRM_DI0_DW_GEN_3__FULL                  0x1F0404AC,0xffffffff
+#define SRM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3     0x1F0404AC,0xFF000000
+#define SRM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1F0404AC,0x00FF0000
+#define SRM_DI0_DW_GEN_3__DI0_CST_3             0x1F0404AC,0x0000C000
+#define SRM_DI0_DW_GEN_3__DI0_PT_6_3            0x1F0404AC,0x00003000
+#define SRM_DI0_DW_GEN_3__DI0_PT_5_3            0x1F0404AC,0x00000C00
+#define SRM_DI0_DW_GEN_3__DI0_PT_4_3            0x1F0404AC,0x00000300
+#define SRM_DI0_DW_GEN_3__DI0_PT_3_3            0x1F0404AC,0x000000C0
+#define SRM_DI0_DW_GEN_3__DI0_PT_2_3            0x1F0404AC,0x00000030
+#define SRM_DI0_DW_GEN_3__DI0_PT_1_3            0x1F0404AC,0x0000000C
+#define SRM_DI0_DW_GEN_3__DI0_PT_0_3            0x1F0404AC,0x00000003
+
+#define SRM_DI0_DW_GEN_3__ADDR                    0x1F0404AC
+#define SRM_DI0_DW_GEN_3__EMPTY                   0x1F0404AC,0x00000000
+#define SRM_DI0_DW_GEN_3__FULL                    0x1F0404AC,0xffffffff
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3     0x1F0404AC,0xFF000000
+#define SRM_DI0_DW_GEN_3__DI0_START_PERIOD_3      0x1F0404AC,0x00FF0000
+#define SRM_DI0_DW_GEN_3__DI0_CST_3               0x1F0404AC,0x0000C000
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1F0404AC,0x000001F0
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_RS_3         0x1F0404AC,0x0000000C
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3        0x1F0404AC,0x00000003
+
+#define SRM_DI0_DW_GEN_4__ADDR                  0x1F0404B0
+#define SRM_DI0_DW_GEN_4__EMPTY                 0x1F0404B0,0x00000000
+#define SRM_DI0_DW_GEN_4__FULL                  0x1F0404B0,0xffffffff
+#define SRM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4     0x1F0404B0,0xFF000000
+#define SRM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1F0404B0,0x00FF0000
+#define SRM_DI0_DW_GEN_4__DI0_CST_4             0x1F0404B0,0x0000C000
+#define SRM_DI0_DW_GEN_4__DI0_PT_6_4            0x1F0404B0,0x00003000
+#define SRM_DI0_DW_GEN_4__DI0_PT_5_4            0x1F0404B0,0x00000C00
+#define SRM_DI0_DW_GEN_4__DI0_PT_4_4            0x1F0404B0,0x00000300
+#define SRM_DI0_DW_GEN_4__DI0_PT_3_4            0x1F0404B0,0x000000C0
+#define SRM_DI0_DW_GEN_4__DI0_PT_2_4            0x1F0404B0,0x00000030
+#define SRM_DI0_DW_GEN_4__DI0_PT_1_4            0x1F0404B0,0x0000000C
+#define SRM_DI0_DW_GEN_4__DI0_PT_0_4            0x1F0404B0,0x00000003
+
+#define SRM_DI0_DW_GEN_4__ADDR                    0x1F0404B0
+#define SRM_DI0_DW_GEN_4__EMPTY                   0x1F0404B0,0x00000000
+#define SRM_DI0_DW_GEN_4__FULL                    0x1F0404B0,0xffffffff
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4     0x1F0404B0,0xFF000000
+#define SRM_DI0_DW_GEN_4__DI0_START_PERIOD_4      0x1F0404B0,0x00FF0000
+#define SRM_DI0_DW_GEN_4__DI0_CST_4               0x1F0404B0,0x0000C000
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1F0404B0,0x000001F0
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_RS_4         0x1F0404B0,0x0000000C
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4        0x1F0404B0,0x00000003
+
+#define SRM_DI0_DW_GEN_5__ADDR                  0x1F0404B4
+#define SRM_DI0_DW_GEN_5__EMPTY                 0x1F0404B4,0x00000000
+#define SRM_DI0_DW_GEN_5__FULL                  0x1F0404B4,0xffffffff
+#define SRM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5     0x1F0404B4,0xFF000000
+#define SRM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1F0404B4,0x00FF0000
+#define SRM_DI0_DW_GEN_5__DI0_CST_5             0x1F0404B4,0x0000C000
+#define SRM_DI0_DW_GEN_5__DI0_PT_6_5            0x1F0404B4,0x00003000
+#define SRM_DI0_DW_GEN_5__DI0_PT_5_5            0x1F0404B4,0x00000C00
+#define SRM_DI0_DW_GEN_5__DI0_PT_4_5            0x1F0404B4,0x00000300
+#define SRM_DI0_DW_GEN_5__DI0_PT_3_5            0x1F0404B4,0x000000C0
+#define SRM_DI0_DW_GEN_5__DI0_PT_2_5            0x1F0404B4,0x00000030
+#define SRM_DI0_DW_GEN_5__DI0_PT_1_5            0x1F0404B4,0x0000000C
+#define SRM_DI0_DW_GEN_5__DI0_PT_0_5            0x1F0404B4,0x00000003
+
+#define SRM_DI0_DW_GEN_5__ADDR                    0x1F0404B4
+#define SRM_DI0_DW_GEN_5__EMPTY                   0x1F0404B4,0x00000000
+#define SRM_DI0_DW_GEN_5__FULL                    0x1F0404B4,0xffffffff
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5     0x1F0404B4,0xFF000000
+#define SRM_DI0_DW_GEN_5__DI0_START_PERIOD_5      0x1F0404B4,0x00FF0000
+#define SRM_DI0_DW_GEN_5__DI0_CST_5               0x1F0404B4,0x0000C000
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1F0404B4,0x000001F0
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_RS_5         0x1F0404B4,0x0000000C
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5        0x1F0404B4,0x00000003
+
+#define SRM_DI0_DW_GEN_6__ADDR                  0x1F0404B8
+#define SRM_DI0_DW_GEN_6__EMPTY                 0x1F0404B8,0x00000000
+#define SRM_DI0_DW_GEN_6__FULL                  0x1F0404B8,0xffffffff
+#define SRM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6     0x1F0404B8,0xFF000000
+#define SRM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1F0404B8,0x00FF0000
+#define SRM_DI0_DW_GEN_6__DI0_CST_6             0x1F0404B8,0x0000C000
+#define SRM_DI0_DW_GEN_6__DI0_PT_6_6            0x1F0404B8,0x00003000
+#define SRM_DI0_DW_GEN_6__DI0_PT_5_6            0x1F0404B8,0x00000C00
+#define SRM_DI0_DW_GEN_6__DI0_PT_4_6            0x1F0404B8,0x00000300
+#define SRM_DI0_DW_GEN_6__DI0_PT_3_6            0x1F0404B8,0x000000C0
+#define SRM_DI0_DW_GEN_6__DI0_PT_2_6            0x1F0404B8,0x00000030
+#define SRM_DI0_DW_GEN_6__DI0_PT_1_6            0x1F0404B8,0x0000000C
+#define SRM_DI0_DW_GEN_6__DI0_PT_0_6            0x1F0404B8,0x00000003
+
+#define SRM_DI0_DW_GEN_6__ADDR                    0x1F0404B8
+#define SRM_DI0_DW_GEN_6__EMPTY                   0x1F0404B8,0x00000000
+#define SRM_DI0_DW_GEN_6__FULL                    0x1F0404B8,0xffffffff
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6     0x1F0404B8,0xFF000000
+#define SRM_DI0_DW_GEN_6__DI0_START_PERIOD_6      0x1F0404B8,0x00FF0000
+#define SRM_DI0_DW_GEN_6__DI0_CST_6               0x1F0404B8,0x0000C000
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1F0404B8,0x000001F0
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_RS_6         0x1F0404B8,0x0000000C
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6        0x1F0404B8,0x00000003
+
+#define SRM_DI0_DW_GEN_7__ADDR                  0x1F0404BC
+#define SRM_DI0_DW_GEN_7__EMPTY                 0x1F0404BC,0x00000000
+#define SRM_DI0_DW_GEN_7__FULL                  0x1F0404BC,0xffffffff
+#define SRM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7     0x1F0404BC,0xFF000000
+#define SRM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1F0404BC,0x00FF0000
+#define SRM_DI0_DW_GEN_7__DI0_CST_7             0x1F0404BC,0x0000C000
+#define SRM_DI0_DW_GEN_7__DI0_PT_6_7            0x1F0404BC,0x00003000
+#define SRM_DI0_DW_GEN_7__DI0_PT_5_7            0x1F0404BC,0x00000C00
+#define SRM_DI0_DW_GEN_7__DI0_PT_4_7            0x1F0404BC,0x00000300
+#define SRM_DI0_DW_GEN_7__DI0_PT_3_7            0x1F0404BC,0x000000C0
+#define SRM_DI0_DW_GEN_7__DI0_PT_2_7            0x1F0404BC,0x00000030
+#define SRM_DI0_DW_GEN_7__DI0_PT_1_7            0x1F0404BC,0x0000000C
+#define SRM_DI0_DW_GEN_7__DI0_PT_0_7            0x1F0404BC,0x00000003
+
+#define SRM_DI0_DW_GEN_7__ADDR                    0x1F0404BC
+#define SRM_DI0_DW_GEN_7__EMPTY                   0x1F0404BC,0x00000000
+#define SRM_DI0_DW_GEN_7__FULL                    0x1F0404BC,0xffffffff
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7     0x1F0404BC,0xFF000000
+#define SRM_DI0_DW_GEN_7__DI0_START_PERIOD_7      0x1F0404BC,0x00FF0000
+#define SRM_DI0_DW_GEN_7__DI0_CST_7               0x1F0404BC,0x0000C000
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1F0404BC,0x000001F0
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_RS_7         0x1F0404BC,0x0000000C
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7        0x1F0404BC,0x00000003
+
+#define SRM_DI0_DW_GEN_8__ADDR                  0x1F0404C0
+#define SRM_DI0_DW_GEN_8__EMPTY                 0x1F0404C0,0x00000000
+#define SRM_DI0_DW_GEN_8__FULL                  0x1F0404C0,0xffffffff
+#define SRM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8     0x1F0404C0,0xFF000000
+#define SRM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1F0404C0,0x00FF0000
+#define SRM_DI0_DW_GEN_8__DI0_CST_8             0x1F0404C0,0x0000C000
+#define SRM_DI0_DW_GEN_8__DI0_PT_6_8            0x1F0404C0,0x00003000
+#define SRM_DI0_DW_GEN_8__DI0_PT_5_8            0x1F0404C0,0x00000C00
+#define SRM_DI0_DW_GEN_8__DI0_PT_4_8            0x1F0404C0,0x00000300
+#define SRM_DI0_DW_GEN_8__DI0_PT_3_8            0x1F0404C0,0x000000C0
+#define SRM_DI0_DW_GEN_8__DI0_PT_2_8            0x1F0404C0,0x00000030
+#define SRM_DI0_DW_GEN_8__DI0_PT_1_8            0x1F0404C0,0x0000000C
+#define SRM_DI0_DW_GEN_8__DI0_PT_0_8            0x1F0404C0,0x00000003
+
+#define SRM_DI0_DW_GEN_8__ADDR                    0x1F0404C0
+#define SRM_DI0_DW_GEN_8__EMPTY                   0x1F0404C0,0x00000000
+#define SRM_DI0_DW_GEN_8__FULL                    0x1F0404C0,0xffffffff
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8     0x1F0404C0,0xFF000000
+#define SRM_DI0_DW_GEN_8__DI0_START_PERIOD_8      0x1F0404C0,0x00FF0000
+#define SRM_DI0_DW_GEN_8__DI0_CST_8               0x1F0404C0,0x0000C000
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1F0404C0,0x000001F0
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_RS_8         0x1F0404C0,0x0000000C
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8        0x1F0404C0,0x00000003
+
+#define SRM_DI0_DW_GEN_9__ADDR                  0x1F0404C4
+#define SRM_DI0_DW_GEN_9__EMPTY                 0x1F0404C4,0x00000000
+#define SRM_DI0_DW_GEN_9__FULL                  0x1F0404C4,0xffffffff
+#define SRM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9     0x1F0404C4,0xFF000000
+#define SRM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1F0404C4,0x00FF0000
+#define SRM_DI0_DW_GEN_9__DI0_CST_9             0x1F0404C4,0x0000C000
+#define SRM_DI0_DW_GEN_9__DI0_PT_6_9            0x1F0404C4,0x00003000
+#define SRM_DI0_DW_GEN_9__DI0_PT_5_9            0x1F0404C4,0x00000C00
+#define SRM_DI0_DW_GEN_9__DI0_PT_4_9            0x1F0404C4,0x00000300
+#define SRM_DI0_DW_GEN_9__DI0_PT_3_9            0x1F0404C4,0x000000C0
+#define SRM_DI0_DW_GEN_9__DI0_PT_2_9            0x1F0404C4,0x00000030
+#define SRM_DI0_DW_GEN_9__DI0_PT_1_9            0x1F0404C4,0x0000000C
+#define SRM_DI0_DW_GEN_9__DI0_PT_0_9            0x1F0404C4,0x00000003
+
+#define SRM_DI0_DW_GEN_9__ADDR                    0x1F0404C4
+#define SRM_DI0_DW_GEN_9__EMPTY                   0x1F0404C4,0x00000000
+#define SRM_DI0_DW_GEN_9__FULL                    0x1F0404C4,0xffffffff
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9     0x1F0404C4,0xFF000000
+#define SRM_DI0_DW_GEN_9__DI0_START_PERIOD_9      0x1F0404C4,0x00FF0000
+#define SRM_DI0_DW_GEN_9__DI0_CST_9               0x1F0404C4,0x0000C000
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1F0404C4,0x000001F0
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_RS_9         0x1F0404C4,0x0000000C
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9        0x1F0404C4,0x00000003
+
+#define SRM_DI0_DW_GEN_10__ADDR                   0x1F0404C8
+#define SRM_DI0_DW_GEN_10__EMPTY                  0x1F0404C8,0x00000000
+#define SRM_DI0_DW_GEN_10__FULL                   0x1F0404C8,0xffffffff
+#define SRM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10     0x1F0404C8,0xFF000000
+#define SRM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1F0404C8,0x00FF0000
+#define SRM_DI0_DW_GEN_10__DI0_CST_10             0x1F0404C8,0x0000C000
+#define SRM_DI0_DW_GEN_10__DI0_PT_6_10            0x1F0404C8,0x00003000
+#define SRM_DI0_DW_GEN_10__DI0_PT_5_10            0x1F0404C8,0x00000C00
+#define SRM_DI0_DW_GEN_10__DI0_PT_4_10            0x1F0404C8,0x00000300
+#define SRM_DI0_DW_GEN_10__DI0_PT_3_10            0x1F0404C8,0x000000C0
+#define SRM_DI0_DW_GEN_10__DI0_PT_2_10            0x1F0404C8,0x00000030
+#define SRM_DI0_DW_GEN_10__DI0_PT_1_10            0x1F0404C8,0x0000000C
+#define SRM_DI0_DW_GEN_10__DI0_PT_0_10            0x1F0404C8,0x00000003
+
+#define SRM_DI0_DW_GEN_10__ADDR                     0x1F0404C8
+#define SRM_DI0_DW_GEN_10__EMPTY                    0x1F0404C8,0x00000000
+#define SRM_DI0_DW_GEN_10__FULL                     0x1F0404C8,0xffffffff
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10     0x1F0404C8,0xFF000000
+#define SRM_DI0_DW_GEN_10__DI0_START_PERIOD_10      0x1F0404C8,0x00FF0000
+#define SRM_DI0_DW_GEN_10__DI0_CST_10               0x1F0404C8,0x0000C000
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F0404C8,0x000001F0
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_RS_10         0x1F0404C8,0x0000000C
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10        0x1F0404C8,0x00000003
+
+#define SRM_DI0_DW_GEN_11__ADDR                   0x1F0404CC
+#define SRM_DI0_DW_GEN_11__EMPTY                  0x1F0404CC,0x00000000
+#define SRM_DI0_DW_GEN_11__FULL                   0x1F0404CC,0xffffffff
+#define SRM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11     0x1F0404CC,0xFF000000
+#define SRM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1F0404CC,0x00FF0000
+#define SRM_DI0_DW_GEN_11__DI0_CST_11             0x1F0404CC,0x0000C000
+#define SRM_DI0_DW_GEN_11__DI0_PT_6_11            0x1F0404CC,0x00003000
+#define SRM_DI0_DW_GEN_11__DI0_PT_5_11            0x1F0404CC,0x00000C00
+#define SRM_DI0_DW_GEN_11__DI0_PT_4_11            0x1F0404CC,0x00000300
+#define SRM_DI0_DW_GEN_11__DI0_PT_3_11            0x1F0404CC,0x000000C0
+#define SRM_DI0_DW_GEN_11__DI0_PT_2_11            0x1F0404CC,0x00000030
+#define SRM_DI0_DW_GEN_11__DI0_PT_1_11            0x1F0404CC,0x0000000C
+#define SRM_DI0_DW_GEN_11__DI0_PT_0_11            0x1F0404CC,0x00000003
+
+#define SRM_DI0_DW_GEN_11__ADDR                     0x1F0404CC
+#define SRM_DI0_DW_GEN_11__EMPTY                    0x1F0404CC,0x00000000
+#define SRM_DI0_DW_GEN_11__FULL                     0x1F0404CC,0xffffffff
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11     0x1F0404CC,0xFF000000
+#define SRM_DI0_DW_GEN_11__DI0_START_PERIOD_11      0x1F0404CC,0x00FF0000
+#define SRM_DI0_DW_GEN_11__DI0_CST_11               0x1F0404CC,0x0000C000
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F0404CC,0x000001F0
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_RS_11         0x1F0404CC,0x0000000C
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11        0x1F0404CC,0x00000003
+
+#define SRM_DI0_DW_SET0_0__ADDR                   0x1F0404D0
+#define SRM_DI0_DW_SET0_0__EMPTY       0x1F0404D0,0x00000000
+#define SRM_DI0_DW_SET0_0__FULL       0x1F0404D0,0xffffffff
+#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0       0x1F0404D0,0x01FF0000
+#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0       0x1F0404D0,0x000001FF
+
+#define SRM_DI0_DW_SET0_1__ADDR                   0x1F0404D4
+#define SRM_DI0_DW_SET0_1__EMPTY       0x1F0404D4,0x00000000
+#define SRM_DI0_DW_SET0_1__FULL       0x1F0404D4,0xffffffff
+#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1       0x1F0404D4,0x01FF0000
+#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1       0x1F0404D4,0x000001FF
+
+#define SRM_DI0_DW_SET0_2__ADDR                   0x1F0404D8
+#define SRM_DI0_DW_SET0_2__EMPTY       0x1F0404D8,0x00000000
+#define SRM_DI0_DW_SET0_2__FULL       0x1F0404D8,0xffffffff
+#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2       0x1F0404D8,0x01FF0000
+#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2       0x1F0404D8,0x000001FF
+
+#define SRM_DI0_DW_SET0_3__ADDR                   0x1F0404DC
+#define SRM_DI0_DW_SET0_3__EMPTY       0x1F0404DC,0x00000000
+#define SRM_DI0_DW_SET0_3__FULL       0x1F0404DC,0xffffffff
+#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3       0x1F0404DC,0x01FF0000
+#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3       0x1F0404DC,0x000001FF
+
+#define SRM_DI0_DW_SET0_4__ADDR                   0x1F0404E0
+#define SRM_DI0_DW_SET0_4__EMPTY       0x1F0404E0,0x00000000
+#define SRM_DI0_DW_SET0_4__FULL       0x1F0404E0,0xffffffff
+#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4       0x1F0404E0,0x01FF0000
+#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4       0x1F0404E0,0x000001FF
+
+#define SRM_DI0_DW_SET0_5__ADDR                   0x1F0404E4
+#define SRM_DI0_DW_SET0_5__EMPTY       0x1F0404E4,0x00000000
+#define SRM_DI0_DW_SET0_5__FULL       0x1F0404E4,0xffffffff
+#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5       0x1F0404E4,0x01FF0000
+#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5       0x1F0404E4,0x000001FF
+
+#define SRM_DI0_DW_SET0_6__ADDR                   0x1F0404E8
+#define SRM_DI0_DW_SET0_6__EMPTY       0x1F0404E8,0x00000000
+#define SRM_DI0_DW_SET0_6__FULL       0x1F0404E8,0xffffffff
+#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6       0x1F0404E8,0x01FF0000
+#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6       0x1F0404E8,0x000001FF
+
+#define SRM_DI0_DW_SET0_7__ADDR                   0x1F0404EC
+#define SRM_DI0_DW_SET0_7__EMPTY       0x1F0404EC,0x00000000
+#define SRM_DI0_DW_SET0_7__FULL       0x1F0404EC,0xffffffff
+#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7       0x1F0404EC,0x01FF0000
+#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7       0x1F0404EC,0x000001FF
+
+#define SRM_DI0_DW_SET0_8__ADDR                   0x1F0404F0
+#define SRM_DI0_DW_SET0_8__EMPTY       0x1F0404F0,0x00000000
+#define SRM_DI0_DW_SET0_8__FULL       0x1F0404F0,0xffffffff
+#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8       0x1F0404F0,0x01FF0000
+#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8       0x1F0404F0,0x000001FF
+
+#define SRM_DI0_DW_SET0_9__ADDR                   0x1F0404F4
+#define SRM_DI0_DW_SET0_9__EMPTY       0x1F0404F4,0x00000000
+#define SRM_DI0_DW_SET0_9__FULL       0x1F0404F4,0xffffffff
+#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9       0x1F0404F4,0x01FF0000
+#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9       0x1F0404F4,0x000001FF
+
+#define SRM_DI0_DW_SET0_10__ADDR                   0x1F0404F8
+#define SRM_DI0_DW_SET0_10__EMPTY       0x1F0404F8,0x00000000
+#define SRM_DI0_DW_SET0_10__FULL       0x1F0404F8,0xffffffff
+#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10       0x1F0404F8,0x01FF0000
+#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10       0x1F0404F8,0x000001FF
+
+#define SRM_DI0_DW_SET0_11__ADDR                   0x1F0404FC
+#define SRM_DI0_DW_SET0_11__EMPTY       0x1F0404FC,0x00000000
+#define SRM_DI0_DW_SET0_11__FULL       0x1F0404FC,0xffffffff
+#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11       0x1F0404FC,0x01FF0000
+#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11       0x1F0404FC,0x000001FF
+
+#define SRM_DI0_DW_SET1_0__ADDR                   0x1F040500
+#define SRM_DI0_DW_SET1_0__EMPTY       0x1F040500,0x00000000
+#define SRM_DI0_DW_SET1_0__FULL       0x1F040500,0xffffffff
+#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0       0x1F040500,0x01FF0000
+#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0       0x1F040500,0x000001FF
+
+#define SRM_DI0_DW_SET1_1__ADDR                   0x1F040504
+#define SRM_DI0_DW_SET1_1__EMPTY       0x1F040504,0x00000000
+#define SRM_DI0_DW_SET1_1__FULL       0x1F040504,0xffffffff
+#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1       0x1F040504,0x01FF0000
+#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1       0x1F040504,0x000001FF
+
+#define SRM_DI0_DW_SET1_2__ADDR                   0x1F040508
+#define SRM_DI0_DW_SET1_2__EMPTY       0x1F040508,0x00000000
+#define SRM_DI0_DW_SET1_2__FULL       0x1F040508,0xffffffff
+#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2       0x1F040508,0x01FF0000
+#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2       0x1F040508,0x000001FF
+
+#define SRM_DI0_DW_SET1_3__ADDR                   0x1F04050C
+#define SRM_DI0_DW_SET1_3__EMPTY       0x1F04050C,0x00000000
+#define SRM_DI0_DW_SET1_3__FULL       0x1F04050C,0xffffffff
+#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3       0x1F04050C,0x01FF0000
+#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3       0x1F04050C,0x000001FF
+
+#define SRM_DI0_DW_SET1_4__ADDR                   0x1F040510
+#define SRM_DI0_DW_SET1_4__EMPTY       0x1F040510,0x00000000
+#define SRM_DI0_DW_SET1_4__FULL       0x1F040510,0xffffffff
+#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4       0x1F040510,0x01FF0000
+#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4       0x1F040510,0x000001FF
+
+#define SRM_DI0_DW_SET1_5__ADDR                   0x1F040514
+#define SRM_DI0_DW_SET1_5__EMPTY       0x1F040514,0x00000000
+#define SRM_DI0_DW_SET1_5__FULL       0x1F040514,0xffffffff
+#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5       0x1F040514,0x01FF0000
+#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5       0x1F040514,0x000001FF
+
+#define SRM_DI0_DW_SET1_6__ADDR                   0x1F040518
+#define SRM_DI0_DW_SET1_6__EMPTY       0x1F040518,0x00000000
+#define SRM_DI0_DW_SET1_6__FULL       0x1F040518,0xffffffff
+#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6       0x1F040518,0x01FF0000
+#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6       0x1F040518,0x000001FF
+
+#define SRM_DI0_DW_SET1_7__ADDR                   0x1F04051C
+#define SRM_DI0_DW_SET1_7__EMPTY       0x1F04051C,0x00000000
+#define SRM_DI0_DW_SET1_7__FULL       0x1F04051C,0xffffffff
+#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7       0x1F04051C,0x01FF0000
+#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7       0x1F04051C,0x000001FF
+
+#define SRM_DI0_DW_SET1_8__ADDR                   0x1F040520
+#define SRM_DI0_DW_SET1_8__EMPTY       0x1F040520,0x00000000
+#define SRM_DI0_DW_SET1_8__FULL       0x1F040520,0xffffffff
+#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8       0x1F040520,0x01FF0000
+#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8       0x1F040520,0x000001FF
+
+#define SRM_DI0_DW_SET1_9__ADDR                   0x1F040524
+#define SRM_DI0_DW_SET1_9__EMPTY       0x1F040524,0x00000000
+#define SRM_DI0_DW_SET1_9__FULL       0x1F040524,0xffffffff
+#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9       0x1F040524,0x01FF0000
+#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9       0x1F040524,0x000001FF
+
+#define SRM_DI0_DW_SET1_10__ADDR                   0x1F040528
+#define SRM_DI0_DW_SET1_10__EMPTY       0x1F040528,0x00000000
+#define SRM_DI0_DW_SET1_10__FULL       0x1F040528,0xffffffff
+#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10       0x1F040528,0x01FF0000
+#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10       0x1F040528,0x000001FF
+
+#define SRM_DI0_DW_SET1_11__ADDR                   0x1F04052C
+#define SRM_DI0_DW_SET1_11__EMPTY       0x1F04052C,0x00000000
+#define SRM_DI0_DW_SET1_11__FULL       0x1F04052C,0xffffffff
+#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11       0x1F04052C,0x01FF0000
+#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11       0x1F04052C,0x000001FF
+
+#define SRM_DI0_DW_SET2_0__ADDR                   0x1F040530
+#define SRM_DI0_DW_SET2_0__EMPTY       0x1F040530,0x00000000
+#define SRM_DI0_DW_SET2_0__FULL       0x1F040530,0xffffffff
+#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0       0x1F040530,0x01FF0000
+#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0       0x1F040530,0x000001FF
+
+#define SRM_DI0_DW_SET2_1__ADDR                   0x1F040534
+#define SRM_DI0_DW_SET2_1__EMPTY       0x1F040534,0x00000000
+#define SRM_DI0_DW_SET2_1__FULL       0x1F040534,0xffffffff
+#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1       0x1F040534,0x01FF0000
+#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1       0x1F040534,0x000001FF
+
+#define SRM_DI0_DW_SET2_2__ADDR                   0x1F040538
+#define SRM_DI0_DW_SET2_2__EMPTY       0x1F040538,0x00000000
+#define SRM_DI0_DW_SET2_2__FULL       0x1F040538,0xffffffff
+#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2       0x1F040538,0x01FF0000
+#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2       0x1F040538,0x000001FF
+
+#define SRM_DI0_DW_SET2_3__ADDR                   0x1F04053C
+#define SRM_DI0_DW_SET2_3__EMPTY       0x1F04053C,0x00000000
+#define SRM_DI0_DW_SET2_3__FULL       0x1F04053C,0xffffffff
+#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3       0x1F04053C,0x01FF0000
+#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3       0x1F04053C,0x000001FF
+
+#define SRM_DI0_DW_SET2_4__ADDR                   0x1F040540
+#define SRM_DI0_DW_SET2_4__EMPTY       0x1F040540,0x00000000
+#define SRM_DI0_DW_SET2_4__FULL       0x1F040540,0xffffffff
+#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4       0x1F040540,0x01FF0000
+#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4       0x1F040540,0x000001FF
+
+#define SRM_DI0_DW_SET2_5__ADDR                   0x1F040544
+#define SRM_DI0_DW_SET2_5__EMPTY       0x1F040544,0x00000000
+#define SRM_DI0_DW_SET2_5__FULL       0x1F040544,0xffffffff
+#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5       0x1F040544,0x01FF0000
+#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5       0x1F040544,0x000001FF
+
+#define SRM_DI0_DW_SET2_6__ADDR                   0x1F040548
+#define SRM_DI0_DW_SET2_6__EMPTY       0x1F040548,0x00000000
+#define SRM_DI0_DW_SET2_6__FULL       0x1F040548,0xffffffff
+#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6       0x1F040548,0x01FF0000
+#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6       0x1F040548,0x000001FF
+
+#define SRM_DI0_DW_SET2_7__ADDR                   0x1F04054C
+#define SRM_DI0_DW_SET2_7__EMPTY       0x1F04054C,0x00000000
+#define SRM_DI0_DW_SET2_7__FULL       0x1F04054C,0xffffffff
+#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7       0x1F04054C,0x01FF0000
+#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7       0x1F04054C,0x000001FF
+
+#define SRM_DI0_DW_SET2_8__ADDR                   0x1F040550
+#define SRM_DI0_DW_SET2_8__EMPTY       0x1F040550,0x00000000
+#define SRM_DI0_DW_SET2_8__FULL       0x1F040550,0xffffffff
+#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8       0x1F040550,0x01FF0000
+#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8       0x1F040550,0x000001FF
+
+#define SRM_DI0_DW_SET2_9__ADDR                   0x1F040554
+#define SRM_DI0_DW_SET2_9__EMPTY       0x1F040554,0x00000000
+#define SRM_DI0_DW_SET2_9__FULL       0x1F040554,0xffffffff
+#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9       0x1F040554,0x01FF0000
+#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9       0x1F040554,0x000001FF
+
+#define SRM_DI0_DW_SET2_10__ADDR                   0x1F040558
+#define SRM_DI0_DW_SET2_10__EMPTY       0x1F040558,0x00000000
+#define SRM_DI0_DW_SET2_10__FULL       0x1F040558,0xffffffff
+#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10       0x1F040558,0x01FF0000
+#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10       0x1F040558,0x000001FF
+
+#define SRM_DI0_DW_SET2_11__ADDR                   0x1F04055C
+#define SRM_DI0_DW_SET2_11__EMPTY       0x1F04055C,0x00000000
+#define SRM_DI0_DW_SET2_11__FULL       0x1F04055C,0xffffffff
+#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11       0x1F04055C,0x01FF0000
+#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11       0x1F04055C,0x000001FF
+
+#define SRM_DI0_DW_SET3_0__ADDR                   0x1F040560
+#define SRM_DI0_DW_SET3_0__EMPTY       0x1F040560,0x00000000
+#define SRM_DI0_DW_SET3_0__FULL       0x1F040560,0xffffffff
+#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0       0x1F040560,0x01FF0000
+#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0       0x1F040560,0x000001FF
+
+#define SRM_DI0_DW_SET3_1__ADDR                   0x1F040564
+#define SRM_DI0_DW_SET3_1__EMPTY       0x1F040564,0x00000000
+#define SRM_DI0_DW_SET3_1__FULL       0x1F040564,0xffffffff
+#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1       0x1F040564,0x01FF0000
+#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1       0x1F040564,0x000001FF
+
+#define SRM_DI0_DW_SET3_2__ADDR                   0x1F040568
+#define SRM_DI0_DW_SET3_2__EMPTY       0x1F040568,0x00000000
+#define SRM_DI0_DW_SET3_2__FULL       0x1F040568,0xffffffff
+#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2       0x1F040568,0x01FF0000
+#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2       0x1F040568,0x000001FF
+
+#define SRM_DI0_DW_SET3_3__ADDR                   0x1F04056C
+#define SRM_DI0_DW_SET3_3__EMPTY       0x1F04056C,0x00000000
+#define SRM_DI0_DW_SET3_3__FULL       0x1F04056C,0xffffffff
+#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3       0x1F04056C,0x01FF0000
+#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3       0x1F04056C,0x000001FF
+
+#define SRM_DI0_DW_SET3_4__ADDR                   0x1F040570
+#define SRM_DI0_DW_SET3_4__EMPTY       0x1F040570,0x00000000
+#define SRM_DI0_DW_SET3_4__FULL       0x1F040570,0xffffffff
+#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4       0x1F040570,0x01FF0000
+#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4       0x1F040570,0x000001FF
+
+#define SRM_DI0_DW_SET3_5__ADDR                   0x1F040574
+#define SRM_DI0_DW_SET3_5__EMPTY       0x1F040574,0x00000000
+#define SRM_DI0_DW_SET3_5__FULL       0x1F040574,0xffffffff
+#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5       0x1F040574,0x01FF0000
+#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5       0x1F040574,0x000001FF
+
+#define SRM_DI0_DW_SET3_6__ADDR                   0x1F040578
+#define SRM_DI0_DW_SET3_6__EMPTY       0x1F040578,0x00000000
+#define SRM_DI0_DW_SET3_6__FULL       0x1F040578,0xffffffff
+#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6       0x1F040578,0x01FF0000
+#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6       0x1F040578,0x000001FF
+
+#define SRM_DI0_DW_SET3_7__ADDR                   0x1F04057C
+#define SRM_DI0_DW_SET3_7__EMPTY       0x1F04057C,0x00000000
+#define SRM_DI0_DW_SET3_7__FULL       0x1F04057C,0xffffffff
+#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7       0x1F04057C,0x01FF0000
+#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7       0x1F04057C,0x000001FF
+
+#define SRM_DI0_DW_SET3_8__ADDR                   0x1F040580
+#define SRM_DI0_DW_SET3_8__EMPTY       0x1F040580,0x00000000
+#define SRM_DI0_DW_SET3_8__FULL       0x1F040580,0xffffffff
+#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8       0x1F040580,0x01FF0000
+#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8       0x1F040580,0x000001FF
+
+#define SRM_DI0_DW_SET3_9__ADDR                   0x1F040584
+#define SRM_DI0_DW_SET3_9__EMPTY       0x1F040584,0x00000000
+#define SRM_DI0_DW_SET3_9__FULL       0x1F040584,0xffffffff
+#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9       0x1F040584,0x01FF0000
+#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9       0x1F040584,0x000001FF
+
+#define SRM_DI0_DW_SET3_10__ADDR                   0x1F040588
+#define SRM_DI0_DW_SET3_10__EMPTY       0x1F040588,0x00000000
+#define SRM_DI0_DW_SET3_10__FULL       0x1F040588,0xffffffff
+#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10       0x1F040588,0x01FF0000
+#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10       0x1F040588,0x000001FF
+
+#define SRM_DI0_DW_SET3_11__ADDR                   0x1F04058C
+#define SRM_DI0_DW_SET3_11__EMPTY       0x1F04058C,0x00000000
+#define SRM_DI0_DW_SET3_11__FULL       0x1F04058C,0xffffffff
+#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11       0x1F04058C,0x01FF0000
+#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11       0x1F04058C,0x000001FF
+
+#define SRM_DI0_STP_REP_1__ADDR                   0x1F040590
+#define SRM_DI0_STP_REP_1__EMPTY       0x1F040590,0x00000000
+#define SRM_DI0_STP_REP_1__FULL       0x1F040590,0xffffffff
+#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_2       0x1F040590,0x0FFF0000
+#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_1       0x1F040590,0x00000FFF
+
+#define SRM_DI0_STP_REP_2__ADDR                   0x1F040594
+#define SRM_DI0_STP_REP_2__EMPTY       0x1F040594,0x00000000
+#define SRM_DI0_STP_REP_2__FULL       0x1F040594,0xffffffff
+#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_4       0x1F040594,0x0FFF0000
+#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_3       0x1F040594,0x00000FFF
+
+#define SRM_DI0_STP_REP_3__ADDR                   0x1F040598
+#define SRM_DI0_STP_REP_3__EMPTY       0x1F040598,0x00000000
+#define SRM_DI0_STP_REP_3__FULL       0x1F040598,0xffffffff
+#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_6       0x1F040598,0x0FFF0000
+#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_5       0x1F040598,0x00000FFF
+
+#define SRM_DI0_STP_REP_4__ADDR                   0x1F04059C
+#define SRM_DI0_STP_REP_4__EMPTY       0x1F04059C,0x00000000
+#define SRM_DI0_STP_REP_4__FULL       0x1F04059C,0xffffffff
+#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_8       0x1F04059C,0x0FFF0000
+#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_7       0x1F04059C,0x00000FFF
+
+#define SRM_DI0_STP_REP_9__ADDR                   0x1F0405A0
+#define SRM_DI0_STP_REP_9__EMPTY       0x1F0405A0,0x00000000
+#define SRM_DI0_STP_REP_9__FULL       0x1F0405A0,0xffffffff
+#define SRM_DI0_STP_REP_9__DI0_STEP_REPEAT_9       0x1F0405A0,0x00000FFF
+
+#define SRM_DI0_SER_CONF__ADDR                   0x1F0405A4
+#define SRM_DI0_SER_CONF__EMPTY       0x1F0405A4,0x00000000
+#define SRM_DI0_SER_CONF__FULL       0x1F0405A4,0xffffffff
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1       0x1F0405A4,0xF0000000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0       0x1F0405A4,0x0F000000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1       0x1F0405A4,0x00F00000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0       0x1F0405A4,0x000F0000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LATCH       0x1F0405A4,0x0000FF00
+#define SRM_DI0_SER_CONF__DI0_LLA_SER_ACCESS       0x1F0405A4,0x00000020
+#define SRM_DI0_SER_CONF__DI0_SER_CLK_POLARITY       0x1F0405A4,0x00000010
+#define SRM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY       0x1F0405A4,0x00000008
+#define SRM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY       0x1F0405A4,0x00000004
+#define SRM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY       0x1F0405A4,0x00000002
+#define SRM_DI0_SER_CONF__DI0_WAIT4SERIAL       0x1F0405A4,0x00000001
+
+#define SRM_DI0_SSC__ADDR                   0x1F0405A8
+#define SRM_DI0_SSC__EMPTY       0x1F0405A8,0x00000000
+#define SRM_DI0_SSC__FULL       0x1F0405A8,0xffffffff
+#define SRM_DI0_SSC__DI0_PIN17_ERM     0x1F0405A8,0x00800000
+#define SRM_DI0_SSC__DI0_PIN16_ERM     0x1F0405A8,0x00400000
+#define SRM_DI0_SSC__DI0_PIN15_ERM     0x1F0405A8,0x00200000
+#define SRM_DI0_SSC__DI0_PIN14_ERM     0x1F0405A8,0x00100000
+#define SRM_DI0_SSC__DI0_PIN13_ERM     0x1F0405A8,0x00080000
+#define SRM_DI0_SSC__DI0_PIN12_ERM     0x1F0405A8,0x00040000
+#define SRM_DI0_SSC__DI0_PIN11_ERM     0x1F0405A8,0x00020000
+#define SRM_DI0_SSC__DI0_CS_ERM        0x1F0405A8,0x00010000
+#define SRM_DI0_SSC__DI0_WAIT_ON       0x1F0405A8,0x00000020
+#define SRM_DI0_SSC__DI0_BYTE_EN_RD_IN       0x1F0405A8,0x00000008
+#define SRM_DI0_SSC__DI0_BYTE_EN_PNTR       0x1F0405A8,0x00000007
+
+#define SRM_DI0_POL__ADDR                   0x1F0405AC
+#define SRM_DI0_POL__EMPTY       0x1F0405AC,0x00000000
+#define SRM_DI0_POL__FULL       0x1F0405AC,0xffffffff
+#define SRM_DI0_POL__DI0_WAIT_POLARITY       0x1F0405AC,0x04000000
+#define SRM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY       0x1F0405AC,0x02000000
+#define SRM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY       0x1F0405AC,0x01000000
+#define SRM_DI0_POL__DI0_CS1_DATA_POLARITY       0x1F0405AC,0x00800000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_17       0x1F0405AC,0x00400000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_16       0x1F0405AC,0x00200000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_15       0x1F0405AC,0x00100000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_14       0x1F0405AC,0x00080000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_13       0x1F0405AC,0x00040000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_12       0x1F0405AC,0x00020000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_11       0x1F0405AC,0x00010000
+#define SRM_DI0_POL__DI0_CS0_DATA_POLARITY       0x1F0405AC,0x00008000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_17       0x1F0405AC,0x00004000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_16       0x1F0405AC,0x00002000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_15       0x1F0405AC,0x00001000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_14       0x1F0405AC,0x00000800
+#define SRM_DI0_POL__DI0_CS0_POLARITY_13       0x1F0405AC,0x00000400
+#define SRM_DI0_POL__DI0_CS0_POLARITY_12       0x1F0405AC,0x00000200
+#define SRM_DI0_POL__DI0_CS0_POLARITY_11       0x1F0405AC,0x00000100
+#define SRM_DI0_POL__DI0_DRDY_DATA_POLARITY       0x1F0405AC,0x00000080
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_17       0x1F0405AC,0x00000040
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_16       0x1F0405AC,0x00000020
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_15       0x1F0405AC,0x00000010
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_14       0x1F0405AC,0x00000008
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_13       0x1F0405AC,0x00000004
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_12       0x1F0405AC,0x00000002
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_11       0x1F0405AC,0x00000001
+
+#define SRM_DI0_AW0__ADDR                   0x1F0405B0
+#define SRM_DI0_AW0__EMPTY       0x1F0405B0,0x00000000
+#define SRM_DI0_AW0__FULL       0x1F0405B0,0xffffffff
+#define SRM_DI0_AW0__DI0_AW_TRIG_SEL       0x1F0405B0,0xF0000000
+#define SRM_DI0_AW0__DI0_AW_HEND       0x1F0405B0,0x0FFF0000
+#define SRM_DI0_AW0__DI0_AW_HCOUNT_SEL       0x1F0405B0,0x0000F000
+#define SRM_DI0_AW0__DI0_AW_HSTART       0x1F0405B0,0x00000FFF
+
+#define SRM_DI0_AW1__ADDR                   0x1F0405B4
+#define SRM_DI0_AW1__EMPTY       0x1F0405B4,0x00000000
+#define SRM_DI0_AW1__FULL       0x1F0405B4,0xffffffff
+#define SRM_DI0_AW1__DI0_AW_VEND       0x1F0405B4,0x0FFF0000
+#define SRM_DI0_AW1__DI0_AW_VCOUNT_SEL       0x1F0405B4,0x0000F000
+#define SRM_DI0_AW1__DI0_AW_VSTART       0x1F0405B4,0x00000FFF
+
+#define SRM_DI0_SCR_CONF__ADDR                   0x1F0405B8
+#define SRM_DI0_SCR_CONF__EMPTY       0x1F0405B8,0x00000000
+#define SRM_DI0_SCR_CONF__FULL       0x1F0405B8,0xffffffff
+#define SRM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT       0x1F0405B8,0x00000FFF
+
+#define SRM_DI1_GENERAL__ADDR                   0x1F0405BC
+#define SRM_DI1_GENERAL__EMPTY       0x1F0405BC,0x00000000
+#define SRM_DI1_GENERAL__FULL       0x1F0405BC,0xffffffff
+#define SRM_DI1_GENERAL__DI1_DISP_Y_SEL       0x1F0405BC,0x70000000
+#define SRM_DI1_GENERAL__DI1_CLOCK_STOP_MODE       0x1F0405BC,0x0F000000
+#define SRM_DI1_GENERAL__DI1_DISP_CLOCK_INIT   0x1F0405BC,0x00800000
+#define SRM_DI1_GENERAL__DI1_MASK_SEL       0x1F0405BC,0x00400000
+#define SRM_DI1_GENERAL__DI1_VSYNC_EXT       0x1F0405BC,0x00200000
+#define SRM_DI1_GENERAL__DI1_CLK_EXT       0x1F0405BC,0x00100000
+#define SRN_DI1_GENERAL__DI1_WATCHDOG_MODE     0x1F0405BC,0x000C0000
+#define SRM_DI1_GENERAL__DI1_POLARITY_DISP_CLK       0x1F0405BC,0x00020000
+#define SRM_DI1_GENERAL__DI1_SYNC_COUNT_SEL       0x1F0405BC,0x0000F000
+#define SRM_DI1_GENERAL__DI1_ERR_TREATMENT       0x1F0405BC,0x00000800
+#define SRM_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1F0405BC,0x00000400
+#define SRM_DI1_GENERAL__DI1_POLARITY_CS1       0x1F0405BC,0x00000200
+#define SRM_DI1_GENERAL__DI1_POLARITY_CS0       0x1F0405BC,0x00000100
+#define SRM_DI1_GENERAL__DI1_POLARITY_8       0x1F0405BC,0x00000080
+#define SRM_DI1_GENERAL__DI1_POLARITY_7       0x1F0405BC,0x00000040
+#define SRM_DI1_GENERAL__DI1_POLARITY_6       0x1F0405BC,0x00000020
+#define SRM_DI1_GENERAL__DI1_POLARITY_5       0x1F0405BC,0x00000010
+#define SRM_DI1_GENERAL__DI1_POLARITY_4       0x1F0405BC,0x00000008
+#define SRM_DI1_GENERAL__DI1_POLARITY_3       0x1F0405BC,0x00000004
+#define SRM_DI1_GENERAL__DI1_POLARITY_2       0x1F0405BC,0x00000002
+#define SRM_DI1_GENERAL__DI1_POLARITY_1       0x1F0405BC,0x00000001
+
+#define SRM_DI1_BS_CLKGEN0__ADDR                   0x1F0405C0
+#define SRM_DI1_BS_CLKGEN0__EMPTY       0x1F0405C0,0x00000000
+#define SRM_DI1_BS_CLKGEN0__FULL       0x1F0405C0,0xffffffff
+#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET       0x1F0405C0,0x01FF0000
+#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD       0x1F0405C0,0x00000FFF
+
+#define SRM_DI1_BS_CLKGEN1__ADDR                   0x1F0405C4
+#define SRM_DI1_BS_CLKGEN1__EMPTY       0x1F0405C4,0x00000000
+#define SRM_DI1_BS_CLKGEN1__FULL       0x1F0405C4,0xffffffff
+#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN       0x1F0405C4,0x01FF0000
+#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP       0x1F0405C4,0x000001FF
+
+#define SRM_DI1_SW_GEN0_1__ADDR                   0x1F0405C8
+#define SRM_DI1_SW_GEN0_1__EMPTY       0x1F0405C8,0x00000000
+#define SRM_DI1_SW_GEN0_1__FULL       0x1F0405C8,0xffffffff
+#define SRM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1       0x1F0405C8,0x7FF80000
+#define SRM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1       0x1F0405C8,0x00070000
+#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1       0x1F0405C8,0x00007FF8
+#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1       0x1F0405C8,0x00000007
+
+#define SRM_DI1_SW_GEN0_2__ADDR                   0x1F0405CC
+#define SRM_DI1_SW_GEN0_2__EMPTY       0x1F0405CC,0x00000000
+#define SRM_DI1_SW_GEN0_2__FULL       0x1F0405CC,0xffffffff
+#define SRM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2       0x1F0405CC,0x7FF80000
+#define SRM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2       0x1F0405CC,0x00070000
+#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2       0x1F0405CC,0x00007FF8
+#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2       0x1F0405CC,0x00000007
+
+#define SRM_DI1_SW_GEN0_3__ADDR                   0x1F0405D0
+#define SRM_DI1_SW_GEN0_3__EMPTY       0x1F0405D0,0x00000000
+#define SRM_DI1_SW_GEN0_3__FULL       0x1F0405D0,0xffffffff
+#define SRM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3       0x1F0405D0,0x7FF80000
+#define SRM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3       0x1F0405D0,0x00070000
+#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3       0x1F0405D0,0x00007FF8
+#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3       0x1F0405D0,0x00000007
+
+#define SRM_DI1_SW_GEN0_4__ADDR                   0x1F0405D4
+#define SRM_DI1_SW_GEN0_4__EMPTY       0x1F0405D4,0x00000000
+#define SRM_DI1_SW_GEN0_4__FULL       0x1F0405D4,0xffffffff
+#define SRM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4       0x1F0405D4,0x7FF80000
+#define SRM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4       0x1F0405D4,0x00070000
+#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4       0x1F0405D4,0x00007FF8
+#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4       0x1F0405D4,0x00000007
+
+#define SRM_DI1_SW_GEN0_5__ADDR                   0x1F0405D8
+#define SRM_DI1_SW_GEN0_5__EMPTY       0x1F0405D8,0x00000000
+#define SRM_DI1_SW_GEN0_5__FULL       0x1F0405D8,0xffffffff
+#define SRM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5       0x1F0405D8,0x7FF80000
+#define SRM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5       0x1F0405D8,0x00070000
+#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5       0x1F0405D8,0x00007FF8
+#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5       0x1F0405D8,0x00000007
+
+#define SRM_DI1_SW_GEN0_6__ADDR                   0x1F0405DC
+#define SRM_DI1_SW_GEN0_6__EMPTY       0x1F0405DC,0x00000000
+#define SRM_DI1_SW_GEN0_6__FULL       0x1F0405DC,0xffffffff
+#define SRM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6       0x1F0405DC,0x7FF80000
+#define SRM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6       0x1F0405DC,0x00070000
+#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6       0x1F0405DC,0x00007FF8
+#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6       0x1F0405DC,0x00000007
+
+#define SRM_DI1_SW_GEN0_7__ADDR                   0x1F0405E0
+#define SRM_DI1_SW_GEN0_7__EMPTY       0x1F0405E0,0x00000000
+#define SRM_DI1_SW_GEN0_7__FULL       0x1F0405E0,0xffffffff
+#define SRM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7       0x1F0405E0,0x7FF80000
+#define SRM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7       0x1F0405E0,0x00070000
+#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7       0x1F0405E0,0x00007FF8
+#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7       0x1F0405E0,0x00000007
+
+#define SRM_DI1_SW_GEN0_8__ADDR                   0x1F0405E4
+#define SRM_DI1_SW_GEN0_8__EMPTY       0x1F0405E4,0x00000000
+#define SRM_DI1_SW_GEN0_8__FULL       0x1F0405E4,0xffffffff
+#define SRM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8       0x1F0405E4,0x7FF80000
+#define SRM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8       0x1F0405E4,0x00070000
+#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8       0x1F0405E4,0x00007FF8
+#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8       0x1F0405E4,0x00000007
+
+#define SRM_DI1_SW_GEN0_9__ADDR                   0x1F0405E8
+#define SRM_DI1_SW_GEN0_9__EMPTY       0x1F0405E8,0x00000000
+#define SRM_DI1_SW_GEN0_9__FULL       0x1F0405E8,0xffffffff
+#define SRM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9       0x1F0405E8,0x7FF80000
+#define SRM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9       0x1F0405E8,0x00070000
+#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9       0x1F0405E8,0x00007FF8
+#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9       0x1F0405E8,0x00000007
+
+#define SRM_DI1_SW_GEN1_1__ADDR                   0x1F0405EC
+#define SRM_DI1_SW_GEN1_1__EMPTY       0x1F0405EC,0x00000000
+#define SRM_DI1_SW_GEN1_1__FULL       0x1F0405EC,0xffffffff
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1       0x1F0405EC,0x60000000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1       0x1F0405EC,0x10000000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1       0x1F0405EC,0x0E000000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1       0x1F0405EC,0x01FF0000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1       0x1F0405EC,0x00007000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1       0x1F0405EC,0x00000E00
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_UP_1       0x1F0405EC,0x000001FF
+
+#define SRM_DI1_SW_GEN1_2__ADDR                   0x1F0405F0
+#define SRM_DI1_SW_GEN1_2__EMPTY       0x1F0405F0,0x00000000
+#define SRM_DI1_SW_GEN1_2__FULL       0x1F0405F0,0xffffffff
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2       0x1F0405F0,0x60000000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2       0x1F0405F0,0x10000000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2       0x1F0405F0,0x0E000000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2       0x1F0405F0,0x01FF0000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2       0x1F0405F0,0x00007000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2       0x1F0405F0,0x00000E00
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_UP_2       0x1F0405F0,0x000001FF
+
+#define SRM_DI1_SW_GEN1_3__ADDR                   0x1F0405F4
+#define SRM_DI1_SW_GEN1_3__EMPTY       0x1F0405F4,0x00000000
+#define SRM_DI1_SW_GEN1_3__FULL       0x1F0405F4,0xffffffff
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3       0x1F0405F4,0x60000000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3       0x1F0405F4,0x10000000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3       0x1F0405F4,0x0E000000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3       0x1F0405F4,0x01FF0000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3       0x1F0405F4,0x00007000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3       0x1F0405F4,0x00000E00
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_UP_3       0x1F0405F4,0x000001FF
+
+#define SRM_DI1_SW_GEN1_4__ADDR                   0x1F0405F8
+#define SRM_DI1_SW_GEN1_4__EMPTY       0x1F0405F8,0x00000000
+#define SRM_DI1_SW_GEN1_4__FULL       0x1F0405F8,0xffffffff
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4       0x1F0405F8,0x60000000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4       0x1F0405F8,0x10000000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4       0x1F0405F8,0x0E000000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4       0x1F0405F8,0x01FF0000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4       0x1F0405F8,0x00007000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4       0x1F0405F8,0x00000E00
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_UP_4       0x1F0405F8,0x000001FF
+
+#define SRM_DI1_SW_GEN1_5__ADDR                   0x1F0405FC
+#define SRM_DI1_SW_GEN1_5__EMPTY       0x1F0405FC,0x00000000
+#define SRM_DI1_SW_GEN1_5__FULL       0x1F0405FC,0xffffffff
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5       0x1F0405FC,0x60000000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5       0x1F0405FC,0x10000000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5       0x1F0405FC,0x0E000000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5       0x1F0405FC,0x01FF0000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5       0x1F0405FC,0x00007000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5       0x1F0405FC,0x00000E00
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_UP_5       0x1F0405FC,0x000001FF
+
+#define SRM_DI1_SW_GEN1_6__ADDR                   0x1F040600
+#define SRM_DI1_SW_GEN1_6__EMPTY       0x1F040600,0x00000000
+#define SRM_DI1_SW_GEN1_6__FULL       0x1F040600,0xffffffff
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6       0x1F040600,0x60000000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6       0x1F040600,0x10000000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6       0x1F040600,0x0E000000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6       0x1F040600,0x01FF0000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6       0x1F040600,0x00007000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6       0x1F040600,0x00000E00
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_UP_6       0x1F040600,0x000001FF
+
+#define SRM_DI1_SW_GEN1_7__ADDR                   0x1F040604
+#define SRM_DI1_SW_GEN1_7__EMPTY       0x1F040604,0x00000000
+#define SRM_DI1_SW_GEN1_7__FULL       0x1F040604,0xffffffff
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7       0x1F040604,0x60000000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7       0x1F040604,0x10000000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7       0x1F040604,0x0E000000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7       0x1F040604,0x01FF0000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7       0x1F040604,0x00007000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7       0x1F040604,0x00000E00
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_UP_7       0x1F040604,0x000001FF
+
+#define SRM_DI1_SW_GEN1_8__ADDR                   0x1F040608
+#define SRM_DI1_SW_GEN1_8__EMPTY       0x1F040608,0x00000000
+#define SRM_DI1_SW_GEN1_8__FULL       0x1F040608,0xffffffff
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8       0x1F040608,0x60000000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8       0x1F040608,0x10000000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8       0x1F040608,0x0E000000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8       0x1F040608,0x01FF0000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8       0x1F040608,0x00007000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8       0x1F040608,0x00000E00
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_UP_8       0x1F040608,0x000001FF
+
+#define SRM_DI1_SW_GEN1_9__ADDR                   0x1F04060C
+#define SRM_DI1_SW_GEN1_9__EMPTY       0x1F04060C,0x00000000
+#define SRM_DI1_SW_GEN1_9__FULL       0x1F04060C,0xffffffff
+#define SRM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9       0x1F04060C,0xE0000000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9       0x1F04060C,0x10000000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9       0x1F04060C,0x0E000000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9       0x1F04060C,0x01FF0000
+#define SRM_DI1_SW_GEN1_9__DI1_TAG_SEL_9       0x1F04060C,0x00008000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_UP_9       0x1F04060C,0x000001FF
+
+#define SRM_DI1_SYNC_AS_GEN__ADDR                   0x1F040610
+#define SRM_DI1_SYNC_AS_GEN__EMPTY       0x1F040610,0x00000000
+#define SRM_DI1_SYNC_AS_GEN__FULL       0x1F040610,0xffffffff
+#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN       0x1F040610,0x10000000
+#define SRM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL       0x1F040610,0x0000E000
+#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START       0x1F040610,0x00000FFF
+
+#define SRM_DI1_DW_GEN_0__ADDR                  0x1F040614
+#define SRM_DI1_DW_GEN_0__EMPTY                 0x1F040614,0x00000000
+#define SRM_DI1_DW_GEN_0__FULL                  0x1F040614,0xffffffff
+#define SRM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0     0x1F040614,0xFF000000
+#define SRM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1F040614,0x00FF0000
+#define SRM_DI1_DW_GEN_0__DI1_CST_0             0x1F040614,0x0000C000
+#define SRM_DI1_DW_GEN_0__DI1_PT_6_0            0x1F040614,0x00003000
+#define SRM_DI1_DW_GEN_0__DI1_PT_5_0            0x1F040614,0x00000C00
+#define SRM_DI1_DW_GEN_0__DI1_PT_4_0            0x1F040614,0x00000300
+#define SRM_DI1_DW_GEN_0__DI1_PT_3_0            0x1F040614,0x000000C0
+#define SRM_DI1_DW_GEN_0__DI1_PT_2_0            0x1F040614,0x00000030
+#define SRM_DI1_DW_GEN_0__DI1_PT_1_0            0x1F040614,0x0000000C
+#define SRM_DI1_DW_GEN_0__DI1_PT_0_0            0x1F040614,0x00000003
+
+#define SRM_DI1_DW_GEN_0__ADDR                    0x1F040614
+#define SRM_DI1_DW_GEN_0__EMPTY                   0x1F040614,0x00000000
+#define SRM_DI1_DW_GEN_0__FULL                    0x1F040614,0xffffffff
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0     0x1F040614,0xFF000000
+#define SRM_DI1_DW_GEN_0__DI1_START_PERIOD_0      0x1F040614,0x00FF0000
+#define SRM_DI1_DW_GEN_0__DI1_CST_0               0x1F040614,0x0000C000
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1F040614,0x000001F0
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_RS_0         0x1F040614,0x0000000C
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0        0x1F040614,0x00000003
+
+#define SRM_DI1_DW_GEN_1__ADDR                  0x1F040618
+#define SRM_DI1_DW_GEN_1__EMPTY                 0x1F040618,0x00000000
+#define SRM_DI1_DW_GEN_1__FULL                  0x1F040618,0xffffffff
+#define SRM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1     0x1F040618,0xFF000000
+#define SRM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1F040618,0x00FF0000
+#define SRM_DI1_DW_GEN_1__DI1_CST_1             0x1F040618,0x0000C000
+#define SRM_DI1_DW_GEN_1__DI1_PT_6_1            0x1F040618,0x00003000
+#define SRM_DI1_DW_GEN_1__DI1_PT_5_1            0x1F040618,0x00000C00
+#define SRM_DI1_DW_GEN_1__DI1_PT_4_1            0x1F040618,0x00000300
+#define SRM_DI1_DW_GEN_1__DI1_PT_3_1            0x1F040618,0x000000C0
+#define SRM_DI1_DW_GEN_1__DI1_PT_2_1            0x1F040618,0x00000030
+#define SRM_DI1_DW_GEN_1__DI1_PT_1_1            0x1F040618,0x0000000C
+#define SRM_DI1_DW_GEN_1__DI1_PT_0_1            0x1F040618,0x00000003
+
+#define SRM_DI1_DW_GEN_1__ADDR                    0x1F040618
+#define SRM_DI1_DW_GEN_1__EMPTY                   0x1F040618,0x00000000
+#define SRM_DI1_DW_GEN_1__FULL                    0x1F040618,0xffffffff
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1     0x1F040618,0xFF000000
+#define SRM_DI1_DW_GEN_1__DI1_START_PERIOD_1      0x1F040618,0x00FF0000
+#define SRM_DI1_DW_GEN_1__DI1_CST_1               0x1F040618,0x0000C000
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1F040618,0x000001F0
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_RS_1         0x1F040618,0x0000000C
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1        0x1F040618,0x00000003
+
+#define SRM_DI1_DW_GEN_2__ADDR                  0x1F04061C
+#define SRM_DI1_DW_GEN_2__EMPTY                 0x1F04061C,0x00000000
+#define SRM_DI1_DW_GEN_2__FULL                  0x1F04061C,0xffffffff
+#define SRM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2     0x1F04061C,0xFF000000
+#define SRM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1F04061C,0x00FF0000
+#define SRM_DI1_DW_GEN_2__DI1_CST_2             0x1F04061C,0x0000C000
+#define SRM_DI1_DW_GEN_2__DI1_PT_6_2            0x1F04061C,0x00003000
+#define SRM_DI1_DW_GEN_2__DI1_PT_5_2            0x1F04061C,0x00000C00
+#define SRM_DI1_DW_GEN_2__DI1_PT_4_2            0x1F04061C,0x00000300
+#define SRM_DI1_DW_GEN_2__DI1_PT_3_2            0x1F04061C,0x000000C0
+#define SRM_DI1_DW_GEN_2__DI1_PT_2_2            0x1F04061C,0x00000030
+#define SRM_DI1_DW_GEN_2__DI1_PT_1_2            0x1F04061C,0x0000000C
+#define SRM_DI1_DW_GEN_2__DI1_PT_0_2            0x1F04061C,0x00000003
+
+#define SRM_DI1_DW_GEN_2__ADDR                    0x1F04061C
+#define SRM_DI1_DW_GEN_2__EMPTY                   0x1F04061C,0x00000000
+#define SRM_DI1_DW_GEN_2__FULL                    0x1F04061C,0xffffffff
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2     0x1F04061C,0xFF000000
+#define SRM_DI1_DW_GEN_2__DI1_START_PERIOD_2      0x1F04061C,0x00FF0000
+#define SRM_DI1_DW_GEN_2__DI1_CST_2               0x1F04061C,0x0000C000
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1F04061C,0x000001F0
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_RS_2         0x1F04061C,0x0000000C
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2        0x1F04061C,0x00000003
+
+#define SRM_DI1_DW_GEN_3__ADDR                  0x1F040620
+#define SRM_DI1_DW_GEN_3__EMPTY                 0x1F040620,0x00000000
+#define SRM_DI1_DW_GEN_3__FULL                  0x1F040620,0xffffffff
+#define SRM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3     0x1F040620,0xFF000000
+#define SRM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1F040620,0x00FF0000
+#define SRM_DI1_DW_GEN_3__DI1_CST_3             0x1F040620,0x0000C000
+#define SRM_DI1_DW_GEN_3__DI1_PT_6_3            0x1F040620,0x00003000
+#define SRM_DI1_DW_GEN_3__DI1_PT_5_3            0x1F040620,0x00000C00
+#define SRM_DI1_DW_GEN_3__DI1_PT_4_3            0x1F040620,0x00000300
+#define SRM_DI1_DW_GEN_3__DI1_PT_3_3            0x1F040620,0x000000C0
+#define SRM_DI1_DW_GEN_3__DI1_PT_2_3            0x1F040620,0x00000030
+#define SRM_DI1_DW_GEN_3__DI1_PT_1_3            0x1F040620,0x0000000C
+#define SRM_DI1_DW_GEN_3__DI1_PT_0_3            0x1F040620,0x00000003
+
+#define SRM_DI1_DW_GEN_3__ADDR                    0x1F040620
+#define SRM_DI1_DW_GEN_3__EMPTY                   0x1F040620,0x00000000
+#define SRM_DI1_DW_GEN_3__FULL                    0x1F040620,0xffffffff
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3     0x1F040620,0xFF000000
+#define SRM_DI1_DW_GEN_3__DI1_START_PERIOD_3      0x1F040620,0x00FF0000
+#define SRM_DI1_DW_GEN_3__DI1_CST_3               0x1F040620,0x0000C000
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1F040620,0x000001F0
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_RS_3         0x1F040620,0x0000000C
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3        0x1F040620,0x00000003
+
+#define SRM_DI1_DW_GEN_4__ADDR                  0x1F040624
+#define SRM_DI1_DW_GEN_4__EMPTY                 0x1F040624,0x00000000
+#define SRM_DI1_DW_GEN_4__FULL                  0x1F040624,0xffffffff
+#define SRM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4     0x1F040624,0xFF000000
+#define SRM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1F040624,0x00FF0000
+#define SRM_DI1_DW_GEN_4__DI1_CST_4             0x1F040624,0x0000C000
+#define SRM_DI1_DW_GEN_4__DI1_PT_6_4            0x1F040624,0x00003000
+#define SRM_DI1_DW_GEN_4__DI1_PT_5_4            0x1F040624,0x00000C00
+#define SRM_DI1_DW_GEN_4__DI1_PT_4_4            0x1F040624,0x00000300
+#define SRM_DI1_DW_GEN_4__DI1_PT_3_4            0x1F040624,0x000000C0
+#define SRM_DI1_DW_GEN_4__DI1_PT_2_4            0x1F040624,0x00000030
+#define SRM_DI1_DW_GEN_4__DI1_PT_1_4            0x1F040624,0x0000000C
+#define SRM_DI1_DW_GEN_4__DI1_PT_0_4            0x1F040624,0x00000003
+
+#define SRM_DI1_DW_GEN_4__ADDR                    0x1F040624
+#define SRM_DI1_DW_GEN_4__EMPTY                   0x1F040624,0x00000000
+#define SRM_DI1_DW_GEN_4__FULL                    0x1F040624,0xffffffff
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4     0x1F040624,0xFF000000
+#define SRM_DI1_DW_GEN_4__DI1_START_PERIOD_4      0x1F040624,0x00FF0000
+#define SRM_DI1_DW_GEN_4__DI1_CST_4               0x1F040624,0x0000C000
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1F040624,0x000001F0
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_RS_4         0x1F040624,0x0000000C
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4        0x1F040624,0x00000003
+
+#define SRM_DI1_DW_GEN_5__ADDR                  0x1F040628
+#define SRM_DI1_DW_GEN_5__EMPTY                 0x1F040628,0x00000000
+#define SRM_DI1_DW_GEN_5__FULL                  0x1F040628,0xffffffff
+#define SRM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5     0x1F040628,0xFF000000
+#define SRM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1F040628,0x00FF0000
+#define SRM_DI1_DW_GEN_5__DI1_CST_5             0x1F040628,0x0000C000
+#define SRM_DI1_DW_GEN_5__DI1_PT_6_5            0x1F040628,0x00003000
+#define SRM_DI1_DW_GEN_5__DI1_PT_5_5            0x1F040628,0x00000C00
+#define SRM_DI1_DW_GEN_5__DI1_PT_4_5            0x1F040628,0x00000300
+#define SRM_DI1_DW_GEN_5__DI1_PT_3_5            0x1F040628,0x000000C0
+#define SRM_DI1_DW_GEN_5__DI1_PT_2_5            0x1F040628,0x00000030
+#define SRM_DI1_DW_GEN_5__DI1_PT_1_5            0x1F040628,0x0000000C
+#define SRM_DI1_DW_GEN_5__DI1_PT_0_5            0x1F040628,0x00000003
+
+#define SRM_DI1_DW_GEN_5__ADDR                    0x1F040628
+#define SRM_DI1_DW_GEN_5__EMPTY                   0x1F040628,0x00000000
+#define SRM_DI1_DW_GEN_5__FULL                    0x1F040628,0xffffffff
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5     0x1F040628,0xFF000000
+#define SRM_DI1_DW_GEN_5__DI1_START_PERIOD_5      0x1F040628,0x00FF0000
+#define SRM_DI1_DW_GEN_5__DI1_CST_5               0x1F040628,0x0000C000
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1F040628,0x000001F0
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_RS_5         0x1F040628,0x0000000C
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5        0x1F040628,0x00000003
+
+#define SRM_DI1_DW_GEN_6__ADDR                  0x1F04062C
+#define SRM_DI1_DW_GEN_6__EMPTY                 0x1F04062C,0x00000000
+#define SRM_DI1_DW_GEN_6__FULL                  0x1F04062C,0xffffffff
+#define SRM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6     0x1F04062C,0xFF000000
+#define SRM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1F04062C,0x00FF0000
+#define SRM_DI1_DW_GEN_6__DI1_CST_6             0x1F04062C,0x0000C000
+#define SRM_DI1_DW_GEN_6__DI1_PT_6_6            0x1F04062C,0x00003000
+#define SRM_DI1_DW_GEN_6__DI1_PT_5_6            0x1F04062C,0x00000C00
+#define SRM_DI1_DW_GEN_6__DI1_PT_4_6            0x1F04062C,0x00000300
+#define SRM_DI1_DW_GEN_6__DI1_PT_3_6            0x1F04062C,0x000000C0
+#define SRM_DI1_DW_GEN_6__DI1_PT_2_6            0x1F04062C,0x00000030
+#define SRM_DI1_DW_GEN_6__DI1_PT_1_6            0x1F04062C,0x0000000C
+#define SRM_DI1_DW_GEN_6__DI1_PT_0_6            0x1F04062C,0x00000003
+
+#define SRM_DI1_DW_GEN_6__ADDR                    0x1F04062C
+#define SRM_DI1_DW_GEN_6__EMPTY                   0x1F04062C,0x00000000
+#define SRM_DI1_DW_GEN_6__FULL                    0x1F04062C,0xffffffff
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6     0x1F04062C,0xFF000000
+#define SRM_DI1_DW_GEN_6__DI1_START_PERIOD_6      0x1F04062C,0x00FF0000
+#define SRM_DI1_DW_GEN_6__DI1_CST_6               0x1F04062C,0x0000C000
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1F04062C,0x000001F0
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_RS_6         0x1F04062C,0x0000000C
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6        0x1F04062C,0x00000003
+
+#define SRM_DI1_DW_GEN_7__ADDR                  0x1F040630
+#define SRM_DI1_DW_GEN_7__EMPTY                 0x1F040630,0x00000000
+#define SRM_DI1_DW_GEN_7__FULL                  0x1F040630,0xffffffff
+#define SRM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7     0x1F040630,0xFF000000
+#define SRM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1F040630,0x00FF0000
+#define SRM_DI1_DW_GEN_7__DI1_CST_7             0x1F040630,0x0000C000
+#define SRM_DI1_DW_GEN_7__DI1_PT_6_7            0x1F040630,0x00003000
+#define SRM_DI1_DW_GEN_7__DI1_PT_5_7            0x1F040630,0x00000C00
+#define SRM_DI1_DW_GEN_7__DI1_PT_4_7            0x1F040630,0x00000300
+#define SRM_DI1_DW_GEN_7__DI1_PT_3_7            0x1F040630,0x000000C0
+#define SRM_DI1_DW_GEN_7__DI1_PT_2_7            0x1F040630,0x00000030
+#define SRM_DI1_DW_GEN_7__DI1_PT_1_7            0x1F040630,0x0000000C
+#define SRM_DI1_DW_GEN_7__DI1_PT_0_7            0x1F040630,0x00000003
+
+#define SRM_DI1_DW_GEN_7__ADDR                    0x1F040630
+#define SRM_DI1_DW_GEN_7__EMPTY                   0x1F040630,0x00000000
+#define SRM_DI1_DW_GEN_7__FULL                    0x1F040630,0xffffffff
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7     0x1F040630,0xFF000000
+#define SRM_DI1_DW_GEN_7__DI1_START_PERIOD_7      0x1F040630,0x00FF0000
+#define SRM_DI1_DW_GEN_7__DI1_CST_7               0x1F040630,0x0000C000
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1F040630,0x000001F0
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_RS_7         0x1F040630,0x0000000C
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7        0x1F040630,0x00000003
+
+#define SRM_DI1_DW_GEN_8__ADDR                  0x1F040634
+#define SRM_DI1_DW_GEN_8__EMPTY                 0x1F040634,0x00000000
+#define SRM_DI1_DW_GEN_8__FULL                  0x1F040634,0xffffffff
+#define SRM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8     0x1F040634,0xFF000000
+#define SRM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1F040634,0x00FF0000
+#define SRM_DI1_DW_GEN_8__DI1_CST_8             0x1F040634,0x0000C000
+#define SRM_DI1_DW_GEN_8__DI1_PT_6_8            0x1F040634,0x00003000
+#define SRM_DI1_DW_GEN_8__DI1_PT_5_8            0x1F040634,0x00000C00
+#define SRM_DI1_DW_GEN_8__DI1_PT_4_8            0x1F040634,0x00000300
+#define SRM_DI1_DW_GEN_8__DI1_PT_3_8            0x1F040634,0x000000C0
+#define SRM_DI1_DW_GEN_8__DI1_PT_2_8            0x1F040634,0x00000030
+#define SRM_DI1_DW_GEN_8__DI1_PT_1_8            0x1F040634,0x0000000C
+#define SRM_DI1_DW_GEN_8__DI1_PT_0_8            0x1F040634,0x00000003
+
+#define SRM_DI1_DW_GEN_8__ADDR                    0x1F040634
+#define SRM_DI1_DW_GEN_8__EMPTY                   0x1F040634,0x00000000
+#define SRM_DI1_DW_GEN_8__FULL                    0x1F040634,0xffffffff
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8     0x1F040634,0xFF000000
+#define SRM_DI1_DW_GEN_8__DI1_START_PERIOD_8      0x1F040634,0x00FF0000
+#define SRM_DI1_DW_GEN_8__DI1_CST_8               0x1F040634,0x0000C000
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1F040634,0x000001F0
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_RS_8         0x1F040634,0x0000000C
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8        0x1F040634,0x00000003
+
+#define SRM_DI1_DW_GEN_9__ADDR                  0x1F040638
+#define SRM_DI1_DW_GEN_9__EMPTY                 0x1F040638,0x00000000
+#define SRM_DI1_DW_GEN_9__FULL                  0x1F040638,0xffffffff
+#define SRM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9     0x1F040638,0xFF000000
+#define SRM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1F040638,0x00FF0000
+#define SRM_DI1_DW_GEN_9__DI1_CST_9             0x1F040638,0x0000C000
+#define SRM_DI1_DW_GEN_9__DI1_PT_6_9            0x1F040638,0x00003000
+#define SRM_DI1_DW_GEN_9__DI1_PT_5_9            0x1F040638,0x00000C00
+#define SRM_DI1_DW_GEN_9__DI1_PT_4_9            0x1F040638,0x00000300
+#define SRM_DI1_DW_GEN_9__DI1_PT_3_9            0x1F040638,0x000000C0
+#define SRM_DI1_DW_GEN_9__DI1_PT_2_9            0x1F040638,0x00000030
+#define SRM_DI1_DW_GEN_9__DI1_PT_1_9            0x1F040638,0x0000000C
+#define SRM_DI1_DW_GEN_9__DI1_PT_0_9            0x1F040638,0x00000003
+
+#define SRM_DI1_DW_GEN_9__ADDR                    0x1F040638
+#define SRM_DI1_DW_GEN_9__EMPTY                   0x1F040638,0x00000000
+#define SRM_DI1_DW_GEN_9__FULL                    0x1F040638,0xffffffff
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9     0x1F040638,0xFF000000
+#define SRM_DI1_DW_GEN_9__DI1_START_PERIOD_9      0x1F040638,0x00FF0000
+#define SRM_DI1_DW_GEN_9__DI1_CST_9               0x1F040638,0x0000C000
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1F040638,0x000001F0
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_RS_9         0x1F040638,0x0000000C
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9        0x1F040638,0x00000003
+
+#define SRM_DI1_DW_GEN_10__ADDR                   0x1F04063C
+#define SRM_DI1_DW_GEN_10__EMPTY                  0x1F04063C,0x00000000
+#define SRM_DI1_DW_GEN_10__FULL                   0x1F04063C,0xffffffff
+#define SRM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10     0x1F04063C,0xFF000000
+#define SRM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1F04063C,0x00FF0000
+#define SRM_DI1_DW_GEN_10__DI1_CST_10             0x1F04063C,0x0000C000
+#define SRM_DI1_DW_GEN_10__DI1_PT_6_10            0x1F04063C,0x00003000
+#define SRM_DI1_DW_GEN_10__DI1_PT_5_10            0x1F04063C,0x00000C00
+#define SRM_DI1_DW_GEN_10__DI1_PT_4_10            0x1F04063C,0x00000300
+#define SRM_DI1_DW_GEN_10__DI1_PT_3_10            0x1F04063C,0x000000C0
+#define SRM_DI1_DW_GEN_10__DI1_PT_2_10            0x1F04063C,0x00000030
+#define SRM_DI1_DW_GEN_10__DI1_PT_1_10            0x1F04063C,0x0000000C
+#define SRM_DI1_DW_GEN_10__DI1_PT_0_10            0x1F04063C,0x00000003
+
+#define SRM_DI1_DW_GEN_10__ADDR                     0x1F04063C
+#define SRM_DI1_DW_GEN_10__EMPTY                    0x1F04063C,0x00000000
+#define SRM_DI1_DW_GEN_10__FULL                     0x1F04063C,0xffffffff
+#define SRM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10     0x1F04063C,0xFF000000
+#define SRM_DI1_DW_GEN_10__DI1_START_PERIOD_10      0x1F04063C,0x00FF0000
+#define SRM_DI1_DW_GEN_10__DI1_CST_10               0x1F04063C,0x0000C000
+#define SRM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F04063C,0x000001F0
+#define SRM_DI1_DW_GEN_10__DI1_SERIAL_RS_10         0x1F04063C,0x0000000C
+#define SRM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10        0x1F04063C,0x00000003
+
+#define SRM_DI1_DW_GEN_11__ADDR                   0x1F040640
+#define SRM_DI1_DW_GEN_11__EMPTY                  0x1F040640,0x00000000
+#define SRM_DI1_DW_GEN_11__FULL                   0x1F040640,0xffffffff
+#define SRM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11     0x1F040640,0xFF000000
+#define SRM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1F040640,0x00FF0000
+#define SRM_DI1_DW_GEN_11__DI1_CST_11             0x1F040640,0x0000C000
+#define SRM_DI1_DW_GEN_11__DI1_PT_6_11            0x1F040640,0x00003000
+#define SRM_DI1_DW_GEN_11__DI1_PT_5_11            0x1F040640,0x00000C00
+#define SRM_DI1_DW_GEN_11__DI1_PT_4_11            0x1F040640,0x00000300
+#define SRM_DI1_DW_GEN_11__DI1_PT_3_11            0x1F040640,0x000000C0
+#define SRM_DI1_DW_GEN_11__DI1_PT_2_11            0x1F040640,0x00000030
+#define SRM_DI1_DW_GEN_11__DI1_PT_1_11            0x1F040640,0x0000000C
+#define SRM_DI1_DW_GEN_11__DI1_PT_0_11            0x1F040640,0x00000003
+
+#define SRM_DI1_DW_GEN_11__ADDR                     0x1F040640
+#define SRM_DI1_DW_GEN_11__EMPTY                    0x1F040640,0x00000000
+#define SRM_DI1_DW_GEN_11__FULL                     0x1F040640,0xffffffff
+#define SRM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11     0x1F040640,0xFF000000
+#define SRM_DI1_DW_GEN_11__DI1_START_PERIOD_11      0x1F040640,0x00FF0000
+#define SRM_DI1_DW_GEN_11__DI1_CST_11               0x1F040640,0x0000C000
+#define SRM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F040640,0x000001F0
+#define SRM_DI1_DW_GEN_11__DI1_SERIAL_RS_11         0x1F040640,0x0000000C
+#define SRM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11        0x1F040640,0x00000003
+
+#define SRM_DI1_DW_SET0_0__ADDR                   0x1F040644
+#define SRM_DI1_DW_SET0_0__EMPTY       0x1F040644,0x00000000
+#define SRM_DI1_DW_SET0_0__FULL       0x1F040644,0xffffffff
+#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0       0x1F040644,0x01FF0000
+#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0       0x1F040644,0x000001FF
+
+#define SRM_DI1_DW_SET0_1__ADDR                   0x1F040648
+#define SRM_DI1_DW_SET0_1__EMPTY       0x1F040648,0x00000000
+#define SRM_DI1_DW_SET0_1__FULL       0x1F040648,0xffffffff
+#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1       0x1F040648,0x01FF0000
+#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1       0x1F040648,0x000001FF
+
+#define SRM_DI1_DW_SET0_2__ADDR                   0x1F04064C
+#define SRM_DI1_DW_SET0_2__EMPTY       0x1F04064C,0x00000000
+#define SRM_DI1_DW_SET0_2__FULL       0x1F04064C,0xffffffff
+#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2       0x1F04064C,0x01FF0000
+#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2       0x1F04064C,0x000001FF
+
+#define SRM_DI1_DW_SET0_3__ADDR                   0x1F040650
+#define SRM_DI1_DW_SET0_3__EMPTY       0x1F040650,0x00000000
+#define SRM_DI1_DW_SET0_3__FULL       0x1F040650,0xffffffff
+#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3       0x1F040650,0x01FF0000
+#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3       0x1F040650,0x000001FF
+
+#define SRM_DI1_DW_SET0_4__ADDR                   0x1F040654
+#define SRM_DI1_DW_SET0_4__EMPTY       0x1F040654,0x00000000
+#define SRM_DI1_DW_SET0_4__FULL       0x1F040654,0xffffffff
+#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4       0x1F040654,0x01FF0000
+#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4       0x1F040654,0x000001FF
+
+#define SRM_DI1_DW_SET0_5__ADDR                   0x1F040658
+#define SRM_DI1_DW_SET0_5__EMPTY       0x1F040658,0x00000000
+#define SRM_DI1_DW_SET0_5__FULL       0x1F040658,0xffffffff
+#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5       0x1F040658,0x01FF0000
+#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5       0x1F040658,0x000001FF
+
+#define SRM_DI1_DW_SET0_6__ADDR                   0x1F04065C
+#define SRM_DI1_DW_SET0_6__EMPTY       0x1F04065C,0x00000000
+#define SRM_DI1_DW_SET0_6__FULL       0x1F04065C,0xffffffff
+#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6       0x1F04065C,0x01FF0000
+#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6       0x1F04065C,0x000001FF
+
+#define SRM_DI1_DW_SET0_7__ADDR                   0x1F040660
+#define SRM_DI1_DW_SET0_7__EMPTY       0x1F040660,0x00000000
+#define SRM_DI1_DW_SET0_7__FULL       0x1F040660,0xffffffff
+#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7       0x1F040660,0x01FF0000
+#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7       0x1F040660,0x000001FF
+
+#define SRM_DI1_DW_SET0_8__ADDR                   0x1F040664
+#define SRM_DI1_DW_SET0_8__EMPTY       0x1F040664,0x00000000
+#define SRM_DI1_DW_SET0_8__FULL       0x1F040664,0xffffffff
+#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8       0x1F040664,0x01FF0000
+#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8       0x1F040664,0x000001FF
+
+#define SRM_DI1_DW_SET0_9__ADDR                   0x1F040668
+#define SRM_DI1_DW_SET0_9__EMPTY       0x1F040668,0x00000000
+#define SRM_DI1_DW_SET0_9__FULL       0x1F040668,0xffffffff
+#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9       0x1F040668,0x01FF0000
+#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9       0x1F040668,0x000001FF
+
+#define SRM_DI1_DW_SET0_10__ADDR                   0x1F04066C
+#define SRM_DI1_DW_SET0_10__EMPTY       0x1F04066C,0x00000000
+#define SRM_DI1_DW_SET0_10__FULL       0x1F04066C,0xffffffff
+#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10       0x1F04066C,0x01FF0000
+#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10       0x1F04066C,0x000001FF
+
+#define SRM_DI1_DW_SET0_11__ADDR                   0x1F040670
+#define SRM_DI1_DW_SET0_11__EMPTY       0x1F040670,0x00000000
+#define SRM_DI1_DW_SET0_11__FULL       0x1F040670,0xffffffff
+#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11       0x1F040670,0x01FF0000
+#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11       0x1F040670,0x000001FF
+
+#define SRM_DI1_DW_SET1_0__ADDR                   0x1F040674
+#define SRM_DI1_DW_SET1_0__EMPTY       0x1F040674,0x00000000
+#define SRM_DI1_DW_SET1_0__FULL       0x1F040674,0xffffffff
+#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0       0x1F040674,0x01FF0000
+#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0       0x1F040674,0x000001FF
+
+#define SRM_DI1_DW_SET1_1__ADDR                   0x1F040678
+#define SRM_DI1_DW_SET1_1__EMPTY       0x1F040678,0x00000000
+#define SRM_DI1_DW_SET1_1__FULL       0x1F040678,0xffffffff
+#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1       0x1F040678,0x01FF0000
+#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1       0x1F040678,0x000001FF
+
+#define SRM_DI1_DW_SET1_2__ADDR                   0x1F04067C
+#define SRM_DI1_DW_SET1_2__EMPTY       0x1F04067C,0x00000000
+#define SRM_DI1_DW_SET1_2__FULL       0x1F04067C,0xffffffff
+#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2       0x1F04067C,0x01FF0000
+#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2       0x1F04067C,0x000001FF
+
+#define SRM_DI1_DW_SET1_3__ADDR                   0x1F040680
+#define SRM_DI1_DW_SET1_3__EMPTY       0x1F040680,0x00000000
+#define SRM_DI1_DW_SET1_3__FULL       0x1F040680,0xffffffff
+#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3       0x1F040680,0x01FF0000
+#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3       0x1F040680,0x000001FF
+
+#define SRM_DI1_DW_SET1_4__ADDR                   0x1F040684
+#define SRM_DI1_DW_SET1_4__EMPTY       0x1F040684,0x00000000
+#define SRM_DI1_DW_SET1_4__FULL       0x1F040684,0xffffffff
+#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4       0x1F040684,0x01FF0000
+#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4       0x1F040684,0x000001FF
+
+#define SRM_DI1_DW_SET1_5__ADDR                   0x1F040688
+#define SRM_DI1_DW_SET1_5__EMPTY       0x1F040688,0x00000000
+#define SRM_DI1_DW_SET1_5__FULL       0x1F040688,0xffffffff
+#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5       0x1F040688,0x01FF0000
+#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5       0x1F040688,0x000001FF
+
+#define SRM_DI1_DW_SET1_6__ADDR                   0x1F04068C
+#define SRM_DI1_DW_SET1_6__EMPTY       0x1F04068C,0x00000000
+#define SRM_DI1_DW_SET1_6__FULL       0x1F04068C,0xffffffff
+#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6       0x1F04068C,0x01FF0000
+#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6       0x1F04068C,0x000001FF
+
+#define SRM_DI1_DW_SET1_7__ADDR                   0x1F040690
+#define SRM_DI1_DW_SET1_7__EMPTY       0x1F040690,0x00000000
+#define SRM_DI1_DW_SET1_7__FULL       0x1F040690,0xffffffff
+#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7       0x1F040690,0x01FF0000
+#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7       0x1F040690,0x000001FF
+
+#define SRM_DI1_DW_SET1_8__ADDR                   0x1F040694
+#define SRM_DI1_DW_SET1_8__EMPTY       0x1F040694,0x00000000
+#define SRM_DI1_DW_SET1_8__FULL       0x1F040694,0xffffffff
+#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8       0x1F040694,0x01FF0000
+#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8       0x1F040694,0x000001FF
+
+#define SRM_DI1_DW_SET1_9__ADDR                   0x1F040698
+#define SRM_DI1_DW_SET1_9__EMPTY       0x1F040698,0x00000000
+#define SRM_DI1_DW_SET1_9__FULL       0x1F040698,0xffffffff
+#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9       0x1F040698,0x01FF0000
+#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9       0x1F040698,0x000001FF
+
+#define SRM_DI1_DW_SET1_10__ADDR                   0x1F04069C
+#define SRM_DI1_DW_SET1_10__EMPTY       0x1F04069C,0x00000000
+#define SRM_DI1_DW_SET1_10__FULL       0x1F04069C,0xffffffff
+#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10       0x1F04069C,0x01FF0000
+#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10       0x1F04069C,0x000001FF
+
+#define SRM_DI1_DW_SET1_11__ADDR                   0x1F0406A0
+#define SRM_DI1_DW_SET1_11__EMPTY       0x1F0406A0,0x00000000
+#define SRM_DI1_DW_SET1_11__FULL       0x1F0406A0,0xffffffff
+#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11       0x1F0406A0,0x01FF0000
+#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11       0x1F0406A0,0x000001FF
+
+#define SRM_DI1_DW_SET2_0__ADDR                   0x1F0406A4
+#define SRM_DI1_DW_SET2_0__EMPTY       0x1F0406A4,0x00000000
+#define SRM_DI1_DW_SET2_0__FULL       0x1F0406A4,0xffffffff
+#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0       0x1F0406A4,0x01FF0000
+#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0       0x1F0406A4,0x000001FF
+
+#define SRM_DI1_DW_SET2_1__ADDR                   0x1F0406A8
+#define SRM_DI1_DW_SET2_1__EMPTY       0x1F0406A8,0x00000000
+#define SRM_DI1_DW_SET2_1__FULL       0x1F0406A8,0xffffffff
+#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1       0x1F0406A8,0x01FF0000
+#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1       0x1F0406A8,0x000001FF
+
+#define SRM_DI1_DW_SET2_2__ADDR                   0x1F0406AC
+#define SRM_DI1_DW_SET2_2__EMPTY       0x1F0406AC,0x00000000
+#define SRM_DI1_DW_SET2_2__FULL       0x1F0406AC,0xffffffff
+#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2       0x1F0406AC,0x01FF0000
+#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2       0x1F0406AC,0x000001FF
+
+#define SRM_DI1_DW_SET2_3__ADDR                   0x1F0406B0
+#define SRM_DI1_DW_SET2_3__EMPTY       0x1F0406B0,0x00000000
+#define SRM_DI1_DW_SET2_3__FULL       0x1F0406B0,0xffffffff
+#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3       0x1F0406B0,0x01FF0000
+#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3       0x1F0406B0,0x000001FF
+
+#define SRM_DI1_DW_SET2_4__ADDR                   0x1F0406B4
+#define SRM_DI1_DW_SET2_4__EMPTY       0x1F0406B4,0x00000000
+#define SRM_DI1_DW_SET2_4__FULL       0x1F0406B4,0xffffffff
+#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4       0x1F0406B4,0x01FF0000
+#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4       0x1F0406B4,0x000001FF
+
+#define SRM_DI1_DW_SET2_5__ADDR                   0x1F0406B8
+#define SRM_DI1_DW_SET2_5__EMPTY       0x1F0406B8,0x00000000
+#define SRM_DI1_DW_SET2_5__FULL       0x1F0406B8,0xffffffff
+#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5       0x1F0406B8,0x01FF0000
+#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5       0x1F0406B8,0x000001FF
+
+#define SRM_DI1_DW_SET2_6__ADDR                   0x1F0406BC
+#define SRM_DI1_DW_SET2_6__EMPTY       0x1F0406BC,0x00000000
+#define SRM_DI1_DW_SET2_6__FULL       0x1F0406BC,0xffffffff
+#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6       0x1F0406BC,0x01FF0000
+#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6       0x1F0406BC,0x000001FF
+
+#define SRM_DI1_DW_SET2_7__ADDR                   0x1F0406C0
+#define SRM_DI1_DW_SET2_7__EMPTY       0x1F0406C0,0x00000000
+#define SRM_DI1_DW_SET2_7__FULL       0x1F0406C0,0xffffffff
+#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7       0x1F0406C0,0x01FF0000
+#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7       0x1F0406C0,0x000001FF
+
+#define SRM_DI1_DW_SET2_8__ADDR                   0x1F0406C4
+#define SRM_DI1_DW_SET2_8__EMPTY       0x1F0406C4,0x00000000
+#define SRM_DI1_DW_SET2_8__FULL       0x1F0406C4,0xffffffff
+#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8       0x1F0406C4,0x01FF0000
+#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8       0x1F0406C4,0x000001FF
+
+#define SRM_DI1_DW_SET2_9__ADDR                   0x1F0406C8
+#define SRM_DI1_DW_SET2_9__EMPTY       0x1F0406C8,0x00000000
+#define SRM_DI1_DW_SET2_9__FULL       0x1F0406C8,0xffffffff
+#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9       0x1F0406C8,0x01FF0000
+#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9       0x1F0406C8,0x000001FF
+
+#define SRM_DI1_DW_SET2_10__ADDR                   0x1F0406CC
+#define SRM_DI1_DW_SET2_10__EMPTY       0x1F0406CC,0x00000000
+#define SRM_DI1_DW_SET2_10__FULL       0x1F0406CC,0xffffffff
+#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10       0x1F0406CC,0x01FF0000
+#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10       0x1F0406CC,0x000001FF
+
+#define SRM_DI1_DW_SET2_11__ADDR                   0x1F0406D0
+#define SRM_DI1_DW_SET2_11__EMPTY       0x1F0406D0,0x00000000
+#define SRM_DI1_DW_SET2_11__FULL       0x1F0406D0,0xffffffff
+#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11       0x1F0406D0,0x01FF0000
+#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11       0x1F0406D0,0x000001FF
+
+#define SRM_DI1_DW_SET3_0__ADDR                   0x1F0406D4
+#define SRM_DI1_DW_SET3_0__EMPTY       0x1F0406D4,0x00000000
+#define SRM_DI1_DW_SET3_0__FULL       0x1F0406D4,0xffffffff
+#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0       0x1F0406D4,0x01FF0000
+#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0       0x1F0406D4,0x000001FF
+
+#define SRM_DI1_DW_SET3_1__ADDR                   0x1F0406D8
+#define SRM_DI1_DW_SET3_1__EMPTY       0x1F0406D8,0x00000000
+#define SRM_DI1_DW_SET3_1__FULL       0x1F0406D8,0xffffffff
+#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1       0x1F0406D8,0x01FF0000
+#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1       0x1F0406D8,0x000001FF
+
+#define SRM_DI1_DW_SET3_2__ADDR                   0x1F0406DC
+#define SRM_DI1_DW_SET3_2__EMPTY       0x1F0406DC,0x00000000
+#define SRM_DI1_DW_SET3_2__FULL       0x1F0406DC,0xffffffff
+#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2       0x1F0406DC,0x01FF0000
+#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2       0x1F0406DC,0x000001FF
+
+#define SRM_DI1_DW_SET3_3__ADDR                   0x1F0406E0
+#define SRM_DI1_DW_SET3_3__EMPTY       0x1F0406E0,0x00000000
+#define SRM_DI1_DW_SET3_3__FULL       0x1F0406E0,0xffffffff
+#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3       0x1F0406E0,0x01FF0000
+#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3       0x1F0406E0,0x000001FF
+
+#define SRM_DI1_DW_SET3_4__ADDR                   0x1F0406E4
+#define SRM_DI1_DW_SET3_4__EMPTY       0x1F0406E4,0x00000000
+#define SRM_DI1_DW_SET3_4__FULL       0x1F0406E4,0xffffffff
+#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4       0x1F0406E4,0x01FF0000
+#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4       0x1F0406E4,0x000001FF
+
+#define SRM_DI1_DW_SET3_5__ADDR                   0x1F0406E8
+#define SRM_DI1_DW_SET3_5__EMPTY       0x1F0406E8,0x00000000
+#define SRM_DI1_DW_SET3_5__FULL       0x1F0406E8,0xffffffff
+#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5       0x1F0406E8,0x01FF0000
+#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5       0x1F0406E8,0x000001FF
+
+#define SRM_DI1_DW_SET3_6__ADDR                   0x1F0406EC
+#define SRM_DI1_DW_SET3_6__EMPTY       0x1F0406EC,0x00000000
+#define SRM_DI1_DW_SET3_6__FULL       0x1F0406EC,0xffffffff
+#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6       0x1F0406EC,0x01FF0000
+#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6       0x1F0406EC,0x000001FF
+
+#define SRM_DI1_DW_SET3_7__ADDR                   0x1F0406F0
+#define SRM_DI1_DW_SET3_7__EMPTY       0x1F0406F0,0x00000000
+#define SRM_DI1_DW_SET3_7__FULL       0x1F0406F0,0xffffffff
+#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7       0x1F0406F0,0x01FF0000
+#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7       0x1F0406F0,0x000001FF
+
+#define SRM_DI1_DW_SET3_8__ADDR                   0x1F0406F4
+#define SRM_DI1_DW_SET3_8__EMPTY       0x1F0406F4,0x00000000
+#define SRM_DI1_DW_SET3_8__FULL       0x1F0406F4,0xffffffff
+#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8       0x1F0406F4,0x01FF0000
+#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8       0x1F0406F4,0x000001FF
+
+#define SRM_DI1_DW_SET3_9__ADDR                   0x1F0406F8
+#define SRM_DI1_DW_SET3_9__EMPTY       0x1F0406F8,0x00000000
+#define SRM_DI1_DW_SET3_9__FULL       0x1F0406F8,0xffffffff
+#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9       0x1F0406F8,0x01FF0000
+#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9       0x1F0406F8,0x000001FF
+
+#define SRM_DI1_DW_SET3_10__ADDR                   0x1F0406FC
+#define SRM_DI1_DW_SET3_10__EMPTY       0x1F0406FC,0x00000000
+#define SRM_DI1_DW_SET3_10__FULL       0x1F0406FC,0xffffffff
+#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10       0x1F0406FC,0x01FF0000
+#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10       0x1F0406FC,0x000001FF
+
+#define SRM_DI1_DW_SET3_11__ADDR                   0x1F040700
+#define SRM_DI1_DW_SET3_11__EMPTY       0x1F040700,0x00000000
+#define SRM_DI1_DW_SET3_11__FULL       0x1F040700,0xffffffff
+#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11       0x1F040700,0x01FF0000
+#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11       0x1F040700,0x000001FF
+
+#define SRM_DI1_STP_REP_1__ADDR                   0x1F040704
+#define SRM_DI1_STP_REP_1__EMPTY       0x1F040704,0x00000000
+#define SRM_DI1_STP_REP_1__FULL       0x1F040704,0xffffffff
+#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_2       0x1F040704,0x0FFF0000
+#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_1       0x1F040704,0x00000FFF
+
+#define SRM_DI1_STP_REP_2__ADDR                   0x1F040708
+#define SRM_DI1_STP_REP_2__EMPTY       0x1F040708,0x00000000
+#define SRM_DI1_STP_REP_2__FULL       0x1F040708,0xffffffff
+#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_4       0x1F040708,0x0FFF0000
+#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_3       0x1F040708,0x00000FFF
+
+#define SRM_DI1_STP_REP_3__ADDR                   0x1F04070C
+#define SRM_DI1_STP_REP_3__EMPTY       0x1F04070C,0x00000000
+#define SRM_DI1_STP_REP_3__FULL       0x1F04070C,0xffffffff
+#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_6       0x1F04070C,0x0FFF0000
+#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_5       0x1F04070C,0x00000FFF
+
+#define SRM_DI1_STP_REP_4__ADDR                   0x1F040710
+#define SRM_DI1_STP_REP_4__EMPTY       0x1F040710,0x00000000
+#define SRM_DI1_STP_REP_4__FULL       0x1F040710,0xffffffff
+#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_8       0x1F040710,0x0FFF0000
+#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_7       0x1F040710,0x00000FFF
+
+#define SRM_DI1_STP_REP_9__ADDR                   0x1F040714
+#define SRM_DI1_STP_REP_9__EMPTY       0x1F040714,0x00000000
+#define SRM_DI1_STP_REP_9__FULL       0x1F040714,0xffffffff
+#define SRM_DI1_STP_REP_9__DI1_STEP_REPEAT_9       0x1F040714,0x00000FFF
+
+#define SRM_DI1_SER_CONF__ADDR                   0x1F040718
+#define SRM_DI1_SER_CONF__EMPTY       0x1F040718,0x00000000
+#define SRM_DI1_SER_CONF__FULL       0x1F040718,0xffffffff
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1       0x1F040718,0xF0000000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0       0x1F040718,0x0F000000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1       0x1F040718,0x00F00000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0       0x1F040718,0x000F0000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LATCH       0x1F040718,0x0000FF00
+#define SRM_DI1_SER_CONF__DI1_LLA_SER_ACCESS       0x1F040718,0x00000020
+#define SRM_DI1_SER_CONF__DI1_SER_CLK_POLARITY       0x1F040718,0x00000010
+#define SRM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY       0x1F040718,0x00000008
+#define SRM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY       0x1F040718,0x00000004
+#define SRM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY       0x1F040718,0x00000002
+#define SRM_DI1_SER_CONF__DI1_WAIT4SERIAL       0x1F040718,0x00000001
+
+#define SRM_DI1_SSC__ADDR                   0x1F04071C
+#define SRM_DI1_SSC__EMPTY       0x1F04071C,0x00000000
+#define SRM_DI1_SSC__FULL       0x1F04071C,0xffffffff
+#define SRM_DI1_SSC__DI1_PIN17_ERM     0x1F04071C,0x00800000
+#define SRM_DI1_SSC__DI1_PIN16_ERM     0x1F04071C,0x00400000
+#define SRM_DI1_SSC__DI1_PIN15_ERM     0x1F04071C,0x00200000
+#define SRM_DI1_SSC__DI1_PIN14_ERM     0x1F04071C,0x00100000
+#define SRM_DI1_SSC__DI1_PIN13_ERM     0x1F04071C,0x00080000
+#define SRM_DI1_SSC__DI1_PIN12_ERM     0x1F04071C,0x00040000
+#define SRM_DI1_SSC__DI1_PIN11_ERM     0x1F04071C,0x00020000
+#define SRM_DI1_SSC__DI1_CS_ERM        0x1F04071C,0x00010000
+#define SRM_DI1_SSC__DI1_WAIT_ON       0x1F04071C,0x00000020
+#define SRM_DI1_SSC__DI1_BYTE_EN_RD_IN       0x1F04071C,0x00000008
+#define SRM_DI1_SSC__DI1_BYTE_EN_PNTR       0x1F04071C,0x00000007
+
+#define SRM_DI1_POL__ADDR                   0x1F040720
+#define SRM_DI1_POL__EMPTY       0x1F040720,0x00000000
+#define SRM_DI1_POL__FULL       0x1F040720,0xffffffff
+#define SRM_DI1_POL__DI1_WAIT_POLARITY       0x1F040720,0x04000000
+#define SRM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY       0x1F040720,0x02000000
+#define SRM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY       0x1F040720,0x01000000
+#define SRM_DI1_POL__DI1_CS1_DATA_POLARITY       0x1F040720,0x00800000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_17       0x1F040720,0x00400000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_16       0x1F040720,0x00200000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_15       0x1F040720,0x00100000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_14       0x1F040720,0x00080000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_13       0x1F040720,0x00040000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_12       0x1F040720,0x00020000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_11       0x1F040720,0x00010000
+#define SRM_DI1_POL__DI1_CS0_DATA_POLARITY       0x1F040720,0x00008000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_17       0x1F040720,0x00004000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_16       0x1F040720,0x00002000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_15       0x1F040720,0x00001000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_14       0x1F040720,0x00000800
+#define SRM_DI1_POL__DI1_CS0_POLARITY_13       0x1F040720,0x00000400
+#define SRM_DI1_POL__DI1_CS0_POLARITY_12       0x1F040720,0x00000200
+#define SRM_DI1_POL__DI1_CS0_POLARITY_11       0x1F040720,0x00000100
+#define SRM_DI1_POL__DI1_DRDY_DATA_POLARITY       0x1F040720,0x00000080
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_17       0x1F040720,0x00000040
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_16       0x1F040720,0x00000020
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_15       0x1F040720,0x00000010
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_14       0x1F040720,0x00000008
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_13       0x1F040720,0x00000004
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_12       0x1F040720,0x00000002
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_11       0x1F040720,0x00000001
+
+#define SRM_DI1_AW0__ADDR                   0x1F040724
+#define SRM_DI1_AW0__EMPTY       0x1F040724,0x00000000
+#define SRM_DI1_AW0__FULL       0x1F040724,0xffffffff
+#define SRM_DI1_AW0__DI1_AW_TRIG_SEL       0x1F040724,0xF0000000
+#define SRM_DI1_AW0__DI1_AW_HEND       0x1F040724,0x0FFF0000
+#define SRM_DI1_AW0__DI1_AW_HCOUNT_SEL       0x1F040724,0x0000F000
+#define SRM_DI1_AW0__DI1_AW_HSTART       0x1F040724,0x00000FFF
+
+#define SRM_DI1_AW1__ADDR                   0x1F040728
+#define SRM_DI1_AW1__EMPTY       0x1F040728,0x00000000
+#define SRM_DI1_AW1__FULL       0x1F040728,0xffffffff
+#define SRM_DI1_AW1__DI1_AW_VEND       0x1F040728,0x0FFF0000
+#define SRM_DI1_AW1__DI1_AW_VCOUNT_SEL       0x1F040728,0x0000F000
+#define SRM_DI1_AW1__DI1_AW_VSTART       0x1F040728,0x00000FFF
+
+#define SRM_DI1_SCR_CONF__ADDR                   0x1F04072C
+#define SRM_DI1_SCR_CONF__EMPTY       0x1F04072C,0x00000000
+#define SRM_DI1_SCR_CONF__FULL       0x1F04072C,0xffffffff
+#define SRM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT       0x1F04072C,0x00000FFF
+
+#define SRM_DC_WR_CH_CONF_2__ADDR                   0x1F040410
+#define SRM_DC_WR_CH_CONF_2__EMPTY       0x1F040410,0x00000000
+#define SRM_DC_WR_CH_CONF_2__FULL       0x1F040410,0xffffffff
+#define SRM_DC_WR_CH_CONF_2__PROG_START_TIME_2       0x1F040410,0x07FF0000
+#define SRM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2       0x1F040410,0x00000100
+#define SRM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2       0x1F040410,0x000000E0
+#define SRM_DC_WR_CH_CONF_2__PROG_DISP_ID_2       0x1F040410,0x00000018
+#define SRM_DC_WR_CH_CONF_2__PROG_DI_ID_2       0x1F040410,0x00000004
+#define SRM_DC_WR_CH_CONF_2__W_SIZE_2       0x1F040410,0x00000003
+
+#define SRM_DC_WR_CH_ADDR_2__ADDR                   0x1F040414
+#define SRM_DC_WR_CH_ADDR_2__EMPTY       0x1F040414,0x00000000
+#define SRM_DC_WR_CH_ADDR_2__FULL       0x1F040414,0xffffffff
+#define SRM_DC_WR_CH_ADDR_2__ST_ADDR_2       0x1F040414,0x1FFFFFFF
+
+#define SRM_DC_RL0_CH_2__ADDR                   0x1F040418
+#define SRM_DC_RL0_CH_2__EMPTY       0x1F040418,0x00000000
+#define SRM_DC_RL0_CH_2__FULL       0x1F040418,0xffffffff
+#define SRM_DC_RL0_CH_2__COD_NL_START_CHAN_2       0x1F040418,0xFF000000
+#define SRM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2       0x1F040418,0x000F0000
+#define SRM_DC_RL0_CH_2__COD_NF_START_CHAN_2       0x1F040418,0x0000FF00
+#define SRM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2       0x1F040418,0x0000000F
+
+#define SRM_DC_RL1_CH_2__ADDR                   0x1F04041C
+#define SRM_DC_RL1_CH_2__EMPTY       0x1F04041C,0x00000000
+#define SRM_DC_RL1_CH_2__FULL       0x1F04041C,0xffffffff
+#define SRM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2       0x1F04041C,0xFF000000
+#define SRM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2       0x1F04041C,0x000F0000
+#define SRM_DC_RL1_CH_2__COD_EOF_START_CHAN_2       0x1F04041C,0x0000FF00
+#define SRM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2       0x1F04041C,0x0000000F
+
+#define SRM_DC_RL2_CH_2__ADDR                   0x1F040420
+#define SRM_DC_RL2_CH_2__EMPTY       0x1F040420,0x00000000
+#define SRM_DC_RL2_CH_2__FULL       0x1F040420,0xffffffff
+#define SRM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2       0x1F040420,0xFF000000
+#define SRM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2       0x1F040420,0x000F0000
+#define SRM_DC_RL2_CH_2__COD_EOL_START_CHAN_2       0x1F040420,0x0000FF00
+#define SRM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2       0x1F040420,0x0000000F
+
+#define SRM_DC_RL3_CH_2__ADDR                   0x1F040424
+#define SRM_DC_RL3_CH_2__EMPTY       0x1F040424,0x00000000
+#define SRM_DC_RL3_CH_2__FULL       0x1F040424,0xffffffff
+#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2       0x1F040424,0xFF000000
+#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2       0x1F040424,0x000F0000
+#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2       0x1F040424,0x0000FF00
+#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2       0x1F040424,0x0000000F
+
+#define SRM_DC_RL4_CH_2__ADDR                   0x1F040428
+#define SRM_DC_RL4_CH_2__EMPTY       0x1F040428,0x00000000
+#define SRM_DC_RL4_CH_2__FULL       0x1F040428,0xffffffff
+#define SRM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2       0x1F040428,0x0000FF00
+#define SRM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2       0x1F040428,0x0000000F
+
+#define SRM_DC_WR_CH_CONF_6__ADDR                   0x1F04042C
+#define SRM_DC_WR_CH_CONF_6__EMPTY       0x1F04042C,0x00000000
+#define SRM_DC_WR_CH_CONF_6__FULL       0x1F04042C,0xffffffff
+#define SRM_DC_WR_CH_CONF_6__PROG_START_TIME_6       0x1F04042C,0x07FF0000
+#define SRM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6       0x1F04042C,0x00000100
+#define SRM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6       0x1F04042C,0x000000E0
+#define SRM_DC_WR_CH_CONF_6__PROG_DISP_ID_6       0x1F04042C,0x00000018
+#define SRM_DC_WR_CH_CONF_6__PROG_DI_ID_6       0x1F04042C,0x00000004
+#define SRM_DC_WR_CH_CONF_6__W_SIZE_6       0x1F04042C,0x00000003
+
+#define SRM_DC_WR_CH_ADDR_6__ADDR                   0x1F040430
+#define SRM_DC_WR_CH_ADDR_6__EMPTY       0x1F040430,0x00000000
+#define SRM_DC_WR_CH_ADDR_6__FULL       0x1F040430,0xffffffff
+#define SRM_DC_WR_CH_ADDR_6__ST_ADDR_6       0x1F040430,0x1FFFFFFF
+
+#define SRM_DC_RL0_CH_6__ADDR                   0x1F040434
+#define SRM_DC_RL0_CH_6__EMPTY       0x1F040434,0x00000000
+#define SRM_DC_RL0_CH_6__FULL       0x1F040434,0xffffffff
+#define SRM_DC_RL0_CH_6__COD_NL_START_CHAN_6       0x1F040434,0xFF000000
+#define SRM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6       0x1F040434,0x000F0000
+#define SRM_DC_RL0_CH_6__COD_NF_START_CHAN_6       0x1F040434,0x0000FF00
+#define SRM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6       0x1F040434,0x0000000F
+
+#define SRM_DC_RL1_CH_6__ADDR                   0x1F040438
+#define SRM_DC_RL1_CH_6__EMPTY       0x1F040438,0x00000000
+#define SRM_DC_RL1_CH_6__FULL       0x1F040438,0xffffffff
+#define SRM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6       0x1F040438,0xFF000000
+#define SRM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6       0x1F040438,0x000F0000
+#define SRM_DC_RL1_CH_6__COD_EOF_START_CHAN_6       0x1F040438,0x0000FF00
+#define SRM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6       0x1F040438,0x0000000F
+
+#define SRM_DC_RL2_CH_6__ADDR                   0x1F04043C
+#define SRM_DC_RL2_CH_6__EMPTY       0x1F04043C,0x00000000
+#define SRM_DC_RL2_CH_6__FULL       0x1F04043C,0xffffffff
+#define SRM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6       0x1F04043C,0xFF000000
+#define SRM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6       0x1F04043C,0x000F0000
+#define SRM_DC_RL2_CH_6__COD_EOL_START_CHAN_6       0x1F04043C,0x0000FF00
+#define SRM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6       0x1F04043C,0x0000000F
+
+#define SRM_DC_RL3_CH_6__ADDR                   0x1F040440
+#define SRM_DC_RL3_CH_6__EMPTY       0x1F040440,0x00000000
+#define SRM_DC_RL3_CH_6__FULL       0x1F040440,0xffffffff
+#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6       0x1F040440,0xFF000000
+#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6       0x1F040440,0x000F0000
+#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6       0x1F040440,0x0000FF00
+#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6       0x1F040440,0x0000000F
+
+#define SRM_DC_RL4_CH_6__ADDR                   0x1F040444
+#define SRM_DC_RL4_CH_6__EMPTY       0x1F040444,0x00000000
+#define SRM_DC_RL4_CH_6__FULL       0x1F040444,0xffffffff
+#define SRM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6       0x1F040444,0x0000FF00
+#define SRM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6       0x1F040444,0x0000000F
+
+#define IPU_MEM_DC_MICROCODE_BASE_ADDR 0x1F080000
+
+#define LPM_MEM_DI0_GENERAL__ADDR                   0x1F040118
+#define LPM_MEM_DI0_GENERAL__EMPTY       0x1F040118,0x00000000
+#define LPM_MEM_DI0_GENERAL__FULL       0x1F040118,0xffffffff
+#define LPM_MEM_DI0_GENERAL__DI0_DISP_Y_SEL       0x1F040118,0x70000000
+#define LPM_MEM_DI0_GENERAL__DI0_CLOCK_STOP_MODE       0x1F040118,0x0F000000
+#define LPM_MEM_DI0_GENERAL__DI0_DISP_CLOCK_INIT       0x1F040118,0x00800000
+#define LPM_MEM_DI0_GENERAL__DI0_MASK_SEL       0x1F040118,0x00400000
+#define LPM_MEM_DI0_GENERAL__DI0_VSYNC_EXT       0x1F040118,0x00200000
+#define LPM_MEM_DI0_GENERAL__DI0_CLK_EXT       0x1F040118,0x00100000
+#define LPM_MEM_DI0_GENERAL__DI0_WATCHDOG_MODE       0x1F040118,0x000C0000
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_DISP_CLK       0x1F040118,0x00020000
+#define LPM_MEM_DI0_GENERAL__DI0_SYNC_COUNT_SEL       0x1F040118,0x0000F000
+#define LPM_MEM_DI0_GENERAL__DI0_ERR_TREATMENT       0x1F040118,0x00000800
+#define LPM_MEM_DI0_GENERAL__DI0_ERM_VSYNC_SEL     0x1F040118,0x00000400
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS1       0x1F040118,0x00000200
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS0       0x1F040118,0x00000100
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_8       0x1F040118,0x00000080
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_7       0x1F040118,0x00000040
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_6       0x1F040118,0x00000020
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_5       0x1F040118,0x00000010
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_4       0x1F040118,0x00000008
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_3       0x1F040118,0x00000004
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_2       0x1F040118,0x00000002
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_1       0x1F040118,0x00000001
+
+#define LPM_MEM_DI0_BS_CLKGEN0__ADDR                   0x1F04011C
+#define LPM_MEM_DI0_BS_CLKGEN0__EMPTY       0x1F04011C,0x00000000
+#define LPM_MEM_DI0_BS_CLKGEN0__FULL       0x1F04011C,0xffffffff
+#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET       0x1F04011C,0x01FF0000
+#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD       0x1F04011C,0x00000FFF
+
+#define LPM_MEM_DI0_BS_CLKGEN1__ADDR                   0x1F040120
+#define LPM_MEM_DI0_BS_CLKGEN1__EMPTY       0x1F040120,0x00000000
+#define LPM_MEM_DI0_BS_CLKGEN1__FULL       0x1F040120,0xffffffff
+#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN       0x1F040120,0x01FF0000
+#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP       0x1F040120,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN0_1__ADDR                   0x1F040124
+#define LPM_MEM_DI0_SW_GEN0_1__EMPTY       0x1F040124,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_1__FULL       0x1F040124,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1       0x1F040124,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1       0x1F040124,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1       0x1F040124,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1       0x1F040124,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_2__ADDR                   0x1F040128
+#define LPM_MEM_DI0_SW_GEN0_2__EMPTY       0x1F040128,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_2__FULL       0x1F040128,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2       0x1F040128,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2       0x1F040128,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2       0x1F040128,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2       0x1F040128,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_3__ADDR                   0x1F04012C
+#define LPM_MEM_DI0_SW_GEN0_3__EMPTY       0x1F04012C,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_3__FULL       0x1F04012C,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3       0x1F04012C,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3       0x1F04012C,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3       0x1F04012C,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3       0x1F04012C,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_4__ADDR                   0x1F040130
+#define LPM_MEM_DI0_SW_GEN0_4__EMPTY       0x1F040130,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_4__FULL       0x1F040130,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4       0x1F040130,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4       0x1F040130,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4       0x1F040130,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4       0x1F040130,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_5__ADDR                   0x1F040134
+#define LPM_MEM_DI0_SW_GEN0_5__EMPTY       0x1F040134,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_5__FULL       0x1F040134,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5       0x1F040134,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5       0x1F040134,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5       0x1F040134,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5       0x1F040134,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_6__ADDR                   0x1F040138
+#define LPM_MEM_DI0_SW_GEN0_6__EMPTY       0x1F040138,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_6__FULL       0x1F040138,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6       0x1F040138,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6       0x1F040138,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6       0x1F040138,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6       0x1F040138,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_7__ADDR                   0x1F04013C
+#define LPM_MEM_DI0_SW_GEN0_7__EMPTY       0x1F04013C,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_7__FULL       0x1F04013C,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7       0x1F04013C,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7       0x1F04013C,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7       0x1F04013C,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7       0x1F04013C,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_8__ADDR                   0x1F040140
+#define LPM_MEM_DI0_SW_GEN0_8__EMPTY       0x1F040140,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_8__FULL       0x1F040140,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8       0x1F040140,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8       0x1F040140,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8       0x1F040140,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8       0x1F040140,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_9__ADDR                   0x1F040144
+#define LPM_MEM_DI0_SW_GEN0_9__EMPTY       0x1F040144,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_9__FULL       0x1F040144,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9       0x1F040144,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9       0x1F040144,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9       0x1F040144,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9       0x1F040144,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN1_1__ADDR                   0x1F040148
+#define LPM_MEM_DI0_SW_GEN1_1__EMPTY       0x1F040148,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_1__FULL       0x1F040148,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1       0x1F040148,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1       0x1F040148,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1       0x1F040148,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1       0x1F040148,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1       0x1F040148,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1       0x1F040148,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_UP_1       0x1F040148,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_2__ADDR                   0x1F04014C
+#define LPM_MEM_DI0_SW_GEN1_2__EMPTY       0x1F04014C,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_2__FULL       0x1F04014C,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2       0x1F04014C,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2       0x1F04014C,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2       0x1F04014C,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2       0x1F04014C,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2       0x1F04014C,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2       0x1F04014C,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_UP_2       0x1F04014C,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_3__ADDR                   0x1F040150
+#define LPM_MEM_DI0_SW_GEN1_3__EMPTY       0x1F040150,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_3__FULL       0x1F040150,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3       0x1F040150,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3       0x1F040150,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3       0x1F040150,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3       0x1F040150,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3       0x1F040150,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3       0x1F040150,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_UP_3       0x1F040150,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_4__ADDR                   0x1F040154
+#define LPM_MEM_DI0_SW_GEN1_4__EMPTY       0x1F040154,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_4__FULL       0x1F040154,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4       0x1F040154,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4       0x1F040154,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4       0x1F040154,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4       0x1F040154,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4       0x1F040154,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4       0x1F040154,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_UP_4       0x1F040154,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_5__ADDR                   0x1F040158
+#define LPM_MEM_DI0_SW_GEN1_5__EMPTY       0x1F040158,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_5__FULL       0x1F040158,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5       0x1F040158,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5       0x1F040158,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5       0x1F040158,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5       0x1F040158,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5       0x1F040158,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5       0x1F040158,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_UP_5       0x1F040158,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_6__ADDR                   0x1F04015C
+#define LPM_MEM_DI0_SW_GEN1_6__EMPTY       0x1F04015C,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_6__FULL       0x1F04015C,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6       0x1F04015C,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6       0x1F04015C,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6       0x1F04015C,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6       0x1F04015C,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6       0x1F04015C,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6       0x1F04015C,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_UP_6       0x1F04015C,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_7__ADDR                   0x1F040160
+#define LPM_MEM_DI0_SW_GEN1_7__EMPTY       0x1F040160,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_7__FULL       0x1F040160,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7       0x1F040160,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7       0x1F040160,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7       0x1F040160,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7       0x1F040160,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7       0x1F040160,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7       0x1F040160,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_UP_7       0x1F040160,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_8__ADDR                   0x1F040164
+#define LPM_MEM_DI0_SW_GEN1_8__EMPTY       0x1F040164,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_8__FULL       0x1F040164,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8       0x1F040164,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8       0x1F040164,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8       0x1F040164,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8       0x1F040164,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8       0x1F040164,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8       0x1F040164,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_UP_8       0x1F040164,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_9__ADDR                   0x1F040168
+#define LPM_MEM_DI0_SW_GEN1_9__EMPTY       0x1F040168,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_9__FULL       0x1F040168,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9       0x1F040168,0xE0000000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9       0x1F040168,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9       0x1F040168,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9       0x1F040168,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_TAG_SEL_9       0x1F040168,0x00008000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_UP_9       0x1F040168,0x000001FF
+
+#define LPM_MEM_DI0_SYNC_AS_GEN__ADDR                   0x1F04016C
+#define LPM_MEM_DI0_SYNC_AS_GEN__EMPTY       0x1F04016C,0x00000000
+#define LPM_MEM_DI0_SYNC_AS_GEN__FULL       0x1F04016C,0xffffffff
+#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN       0x1F04016C,0x10000000
+#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL       0x1F04016C,0x0000E000
+#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START       0x1F04016C,0x00000FFF
+
+#define LPM_MEM_DI0_DW_GEN_0__ADDR                   0x1F040170
+#define LPM_MEM_DI0_DW_GEN_0__EMPTY       0x1F040170,0x00000000
+#define LPM_MEM_DI0_DW_GEN_0__FULL       0x1F040170,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0       0x1F040170,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0       0x1F040170,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0       0x1F040170,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_6_0       0x1F040170,0x00003000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_5_0       0x1F040170,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_4_0       0x1F040170,0x00000300
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_3_0       0x1F040170,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_2_0       0x1F040170,0x00000030
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_1_0       0x1F040170,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_0_0       0x1F040170,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_0__ADDR                   0x1F040170
+#define LPM_MEM_DI0_DW_GEN_0__EMPTY       0x1F040170,0x00000000
+#define LPM_MEM_DI0_DW_GEN_0__FULL       0x1F040170,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0       0x1F040170,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_START_PERIOD_0       0x1F040170,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0       0x1F040170,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0       0x1F040170,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_RS_0       0x1F040170,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0       0x1F040170,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_1__ADDR                   0x1F040174
+#define LPM_MEM_DI0_DW_GEN_1__EMPTY       0x1F040174,0x00000000
+#define LPM_MEM_DI0_DW_GEN_1__FULL       0x1F040174,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1       0x1F040174,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1       0x1F040174,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1       0x1F040174,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_6_1       0x1F040174,0x00003000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_5_1       0x1F040174,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_4_1       0x1F040174,0x00000300
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_3_1       0x1F040174,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_2_1       0x1F040174,0x00000030
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_1_1       0x1F040174,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_0_1       0x1F040174,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_1__ADDR                   0x1F040174
+#define LPM_MEM_DI0_DW_GEN_1__EMPTY       0x1F040174,0x00000000
+#define LPM_MEM_DI0_DW_GEN_1__FULL       0x1F040174,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1       0x1F040174,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_START_PERIOD_1       0x1F040174,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1       0x1F040174,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1       0x1F040174,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_RS_1       0x1F040174,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1       0x1F040174,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_2__ADDR                   0x1F040178
+#define LPM_MEM_DI0_DW_GEN_2__EMPTY       0x1F040178,0x00000000
+#define LPM_MEM_DI0_DW_GEN_2__FULL       0x1F040178,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2       0x1F040178,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2       0x1F040178,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2       0x1F040178,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_6_2       0x1F040178,0x00003000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_5_2       0x1F040178,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_4_2       0x1F040178,0x00000300
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_3_2       0x1F040178,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_2_2       0x1F040178,0x00000030
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_1_2       0x1F040178,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_0_2       0x1F040178,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_2__ADDR                   0x1F040178
+#define LPM_MEM_DI0_DW_GEN_2__EMPTY       0x1F040178,0x00000000
+#define LPM_MEM_DI0_DW_GEN_2__FULL       0x1F040178,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2       0x1F040178,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_START_PERIOD_2       0x1F040178,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2       0x1F040178,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2       0x1F040178,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_RS_2       0x1F040178,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2       0x1F040178,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_3__ADDR                   0x1F04017C
+#define LPM_MEM_DI0_DW_GEN_3__EMPTY       0x1F04017C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_3__FULL       0x1F04017C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3       0x1F04017C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3       0x1F04017C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3       0x1F04017C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_6_3       0x1F04017C,0x00003000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_5_3       0x1F04017C,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_4_3       0x1F04017C,0x00000300
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_3_3       0x1F04017C,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_2_3       0x1F04017C,0x00000030
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_1_3       0x1F04017C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_0_3       0x1F04017C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_3__ADDR                   0x1F04017C
+#define LPM_MEM_DI0_DW_GEN_3__EMPTY       0x1F04017C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_3__FULL       0x1F04017C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3       0x1F04017C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_START_PERIOD_3       0x1F04017C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3       0x1F04017C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3       0x1F04017C,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_RS_3       0x1F04017C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3       0x1F04017C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_4__ADDR                   0x1F040180
+#define LPM_MEM_DI0_DW_GEN_4__EMPTY       0x1F040180,0x00000000
+#define LPM_MEM_DI0_DW_GEN_4__FULL       0x1F040180,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4       0x1F040180,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4       0x1F040180,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4       0x1F040180,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_6_4       0x1F040180,0x00003000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_5_4       0x1F040180,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_4_4       0x1F040180,0x00000300
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_3_4       0x1F040180,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_2_4       0x1F040180,0x00000030
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_1_4       0x1F040180,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_0_4       0x1F040180,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_4__ADDR                   0x1F040180
+#define LPM_MEM_DI0_DW_GEN_4__EMPTY       0x1F040180,0x00000000
+#define LPM_MEM_DI0_DW_GEN_4__FULL       0x1F040180,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4       0x1F040180,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_START_PERIOD_4       0x1F040180,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4       0x1F040180,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4       0x1F040180,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_RS_4       0x1F040180,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4       0x1F040180,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_5__ADDR                   0x1F040184
+#define LPM_MEM_DI0_DW_GEN_5__EMPTY       0x1F040184,0x00000000
+#define LPM_MEM_DI0_DW_GEN_5__FULL       0x1F040184,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5       0x1F040184,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5       0x1F040184,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5       0x1F040184,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_6_5       0x1F040184,0x00003000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_5_5       0x1F040184,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_4_5       0x1F040184,0x00000300
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_3_5       0x1F040184,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_2_5       0x1F040184,0x00000030
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_1_5       0x1F040184,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_0_5       0x1F040184,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_5__ADDR                   0x1F040184
+#define LPM_MEM_DI0_DW_GEN_5__EMPTY       0x1F040184,0x00000000
+#define LPM_MEM_DI0_DW_GEN_5__FULL       0x1F040184,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5       0x1F040184,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_START_PERIOD_5       0x1F040184,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5       0x1F040184,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5       0x1F040184,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_RS_5       0x1F040184,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5       0x1F040184,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_6__ADDR                   0x1F040188
+#define LPM_MEM_DI0_DW_GEN_6__EMPTY       0x1F040188,0x00000000
+#define LPM_MEM_DI0_DW_GEN_6__FULL       0x1F040188,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6       0x1F040188,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6       0x1F040188,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6       0x1F040188,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_6_6       0x1F040188,0x00003000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_5_6       0x1F040188,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_4_6       0x1F040188,0x00000300
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_3_6       0x1F040188,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_2_6       0x1F040188,0x00000030
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_1_6       0x1F040188,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_0_6       0x1F040188,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_6__ADDR                   0x1F040188
+#define LPM_MEM_DI0_DW_GEN_6__EMPTY       0x1F040188,0x00000000
+#define LPM_MEM_DI0_DW_GEN_6__FULL       0x1F040188,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6       0x1F040188,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_START_PERIOD_6       0x1F040188,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6       0x1F040188,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6       0x1F040188,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_RS_6       0x1F040188,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6       0x1F040188,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_7__ADDR                   0x1F04018C
+#define LPM_MEM_DI0_DW_GEN_7__EMPTY       0x1F04018C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_7__FULL       0x1F04018C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7       0x1F04018C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7       0x1F04018C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7       0x1F04018C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_6_7       0x1F04018C,0x00003000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_5_7       0x1F04018C,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_4_7       0x1F04018C,0x00000300
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_3_7       0x1F04018C,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_2_7       0x1F04018C,0x00000030
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_1_7       0x1F04018C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_0_7       0x1F04018C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_7__ADDR                   0x1F04018C
+#define LPM_MEM_DI0_DW_GEN_7__EMPTY       0x1F04018C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_7__FULL       0x1F04018C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7       0x1F04018C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_START_PERIOD_7       0x1F04018C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7       0x1F04018C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7       0x1F04018C,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_RS_7       0x1F04018C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7       0x1F04018C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_8__ADDR                   0x1F040190
+#define LPM_MEM_DI0_DW_GEN_8__EMPTY       0x1F040190,0x00000000
+#define LPM_MEM_DI0_DW_GEN_8__FULL       0x1F040190,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8       0x1F040190,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8       0x1F040190,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8       0x1F040190,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_6_8       0x1F040190,0x00003000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_5_8       0x1F040190,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_4_8       0x1F040190,0x00000300
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_3_8       0x1F040190,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_2_8       0x1F040190,0x00000030
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_1_8       0x1F040190,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_0_8       0x1F040190,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_8__ADDR                   0x1F040190
+#define LPM_MEM_DI0_DW_GEN_8__EMPTY       0x1F040190,0x00000000
+#define LPM_MEM_DI0_DW_GEN_8__FULL       0x1F040190,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8       0x1F040190,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_START_PERIOD_8       0x1F040190,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8       0x1F040190,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8       0x1F040190,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_RS_8       0x1F040190,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8       0x1F040190,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_9__ADDR                   0x1F040194
+#define LPM_MEM_DI0_DW_GEN_9__EMPTY       0x1F040194,0x00000000
+#define LPM_MEM_DI0_DW_GEN_9__FULL       0x1F040194,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9       0x1F040194,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9       0x1F040194,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9       0x1F040194,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_6_9       0x1F040194,0x00003000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_5_9       0x1F040194,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_4_9       0x1F040194,0x00000300
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_3_9       0x1F040194,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_2_9       0x1F040194,0x00000030
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_1_9       0x1F040194,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_0_9       0x1F040194,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_9__ADDR                   0x1F040194
+#define LPM_MEM_DI0_DW_GEN_9__EMPTY       0x1F040194,0x00000000
+#define LPM_MEM_DI0_DW_GEN_9__FULL       0x1F040194,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9       0x1F040194,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_START_PERIOD_9       0x1F040194,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9       0x1F040194,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9       0x1F040194,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_RS_9       0x1F040194,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9       0x1F040194,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_10__ADDR                   0x1F040198
+#define LPM_MEM_DI0_DW_GEN_10__EMPTY       0x1F040198,0x00000000
+#define LPM_MEM_DI0_DW_GEN_10__FULL       0x1F040198,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10       0x1F040198,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10       0x1F040198,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10       0x1F040198,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_6_10       0x1F040198,0x00003000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_5_10       0x1F040198,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_4_10       0x1F040198,0x00000300
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_3_10       0x1F040198,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_2_10       0x1F040198,0x00000030
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_1_10       0x1F040198,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_0_10       0x1F040198,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_10__ADDR                   0x1F040198
+#define LPM_MEM_DI0_DW_GEN_10__EMPTY       0x1F040198,0x00000000
+#define LPM_MEM_DI0_DW_GEN_10__FULL       0x1F040198,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10       0x1F040198,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_START_PERIOD_10       0x1F040198,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10       0x1F040198,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10       0x1F040198,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_RS_10       0x1F040198,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10       0x1F040198,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_11__ADDR                   0x1F04019C
+#define LPM_MEM_DI0_DW_GEN_11__EMPTY       0x1F04019C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_11__FULL       0x1F04019C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11       0x1F04019C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11       0x1F04019C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11       0x1F04019C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_6_11       0x1F04019C,0x00003000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_5_11       0x1F04019C,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_4_11       0x1F04019C,0x00000300
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_3_11       0x1F04019C,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_2_11       0x1F04019C,0x00000030
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_1_11       0x1F04019C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_0_11       0x1F04019C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_11__ADDR                   0x1F04019C
+#define LPM_MEM_DI0_DW_GEN_11__EMPTY       0x1F04019C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_11__FULL       0x1F04019C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11       0x1F04019C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_START_PERIOD_11       0x1F04019C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11       0x1F04019C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11       0x1F04019C,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_RS_11       0x1F04019C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11       0x1F04019C,0x00000003
+
+#define LPM_MEM_DI0_DW_SET0_0__ADDR                   0x1F0401A0
+#define LPM_MEM_DI0_DW_SET0_0__EMPTY       0x1F0401A0,0x00000000
+#define LPM_MEM_DI0_DW_SET0_0__FULL       0x1F0401A0,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0       0x1F0401A0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0       0x1F0401A0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_1__ADDR                   0x1F0401A4
+#define LPM_MEM_DI0_DW_SET0_1__EMPTY       0x1F0401A4,0x00000000
+#define LPM_MEM_DI0_DW_SET0_1__FULL       0x1F0401A4,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1       0x1F0401A4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1       0x1F0401A4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_2__ADDR                   0x1F0401A8
+#define LPM_MEM_DI0_DW_SET0_2__EMPTY       0x1F0401A8,0x00000000
+#define LPM_MEM_DI0_DW_SET0_2__FULL       0x1F0401A8,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2       0x1F0401A8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2       0x1F0401A8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_3__ADDR                   0x1F0401AC
+#define LPM_MEM_DI0_DW_SET0_3__EMPTY       0x1F0401AC,0x00000000
+#define LPM_MEM_DI0_DW_SET0_3__FULL       0x1F0401AC,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3       0x1F0401AC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3       0x1F0401AC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_4__ADDR                   0x1F0401B0
+#define LPM_MEM_DI0_DW_SET0_4__EMPTY       0x1F0401B0,0x00000000
+#define LPM_MEM_DI0_DW_SET0_4__FULL       0x1F0401B0,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4       0x1F0401B0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4       0x1F0401B0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_5__ADDR                   0x1F0401B4
+#define LPM_MEM_DI0_DW_SET0_5__EMPTY       0x1F0401B4,0x00000000
+#define LPM_MEM_DI0_DW_SET0_5__FULL       0x1F0401B4,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5       0x1F0401B4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5       0x1F0401B4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_6__ADDR                   0x1F0401B8
+#define LPM_MEM_DI0_DW_SET0_6__EMPTY       0x1F0401B8,0x00000000
+#define LPM_MEM_DI0_DW_SET0_6__FULL       0x1F0401B8,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6       0x1F0401B8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6       0x1F0401B8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_7__ADDR                   0x1F0401BC
+#define LPM_MEM_DI0_DW_SET0_7__EMPTY       0x1F0401BC,0x00000000
+#define LPM_MEM_DI0_DW_SET0_7__FULL       0x1F0401BC,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7       0x1F0401BC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7       0x1F0401BC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_8__ADDR                   0x1F0401C0
+#define LPM_MEM_DI0_DW_SET0_8__EMPTY       0x1F0401C0,0x00000000
+#define LPM_MEM_DI0_DW_SET0_8__FULL       0x1F0401C0,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8       0x1F0401C0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8       0x1F0401C0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_9__ADDR                   0x1F0401C4
+#define LPM_MEM_DI0_DW_SET0_9__EMPTY       0x1F0401C4,0x00000000
+#define LPM_MEM_DI0_DW_SET0_9__FULL       0x1F0401C4,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9       0x1F0401C4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9       0x1F0401C4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_10__ADDR                   0x1F0401C8
+#define LPM_MEM_DI0_DW_SET0_10__EMPTY       0x1F0401C8,0x00000000
+#define LPM_MEM_DI0_DW_SET0_10__FULL       0x1F0401C8,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10       0x1F0401C8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10       0x1F0401C8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_11__ADDR                   0x1F0401CC
+#define LPM_MEM_DI0_DW_SET0_11__EMPTY       0x1F0401CC,0x00000000
+#define LPM_MEM_DI0_DW_SET0_11__FULL       0x1F0401CC,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11       0x1F0401CC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11       0x1F0401CC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_0__ADDR                   0x1F0401D0
+#define LPM_MEM_DI0_DW_SET1_0__EMPTY       0x1F0401D0,0x00000000
+#define LPM_MEM_DI0_DW_SET1_0__FULL       0x1F0401D0,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0       0x1F0401D0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0       0x1F0401D0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_1__ADDR                   0x1F0401D4
+#define LPM_MEM_DI0_DW_SET1_1__EMPTY       0x1F0401D4,0x00000000
+#define LPM_MEM_DI0_DW_SET1_1__FULL       0x1F0401D4,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1       0x1F0401D4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1       0x1F0401D4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_2__ADDR                   0x1F0401D8
+#define LPM_MEM_DI0_DW_SET1_2__EMPTY       0x1F0401D8,0x00000000
+#define LPM_MEM_DI0_DW_SET1_2__FULL       0x1F0401D8,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2       0x1F0401D8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2       0x1F0401D8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_3__ADDR                   0x1F0401DC
+#define LPM_MEM_DI0_DW_SET1_3__EMPTY       0x1F0401DC,0x00000000
+#define LPM_MEM_DI0_DW_SET1_3__FULL       0x1F0401DC,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3       0x1F0401DC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3       0x1F0401DC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_4__ADDR                   0x1F0401E0
+#define LPM_MEM_DI0_DW_SET1_4__EMPTY       0x1F0401E0,0x00000000
+#define LPM_MEM_DI0_DW_SET1_4__FULL       0x1F0401E0,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4       0x1F0401E0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4       0x1F0401E0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_5__ADDR                   0x1F0401E4
+#define LPM_MEM_DI0_DW_SET1_5__EMPTY       0x1F0401E4,0x00000000
+#define LPM_MEM_DI0_DW_SET1_5__FULL       0x1F0401E4,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5       0x1F0401E4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5       0x1F0401E4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_6__ADDR                   0x1F0401E8
+#define LPM_MEM_DI0_DW_SET1_6__EMPTY       0x1F0401E8,0x00000000
+#define LPM_MEM_DI0_DW_SET1_6__FULL       0x1F0401E8,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6       0x1F0401E8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6       0x1F0401E8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_7__ADDR                   0x1F0401EC
+#define LPM_MEM_DI0_DW_SET1_7__EMPTY       0x1F0401EC,0x00000000
+#define LPM_MEM_DI0_DW_SET1_7__FULL       0x1F0401EC,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7       0x1F0401EC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7       0x1F0401EC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_8__ADDR                   0x1F0401F0
+#define LPM_MEM_DI0_DW_SET1_8__EMPTY       0x1F0401F0,0x00000000
+#define LPM_MEM_DI0_DW_SET1_8__FULL       0x1F0401F0,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8       0x1F0401F0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8       0x1F0401F0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_9__ADDR                   0x1F0401F4
+#define LPM_MEM_DI0_DW_SET1_9__EMPTY       0x1F0401F4,0x00000000
+#define LPM_MEM_DI0_DW_SET1_9__FULL       0x1F0401F4,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9       0x1F0401F4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9       0x1F0401F4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_10__ADDR                   0x1F0401F8
+#define LPM_MEM_DI0_DW_SET1_10__EMPTY       0x1F0401F8,0x00000000
+#define LPM_MEM_DI0_DW_SET1_10__FULL       0x1F0401F8,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10       0x1F0401F8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10       0x1F0401F8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_11__ADDR                   0x1F0401FC
+#define LPM_MEM_DI0_DW_SET1_11__EMPTY       0x1F0401FC,0x00000000
+#define LPM_MEM_DI0_DW_SET1_11__FULL       0x1F0401FC,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11       0x1F0401FC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11       0x1F0401FC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_0__ADDR                   0x1F040200
+#define LPM_MEM_DI0_DW_SET2_0__EMPTY       0x1F040200,0x00000000
+#define LPM_MEM_DI0_DW_SET2_0__FULL       0x1F040200,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0       0x1F040200,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0       0x1F040200,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_1__ADDR                   0x1F040204
+#define LPM_MEM_DI0_DW_SET2_1__EMPTY       0x1F040204,0x00000000
+#define LPM_MEM_DI0_DW_SET2_1__FULL       0x1F040204,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1       0x1F040204,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1       0x1F040204,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_2__ADDR                   0x1F040208
+#define LPM_MEM_DI0_DW_SET2_2__EMPTY       0x1F040208,0x00000000
+#define LPM_MEM_DI0_DW_SET2_2__FULL       0x1F040208,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2       0x1F040208,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2       0x1F040208,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_3__ADDR                   0x1F04020C
+#define LPM_MEM_DI0_DW_SET2_3__EMPTY       0x1F04020C,0x00000000
+#define LPM_MEM_DI0_DW_SET2_3__FULL       0x1F04020C,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3       0x1F04020C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3       0x1F04020C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_4__ADDR                   0x1F040210
+#define LPM_MEM_DI0_DW_SET2_4__EMPTY       0x1F040210,0x00000000
+#define LPM_MEM_DI0_DW_SET2_4__FULL       0x1F040210,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4       0x1F040210,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4       0x1F040210,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_5__ADDR                   0x1F040214
+#define LPM_MEM_DI0_DW_SET2_5__EMPTY       0x1F040214,0x00000000
+#define LPM_MEM_DI0_DW_SET2_5__FULL       0x1F040214,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5       0x1F040214,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5       0x1F040214,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_6__ADDR                   0x1F040218
+#define LPM_MEM_DI0_DW_SET2_6__EMPTY       0x1F040218,0x00000000
+#define LPM_MEM_DI0_DW_SET2_6__FULL       0x1F040218,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6       0x1F040218,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6       0x1F040218,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_7__ADDR                   0x1F04021C
+#define LPM_MEM_DI0_DW_SET2_7__EMPTY       0x1F04021C,0x00000000
+#define LPM_MEM_DI0_DW_SET2_7__FULL       0x1F04021C,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7       0x1F04021C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7       0x1F04021C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_8__ADDR                   0x1F040220
+#define LPM_MEM_DI0_DW_SET2_8__EMPTY       0x1F040220,0x00000000
+#define LPM_MEM_DI0_DW_SET2_8__FULL       0x1F040220,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8       0x1F040220,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8       0x1F040220,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_9__ADDR                   0x1F040224
+#define LPM_MEM_DI0_DW_SET2_9__EMPTY       0x1F040224,0x00000000
+#define LPM_MEM_DI0_DW_SET2_9__FULL       0x1F040224,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9       0x1F040224,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9       0x1F040224,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_10__ADDR                   0x1F040228
+#define LPM_MEM_DI0_DW_SET2_10__EMPTY       0x1F040228,0x00000000
+#define LPM_MEM_DI0_DW_SET2_10__FULL       0x1F040228,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10       0x1F040228,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10       0x1F040228,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_11__ADDR                   0x1F04022C
+#define LPM_MEM_DI0_DW_SET2_11__EMPTY       0x1F04022C,0x00000000
+#define LPM_MEM_DI0_DW_SET2_11__FULL       0x1F04022C,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11       0x1F04022C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11       0x1F04022C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_0__ADDR                   0x1F040230
+#define LPM_MEM_DI0_DW_SET3_0__EMPTY       0x1F040230,0x00000000
+#define LPM_MEM_DI0_DW_SET3_0__FULL       0x1F040230,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0       0x1F040230,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0       0x1F040230,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_1__ADDR                   0x1F040234
+#define LPM_MEM_DI0_DW_SET3_1__EMPTY       0x1F040234,0x00000000
+#define LPM_MEM_DI0_DW_SET3_1__FULL       0x1F040234,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1       0x1F040234,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1       0x1F040234,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_2__ADDR                   0x1F040238
+#define LPM_MEM_DI0_DW_SET3_2__EMPTY       0x1F040238,0x00000000
+#define LPM_MEM_DI0_DW_SET3_2__FULL       0x1F040238,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2       0x1F040238,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2       0x1F040238,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_3__ADDR                   0x1F04023C
+#define LPM_MEM_DI0_DW_SET3_3__EMPTY       0x1F04023C,0x00000000
+#define LPM_MEM_DI0_DW_SET3_3__FULL       0x1F04023C,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3       0x1F04023C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3       0x1F04023C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_4__ADDR                   0x1F040240
+#define LPM_MEM_DI0_DW_SET3_4__EMPTY       0x1F040240,0x00000000
+#define LPM_MEM_DI0_DW_SET3_4__FULL       0x1F040240,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4       0x1F040240,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4       0x1F040240,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_5__ADDR                   0x1F040244
+#define LPM_MEM_DI0_DW_SET3_5__EMPTY       0x1F040244,0x00000000
+#define LPM_MEM_DI0_DW_SET3_5__FULL       0x1F040244,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5       0x1F040244,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5       0x1F040244,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_6__ADDR                   0x1F040248
+#define LPM_MEM_DI0_DW_SET3_6__EMPTY       0x1F040248,0x00000000
+#define LPM_MEM_DI0_DW_SET3_6__FULL       0x1F040248,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6       0x1F040248,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6       0x1F040248,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_7__ADDR                   0x1F04024C
+#define LPM_MEM_DI0_DW_SET3_7__EMPTY       0x1F04024C,0x00000000
+#define LPM_MEM_DI0_DW_SET3_7__FULL       0x1F04024C,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7       0x1F04024C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7       0x1F04024C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_8__ADDR                   0x1F040250
+#define LPM_MEM_DI0_DW_SET3_8__EMPTY       0x1F040250,0x00000000
+#define LPM_MEM_DI0_DW_SET3_8__FULL       0x1F040250,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8       0x1F040250,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8       0x1F040250,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_9__ADDR                   0x1F040254
+#define LPM_MEM_DI0_DW_SET3_9__EMPTY       0x1F040254,0x00000000
+#define LPM_MEM_DI0_DW_SET3_9__FULL       0x1F040254,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9       0x1F040254,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9       0x1F040254,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_10__ADDR                   0x1F040258
+#define LPM_MEM_DI0_DW_SET3_10__EMPTY       0x1F040258,0x00000000
+#define LPM_MEM_DI0_DW_SET3_10__FULL       0x1F040258,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10       0x1F040258,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10       0x1F040258,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_11__ADDR                   0x1F04025C
+#define LPM_MEM_DI0_DW_SET3_11__EMPTY       0x1F04025C,0x00000000
+#define LPM_MEM_DI0_DW_SET3_11__FULL       0x1F04025C,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11       0x1F04025C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11       0x1F04025C,0x000001FF
+
+#define LPM_MEM_DI0_STP_REP_1__ADDR                   0x1F040260
+#define LPM_MEM_DI0_STP_REP_1__EMPTY       0x1F040260,0x00000000
+#define LPM_MEM_DI0_STP_REP_1__FULL       0x1F040260,0xffffffff
+#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_2       0x1F040260,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_1       0x1F040260,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_2__ADDR                   0x1F040264
+#define LPM_MEM_DI0_STP_REP_2__EMPTY       0x1F040264,0x00000000
+#define LPM_MEM_DI0_STP_REP_2__FULL       0x1F040264,0xffffffff
+#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_4       0x1F040264,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_3       0x1F040264,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_3__ADDR                   0x1F040268
+#define LPM_MEM_DI0_STP_REP_3__EMPTY       0x1F040268,0x00000000
+#define LPM_MEM_DI0_STP_REP_3__FULL       0x1F040268,0xffffffff
+#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_6       0x1F040268,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_5       0x1F040268,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_4__ADDR                   0x1F04026C
+#define LPM_MEM_DI0_STP_REP_4__EMPTY       0x1F04026C,0x00000000
+#define LPM_MEM_DI0_STP_REP_4__FULL       0x1F04026C,0xffffffff
+#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_8       0x1F04026C,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_7       0x1F04026C,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_9__ADDR                   0x1F040270
+#define LPM_MEM_DI0_STP_REP_9__EMPTY       0x1F040270,0x00000000
+#define LPM_MEM_DI0_STP_REP_9__FULL       0x1F040270,0xffffffff
+#define LPM_MEM_DI0_STP_REP_9__DI0_STEP_REPEAT_9       0x1F040270,0x00000FFF
+
+#define LPM_MEM_DI0_SER_CONF__ADDR                   0x1F040274
+#define LPM_MEM_DI0_SER_CONF__EMPTY       0x1F040274,0x00000000
+#define LPM_MEM_DI0_SER_CONF__FULL       0x1F040274,0xffffffff
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1       0x1F040274,0xF0000000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0       0x1F040274,0x0F000000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1       0x1F040274,0x00F00000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0       0x1F040274,0x000F0000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LATCH       0x1F040274,0x0000FF00
+#define LPM_MEM_DI0_SER_CONF__DI0_LLA_SER_ACCESS       0x1F040274,0x00000020
+#define LPM_MEM_DI0_SER_CONF__DI0_SER_CLK_POLARITY       0x1F040274,0x00000010
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY       0x1F040274,0x00000008
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY       0x1F040274,0x00000004
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY       0x1F040274,0x00000002
+#define LPM_MEM_DI0_SER_CONF__DI0_WAIT4SERIAL       0x1F040274,0x00000001
+
+#define LPM_MEM_DI0_SSC__ADDR                   0x1F040278
+#define LPM_MEM_DI0_SSC__EMPTY       0x1F040278,0x00000000
+#define LPM_MEM_DI0_SSC__FULL       0x1F040278,0xffffffff
+#define LPM_MEM_DI0_SSC__DI0_PIN17_ERM       0x1F040278,0x00800000
+#define LPM_MEM_DI0_SSC__DI0_PIN16_ERM       0x1F040278,0x00400000
+#define LPM_MEM_DI0_SSC__DI0_PIN15_ERM       0x1F040278,0x00200000
+#define LPM_MEM_DI0_SSC__DI0_PIN14_ERM       0x1F040278,0x00100000
+#define LPM_MEM_DI0_SSC__DI0_PIN13_ERM       0x1F040278,0x00080000
+#define LPM_MEM_DI0_SSC__DI0_PIN12_ERM       0x1F040278,0x00040000
+#define LPM_MEM_DI0_SSC__DI0_PIN11_ERM       0x1F040278,0x00020000
+#define LPM_MEM_DI0_SSC__DI0_CS_ERM       0x1F040278,0x00010000
+#define LPM_MEM_DI0_SSC__DI0_WAIT_ON       0x1F040278,0x00000020
+#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_RD_IN       0x1F040278,0x00000008
+#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_PNTR       0x1F040278,0x00000007
+
+#define LPM_MEM_DI0_POL__ADDR                   0x1F04027C
+#define LPM_MEM_DI0_POL__EMPTY       0x1F04027C,0x00000000
+#define LPM_MEM_DI0_POL__FULL       0x1F04027C,0xffffffff
+#define LPM_MEM_DI0_POL__DI0_WAIT_POLARITY       0x1F04027C,0x04000000
+#define LPM_MEM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY       0x1F04027C,0x02000000
+#define LPM_MEM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY       0x1F04027C,0x01000000
+#define LPM_MEM_DI0_POL__DI0_CS1_DATA_POLARITY       0x1F04027C,0x00800000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_17       0x1F04027C,0x00400000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_16       0x1F04027C,0x00200000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_15       0x1F04027C,0x00100000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_14       0x1F04027C,0x00080000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_13       0x1F04027C,0x00040000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_12       0x1F04027C,0x00020000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_11       0x1F04027C,0x00010000
+#define LPM_MEM_DI0_POL__DI0_CS0_DATA_POLARITY       0x1F04027C,0x00008000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_17       0x1F04027C,0x00004000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_16       0x1F04027C,0x00002000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_15       0x1F04027C,0x00001000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_14       0x1F04027C,0x00000800
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_13       0x1F04027C,0x00000400
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_12       0x1F04027C,0x00000200
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_11       0x1F04027C,0x00000100
+#define LPM_MEM_DI0_POL__DI0_DRDY_DATA_POLARITY       0x1F04027C,0x00000080
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_17       0x1F04027C,0x00000040
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_16       0x1F04027C,0x00000020
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_15       0x1F04027C,0x00000010
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_14       0x1F04027C,0x00000008
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_13       0x1F04027C,0x00000004
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_12       0x1F04027C,0x00000002
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_11       0x1F04027C,0x00000001
+
+#define LPM_MEM_DI0_AW0__ADDR                   0x1F040280
+#define LPM_MEM_DI0_AW0__EMPTY       0x1F040280,0x00000000
+#define LPM_MEM_DI0_AW0__FULL       0x1F040280,0xffffffff
+#define LPM_MEM_DI0_AW0__DI0_AW_TRIG_SEL       0x1F040280,0xF0000000
+#define LPM_MEM_DI0_AW0__DI0_AW_HEND       0x1F040280,0x0FFF0000
+#define LPM_MEM_DI0_AW0__DI0_AW_HCOUNT_SEL       0x1F040280,0x0000F000
+#define LPM_MEM_DI0_AW0__DI0_AW_HSTART       0x1F040280,0x00000FFF
+
+#define LPM_MEM_DI0_AW1__ADDR                   0x1F040284
+#define LPM_MEM_DI0_AW1__EMPTY       0x1F040284,0x00000000
+#define LPM_MEM_DI0_AW1__FULL       0x1F040284,0xffffffff
+#define LPM_MEM_DI0_AW1__DI0_AW_VEND       0x1F040284,0x0FFF0000
+#define LPM_MEM_DI0_AW1__DI0_AW_VCOUNT_SEL       0x1F040284,0x0000F000
+#define LPM_MEM_DI0_AW1__DI0_AW_VSTART       0x1F040284,0x00000FFF
+
+#define LPM_MEM_DI0_SCR_CONF__ADDR                   0x1F040288
+#define LPM_MEM_DI0_SCR_CONF__EMPTY       0x1F040288,0x00000000
+#define LPM_MEM_DI0_SCR_CONF__FULL       0x1F040288,0xffffffff
+#define LPM_MEM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT       0x1F040288,0x00000FFF
+
+#define LPM_MEM_DI1_GENERAL__ADDR                   0x1F04028C
+#define LPM_MEM_DI1_GENERAL__EMPTY       0x1F04028C,0x00000000
+#define LPM_MEM_DI1_GENERAL__FULL       0x1F04028C,0xffffffff
+#define LPM_MEM_DI1_GENERAL__DI1_DISP_Y_SEL       0x1F04028C,0x70000000
+#define LPM_MEM_DI1_GENERAL__DI1_CLOCK_STOP_MODE       0x1F04028C,0x0F000000
+#define LPM_MEM_DI1_GENERAL__DI1_DISP_CLOCK_INIT       0x1F04028C,0x00800000
+#define LPM_MEM_DI1_GENERAL__DI1_MASK_SEL       0x1F04028C,0x00400000
+#define LPM_MEM_DI1_GENERAL__DI1_VSYNC_EXT       0x1F04028C,0x00200000
+#define LPM_MEM_DI1_GENERAL__DI1_CLK_EXT       0x1F04028C,0x00100000
+#define LPM_MEM_DI1_GENERAL__DI1_WATCHDOG_MODE       0x1F04028C,0x000C0000
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_DISP_CLK       0x1F04028C,0x00020000
+#define LPM_MEM_DI1_GENERAL__DI1_SYNC_COUNT_SEL       0x1F04028C,0x0000F000
+#define LPM_MEM_DI1_GENERAL__DI1_ERR_TREATMENT       0x1F04028C,0x00000800
+#define LPM_MEM_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1F04028C,0x00000400
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS1       0x1F04028C,0x00000200
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS0       0x1F04028C,0x00000100
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_8       0x1F04028C,0x00000080
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_7       0x1F04028C,0x00000040
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_6       0x1F04028C,0x00000020
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_5       0x1F04028C,0x00000010
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_4       0x1F04028C,0x00000008
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_3       0x1F04028C,0x00000004
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_2       0x1F04028C,0x00000002
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_1       0x1F04028C,0x00000001
+
+#define LPM_MEM_DI1_BS_CLKGEN0__ADDR                   0x1F040290
+#define LPM_MEM_DI1_BS_CLKGEN0__EMPTY       0x1F040290,0x00000000
+#define LPM_MEM_DI1_BS_CLKGEN0__FULL       0x1F040290,0xffffffff
+#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET       0x1F040290,0x01FF0000
+#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD       0x1F040290,0x00000FFF
+
+#define LPM_MEM_DI1_BS_CLKGEN1__ADDR                   0x1F040294
+#define LPM_MEM_DI1_BS_CLKGEN1__EMPTY       0x1F040294,0x00000000
+#define LPM_MEM_DI1_BS_CLKGEN1__FULL       0x1F040294,0xffffffff
+#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN       0x1F040294,0x01FF0000
+#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP       0x1F040294,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN0_1__ADDR                   0x1F040298
+#define LPM_MEM_DI1_SW_GEN0_1__EMPTY       0x1F040298,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_1__FULL       0x1F040298,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1       0x1F040298,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1       0x1F040298,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1       0x1F040298,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1       0x1F040298,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_2__ADDR                   0x1F04029C
+#define LPM_MEM_DI1_SW_GEN0_2__EMPTY       0x1F04029C,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_2__FULL       0x1F04029C,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2       0x1F04029C,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2       0x1F04029C,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2       0x1F04029C,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2       0x1F04029C,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_3__ADDR                   0x1F0402A0
+#define LPM_MEM_DI1_SW_GEN0_3__EMPTY       0x1F0402A0,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_3__FULL       0x1F0402A0,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3       0x1F0402A0,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3       0x1F0402A0,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3       0x1F0402A0,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3       0x1F0402A0,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_4__ADDR                   0x1F0402A4
+#define LPM_MEM_DI1_SW_GEN0_4__EMPTY       0x1F0402A4,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_4__FULL       0x1F0402A4,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4       0x1F0402A4,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4       0x1F0402A4,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4       0x1F0402A4,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4       0x1F0402A4,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_5__ADDR                   0x1F0402A8
+#define LPM_MEM_DI1_SW_GEN0_5__EMPTY       0x1F0402A8,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_5__FULL       0x1F0402A8,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5       0x1F0402A8,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5       0x1F0402A8,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5       0x1F0402A8,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5       0x1F0402A8,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_6__ADDR                   0x1F0402AC
+#define LPM_MEM_DI1_SW_GEN0_6__EMPTY       0x1F0402AC,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_6__FULL       0x1F0402AC,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6       0x1F0402AC,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6       0x1F0402AC,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6       0x1F0402AC,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6       0x1F0402AC,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_7__ADDR                   0x1F0402B0
+#define LPM_MEM_DI1_SW_GEN0_7__EMPTY       0x1F0402B0,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_7__FULL       0x1F0402B0,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7       0x1F0402B0,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7       0x1F0402B0,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7       0x1F0402B0,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7       0x1F0402B0,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_8__ADDR                   0x1F0402B4
+#define LPM_MEM_DI1_SW_GEN0_8__EMPTY       0x1F0402B4,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_8__FULL       0x1F0402B4,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8       0x1F0402B4,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8       0x1F0402B4,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8       0x1F0402B4,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8       0x1F0402B4,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_9__ADDR                   0x1F0402B8
+#define LPM_MEM_DI1_SW_GEN0_9__EMPTY       0x1F0402B8,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_9__FULL       0x1F0402B8,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9       0x1F0402B8,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9       0x1F0402B8,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9       0x1F0402B8,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9       0x1F0402B8,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN1_1__ADDR                   0x1F0402BC
+#define LPM_MEM_DI1_SW_GEN1_1__EMPTY       0x1F0402BC,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_1__FULL       0x1F0402BC,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1       0x1F0402BC,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1       0x1F0402BC,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1       0x1F0402BC,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1       0x1F0402BC,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1       0x1F0402BC,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1       0x1F0402BC,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_UP_1       0x1F0402BC,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_2__ADDR                   0x1F0402C0
+#define LPM_MEM_DI1_SW_GEN1_2__EMPTY       0x1F0402C0,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_2__FULL       0x1F0402C0,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2       0x1F0402C0,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2       0x1F0402C0,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2       0x1F0402C0,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2       0x1F0402C0,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2       0x1F0402C0,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2       0x1F0402C0,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_UP_2       0x1F0402C0,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_3__ADDR                   0x1F0402C4
+#define LPM_MEM_DI1_SW_GEN1_3__EMPTY       0x1F0402C4,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_3__FULL       0x1F0402C4,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3       0x1F0402C4,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3       0x1F0402C4,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3       0x1F0402C4,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3       0x1F0402C4,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3       0x1F0402C4,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3       0x1F0402C4,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_UP_3       0x1F0402C4,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_4__ADDR                   0x1F0402C8
+#define LPM_MEM_DI1_SW_GEN1_4__EMPTY       0x1F0402C8,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_4__FULL       0x1F0402C8,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4       0x1F0402C8,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4       0x1F0402C8,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4       0x1F0402C8,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4       0x1F0402C8,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4       0x1F0402C8,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4       0x1F0402C8,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_UP_4       0x1F0402C8,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_5__ADDR                   0x1F0402CC
+#define LPM_MEM_DI1_SW_GEN1_5__EMPTY       0x1F0402CC,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_5__FULL       0x1F0402CC,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5       0x1F0402CC,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5       0x1F0402CC,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5       0x1F0402CC,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5       0x1F0402CC,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5       0x1F0402CC,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5       0x1F0402CC,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_UP_5       0x1F0402CC,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_6__ADDR                   0x1F0402D0
+#define LPM_MEM_DI1_SW_GEN1_6__EMPTY       0x1F0402D0,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_6__FULL       0x1F0402D0,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6       0x1F0402D0,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6       0x1F0402D0,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6       0x1F0402D0,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6       0x1F0402D0,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6       0x1F0402D0,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6       0x1F0402D0,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_UP_6       0x1F0402D0,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_7__ADDR                   0x1F0402D4
+#define LPM_MEM_DI1_SW_GEN1_7__EMPTY       0x1F0402D4,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_7__FULL       0x1F0402D4,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7       0x1F0402D4,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7       0x1F0402D4,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7       0x1F0402D4,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7       0x1F0402D4,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7       0x1F0402D4,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7       0x1F0402D4,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_UP_7       0x1F0402D4,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_8__ADDR                   0x1F0402D8
+#define LPM_MEM_DI1_SW_GEN1_8__EMPTY       0x1F0402D8,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_8__FULL       0x1F0402D8,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8       0x1F0402D8,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8       0x1F0402D8,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8       0x1F0402D8,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8       0x1F0402D8,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8       0x1F0402D8,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8       0x1F0402D8,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_UP_8       0x1F0402D8,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_9__ADDR                   0x1F0402DC
+#define LPM_MEM_DI1_SW_GEN1_9__EMPTY       0x1F0402DC,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_9__FULL       0x1F0402DC,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9       0x1F0402DC,0xE0000000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9       0x1F0402DC,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9       0x1F0402DC,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9       0x1F0402DC,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_TAG_SEL_9       0x1F0402DC,0x00008000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_UP_9       0x1F0402DC,0x000001FF
+
+#define LPM_MEM_DI1_SYNC_AS_GEN__ADDR                   0x1F0402E0
+#define LPM_MEM_DI1_SYNC_AS_GEN__EMPTY       0x1F0402E0,0x00000000
+#define LPM_MEM_DI1_SYNC_AS_GEN__FULL       0x1F0402E0,0xffffffff
+#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN       0x1F0402E0,0x10000000
+#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL       0x1F0402E0,0x0000E000
+#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START       0x1F0402E0,0x00000FFF
+
+#define LPM_MEM_DI1_DW_GEN_0__ADDR                   0x1F0402E4
+#define LPM_MEM_DI1_DW_GEN_0__EMPTY       0x1F0402E4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_0__FULL       0x1F0402E4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0       0x1F0402E4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0       0x1F0402E4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0       0x1F0402E4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_6_0       0x1F0402E4,0x00003000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_5_0       0x1F0402E4,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_4_0       0x1F0402E4,0x00000300
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_3_0       0x1F0402E4,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_2_0       0x1F0402E4,0x00000030
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_1_0       0x1F0402E4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_0_0       0x1F0402E4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_0__ADDR                   0x1F0402E4
+#define LPM_MEM_DI1_DW_GEN_0__EMPTY       0x1F0402E4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_0__FULL       0x1F0402E4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0       0x1F0402E4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_START_PERIOD_0       0x1F0402E4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0       0x1F0402E4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0       0x1F0402E4,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_RS_0       0x1F0402E4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0       0x1F0402E4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_1__ADDR                   0x1F0402E8
+#define LPM_MEM_DI1_DW_GEN_1__EMPTY       0x1F0402E8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_1__FULL       0x1F0402E8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1       0x1F0402E8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1       0x1F0402E8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1       0x1F0402E8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_6_1       0x1F0402E8,0x00003000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_5_1       0x1F0402E8,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_4_1       0x1F0402E8,0x00000300
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_3_1       0x1F0402E8,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_2_1       0x1F0402E8,0x00000030
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_1_1       0x1F0402E8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_0_1       0x1F0402E8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_1__ADDR                   0x1F0402E8
+#define LPM_MEM_DI1_DW_GEN_1__EMPTY       0x1F0402E8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_1__FULL       0x1F0402E8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1       0x1F0402E8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_START_PERIOD_1       0x1F0402E8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1       0x1F0402E8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1       0x1F0402E8,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_RS_1       0x1F0402E8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1       0x1F0402E8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_2__ADDR                   0x1F0402EC
+#define LPM_MEM_DI1_DW_GEN_2__EMPTY       0x1F0402EC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_2__FULL       0x1F0402EC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2       0x1F0402EC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2       0x1F0402EC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2       0x1F0402EC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_6_2       0x1F0402EC,0x00003000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_5_2       0x1F0402EC,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_4_2       0x1F0402EC,0x00000300
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_3_2       0x1F0402EC,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_2_2       0x1F0402EC,0x00000030
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_1_2       0x1F0402EC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_0_2       0x1F0402EC,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_2__ADDR                   0x1F0402EC
+#define LPM_MEM_DI1_DW_GEN_2__EMPTY       0x1F0402EC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_2__FULL       0x1F0402EC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2       0x1F0402EC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_START_PERIOD_2       0x1F0402EC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2       0x1F0402EC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2       0x1F0402EC,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_RS_2       0x1F0402EC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2       0x1F0402EC,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_3__ADDR                   0x1F0402F0
+#define LPM_MEM_DI1_DW_GEN_3__EMPTY       0x1F0402F0,0x00000000
+#define LPM_MEM_DI1_DW_GEN_3__FULL       0x1F0402F0,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3       0x1F0402F0,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3       0x1F0402F0,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3       0x1F0402F0,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_6_3       0x1F0402F0,0x00003000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_5_3       0x1F0402F0,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_4_3       0x1F0402F0,0x00000300
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_3_3       0x1F0402F0,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_2_3       0x1F0402F0,0x00000030
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_1_3       0x1F0402F0,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_0_3       0x1F0402F0,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_3__ADDR                   0x1F0402F0
+#define LPM_MEM_DI1_DW_GEN_3__EMPTY       0x1F0402F0,0x00000000
+#define LPM_MEM_DI1_DW_GEN_3__FULL       0x1F0402F0,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3       0x1F0402F0,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_START_PERIOD_3       0x1F0402F0,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3       0x1F0402F0,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3       0x1F0402F0,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_RS_3       0x1F0402F0,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3       0x1F0402F0,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_4__ADDR                   0x1F0402F4
+#define LPM_MEM_DI1_DW_GEN_4__EMPTY       0x1F0402F4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_4__FULL       0x1F0402F4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4       0x1F0402F4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4       0x1F0402F4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4       0x1F0402F4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_6_4       0x1F0402F4,0x00003000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_5_4       0x1F0402F4,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_4_4       0x1F0402F4,0x00000300
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_3_4       0x1F0402F4,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_2_4       0x1F0402F4,0x00000030
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_1_4       0x1F0402F4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_0_4       0x1F0402F4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_4__ADDR                   0x1F0402F4
+#define LPM_MEM_DI1_DW_GEN_4__EMPTY       0x1F0402F4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_4__FULL       0x1F0402F4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4       0x1F0402F4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_START_PERIOD_4       0x1F0402F4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4       0x1F0402F4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4       0x1F0402F4,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_RS_4       0x1F0402F4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4       0x1F0402F4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_5__ADDR                   0x1F0402F8
+#define LPM_MEM_DI1_DW_GEN_5__EMPTY       0x1F0402F8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_5__FULL       0x1F0402F8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5       0x1F0402F8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5       0x1F0402F8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5       0x1F0402F8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_6_5       0x1F0402F8,0x00003000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_5_5       0x1F0402F8,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_4_5       0x1F0402F8,0x00000300
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_3_5       0x1F0402F8,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_2_5       0x1F0402F8,0x00000030
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_1_5       0x1F0402F8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_0_5       0x1F0402F8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_5__ADDR                   0x1F0402F8
+#define LPM_MEM_DI1_DW_GEN_5__EMPTY       0x1F0402F8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_5__FULL       0x1F0402F8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5       0x1F0402F8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_START_PERIOD_5       0x1F0402F8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5       0x1F0402F8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5       0x1F0402F8,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_RS_5       0x1F0402F8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5       0x1F0402F8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_6__ADDR                   0x1F0402FC
+#define LPM_MEM_DI1_DW_GEN_6__EMPTY       0x1F0402FC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_6__FULL       0x1F0402FC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6       0x1F0402FC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6       0x1F0402FC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6       0x1F0402FC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_6_6       0x1F0402FC,0x00003000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_5_6       0x1F0402FC,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_4_6       0x1F0402FC,0x00000300
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_3_6       0x1F0402FC,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_2_6       0x1F0402FC,0x00000030
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_1_6       0x1F0402FC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_0_6       0x1F0402FC,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_6__ADDR                   0x1F0402FC
+#define LPM_MEM_DI1_DW_GEN_6__EMPTY       0x1F0402FC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_6__FULL       0x1F0402FC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6       0x1F0402FC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_START_PERIOD_6       0x1F0402FC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6       0x1F0402FC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6       0x1F0402FC,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_RS_6       0x1F0402FC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6       0x1F0402FC,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_7__ADDR                   0x1F040300
+#define LPM_MEM_DI1_DW_GEN_7__EMPTY       0x1F040300,0x00000000
+#define LPM_MEM_DI1_DW_GEN_7__FULL       0x1F040300,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7       0x1F040300,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7       0x1F040300,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7       0x1F040300,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_6_7       0x1F040300,0x00003000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_5_7       0x1F040300,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_4_7       0x1F040300,0x00000300
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_3_7       0x1F040300,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_2_7       0x1F040300,0x00000030
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_1_7       0x1F040300,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_0_7       0x1F040300,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_7__ADDR                   0x1F040300
+#define LPM_MEM_DI1_DW_GEN_7__EMPTY       0x1F040300,0x00000000
+#define LPM_MEM_DI1_DW_GEN_7__FULL       0x1F040300,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7       0x1F040300,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_START_PERIOD_7       0x1F040300,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7       0x1F040300,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7       0x1F040300,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_RS_7       0x1F040300,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7       0x1F040300,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_8__ADDR                   0x1F040304
+#define LPM_MEM_DI1_DW_GEN_8__EMPTY       0x1F040304,0x00000000
+#define LPM_MEM_DI1_DW_GEN_8__FULL       0x1F040304,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8       0x1F040304,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8       0x1F040304,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8       0x1F040304,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_6_8       0x1F040304,0x00003000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_5_8       0x1F040304,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_4_8       0x1F040304,0x00000300
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_3_8       0x1F040304,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_2_8       0x1F040304,0x00000030
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_1_8       0x1F040304,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_0_8       0x1F040304,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_8__ADDR                   0x1F040304
+#define LPM_MEM_DI1_DW_GEN_8__EMPTY       0x1F040304,0x00000000
+#define LPM_MEM_DI1_DW_GEN_8__FULL       0x1F040304,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8       0x1F040304,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_START_PERIOD_8       0x1F040304,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8       0x1F040304,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8       0x1F040304,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_RS_8       0x1F040304,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8       0x1F040304,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_9__ADDR                   0x1F040308
+#define LPM_MEM_DI1_DW_GEN_9__EMPTY       0x1F040308,0x00000000
+#define LPM_MEM_DI1_DW_GEN_9__FULL       0x1F040308,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9       0x1F040308,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9       0x1F040308,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9       0x1F040308,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_6_9       0x1F040308,0x00003000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_5_9       0x1F040308,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_4_9       0x1F040308,0x00000300
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_3_9       0x1F040308,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_2_9       0x1F040308,0x00000030
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_1_9       0x1F040308,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_0_9       0x1F040308,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_9__ADDR                   0x1F040308
+#define LPM_MEM_DI1_DW_GEN_9__EMPTY       0x1F040308,0x00000000
+#define LPM_MEM_DI1_DW_GEN_9__FULL       0x1F040308,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9       0x1F040308,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_START_PERIOD_9       0x1F040308,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9       0x1F040308,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9       0x1F040308,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_RS_9       0x1F040308,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9       0x1F040308,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_10__ADDR                   0x1F04030C
+#define LPM_MEM_DI1_DW_GEN_10__EMPTY       0x1F04030C,0x00000000
+#define LPM_MEM_DI1_DW_GEN_10__FULL       0x1F04030C,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10       0x1F04030C,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10       0x1F04030C,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10       0x1F04030C,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_6_10       0x1F04030C,0x00003000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_5_10       0x1F04030C,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_4_10       0x1F04030C,0x00000300
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_3_10       0x1F04030C,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_2_10       0x1F04030C,0x00000030
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_1_10       0x1F04030C,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_0_10       0x1F04030C,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_10__ADDR                   0x1F04030C
+#define LPM_MEM_DI1_DW_GEN_10__EMPTY       0x1F04030C,0x00000000
+#define LPM_MEM_DI1_DW_GEN_10__FULL       0x1F04030C,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10       0x1F04030C,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_START_PERIOD_10       0x1F04030C,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10       0x1F04030C,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10       0x1F04030C,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_RS_10       0x1F04030C,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10       0x1F04030C,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_11__ADDR                   0x1F040310
+#define LPM_MEM_DI1_DW_GEN_11__EMPTY       0x1F040310,0x00000000
+#define LPM_MEM_DI1_DW_GEN_11__FULL       0x1F040310,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11       0x1F040310,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11       0x1F040310,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11       0x1F040310,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_6_11       0x1F040310,0x00003000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_5_11       0x1F040310,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_4_11       0x1F040310,0x00000300
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_3_11       0x1F040310,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_2_11       0x1F040310,0x00000030
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_1_11       0x1F040310,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_0_11       0x1F040310,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_11__ADDR                   0x1F040310
+#define LPM_MEM_DI1_DW_GEN_11__EMPTY       0x1F040310,0x00000000
+#define LPM_MEM_DI1_DW_GEN_11__FULL       0x1F040310,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11       0x1F040310,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_START_PERIOD_11       0x1F040310,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11       0x1F040310,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11       0x1F040310,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_RS_11       0x1F040310,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11       0x1F040310,0x00000003
+
+#define LPM_MEM_DI1_DW_SET0_0__ADDR                   0x1F040314
+#define LPM_MEM_DI1_DW_SET0_0__EMPTY       0x1F040314,0x00000000
+#define LPM_MEM_DI1_DW_SET0_0__FULL       0x1F040314,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0       0x1F040314,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0       0x1F040314,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_1__ADDR                   0x1F040318
+#define LPM_MEM_DI1_DW_SET0_1__EMPTY       0x1F040318,0x00000000
+#define LPM_MEM_DI1_DW_SET0_1__FULL       0x1F040318,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1       0x1F040318,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1       0x1F040318,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_2__ADDR                   0x1F04031C
+#define LPM_MEM_DI1_DW_SET0_2__EMPTY       0x1F04031C,0x00000000
+#define LPM_MEM_DI1_DW_SET0_2__FULL       0x1F04031C,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2       0x1F04031C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2       0x1F04031C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_3__ADDR                   0x1F040320
+#define LPM_MEM_DI1_DW_SET0_3__EMPTY       0x1F040320,0x00000000
+#define LPM_MEM_DI1_DW_SET0_3__FULL       0x1F040320,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3       0x1F040320,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3       0x1F040320,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_4__ADDR                   0x1F040324
+#define LPM_MEM_DI1_DW_SET0_4__EMPTY       0x1F040324,0x00000000
+#define LPM_MEM_DI1_DW_SET0_4__FULL       0x1F040324,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4       0x1F040324,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4       0x1F040324,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_5__ADDR                   0x1F040328
+#define LPM_MEM_DI1_DW_SET0_5__EMPTY       0x1F040328,0x00000000
+#define LPM_MEM_DI1_DW_SET0_5__FULL       0x1F040328,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5       0x1F040328,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5       0x1F040328,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_6__ADDR                   0x1F04032C
+#define LPM_MEM_DI1_DW_SET0_6__EMPTY       0x1F04032C,0x00000000
+#define LPM_MEM_DI1_DW_SET0_6__FULL       0x1F04032C,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6       0x1F04032C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6       0x1F04032C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_7__ADDR                   0x1F040330
+#define LPM_MEM_DI1_DW_SET0_7__EMPTY       0x1F040330,0x00000000
+#define LPM_MEM_DI1_DW_SET0_7__FULL       0x1F040330,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7       0x1F040330,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7       0x1F040330,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_8__ADDR                   0x1F040334
+#define LPM_MEM_DI1_DW_SET0_8__EMPTY       0x1F040334,0x00000000
+#define LPM_MEM_DI1_DW_SET0_8__FULL       0x1F040334,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8       0x1F040334,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8       0x1F040334,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_9__ADDR                   0x1F040338
+#define LPM_MEM_DI1_DW_SET0_9__EMPTY       0x1F040338,0x00000000
+#define LPM_MEM_DI1_DW_SET0_9__FULL       0x1F040338,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9       0x1F040338,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9       0x1F040338,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_10__ADDR                   0x1F04033C
+#define LPM_MEM_DI1_DW_SET0_10__EMPTY       0x1F04033C,0x00000000
+#define LPM_MEM_DI1_DW_SET0_10__FULL       0x1F04033C,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10       0x1F04033C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10       0x1F04033C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_11__ADDR                   0x1F040340
+#define LPM_MEM_DI1_DW_SET0_11__EMPTY       0x1F040340,0x00000000
+#define LPM_MEM_DI1_DW_SET0_11__FULL       0x1F040340,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11       0x1F040340,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11       0x1F040340,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_0__ADDR                   0x1F040344
+#define LPM_MEM_DI1_DW_SET1_0__EMPTY       0x1F040344,0x00000000
+#define LPM_MEM_DI1_DW_SET1_0__FULL       0x1F040344,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0       0x1F040344,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0       0x1F040344,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_1__ADDR                   0x1F040348
+#define LPM_MEM_DI1_DW_SET1_1__EMPTY       0x1F040348,0x00000000
+#define LPM_MEM_DI1_DW_SET1_1__FULL       0x1F040348,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1       0x1F040348,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1       0x1F040348,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_2__ADDR                   0x1F04034C
+#define LPM_MEM_DI1_DW_SET1_2__EMPTY       0x1F04034C,0x00000000
+#define LPM_MEM_DI1_DW_SET1_2__FULL       0x1F04034C,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2       0x1F04034C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2       0x1F04034C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_3__ADDR                   0x1F040350
+#define LPM_MEM_DI1_DW_SET1_3__EMPTY       0x1F040350,0x00000000
+#define LPM_MEM_DI1_DW_SET1_3__FULL       0x1F040350,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3       0x1F040350,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3       0x1F040350,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_4__ADDR                   0x1F040354
+#define LPM_MEM_DI1_DW_SET1_4__EMPTY       0x1F040354,0x00000000
+#define LPM_MEM_DI1_DW_SET1_4__FULL       0x1F040354,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4       0x1F040354,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4       0x1F040354,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_5__ADDR                   0x1F040358
+#define LPM_MEM_DI1_DW_SET1_5__EMPTY       0x1F040358,0x00000000
+#define LPM_MEM_DI1_DW_SET1_5__FULL       0x1F040358,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5       0x1F040358,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5       0x1F040358,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_6__ADDR                   0x1F04035C
+#define LPM_MEM_DI1_DW_SET1_6__EMPTY       0x1F04035C,0x00000000
+#define LPM_MEM_DI1_DW_SET1_6__FULL       0x1F04035C,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6       0x1F04035C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6       0x1F04035C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_7__ADDR                   0x1F040360
+#define LPM_MEM_DI1_DW_SET1_7__EMPTY       0x1F040360,0x00000000
+#define LPM_MEM_DI1_DW_SET1_7__FULL       0x1F040360,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7       0x1F040360,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7       0x1F040360,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_8__ADDR                   0x1F040364
+#define LPM_MEM_DI1_DW_SET1_8__EMPTY       0x1F040364,0x00000000
+#define LPM_MEM_DI1_DW_SET1_8__FULL       0x1F040364,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8       0x1F040364,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8       0x1F040364,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_9__ADDR                   0x1F040368
+#define LPM_MEM_DI1_DW_SET1_9__EMPTY       0x1F040368,0x00000000
+#define LPM_MEM_DI1_DW_SET1_9__FULL       0x1F040368,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9       0x1F040368,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9       0x1F040368,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_10__ADDR                   0x1F04036C
+#define LPM_MEM_DI1_DW_SET1_10__EMPTY       0x1F04036C,0x00000000
+#define LPM_MEM_DI1_DW_SET1_10__FULL       0x1F04036C,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10       0x1F04036C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10       0x1F04036C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_11__ADDR                   0x1F040370
+#define LPM_MEM_DI1_DW_SET1_11__EMPTY       0x1F040370,0x00000000
+#define LPM_MEM_DI1_DW_SET1_11__FULL       0x1F040370,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11       0x1F040370,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11       0x1F040370,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_0__ADDR                   0x1F040374
+#define LPM_MEM_DI1_DW_SET2_0__EMPTY       0x1F040374,0x00000000
+#define LPM_MEM_DI1_DW_SET2_0__FULL       0x1F040374,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0       0x1F040374,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0       0x1F040374,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_1__ADDR                   0x1F040378
+#define LPM_MEM_DI1_DW_SET2_1__EMPTY       0x1F040378,0x00000000
+#define LPM_MEM_DI1_DW_SET2_1__FULL       0x1F040378,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1       0x1F040378,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1       0x1F040378,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_2__ADDR                   0x1F04037C
+#define LPM_MEM_DI1_DW_SET2_2__EMPTY       0x1F04037C,0x00000000
+#define LPM_MEM_DI1_DW_SET2_2__FULL       0x1F04037C,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2       0x1F04037C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2       0x1F04037C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_3__ADDR                   0x1F040380
+#define LPM_MEM_DI1_DW_SET2_3__EMPTY       0x1F040380,0x00000000
+#define LPM_MEM_DI1_DW_SET2_3__FULL       0x1F040380,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3       0x1F040380,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3       0x1F040380,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_4__ADDR                   0x1F040384
+#define LPM_MEM_DI1_DW_SET2_4__EMPTY       0x1F040384,0x00000000
+#define LPM_MEM_DI1_DW_SET2_4__FULL       0x1F040384,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4       0x1F040384,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4       0x1F040384,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_5__ADDR                   0x1F040388
+#define LPM_MEM_DI1_DW_SET2_5__EMPTY       0x1F040388,0x00000000
+#define LPM_MEM_DI1_DW_SET2_5__FULL       0x1F040388,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5       0x1F040388,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5       0x1F040388,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_6__ADDR                   0x1F04038C
+#define LPM_MEM_DI1_DW_SET2_6__EMPTY       0x1F04038C,0x00000000
+#define LPM_MEM_DI1_DW_SET2_6__FULL       0x1F04038C,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6       0x1F04038C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6       0x1F04038C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_7__ADDR                   0x1F040390
+#define LPM_MEM_DI1_DW_SET2_7__EMPTY       0x1F040390,0x00000000
+#define LPM_MEM_DI1_DW_SET2_7__FULL       0x1F040390,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7       0x1F040390,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7       0x1F040390,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_8__ADDR                   0x1F040394
+#define LPM_MEM_DI1_DW_SET2_8__EMPTY       0x1F040394,0x00000000
+#define LPM_MEM_DI1_DW_SET2_8__FULL       0x1F040394,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8       0x1F040394,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8       0x1F040394,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_9__ADDR                   0x1F040398
+#define LPM_MEM_DI1_DW_SET2_9__EMPTY       0x1F040398,0x00000000
+#define LPM_MEM_DI1_DW_SET2_9__FULL       0x1F040398,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9       0x1F040398,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9       0x1F040398,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_10__ADDR                   0x1F04039C
+#define LPM_MEM_DI1_DW_SET2_10__EMPTY       0x1F04039C,0x00000000
+#define LPM_MEM_DI1_DW_SET2_10__FULL       0x1F04039C,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10       0x1F04039C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10       0x1F04039C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_11__ADDR                   0x1F0403A0
+#define LPM_MEM_DI1_DW_SET2_11__EMPTY       0x1F0403A0,0x00000000
+#define LPM_MEM_DI1_DW_SET2_11__FULL       0x1F0403A0,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11       0x1F0403A0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11       0x1F0403A0,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_0__ADDR                   0x1F0403A4
+#define LPM_MEM_DI1_DW_SET3_0__EMPTY       0x1F0403A4,0x00000000
+#define LPM_MEM_DI1_DW_SET3_0__FULL       0x1F0403A4,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0       0x1F0403A4,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0       0x1F0403A4,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_1__ADDR                   0x1F0403A8
+#define LPM_MEM_DI1_DW_SET3_1__EMPTY       0x1F0403A8,0x00000000
+#define LPM_MEM_DI1_DW_SET3_1__FULL       0x1F0403A8,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1       0x1F0403A8,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1       0x1F0403A8,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_2__ADDR                   0x1F0403AC
+#define LPM_MEM_DI1_DW_SET3_2__EMPTY       0x1F0403AC,0x00000000
+#define LPM_MEM_DI1_DW_SET3_2__FULL       0x1F0403AC,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2       0x1F0403AC,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2       0x1F0403AC,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_3__ADDR                   0x1F0403B0
+#define LPM_MEM_DI1_DW_SET3_3__EMPTY       0x1F0403B0,0x00000000
+#define LPM_MEM_DI1_DW_SET3_3__FULL       0x1F0403B0,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3       0x1F0403B0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3       0x1F0403B0,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_4__ADDR                   0x1F0403B4
+#define LPM_MEM_DI1_DW_SET3_4__EMPTY       0x1F0403B4,0x00000000
+#define LPM_MEM_DI1_DW_SET3_4__FULL       0x1F0403B4,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4       0x1F0403B4,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4       0x1F0403B4,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_5__ADDR                   0x1F0403B8
+#define LPM_MEM_DI1_DW_SET3_5__EMPTY       0x1F0403B8,0x00000000
+#define LPM_MEM_DI1_DW_SET3_5__FULL       0x1F0403B8,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5       0x1F0403B8,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5       0x1F0403B8,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_6__ADDR                   0x1F0403BC
+#define LPM_MEM_DI1_DW_SET3_6__EMPTY       0x1F0403BC,0x00000000
+#define LPM_MEM_DI1_DW_SET3_6__FULL       0x1F0403BC,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6       0x1F0403BC,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6       0x1F0403BC,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_7__ADDR                   0x1F0403C0
+#define LPM_MEM_DI1_DW_SET3_7__EMPTY       0x1F0403C0,0x00000000
+#define LPM_MEM_DI1_DW_SET3_7__FULL       0x1F0403C0,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7       0x1F0403C0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7       0x1F0403C0,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_8__ADDR                   0x1F0403C4
+#define LPM_MEM_DI1_DW_SET3_8__EMPTY       0x1F0403C4,0x00000000
+#define LPM_MEM_DI1_DW_SET3_8__FULL       0x1F0403C4,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8       0x1F0403C4,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8       0x1F0403C4,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_9__ADDR                   0x1F0403C8
+#define LPM_MEM_DI1_DW_SET3_9__EMPTY       0x1F0403C8,0x00000000
+#define LPM_MEM_DI1_DW_SET3_9__FULL       0x1F0403C8,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9       0x1F0403C8,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9       0x1F0403C8,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_10__ADDR                   0x1F0403CC
+#define LPM_MEM_DI1_DW_SET3_10__EMPTY       0x1F0403CC,0x00000000
+#define LPM_MEM_DI1_DW_SET3_10__FULL       0x1F0403CC,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10       0x1F0403CC,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10       0x1F0403CC,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_11__ADDR                   0x1F0403D0
+#define LPM_MEM_DI1_DW_SET3_11__EMPTY       0x1F0403D0,0x00000000
+#define LPM_MEM_DI1_DW_SET3_11__FULL       0x1F0403D0,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11       0x1F0403D0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11       0x1F0403D0,0x000001FF
+
+#define LPM_MEM_DI1_STP_REP_1__ADDR                   0x1F0403D4
+#define LPM_MEM_DI1_STP_REP_1__EMPTY       0x1F0403D4,0x00000000
+#define LPM_MEM_DI1_STP_REP_1__FULL       0x1F0403D4,0xffffffff
+#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_2       0x1F0403D4,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_1       0x1F0403D4,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_2__ADDR                   0x1F0403D8
+#define LPM_MEM_DI1_STP_REP_2__EMPTY       0x1F0403D8,0x00000000
+#define LPM_MEM_DI1_STP_REP_2__FULL       0x1F0403D8,0xffffffff
+#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_4       0x1F0403D8,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_3       0x1F0403D8,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_3__ADDR                   0x1F0403DC
+#define LPM_MEM_DI1_STP_REP_3__EMPTY       0x1F0403DC,0x00000000
+#define LPM_MEM_DI1_STP_REP_3__FULL       0x1F0403DC,0xffffffff
+#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_6       0x1F0403DC,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_5       0x1F0403DC,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_4__ADDR                   0x1F0403E0
+#define LPM_MEM_DI1_STP_REP_4__EMPTY       0x1F0403E0,0x00000000
+#define LPM_MEM_DI1_STP_REP_4__FULL       0x1F0403E0,0xffffffff
+#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_8       0x1F0403E0,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_7       0x1F0403E0,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_9__ADDR                   0x1F0403E4
+#define LPM_MEM_DI1_STP_REP_9__EMPTY       0x1F0403E4,0x00000000
+#define LPM_MEM_DI1_STP_REP_9__FULL       0x1F0403E4,0xffffffff
+#define LPM_MEM_DI1_STP_REP_9__DI1_STEP_REPEAT_9       0x1F0403E4,0x00000FFF
+
+#define LPM_MEM_DI1_SER_CONF__ADDR                   0x1F0403E8
+#define LPM_MEM_DI1_SER_CONF__EMPTY       0x1F0403E8,0x00000000
+#define LPM_MEM_DI1_SER_CONF__FULL       0x1F0403E8,0xffffffff
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1       0x1F0403E8,0xF0000000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0       0x1F0403E8,0x0F000000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1       0x1F0403E8,0x00F00000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0       0x1F0403E8,0x000F0000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LATCH       0x1F0403E8,0x0000FF00
+#define LPM_MEM_DI1_SER_CONF__DI1_LLA_SER_ACCESS       0x1F0403E8,0x00000020
+#define LPM_MEM_DI1_SER_CONF__DI1_SER_CLK_POLARITY       0x1F0403E8,0x00000010
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY       0x1F0403E8,0x00000008
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY       0x1F0403E8,0x00000004
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY       0x1F0403E8,0x00000002
+#define LPM_MEM_DI1_SER_CONF__DI1_WAIT4SERIAL       0x1F0403E8,0x00000001
+
+#define LPM_MEM_DI1_SSC__ADDR                   0x1F0403EC
+#define LPM_MEM_DI1_SSC__EMPTY       0x1F0403EC,0x00000000
+#define LPM_MEM_DI1_SSC__FULL       0x1F0403EC,0xffffffff
+#define LPM_MEM_DI1_SSC__DI1_PIN17_ERM       0x1F0403EC,0x00800000
+#define LPM_MEM_DI1_SSC__DI1_PIN16_ERM       0x1F0403EC,0x00400000
+#define LPM_MEM_DI1_SSC__DI1_PIN15_ERM       0x1F0403EC,0x00200000
+#define LPM_MEM_DI1_SSC__DI1_PIN14_ERM       0x1F0403EC,0x00100000
+#define LPM_MEM_DI1_SSC__DI1_PIN13_ERM       0x1F0403EC,0x00080000
+#define LPM_MEM_DI1_SSC__DI1_PIN12_ERM       0x1F0403EC,0x00040000
+#define LPM_MEM_DI1_SSC__DI1_PIN11_ERM       0x1F0403EC,0x00020000
+#define LPM_MEM_DI1_SSC__DI1_CS_ERM       0x1F0403EC,0x00010000
+#define LPM_MEM_DI1_SSC__DI1_WAIT_ON       0x1F0403EC,0x00000020
+#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_RD_IN       0x1F0403EC,0x00000008
+#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_PNTR       0x1F0403EC,0x00000007
+
+#define LPM_MEM_DI1_POL__ADDR                   0x1F0403F0
+#define LPM_MEM_DI1_POL__EMPTY       0x1F0403F0,0x00000000
+#define LPM_MEM_DI1_POL__FULL       0x1F0403F0,0xffffffff
+#define LPM_MEM_DI1_POL__DI1_WAIT_POLARITY       0x1F0403F0,0x04000000
+#define LPM_MEM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY       0x1F0403F0,0x02000000
+#define LPM_MEM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY       0x1F0403F0,0x01000000
+#define LPM_MEM_DI1_POL__DI1_CS1_DATA_POLARITY       0x1F0403F0,0x00800000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_17       0x1F0403F0,0x00400000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_16       0x1F0403F0,0x00200000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_15       0x1F0403F0,0x00100000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_14       0x1F0403F0,0x00080000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_13       0x1F0403F0,0x00040000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_12       0x1F0403F0,0x00020000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_11       0x1F0403F0,0x00010000
+#define LPM_MEM_DI1_POL__DI1_CS0_DATA_POLARITY       0x1F0403F0,0x00008000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_17       0x1F0403F0,0x00004000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_16       0x1F0403F0,0x00002000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_15       0x1F0403F0,0x00001000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_14       0x1F0403F0,0x00000800
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_13       0x1F0403F0,0x00000400
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_12       0x1F0403F0,0x00000200
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_11       0x1F0403F0,0x00000100
+#define LPM_MEM_DI1_POL__DI1_DRDY_DATA_POLARITY       0x1F0403F0,0x00000080
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_17       0x1F0403F0,0x00000040
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_16       0x1F0403F0,0x00000020
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_15       0x1F0403F0,0x00000010
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_14       0x1F0403F0,0x00000008
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_13       0x1F0403F0,0x00000004
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_12       0x1F0403F0,0x00000002
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_11       0x1F0403F0,0x00000001
+
+#define LPM_MEM_DI1_AW0__ADDR                   0x1F0403F4
+#define LPM_MEM_DI1_AW0__EMPTY       0x1F0403F4,0x00000000
+#define LPM_MEM_DI1_AW0__FULL       0x1F0403F4,0xffffffff
+#define LPM_MEM_DI1_AW0__DI1_AW_TRIG_SEL       0x1F0403F4,0xF0000000
+#define LPM_MEM_DI1_AW0__DI1_AW_HEND       0x1F0403F4,0x0FFF0000
+#define LPM_MEM_DI1_AW0__DI1_AW_HCOUNT_SEL       0x1F0403F4,0x0000F000
+#define LPM_MEM_DI1_AW0__DI1_AW_HSTART       0x1F0403F4,0x00000FFF
+
+#define LPM_MEM_DI1_AW1__ADDR                   0x1F0403F8
+#define LPM_MEM_DI1_AW1__EMPTY       0x1F0403F8,0x00000000
+#define LPM_MEM_DI1_AW1__FULL       0x1F0403F8,0xffffffff
+#define LPM_MEM_DI1_AW1__DI1_AW_VEND       0x1F0403F8,0x0FFF0000
+#define LPM_MEM_DI1_AW1__DI1_AW_VCOUNT_SEL       0x1F0403F8,0x0000F000
+#define LPM_MEM_DI1_AW1__DI1_AW_VSTART       0x1F0403F8,0x00000FFF
+
+#define LPM_MEM_DI1_SCR_CONF__ADDR                   0x1F0403FC
+#define LPM_MEM_DI1_SCR_CONF__EMPTY       0x1F0403FC,0x00000000
+#define LPM_MEM_DI1_SCR_CONF__FULL       0x1F0403FC,0xffffffff
+#define LPM_MEM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT       0x1F0403FC,0x00000FFF
+
+#define LPM_MEM_DMFC_RD_CHAN__ADDR                   0x1F040400
+#define LPM_MEM_DMFC_RD_CHAN__EMPTY       0x1F040400,0x00000000
+#define LPM_MEM_DMFC_RD_CHAN__FULL       0x1F040400,0xffffffff
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_PPW_C       0x1F040400,0x03000000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_CLR_0       0x1F040400,0x00E00000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_SET_0       0x1F040400,0x001C0000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_EN_0       0x1F040400,0x00020000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_BURST_SIZE_0       0x1F040400,0x000000C0
+
+#define LPM_MEM_DMFC_WR_CHAN__ADDR                   0x1F040404
+#define LPM_MEM_DMFC_WR_CHAN__EMPTY       0x1F040404,0x00000000
+#define LPM_MEM_DMFC_WR_CHAN__FULL       0x1F040404,0xffffffff
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C       0x1F040404,0xC0000000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C       0x1F040404,0x38000000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2C       0x1F040404,0x07000000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C       0x1F040404,0x00C00000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C       0x1F040404,0x00380000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1C       0x1F040404,0x00070000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2       0x1F040404,0x0000C000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2       0x1F040404,0x00003800
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2       0x1F040404,0x00000700
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1       0x1F040404,0x000000C0
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1       0x1F040404,0x00000038
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1       0x1F040404,0x00000007
+
+#define LPM_MEM_DMFC_WR_CHAN_DEF__ADDR                   0x1F040408
+#define LPM_MEM_DMFC_WR_CHAN_DEF__EMPTY       0x1F040408,0x00000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__FULL       0x1F040408,0xffffffff
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C       0x1F040408,0xE0000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C       0x1F040408,0x1C000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C       0x1F040408,0x02000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C       0x1F040408,0x00E00000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C       0x1F040408,0x001C0000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C       0x1F040408,0x00020000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2       0x1F040408,0x0000E000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2       0x1F040408,0x00001C00
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2       0x1F040408,0x00000200
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1       0x1F040408,0x000000E0
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1       0x1F040408,0x0000001C
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1       0x1F040408,0x00000002
+
+#define LPM_MEM_DMFC_DP_CHAN__ADDR                   0x1F04040C
+#define LPM_MEM_DMFC_DP_CHAN__EMPTY       0x1F04040C,0x00000000
+#define LPM_MEM_DMFC_DP_CHAN__FULL       0x1F04040C,0xffffffff
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F       0x1F04040C,0xC0000000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F       0x1F04040C,0x38000000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6F       0x1F04040C,0x07000000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B       0x1F04040C,0x00C00000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B       0x1F04040C,0x00380000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6B       0x1F04040C,0x00070000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F       0x1F04040C,0x0000C000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F       0x1F04040C,0x00003800
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5F       0x1F04040C,0x00000700
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B       0x1F04040C,0x000000C0
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B       0x1F04040C,0x00000038
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5B       0x1F04040C,0x00000007
+
+#define LPM_MEM_DMFC_DP_CHAN_DEF__ADDR                   0x1F040410
+#define LPM_MEM_DMFC_DP_CHAN_DEF__EMPTY       0x1F040410,0x00000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__FULL       0x1F040410,0xffffffff
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F       0x1F040410,0xE0000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F       0x1F040410,0x1C000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F       0x1F040410,0x02000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B       0x1F040410,0x00E00000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B       0x1F040410,0x001C0000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B       0x1F040410,0x00020000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F       0x1F040410,0x0000E000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F       0x1F040410,0x00001C00
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F       0x1F040410,0x00000200
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B       0x1F040410,0x000000E0
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B       0x1F040410,0x0000001C
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B       0x1F040410,0x00000002
+
+#define LPM_MEM_DMFC_GENERAL1__ADDR                   0x1F040414
+#define LPM_MEM_DMFC_GENERAL1__EMPTY       0x1F040414,0x00000000
+#define LPM_MEM_DMFC_GENERAL1__FULL       0x1F040414,0xffffffff
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_9       0x1F040414,0x01000000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6F       0x1F040414,0x00800000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6B       0x1F040414,0x00400000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5F       0x1F040414,0x00200000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5B       0x1F040414,0x00100000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_4       0x1F040414,0x00080000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_3       0x1F040414,0x00040000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_2       0x1F040414,0x00020000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_1       0x1F040414,0x00010000
+#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_CLR_9     0x1F040414,0x0000E000
+#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_SET_9     0x1F040414,0x00001C00
+#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_EN_9      0x1F040414,0x00000200
+#define LPM_MEM_DMFC_GENERAL1__DMFC_BURST_SIZE_9       0x1F040414,0x00000060
+#define LPM_MEM_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR       0x1F040414,0x00000003
+
+#define LPM_MEM_DMFC_GENERAL2__ADDR                   0x1F040418
+#define LPM_MEM_DMFC_GENERAL2__EMPTY       0x1F040418,0x00000000
+#define LPM_MEM_DMFC_GENERAL2__FULL       0x1F040418,0xffffffff
+#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD       0x1F040418,0x1FFF0000
+#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD       0x1F040418,0x00001FFF
+
+#define LPM_MEM_DMFC_IC_CTRL__ADDR                   0x1F04041C
+#define LPM_MEM_DMFC_IC_CTRL__EMPTY       0x1F04041C,0x00000000
+#define LPM_MEM_DMFC_IC_CTRL__FULL       0x1F04041C,0xffffffff
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD       0x1F04041C,0xFFF80000
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD       0x1F04041C,0x0007FFC0
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_PPW_C       0x1F04041C,0x00000030
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_IN_PORT         0x1F04041C,0x00000007
+
+#define LPM_MEM_DC_READ_CH_CONF__ADDR                   0x1F040420
+#define LPM_MEM_DC_READ_CH_CONF__EMPTY       0x1F040420,0x00000000
+#define LPM_MEM_DC_READ_CH_CONF__FULL       0x1F040420,0xffffffff
+#define LPM_MEM_DC_READ_CH_CONF__TIME_OUT_VALUE       0x1F040420,0xFFFF0000
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_3       0x1F040420,0x00000800
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_2       0x1F040420,0x00000400
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_1       0x1F040420,0x00000200
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_0       0x1F040420,0x00000100
+#define LPM_MEM_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0       0x1F040420,0x00000040
+#define LPM_MEM_DC_READ_CH_CONF__W_SIZE_0       0x1F040420,0x00000030
+#define LPM_MEM_DC_READ_CH_CONF__PROG_DISP_ID_0       0x1F040420,0x0000000C
+#define LPM_MEM_DC_READ_CH_CONF__PROG_DI_ID_0       0x1F040420,0x00000002
+#define LPM_MEM_DC_READ_CH_CONF__RD_CHANNEL_EN       0x1F040420,0x00000001
+
+#define LPM_MEM_DC_READ_CH_ADDR__ADDR                   0x1F040424
+#define LPM_MEM_DC_READ_CH_ADDR__EMPTY       0x1F040424,0x00000000
+#define LPM_MEM_DC_READ_CH_ADDR__FULL       0x1F040424,0xffffffff
+#define LPM_MEM_DC_READ_CH_ADDR__ST_ADDR_0       0x1F040424,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_0__ADDR                   0x1F040428
+#define LPM_MEM_DC_RL0_CH_0__EMPTY       0x1F040428,0x00000000
+#define LPM_MEM_DC_RL0_CH_0__FULL       0x1F040428,0xffffffff
+#define LPM_MEM_DC_RL0_CH_0__COD_NL_START_CHAN_0       0x1F040428,0xFF000000
+#define LPM_MEM_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0       0x1F040428,0x000F0000
+#define LPM_MEM_DC_RL0_CH_0__COD_NF_START_CHAN_0       0x1F040428,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0       0x1F040428,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_0__ADDR                   0x1F04042C
+#define LPM_MEM_DC_RL1_CH_0__EMPTY       0x1F04042C,0x00000000
+#define LPM_MEM_DC_RL1_CH_0__FULL       0x1F04042C,0xffffffff
+#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0       0x1F04042C,0xFF000000
+#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0       0x1F04042C,0x000F0000
+#define LPM_MEM_DC_RL1_CH_0__COD_EOF_START_CHAN_0       0x1F04042C,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0       0x1F04042C,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_0__ADDR                   0x1F040430
+#define LPM_MEM_DC_RL2_CH_0__EMPTY       0x1F040430,0x00000000
+#define LPM_MEM_DC_RL2_CH_0__FULL       0x1F040430,0xffffffff
+#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0       0x1F040430,0xFF000000
+#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0       0x1F040430,0x000F0000
+#define LPM_MEM_DC_RL2_CH_0__COD_EOL_START_CHAN_0       0x1F040430,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0       0x1F040430,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_0__ADDR                   0x1F040434
+#define LPM_MEM_DC_RL3_CH_0__EMPTY       0x1F040434,0x00000000
+#define LPM_MEM_DC_RL3_CH_0__FULL       0x1F040434,0xffffffff
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0       0x1F040434,0xFF000000
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0       0x1F040434,0x000F0000
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0       0x1F040434,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0       0x1F040434,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_0__ADDR                   0x1F040438
+#define LPM_MEM_DC_RL4_CH_0__EMPTY       0x1F040438,0x00000000
+#define LPM_MEM_DC_RL4_CH_0__FULL       0x1F040438,0xffffffff
+#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0       0x1F040438,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0       0x1F040438,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF_1__ADDR                   0x1F04043C
+#define LPM_MEM_DC_WR_CH_CONF_1__EMPTY       0x1F04043C,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_1__FULL       0x1F04043C,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_START_TIME_1       0x1F04043C,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_1__FIELD_MODE_1       0x1F04043C,0x00000200
+#define LPM_MEM_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1       0x1F04043C,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1       0x1F04043C,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DISP_ID_1       0x1F04043C,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DI_ID_1       0x1F04043C,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_1__W_SIZE_1       0x1F04043C,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_1__ADDR                   0x1F040440
+#define LPM_MEM_DC_WR_CH_ADDR_1__EMPTY       0x1F040440,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_1__FULL       0x1F040440,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_1__ST_ADDR_1       0x1F040440,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_1__ADDR                   0x1F040444
+#define LPM_MEM_DC_RL0_CH_1__EMPTY       0x1F040444,0x00000000
+#define LPM_MEM_DC_RL0_CH_1__FULL       0x1F040444,0xffffffff
+#define LPM_MEM_DC_RL0_CH_1__COD_NL_START_CHAN_1       0x1F040444,0xFF000000
+#define LPM_MEM_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1       0x1F040444,0x000F0000
+#define LPM_MEM_DC_RL0_CH_1__COD_NF_START_CHAN_1       0x1F040444,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1       0x1F040444,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_1__ADDR                   0x1F040448
+#define LPM_MEM_DC_RL1_CH_1__EMPTY       0x1F040448,0x00000000
+#define LPM_MEM_DC_RL1_CH_1__FULL       0x1F040448,0xffffffff
+#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1       0x1F040448,0xFF000000
+#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1       0x1F040448,0x000F0000
+#define LPM_MEM_DC_RL1_CH_1__COD_EOF_START_CHAN_1       0x1F040448,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1       0x1F040448,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_1__ADDR                   0x1F04044C
+#define LPM_MEM_DC_RL2_CH_1__EMPTY       0x1F04044C,0x00000000
+#define LPM_MEM_DC_RL2_CH_1__FULL       0x1F04044C,0xffffffff
+#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1       0x1F04044C,0xFF000000
+#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1       0x1F04044C,0x000F0000
+#define LPM_MEM_DC_RL2_CH_1__COD_EOL_START_CHAN_1       0x1F04044C,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1       0x1F04044C,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_1__ADDR                   0x1F040450
+#define LPM_MEM_DC_RL3_CH_1__EMPTY       0x1F040450,0x00000000
+#define LPM_MEM_DC_RL3_CH_1__FULL       0x1F040450,0xffffffff
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1       0x1F040450,0xFF000000
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1       0x1F040450,0x000F0000
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1       0x1F040450,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1       0x1F040450,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_1__ADDR                   0x1F040454
+#define LPM_MEM_DC_RL4_CH_1__EMPTY       0x1F040454,0x00000000
+#define LPM_MEM_DC_RL4_CH_1__FULL       0x1F040454,0xffffffff
+#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1       0x1F040454,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1       0x1F040454,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF_2__ADDR                   0x1F040458
+#define LPM_MEM_DC_WR_CH_CONF_2__EMPTY       0x1F040458,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_2__FULL       0x1F040458,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_START_TIME_2       0x1F040458,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2       0x1F040458,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2       0x1F040458,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DISP_ID_2       0x1F040458,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DI_ID_2       0x1F040458,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_2__W_SIZE_2       0x1F040458,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_2__ADDR                   0x1F04045C
+#define LPM_MEM_DC_WR_CH_ADDR_2__EMPTY       0x1F04045C,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_2__FULL       0x1F04045C,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_2__ST_ADDR_2       0x1F04045C,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_2__ADDR                   0x1F040460
+#define LPM_MEM_DC_RL0_CH_2__EMPTY       0x1F040460,0x00000000
+#define LPM_MEM_DC_RL0_CH_2__FULL       0x1F040460,0xffffffff
+#define LPM_MEM_DC_RL0_CH_2__COD_NL_START_CHAN_2       0x1F040460,0xFF000000
+#define LPM_MEM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2       0x1F040460,0x000F0000
+#define LPM_MEM_DC_RL0_CH_2__COD_NF_START_CHAN_2       0x1F040460,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2       0x1F040460,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_2__ADDR                   0x1F040464
+#define LPM_MEM_DC_RL1_CH_2__EMPTY       0x1F040464,0x00000000
+#define LPM_MEM_DC_RL1_CH_2__FULL       0x1F040464,0xffffffff
+#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2       0x1F040464,0xFF000000
+#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2       0x1F040464,0x000F0000
+#define LPM_MEM_DC_RL1_CH_2__COD_EOF_START_CHAN_2       0x1F040464,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2       0x1F040464,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_2__ADDR                   0x1F040468
+#define LPM_MEM_DC_RL2_CH_2__EMPTY       0x1F040468,0x00000000
+#define LPM_MEM_DC_RL2_CH_2__FULL       0x1F040468,0xffffffff
+#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2       0x1F040468,0xFF000000
+#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2       0x1F040468,0x000F0000
+#define LPM_MEM_DC_RL2_CH_2__COD_EOL_START_CHAN_2       0x1F040468,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2       0x1F040468,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_2__ADDR                   0x1F04046C
+#define LPM_MEM_DC_RL3_CH_2__EMPTY       0x1F04046C,0x00000000
+#define LPM_MEM_DC_RL3_CH_2__FULL       0x1F04046C,0xffffffff
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2       0x1F04046C,0xFF000000
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2       0x1F04046C,0x000F0000
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2       0x1F04046C,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2       0x1F04046C,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_2__ADDR                   0x1F040470
+#define LPM_MEM_DC_RL4_CH_2__EMPTY       0x1F040470,0x00000000
+#define LPM_MEM_DC_RL4_CH_2__FULL       0x1F040470,0xffffffff
+#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2       0x1F040470,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2       0x1F040470,0x0000000F
+
+#define LPM_MEM_DC_CMD_CH_CONF_3__ADDR                   0x1F040474
+#define LPM_MEM_DC_CMD_CH_CONF_3__EMPTY       0x1F040474,0x00000000
+#define LPM_MEM_DC_CMD_CH_CONF_3__FULL       0x1F040474,0xffffffff
+#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3       0x1F040474,0xFF000000
+#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3       0x1F040474,0x0000FF00
+#define LPM_MEM_DC_CMD_CH_CONF_3__W_SIZE_3       0x1F040474,0x00000003
+
+#define LPM_MEM_DC_CMD_CH_CONF_4__ADDR                   0x1F040478
+#define LPM_MEM_DC_CMD_CH_CONF_4__EMPTY       0x1F040478,0x00000000
+#define LPM_MEM_DC_CMD_CH_CONF_4__FULL       0x1F040478,0xffffffff
+#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4       0x1F040478,0xFF000000
+#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4       0x1F040478,0x0000FF00
+#define LPM_MEM_DC_CMD_CH_CONF_4__W_SIZE_4       0x1F040478,0x00000003
+
+#define LPM_MEM_DC_WR_CH_CONF_5__ADDR                   0x1F04047C
+#define LPM_MEM_DC_WR_CH_CONF_5__EMPTY       0x1F04047C,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_5__FULL       0x1F04047C,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_START_TIME_5       0x1F04047C,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_5__FIELD_MODE_5       0x1F04047C,0x00000200
+#define LPM_MEM_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5       0x1F04047C,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5       0x1F04047C,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DISP_ID_5       0x1F04047C,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DI_ID_5       0x1F04047C,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_5__W_SIZE_5       0x1F04047C,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_5__ADDR                   0x1F040480
+#define LPM_MEM_DC_WR_CH_ADDR_5__EMPTY       0x1F040480,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_5__FULL       0x1F040480,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_5__ST_ADDR_5       0x1F040480,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_5__ADDR                   0x1F040484
+#define LPM_MEM_DC_RL0_CH_5__EMPTY       0x1F040484,0x00000000
+#define LPM_MEM_DC_RL0_CH_5__FULL       0x1F040484,0xffffffff
+#define LPM_MEM_DC_RL0_CH_5__COD_NL_START_CHAN_5       0x1F040484,0xFF000000
+#define LPM_MEM_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5       0x1F040484,0x000F0000
+#define LPM_MEM_DC_RL0_CH_5__COD_NF_START_CHAN_5       0x1F040484,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5       0x1F040484,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_5__ADDR                   0x1F040488
+#define LPM_MEM_DC_RL1_CH_5__EMPTY       0x1F040488,0x00000000
+#define LPM_MEM_DC_RL1_CH_5__FULL       0x1F040488,0xffffffff
+#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5       0x1F040488,0xFF000000
+#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5       0x1F040488,0x000F0000
+#define LPM_MEM_DC_RL1_CH_5__COD_EOF_START_CHAN_5       0x1F040488,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5       0x1F040488,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_5__ADDR                   0x1F04048C
+#define LPM_MEM_DC_RL2_CH_5__EMPTY       0x1F04048C,0x00000000
+#define LPM_MEM_DC_RL2_CH_5__FULL       0x1F04048C,0xffffffff
+#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5       0x1F04048C,0xFF000000
+#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5       0x1F04048C,0x000F0000
+#define LPM_MEM_DC_RL2_CH_5__COD_EOL_START_CHAN_5       0x1F04048C,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5       0x1F04048C,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_5__ADDR                   0x1F040490
+#define LPM_MEM_DC_RL3_CH_5__EMPTY       0x1F040490,0x00000000
+#define LPM_MEM_DC_RL3_CH_5__FULL       0x1F040490,0xffffffff
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5       0x1F040490,0xFF000000
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5       0x1F040490,0x000F0000
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5       0x1F040490,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5       0x1F040490,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_5__ADDR                   0x1F040494
+#define LPM_MEM_DC_RL4_CH_5__EMPTY       0x1F040494,0x00000000
+#define LPM_MEM_DC_RL4_CH_5__FULL       0x1F040494,0xffffffff
+#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5       0x1F040494,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5       0x1F040494,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF_6__ADDR                   0x1F040498
+#define LPM_MEM_DC_WR_CH_CONF_6__EMPTY       0x1F040498,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_6__FULL       0x1F040498,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_START_TIME_6       0x1F040498,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6       0x1F040498,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6       0x1F040498,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DISP_ID_6       0x1F040498,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DI_ID_6       0x1F040498,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_6__W_SIZE_6       0x1F040498,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_6__ADDR                   0x1F04049C
+#define LPM_MEM_DC_WR_CH_ADDR_6__EMPTY       0x1F04049C,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_6__FULL       0x1F04049C,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_6__ST_ADDR_6       0x1F04049C,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_6__ADDR                   0x1F0404A0
+#define LPM_MEM_DC_RL0_CH_6__EMPTY       0x1F0404A0,0x00000000
+#define LPM_MEM_DC_RL0_CH_6__FULL       0x1F0404A0,0xffffffff
+#define LPM_MEM_DC_RL0_CH_6__COD_NL_START_CHAN_6       0x1F0404A0,0xFF000000
+#define LPM_MEM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6       0x1F0404A0,0x000F0000
+#define LPM_MEM_DC_RL0_CH_6__COD_NF_START_CHAN_6       0x1F0404A0,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6       0x1F0404A0,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_6__ADDR                   0x1F0404A4
+#define LPM_MEM_DC_RL1_CH_6__EMPTY       0x1F0404A4,0x00000000
+#define LPM_MEM_DC_RL1_CH_6__FULL       0x1F0404A4,0xffffffff
+#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6       0x1F0404A4,0xFF000000
+#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6       0x1F0404A4,0x000F0000
+#define LPM_MEM_DC_RL1_CH_6__COD_EOF_START_CHAN_6       0x1F0404A4,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6       0x1F0404A4,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_6__ADDR                   0x1F0404A8
+#define LPM_MEM_DC_RL2_CH_6__EMPTY       0x1F0404A8,0x00000000
+#define LPM_MEM_DC_RL2_CH_6__FULL       0x1F0404A8,0xffffffff
+#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6       0x1F0404A8,0xFF000000
+#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6       0x1F0404A8,0x000F0000
+#define LPM_MEM_DC_RL2_CH_6__COD_EOL_START_CHAN_6       0x1F0404A8,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6       0x1F0404A8,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_6__ADDR                   0x1F0404AC
+#define LPM_MEM_DC_RL3_CH_6__EMPTY       0x1F0404AC,0x00000000
+#define LPM_MEM_DC_RL3_CH_6__FULL       0x1F0404AC,0xffffffff
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6       0x1F0404AC,0xFF000000
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6       0x1F0404AC,0x000F0000
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6       0x1F0404AC,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6       0x1F0404AC,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_6__ADDR                   0x1F0404B0
+#define LPM_MEM_DC_RL4_CH_6__EMPTY       0x1F0404B0,0x00000000
+#define LPM_MEM_DC_RL4_CH_6__FULL       0x1F0404B0,0xffffffff
+#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6       0x1F0404B0,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6       0x1F0404B0,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF1_8__ADDR                   0x1F0404B4
+#define LPM_MEM_DC_WR_CH_CONF1_8__EMPTY       0x1F0404B4,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF1_8__FULL       0x1F0404B4,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF1_8__MCU_DISP_ID_8       0x1F0404B4,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8       0x1F0404B4,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF1_8__W_SIZE_8       0x1F0404B4,0x00000003
+
+#define LPM_MEM_DC_WR_CH_CONF2_8__ADDR                   0x1F0404B8
+#define LPM_MEM_DC_WR_CH_CONF2_8__EMPTY       0x1F0404B8,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF2_8__FULL       0x1F0404B8,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8       0x1F0404B8,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL1_CH_8__ADDR                   0x1F0404BC
+#define LPM_MEM_DC_RL1_CH_8__EMPTY       0x1F0404BC,0x00000000
+#define LPM_MEM_DC_RL1_CH_8__FULL       0x1F0404BC,0xffffffff
+#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1       0x1F0404BC,0xFF000000
+#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0       0x1F0404BC,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8       0x1F0404BC,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_8__ADDR                   0x1F0404C0
+#define LPM_MEM_DC_RL2_CH_8__EMPTY       0x1F0404C0,0x00000000
+#define LPM_MEM_DC_RL2_CH_8__FULL       0x1F0404C0,0xffffffff
+#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1       0x1F0404C0,0xFF000000
+#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0       0x1F0404C0,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8       0x1F0404C0,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_8__ADDR                   0x1F0404C4
+#define LPM_MEM_DC_RL3_CH_8__EMPTY       0x1F0404C4,0x00000000
+#define LPM_MEM_DC_RL3_CH_8__FULL       0x1F0404C4,0xffffffff
+#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1       0x1F0404C4,0xFF000000
+#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0       0x1F0404C4,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8       0x1F0404C4,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_8__ADDR                   0x1F0404C8
+#define LPM_MEM_DC_RL4_CH_8__EMPTY       0x1F0404C8,0x00000000
+#define LPM_MEM_DC_RL4_CH_8__FULL       0x1F0404C8,0xffffffff
+#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1       0x1F0404C8,0xFF000000
+#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0       0x1F0404C8,0x0000FF00
+
+#define LPM_MEM_DC_RL5_CH_8__ADDR                   0x1F0404CC
+#define LPM_MEM_DC_RL5_CH_8__EMPTY       0x1F0404CC,0x00000000
+#define LPM_MEM_DC_RL5_CH_8__FULL       0x1F0404CC,0xffffffff
+#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1       0x1F0404CC,0xFF000000
+#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0       0x1F0404CC,0x0000FF00
+
+#define LPM_MEM_DC_RL6_CH_8__ADDR                   0x1F0404D0
+#define LPM_MEM_DC_RL6_CH_8__EMPTY       0x1F0404D0,0x00000000
+#define LPM_MEM_DC_RL6_CH_8__FULL       0x1F0404D0,0xffffffff
+#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1       0x1F0404D0,0xFF000000
+#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0       0x1F0404D0,0x0000FF00
+
+#define LPM_MEM_DC_WR_CH_CONF1_9__ADDR                   0x1F0404D4
+#define LPM_MEM_DC_WR_CH_CONF1_9__EMPTY       0x1F0404D4,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF1_9__FULL       0x1F0404D4,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF1_9__MCU_DISP_ID_9       0x1F0404D4,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9       0x1F0404D4,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF1_9__W_SIZE_9       0x1F0404D4,0x00000003
+
+#define LPM_MEM_DC_WR_CH_CONF2_9__ADDR                   0x1F0404D8
+#define LPM_MEM_DC_WR_CH_CONF2_9__EMPTY       0x1F0404D8,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF2_9__FULL       0x1F0404D8,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9       0x1F0404D8,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL1_CH_9__ADDR                   0x1F0404DC
+#define LPM_MEM_DC_RL1_CH_9__EMPTY       0x1F0404DC,0x00000000
+#define LPM_MEM_DC_RL1_CH_9__FULL       0x1F0404DC,0xffffffff
+#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1       0x1F0404DC,0xFF000000
+#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0       0x1F0404DC,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9       0x1F0404DC,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_9__ADDR                   0x1F0404E0
+#define LPM_MEM_DC_RL2_CH_9__EMPTY       0x1F0404E0,0x00000000
+#define LPM_MEM_DC_RL2_CH_9__FULL       0x1F0404E0,0xffffffff
+#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1       0x1F0404E0,0xFF000000
+#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0       0x1F0404E0,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9       0x1F0404E0,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_9__ADDR                   0x1F0404E4
+#define LPM_MEM_DC_RL3_CH_9__EMPTY       0x1F0404E4,0x00000000
+#define LPM_MEM_DC_RL3_CH_9__FULL       0x1F0404E4,0xffffffff
+#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1       0x1F0404E4,0xFF000000
+#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0       0x1F0404E4,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9       0x1F0404E4,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_9__ADDR                   0x1F0404E8
+#define LPM_MEM_DC_RL4_CH_9__EMPTY       0x1F0404E8,0x00000000
+#define LPM_MEM_DC_RL4_CH_9__FULL       0x1F0404E8,0xffffffff
+#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1       0x1F0404E8,0xFF000000
+#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0       0x1F0404E8,0x0000FF00
+
+#define LPM_MEM_DC_RL5_CH_9__ADDR                   0x1F0404EC
+#define LPM_MEM_DC_RL5_CH_9__EMPTY       0x1F0404EC,0x00000000
+#define LPM_MEM_DC_RL5_CH_9__FULL       0x1F0404EC,0xffffffff
+#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1       0x1F0404EC,0xFF000000
+#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0       0x1F0404EC,0x0000FF00
+
+#define LPM_MEM_DC_RL6_CH_9__ADDR                   0x1F0404F0
+#define LPM_MEM_DC_RL6_CH_9__EMPTY       0x1F0404F0,0x00000000
+#define LPM_MEM_DC_RL6_CH_9__FULL       0x1F0404F0,0xffffffff
+#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1       0x1F0404F0,0xFF000000
+#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0       0x1F0404F0,0x0000FF00
+
+#define LPM_MEM_DC_GEN__ADDR                   0x1F0404F4
+#define LPM_MEM_DC_GEN__EMPTY       0x1F0404F4,0x00000000
+#define LPM_MEM_DC_GEN__FULL       0x1F0404F4,0xffffffff
+#define LPM_MEM_DC_GEN__DC_BK_EN       0x1F0404F4,0x01000000
+#define LPM_MEM_DC_GEN__DC_BKDIV       0x1F0404F4,0x00FF0000
+#define LPM_MEM_DC_GEN__DC_CH5_TYPE       0x1F0404F4,0x00000100
+#define LPM_MEM_DC_GEN__SYNC_PRIORITY_1       0x1F0404F4,0x00000080
+#define LPM_MEM_DC_GEN__SYNC_PRIORITY_5       0x1F0404F4,0x00000040
+#define LPM_MEM_DC_GEN__MASK4CHAN_5       0x1F0404F4,0x00000020
+#define LPM_MEM_DC_GEN__MASK_EN       0x1F0404F4,0x00000010
+#define LPM_MEM_DC_GEN__SYNC_1_6       0x1F0404F4,0x00000006
+
+#define LPM_MEM_DC_DISP_CONF1_0__ADDR                0x1F0404F8
+#define LPM_MEM_DC_DISP_CONF1_0__EMPTY               0x1F0404F8,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_0__FULL                0x1F0404F8,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1F0404F8,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0   0x1F0404F8,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_0__ADDR_BE_L_INC_0     0x1F0404F8,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_0__ADDR_INCREMENT_0    0x1F0404F8,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_0__DISP_TYP_0          0x1F0404F8,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF1_1__ADDR                0x1F0404FC
+#define LPM_MEM_DC_DISP_CONF1_1__EMPTY               0x1F0404FC,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_1__FULL                0x1F0404FC,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1F0404FC,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1   0x1F0404FC,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_1__ADDR_BE_L_INC_1     0x1F0404FC,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_1__ADDR_INCREMENT_1    0x1F0404FC,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_1__DISP_TYP_1          0x1F0404FC,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF1_2__ADDR                0x1F040500
+#define LPM_MEM_DC_DISP_CONF1_2__EMPTY               0x1F040500,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_2__FULL                0x1F040500,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1F040500,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2   0x1F040500,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_2__ADDR_BE_L_INC_2     0x1F040500,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_2__ADDR_INCREMENT_2    0x1F040500,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_2__DISP_TYP_2          0x1F040500,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF1_3__ADDR                0x1F040504
+#define LPM_MEM_DC_DISP_CONF1_3__EMPTY               0x1F040504,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_3__FULL                0x1F040504,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1F040504,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3   0x1F040504,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_3__ADDR_BE_L_INC_3     0x1F040504,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_3__ADDR_INCREMENT_3    0x1F040504,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_3__DISP_TYP_3          0x1F040504,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF2_0__ADDR                   0x1F040508
+#define LPM_MEM_DC_DISP_CONF2_0__EMPTY       0x1F040508,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_0__FULL       0x1F040508,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_0__SL_0       0x1F040508,0x1FFFFFFF
+
+#define LPM_MEM_DC_DISP_CONF2_1__ADDR                   0x1F04050C
+#define LPM_MEM_DC_DISP_CONF2_1__EMPTY       0x1F04050C,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_1__FULL       0x1F04050C,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_1__SL_1       0x1F04050C,0x1FFFFFFF
+
+#define LPM_MEM_DC_DISP_CONF2_2__ADDR                   0x1F040510
+#define LPM_MEM_DC_DISP_CONF2_2__EMPTY       0x1F040510,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_2__FULL       0x1F040510,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_2__SL_2       0x1F040510,0x1FFFFFFF
+
+#define LPM_MEM_DC_DISP_CONF2_3__ADDR                   0x1F040514
+#define LPM_MEM_DC_DISP_CONF2_3__EMPTY       0x1F040514,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_3__FULL       0x1F040514,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_3__SL_3       0x1F040514,0x1FFFFFFF
+
+#define LPM_MEM_DC_DI0_CONF_1__ADDR                   0x1F040518
+#define LPM_MEM_DC_DI0_CONF_1__EMPTY       0x1F040518,0x00000000
+#define LPM_MEM_DC_DI0_CONF_1__FULL       0x1F040518,0xffffffff
+#define LPM_MEM_DC_DI0_CONF_1__DI_READ_DATA_MASK_0       0x1F040518,0xFFFFFFFF
+
+#define LPM_MEM_DC_DI0_CONF_2__ADDR                   0x1F04051C
+#define LPM_MEM_DC_DI0_CONF_2__EMPTY       0x1F04051C,0x00000000
+#define LPM_MEM_DC_DI0_CONF_2__FULL       0x1F04051C,0xffffffff
+#define LPM_MEM_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0       0x1F04051C,0xFFFFFFFF
+
+#define LPM_MEM_DC_DI1_CONF_1__ADDR                   0x1F040520
+#define LPM_MEM_DC_DI1_CONF_1__EMPTY       0x1F040520,0x00000000
+#define LPM_MEM_DC_DI1_CONF_1__FULL       0x1F040520,0xffffffff
+#define LPM_MEM_DC_DI1_CONF_1__DI_READ_DATA_MASK_1       0x1F040520,0xFFFFFFFF
+
+#define LPM_MEM_DC_DI1_CONF_2__ADDR                   0x1F040524
+#define LPM_MEM_DC_DI1_CONF_2__EMPTY       0x1F040524,0x00000000
+#define LPM_MEM_DC_DI1_CONF_2__FULL       0x1F040524,0xffffffff
+#define LPM_MEM_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1       0x1F040524,0xFFFFFFFF
+
+#define LPM_MEM_DC_MAP_CONF_0__ADDR                   0x1F040528
+#define LPM_MEM_DC_MAP_CONF_0__EMPTY       0x1F040528,0x00000000
+#define LPM_MEM_DC_MAP_CONF_0__FULL       0x1F040528,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1       0x1F040528,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1       0x1F040528,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1       0x1F040528,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0       0x1F040528,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0       0x1F040528,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0       0x1F040528,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_1__ADDR                   0x1F04052C
+#define LPM_MEM_DC_MAP_CONF_1__EMPTY       0x1F04052C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_1__FULL       0x1F04052C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3       0x1F04052C,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3       0x1F04052C,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3       0x1F04052C,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2       0x1F04052C,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2       0x1F04052C,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2       0x1F04052C,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_2__ADDR                   0x1F040530
+#define LPM_MEM_DC_MAP_CONF_2__EMPTY       0x1F040530,0x00000000
+#define LPM_MEM_DC_MAP_CONF_2__FULL       0x1F040530,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5       0x1F040530,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5       0x1F040530,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5       0x1F040530,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4       0x1F040530,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4       0x1F040530,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4       0x1F040530,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_3__ADDR                   0x1F040534
+#define LPM_MEM_DC_MAP_CONF_3__EMPTY       0x1F040534,0x00000000
+#define LPM_MEM_DC_MAP_CONF_3__FULL       0x1F040534,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7       0x1F040534,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7       0x1F040534,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7       0x1F040534,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6       0x1F040534,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6       0x1F040534,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6       0x1F040534,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_4__ADDR                   0x1F040538
+#define LPM_MEM_DC_MAP_CONF_4__EMPTY       0x1F040538,0x00000000
+#define LPM_MEM_DC_MAP_CONF_4__FULL       0x1F040538,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9       0x1F040538,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9       0x1F040538,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9       0x1F040538,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8       0x1F040538,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8       0x1F040538,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8       0x1F040538,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_5__ADDR                   0x1F04053C
+#define LPM_MEM_DC_MAP_CONF_5__EMPTY       0x1F04053C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_5__FULL       0x1F04053C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11       0x1F04053C,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11       0x1F04053C,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11       0x1F04053C,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10       0x1F04053C,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10       0x1F04053C,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10       0x1F04053C,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_6__ADDR                   0x1F040540
+#define LPM_MEM_DC_MAP_CONF_6__EMPTY       0x1F040540,0x00000000
+#define LPM_MEM_DC_MAP_CONF_6__FULL       0x1F040540,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13       0x1F040540,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13       0x1F040540,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13       0x1F040540,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12       0x1F040540,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12       0x1F040540,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12       0x1F040540,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_7__ADDR                   0x1F040544
+#define LPM_MEM_DC_MAP_CONF_7__EMPTY       0x1F040544,0x00000000
+#define LPM_MEM_DC_MAP_CONF_7__FULL       0x1F040544,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15       0x1F040544,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15       0x1F040544,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15       0x1F040544,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14       0x1F040544,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14       0x1F040544,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14       0x1F040544,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_8__ADDR                   0x1F040548
+#define LPM_MEM_DC_MAP_CONF_8__EMPTY       0x1F040548,0x00000000
+#define LPM_MEM_DC_MAP_CONF_8__FULL       0x1F040548,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17       0x1F040548,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17       0x1F040548,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17       0x1F040548,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16       0x1F040548,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16       0x1F040548,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16       0x1F040548,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_9__ADDR                   0x1F04054C
+#define LPM_MEM_DC_MAP_CONF_9__EMPTY       0x1F04054C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_9__FULL       0x1F04054C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19       0x1F04054C,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19       0x1F04054C,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19       0x1F04054C,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18       0x1F04054C,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18       0x1F04054C,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18       0x1F04054C,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_10__ADDR                   0x1F040550
+#define LPM_MEM_DC_MAP_CONF_10__EMPTY       0x1F040550,0x00000000
+#define LPM_MEM_DC_MAP_CONF_10__FULL       0x1F040550,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21       0x1F040550,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21       0x1F040550,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21       0x1F040550,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20       0x1F040550,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20       0x1F040550,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20       0x1F040550,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_11__ADDR                   0x1F040554
+#define LPM_MEM_DC_MAP_CONF_11__EMPTY       0x1F040554,0x00000000
+#define LPM_MEM_DC_MAP_CONF_11__FULL       0x1F040554,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23       0x1F040554,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23       0x1F040554,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23       0x1F040554,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22       0x1F040554,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22       0x1F040554,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22       0x1F040554,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_12__ADDR                   0x1F040558
+#define LPM_MEM_DC_MAP_CONF_12__EMPTY       0x1F040558,0x00000000
+#define LPM_MEM_DC_MAP_CONF_12__FULL       0x1F040558,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25       0x1F040558,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25       0x1F040558,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25       0x1F040558,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24       0x1F040558,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24       0x1F040558,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24       0x1F040558,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_13__ADDR                   0x1F04055C
+#define LPM_MEM_DC_MAP_CONF_13__EMPTY       0x1F04055C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_13__FULL       0x1F04055C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27       0x1F04055C,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27       0x1F04055C,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27       0x1F04055C,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26       0x1F04055C,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26       0x1F04055C,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26       0x1F04055C,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_14__ADDR                   0x1F040560
+#define LPM_MEM_DC_MAP_CONF_14__EMPTY       0x1F040560,0x00000000
+#define LPM_MEM_DC_MAP_CONF_14__FULL       0x1F040560,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29       0x1F040560,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29       0x1F040560,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29       0x1F040560,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28       0x1F040560,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28       0x1F040560,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28       0x1F040560,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_15__ADDR                   0x1F040564
+#define LPM_MEM_DC_MAP_CONF_15__EMPTY       0x1F040564,0x00000000
+#define LPM_MEM_DC_MAP_CONF_15__FULL       0x1F040564,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_1       0x1F040564,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_1       0x1F040564,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_0       0x1F040564,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_0       0x1F040564,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_16__ADDR                   0x1F040568
+#define LPM_MEM_DC_MAP_CONF_16__EMPTY       0x1F040568,0x00000000
+#define LPM_MEM_DC_MAP_CONF_16__FULL       0x1F040568,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_3       0x1F040568,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_3       0x1F040568,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_2       0x1F040568,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_2       0x1F040568,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_17__ADDR                   0x1F04056C
+#define LPM_MEM_DC_MAP_CONF_17__EMPTY       0x1F04056C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_17__FULL       0x1F04056C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_5       0x1F04056C,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_5       0x1F04056C,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_4       0x1F04056C,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_4       0x1F04056C,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_18__ADDR                   0x1F040570
+#define LPM_MEM_DC_MAP_CONF_18__EMPTY       0x1F040570,0x00000000
+#define LPM_MEM_DC_MAP_CONF_18__FULL       0x1F040570,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_7       0x1F040570,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_7       0x1F040570,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_6       0x1F040570,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_6       0x1F040570,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_19__ADDR                   0x1F040574
+#define LPM_MEM_DC_MAP_CONF_19__EMPTY       0x1F040574,0x00000000
+#define LPM_MEM_DC_MAP_CONF_19__FULL       0x1F040574,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_9       0x1F040574,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_9       0x1F040574,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_8       0x1F040574,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_8       0x1F040574,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_20__ADDR                   0x1F040578
+#define LPM_MEM_DC_MAP_CONF_20__EMPTY       0x1F040578,0x00000000
+#define LPM_MEM_DC_MAP_CONF_20__FULL       0x1F040578,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_11       0x1F040578,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_11       0x1F040578,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_10       0x1F040578,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_10       0x1F040578,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_21__ADDR                   0x1F04057C
+#define LPM_MEM_DC_MAP_CONF_21__EMPTY       0x1F04057C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_21__FULL       0x1F04057C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_13       0x1F04057C,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_13       0x1F04057C,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_12       0x1F04057C,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_12       0x1F04057C,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_22__ADDR                   0x1F040580
+#define LPM_MEM_DC_MAP_CONF_22__EMPTY       0x1F040580,0x00000000
+#define LPM_MEM_DC_MAP_CONF_22__FULL       0x1F040580,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_15       0x1F040580,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_15       0x1F040580,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_14       0x1F040580,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_14       0x1F040580,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_23__ADDR                   0x1F040584
+#define LPM_MEM_DC_MAP_CONF_23__EMPTY       0x1F040584,0x00000000
+#define LPM_MEM_DC_MAP_CONF_23__FULL       0x1F040584,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_17       0x1F040584,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_17       0x1F040584,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_16       0x1F040584,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_16       0x1F040584,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_24__ADDR                   0x1F040588
+#define LPM_MEM_DC_MAP_CONF_24__EMPTY       0x1F040588,0x00000000
+#define LPM_MEM_DC_MAP_CONF_24__FULL       0x1F040588,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_19       0x1F040588,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_19       0x1F040588,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_18       0x1F040588,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_18       0x1F040588,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_25__ADDR                   0x1F04058C
+#define LPM_MEM_DC_MAP_CONF_25__EMPTY       0x1F04058C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_25__FULL       0x1F04058C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_21       0x1F04058C,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_21       0x1F04058C,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_20       0x1F04058C,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_20       0x1F04058C,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_26__ADDR                   0x1F040590
+#define LPM_MEM_DC_MAP_CONF_26__EMPTY       0x1F040590,0x00000000
+#define LPM_MEM_DC_MAP_CONF_26__FULL       0x1F040590,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_23       0x1F040590,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_23       0x1F040590,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_22       0x1F040590,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_22       0x1F040590,0x000000FF
+
+#define LPM_MEM_DC_UGDE0_0__ADDR                   0x1F040594
+#define LPM_MEM_DC_UGDE0_0__EMPTY       0x1F040594,0x00000000
+#define LPM_MEM_DC_UGDE0_0__FULL       0x1F040594,0xffffffff
+#define LPM_MEM_DC_UGDE0_0__NF_NL_0       0x1F040594,0x18000000
+#define LPM_MEM_DC_UGDE0_0__AUTORESTART_0       0x1F040594,0x04000000
+#define LPM_MEM_DC_UGDE0_0__ODD_EN_0       0x1F040594,0x02000000
+#define LPM_MEM_DC_UGDE0_0__COD_ODD_START_0       0x1F040594,0x00FF0000
+#define LPM_MEM_DC_UGDE0_0__COD_EV_START_0       0x1F040594,0x0000FF00
+#define LPM_MEM_DC_UGDE0_0__COD_EV_PRIORITY_0       0x1F040594,0x00000078
+#define LPM_MEM_DC_UGDE0_0__ID_CODED_0       0x1F040594,0x00000007
+
+#define LPM_MEM_DC_UGDE0_1__ADDR                   0x1F040598
+#define LPM_MEM_DC_UGDE0_1__EMPTY       0x1F040598,0x00000000
+#define LPM_MEM_DC_UGDE0_1__FULL       0x1F040598,0xffffffff
+#define LPM_MEM_DC_UGDE0_1__STEP_0       0x1F040598,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE0_2__ADDR                   0x1F04059C
+#define LPM_MEM_DC_UGDE0_2__EMPTY       0x1F04059C,0x00000000
+#define LPM_MEM_DC_UGDE0_2__FULL       0x1F04059C,0xffffffff
+#define LPM_MEM_DC_UGDE0_2__OFFSET_DT_0       0x1F04059C,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE0_3__ADDR                   0x1F0405A0
+#define LPM_MEM_DC_UGDE0_3__EMPTY       0x1F0405A0,0x00000000
+#define LPM_MEM_DC_UGDE0_3__FULL       0x1F0405A0,0xffffffff
+#define LPM_MEM_DC_UGDE0_3__STEP_REPEAT_0       0x1F0405A0,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE1_0__ADDR                   0x1F0405A4
+#define LPM_MEM_DC_UGDE1_0__EMPTY       0x1F0405A4,0x00000000
+#define LPM_MEM_DC_UGDE1_0__FULL       0x1F0405A4,0xffffffff
+#define LPM_MEM_DC_UGDE1_0__NF_NL_1       0x1F0405A4,0x18000000
+#define LPM_MEM_DC_UGDE1_0__AUTORESTART_1       0x1F0405A4,0x04000000
+#define LPM_MEM_DC_UGDE1_0__ODD_EN_1       0x1F0405A4,0x02000000
+#define LPM_MEM_DC_UGDE1_0__COD_ODD_START_1       0x1F0405A4,0x00FF0000
+#define LPM_MEM_DC_UGDE1_0__COD_EV_START_1       0x1F0405A4,0x00007F80
+#define LPM_MEM_DC_UGDE1_0__COD_EV_PRIORITY_1       0x1F0405A4,0x00000078
+#define LPM_MEM_DC_UGDE1_0__ID_CODED_1       0x1F0405A4,0x00000007
+
+#define LPM_MEM_DC_UGDE1_1__ADDR                   0x1F0405A8
+#define LPM_MEM_DC_UGDE1_1__EMPTY       0x1F0405A8,0x00000000
+#define LPM_MEM_DC_UGDE1_1__FULL       0x1F0405A8,0xffffffff
+#define LPM_MEM_DC_UGDE1_1__STEP_1       0x1F0405A8,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE1_2__ADDR                   0x1F0405AC
+#define LPM_MEM_DC_UGDE1_2__EMPTY       0x1F0405AC,0x00000000
+#define LPM_MEM_DC_UGDE1_2__FULL       0x1F0405AC,0xffffffff
+#define LPM_MEM_DC_UGDE1_2__OFFSET_DT_1       0x1F0405AC,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE1_3__ADDR                   0x1F0405B0
+#define LPM_MEM_DC_UGDE1_3__EMPTY       0x1F0405B0,0x00000000
+#define LPM_MEM_DC_UGDE1_3__FULL       0x1F0405B0,0xffffffff
+#define LPM_MEM_DC_UGDE1_3__STEP_REPEAT_1       0x1F0405B0,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE2_0__ADDR                   0x1F0405B4
+#define LPM_MEM_DC_UGDE2_0__EMPTY       0x1F0405B4,0x00000000
+#define LPM_MEM_DC_UGDE2_0__FULL       0x1F0405B4,0xffffffff
+#define LPM_MEM_DC_UGDE2_0__NF_NL_2       0x1F0405B4,0x18000000
+#define LPM_MEM_DC_UGDE2_0__AUTORESTART_2       0x1F0405B4,0x04000000
+#define LPM_MEM_DC_UGDE2_0__ODD_EN_2       0x1F0405B4,0x02000000
+#define LPM_MEM_DC_UGDE2_0__COD_ODD_START_2       0x1F0405B4,0x00FF0000
+#define LPM_MEM_DC_UGDE2_0__COD_EV_START_2       0x1F0405B4,0x00007F80
+#define LPM_MEM_DC_UGDE2_0__COD_EV_PRIORITY_2       0x1F0405B4,0x00000078
+#define LPM_MEM_DC_UGDE2_0__ID_CODED_2       0x1F0405B4,0x00000007
+
+#define LPM_MEM_DC_UGDE2_1__ADDR                   0x1F0405B8
+#define LPM_MEM_DC_UGDE2_1__EMPTY       0x1F0405B8,0x00000000
+#define LPM_MEM_DC_UGDE2_1__FULL       0x1F0405B8,0xffffffff
+#define LPM_MEM_DC_UGDE2_1__STEP_2       0x1F0405B8,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE2_2__ADDR                   0x1F0405BC
+#define LPM_MEM_DC_UGDE2_2__EMPTY       0x1F0405BC,0x00000000
+#define LPM_MEM_DC_UGDE2_2__FULL       0x1F0405BC,0xffffffff
+#define LPM_MEM_DC_UGDE2_2__OFFSET_DT_2       0x1F0405BC,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE2_3__ADDR                   0x1F0405C0
+#define LPM_MEM_DC_UGDE2_3__EMPTY       0x1F0405C0,0x00000000
+#define LPM_MEM_DC_UGDE2_3__FULL       0x1F0405C0,0xffffffff
+#define LPM_MEM_DC_UGDE2_3__STEP_REPEAT_2       0x1F0405C0,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE3_0__ADDR                   0x1F0405C4
+#define LPM_MEM_DC_UGDE3_0__EMPTY       0x1F0405C4,0x00000000
+#define LPM_MEM_DC_UGDE3_0__FULL       0x1F0405C4,0xffffffff
+#define LPM_MEM_DC_UGDE3_0__NF_NL_3       0x1F0405C4,0x18000000
+#define LPM_MEM_DC_UGDE3_0__AUTORESTART_3       0x1F0405C4,0x04000000
+#define LPM_MEM_DC_UGDE3_0__ODD_EN_3       0x1F0405C4,0x02000000
+#define LPM_MEM_DC_UGDE3_0__COD_ODD_START_3       0x1F0405C4,0x00FF0000
+#define LPM_MEM_DC_UGDE3_0__COD_EV_START_3       0x1F0405C4,0x00007F80
+#define LPM_MEM_DC_UGDE3_0__COD_EV_PRIORITY_3       0x1F0405C4,0x00000078
+#define LPM_MEM_DC_UGDE3_0__ID_CODED_3       0x1F0405C4,0x00000007
+
+#define LPM_MEM_DC_UGDE3_1__ADDR                   0x1F0405C8
+#define LPM_MEM_DC_UGDE3_1__EMPTY       0x1F0405C8,0x00000000
+#define LPM_MEM_DC_UGDE3_1__FULL       0x1F0405C8,0xffffffff
+#define LPM_MEM_DC_UGDE3_1__STEP_3       0x1F0405C8,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE3_2__ADDR                   0x1F0405CC
+#define LPM_MEM_DC_UGDE3_2__EMPTY       0x1F0405CC,0x00000000
+#define LPM_MEM_DC_UGDE3_2__FULL       0x1F0405CC,0xffffffff
+#define LPM_MEM_DC_UGDE3_2__OFFSET_DT_3       0x1F0405CC,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE3_3__ADDR                   0x1F0405D0
+#define LPM_MEM_DC_UGDE3_3__EMPTY       0x1F0405D0,0x00000000
+#define LPM_MEM_DC_UGDE3_3__FULL       0x1F0405D0,0xffffffff
+#define LPM_MEM_DC_UGDE3_3__STEP_REPEAT_3       0x1F0405D0,0x1FFFFFFF
+
+#define LPM_MEM_DC_LLA0__ADDR                   0x1F0405D4
+#define LPM_MEM_DC_LLA0__EMPTY       0x1F0405D4,0x00000000
+#define LPM_MEM_DC_LLA0__FULL       0x1F0405D4,0xffffffff
+#define LPM_MEM_DC_LLA0__MCU_RS_3_0       0x1F0405D4,0xFF000000
+#define LPM_MEM_DC_LLA0__MCU_RS_2_0       0x1F0405D4,0x00FF0000
+#define LPM_MEM_DC_LLA0__MCU_RS_1_0       0x1F0405D4,0x0000FF00
+#define LPM_MEM_DC_LLA0__MCU_RS_0_0       0x1F0405D4,0x000000FF
+
+#define LPM_MEM_DC_LLA1__ADDR                   0x1F0405D8
+#define LPM_MEM_DC_LLA1__EMPTY       0x1F0405D8,0x00000000
+#define LPM_MEM_DC_LLA1__FULL       0x1F0405D8,0xffffffff
+#define LPM_MEM_DC_LLA1__MCU_RS_3_1       0x1F0405D8,0xFF000000
+#define LPM_MEM_DC_LLA1__MCU_RS_2_1       0x1F0405D8,0x00FF0000
+#define LPM_MEM_DC_LLA1__MCU_RS_1_1       0x1F0405D8,0x0000FF00
+#define LPM_MEM_DC_LLA1__MCU_RS_0_1       0x1F0405D8,0x000000FF
+
+#define LPM_MEM_DC_R_LLA0__ADDR                   0x1F0405DC
+#define LPM_MEM_DC_R_LLA0__EMPTY       0x1F0405DC,0x00000000
+#define LPM_MEM_DC_R_LLA0__FULL       0x1F0405DC,0xffffffff
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_3_0       0x1F0405DC,0xFF000000
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_2_0       0x1F0405DC,0x00FF0000
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_1_0       0x1F0405DC,0x0000FF00
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_0_0       0x1F0405DC,0x000000FF
+
+#define LPM_MEM_DC_R_LLA1__ADDR                   0x1F0405E0
+#define LPM_MEM_DC_R_LLA1__EMPTY       0x1F0405E0,0x00000000
+#define LPM_MEM_DC_R_LLA1__FULL       0x1F0405E0,0xffffffff
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_3_1       0x1F0405E0,0xFF000000
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_2_1       0x1F0405E0,0x00FF0000
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_1_1       0x1F0405E0,0x0000FF00
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_0_1       0x1F0405E0,0x000000FF
+
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ADDR                   0x1F0405E4
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__EMPTY       0x1F0405E4,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__FULL       0x1F0405E4,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT       0x1F0405E4,0x1FFFFFFF
+
+#define LPM_MEM_IDMAC_CONF__ADDR                   0x1F0405E8
+#define LPM_MEM_IDMAC_CONF__EMPTY       0x1F0405E8,0x00000000
+#define LPM_MEM_IDMAC_CONF__FULL       0x1F0405E8,0xffffffff
+#define LPM_MEM_IDMAC_CONF__P_ENDIAN       0x1F0405E8,0x00010000
+#define LPM_MEM_IDMAC_CONF__WIDPT       0x1F0405E8,0x00000018
+#define LPM_MEM_IDMAC_CONF__MAX_REQ_READ       0x1F0405E8,0x00000007
+
+#define LPM_MEM_IDMAC_CH_EN_1__ADDR                   0x1F0405EC
+#define LPM_MEM_IDMAC_CH_EN_1__EMPTY       0x1F0405EC,0x00000000
+#define LPM_MEM_IDMAC_CH_EN_1__FULL       0x1F0405EC,0xffffffff
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_31       0x1F0405EC,0x80000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_29       0x1F0405EC,0x20000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_28       0x1F0405EC,0x10000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_27       0x1F0405EC,0x08000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_24       0x1F0405EC,0x01000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_23       0x1F0405EC,0x00800000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_22       0x1F0405EC,0x00400000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_21       0x1F0405EC,0x00200000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_20       0x1F0405EC,0x00100000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_18       0x1F0405EC,0x00040000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_17       0x1F0405EC,0x00020000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_15       0x1F0405EC,0x00008000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_14       0x1F0405EC,0x00004000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_12       0x1F0405EC,0x00001000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_11       0x1F0405EC,0x00000800
+
+#define LPM_MEM_IDMAC_CH_EN_2__ADDR                   0x1F0405F0
+#define LPM_MEM_IDMAC_CH_EN_2__EMPTY       0x1F0405F0,0x00000000
+#define LPM_MEM_IDMAC_CH_EN_2__FULL       0x1F0405F0,0xffffffff
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_52       0x1F0405F0,0x00100000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_51       0x1F0405F0,0x00080000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_50       0x1F0405F0,0x00040000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_49       0x1F0405F0,0x00020000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_48       0x1F0405F0,0x00010000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_47       0x1F0405F0,0x00008000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_46       0x1F0405F0,0x00004000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_45       0x1F0405F0,0x00002000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_44       0x1F0405F0,0x00001000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_43       0x1F0405F0,0x00000800
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_42       0x1F0405F0,0x00000400
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_41       0x1F0405F0,0x00000200
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_40       0x1F0405F0,0x00000100
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_33       0x1F0405F0,0x00000002
+
+#define LPM_MEM_IDMAC_SEP_ALPHA__ADDR                   0x1F0405F4
+#define LPM_MEM_IDMAC_SEP_ALPHA__EMPTY       0x1F0405F4,0x00000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__FULL       0x1F0405F4,0xffffffff
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29       0x1F0405F4,0x20000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27       0x1F0405F4,0x08000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24       0x1F0405F4,0x01000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23       0x1F0405F4,0x00800000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15       0x1F0405F4,0x00008000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14       0x1F0405F4,0x00004000
+
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__ADDR                   0x1F0405F8
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__EMPTY       0x1F0405F8,0x00000000
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__FULL       0x1F0405F8,0xffffffff
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29       0x1F0405F8,0x20000000
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24       0x1F0405F8,0x01000000
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23       0x1F0405F8,0x00800000
+
+#define LPM_MEM_IDMAC_CH_PRI_1__ADDR                   0x1F0405FC
+#define LPM_MEM_IDMAC_CH_PRI_1__EMPTY       0x1F0405FC,0x00000000
+#define LPM_MEM_IDMAC_CH_PRI_1__FULL       0x1F0405FC,0xffffffff
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29       0x1F0405FC,0x20000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28       0x1F0405FC,0x10000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27       0x1F0405FC,0x08000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24       0x1F0405FC,0x01000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23       0x1F0405FC,0x00800000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22       0x1F0405FC,0x00400000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21       0x1F0405FC,0x00200000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20       0x1F0405FC,0x00100000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15       0x1F0405FC,0x00008000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14       0x1F0405FC,0x00004000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12       0x1F0405FC,0x00001000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11       0x1F0405FC,0x00000800
+
+#define LPM_MEM_IDMAC_CH_PRI_2__ADDR                   0x1F040600
+#define LPM_MEM_IDMAC_CH_PRI_2__EMPTY       0x1F040600,0x00000000
+#define LPM_MEM_IDMAC_CH_PRI_2__FULL       0x1F040600,0xffffffff
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50       0x1F040600,0x00040000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49       0x1F040600,0x00020000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48       0x1F040600,0x00010000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47       0x1F040600,0x00008000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46       0x1F040600,0x00004000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45       0x1F040600,0x00002000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44       0x1F040600,0x00001000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43       0x1F040600,0x00000800
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42       0x1F040600,0x00000400
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41       0x1F040600,0x00000200
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40       0x1F040600,0x00000100
+
+#define LPM_MEM_IDMAC_WM_EN_1__ADDR                   0x1F040604
+#define LPM_MEM_IDMAC_WM_EN_1__EMPTY       0x1F040604,0x00000000
+#define LPM_MEM_IDMAC_WM_EN_1__FULL       0x1F040604,0xffffffff
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_29       0x1F040604,0x20000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_28       0x1F040604,0x10000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_27       0x1F040604,0x08000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_24       0x1F040604,0x01000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_23       0x1F040604,0x00800000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_14       0x1F040604,0x00004000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_12       0x1F040604,0x00001000
+
+#define LPM_MEM_IDMAC_WM_EN_2__ADDR                   0x1F040608
+#define LPM_MEM_IDMAC_WM_EN_2__EMPTY       0x1F040608,0x00000000
+#define LPM_MEM_IDMAC_WM_EN_2__FULL       0x1F040608,0xffffffff
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_44       0x1F040608,0x00001000
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_43       0x1F040608,0x00000800
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_42       0x1F040608,0x00000400
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_41       0x1F040608,0x00000200
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_40       0x1F040608,0x00000100
+
+#define LPM_MEM_IDMAC_LOCK_EN_2__ADDR                   0x1F04060C
+#define LPM_MEM_IDMAC_LOCK_EN_2__EMPTY       0x1F04060C,0x00000000
+#define LPM_MEM_IDMAC_LOCK_EN_2__FULL       0x1F04060C,0xffffffff
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50       0x1F04060C,0x00040000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49       0x1F04060C,0x00020000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48       0x1F04060C,0x00010000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47       0x1F04060C,0x00008000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46       0x1F04060C,0x00004000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45       0x1F04060C,0x00002000
+
+#define LPM_MEM_IDMAC_SUB_ADDR_1__ADDR                   0x1F040614
+#define LPM_MEM_IDMAC_SUB_ADDR_1__EMPTY       0x1F040614,0x00000000
+#define LPM_MEM_IDMAC_SUB_ADDR_1__FULL       0x1F040614,0xffffffff
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33       0x1F040614,0x7F000000
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29       0x1F040614,0x007F0000
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24       0x1F040614,0x00007F00
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23       0x1F040614,0x0000007F
+
+#define LPM_MEM_IDMAC_SUB_ADDR_2__ADDR                   0x1F040618
+#define LPM_MEM_IDMAC_SUB_ADDR_2__EMPTY       0x1F040618,0x00000000
+#define LPM_MEM_IDMAC_SUB_ADDR_2__FULL       0x1F040618,0xffffffff
+#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52       0x1F040618,0x007F0000
+#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51       0x1F040618,0x00007F00
+#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41       0x1F040618,0x0000007F
+
+#define LPM_MEM_IDMAC_BNDM_EN_1__ADDR                   0x1F04061C
+#define LPM_MEM_IDMAC_BNDM_EN_1__EMPTY       0x1F04061C,0x00000000
+#define LPM_MEM_IDMAC_BNDM_EN_1__FULL       0x1F04061C,0xffffffff
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22       0x1F04061C,0x00400000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21       0x1F04061C,0x00200000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20       0x1F04061C,0x00100000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12       0x1F04061C,0x00001000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11       0x1F04061C,0x00000800
+
+#define LPM_MEM_IDMAC_BNDM_EN_2__ADDR                   0x1F040620
+#define LPM_MEM_IDMAC_BNDM_EN_2__EMPTY       0x1F040620,0x00000000
+#define LPM_MEM_IDMAC_BNDM_EN_2__FULL       0x1F040620,0xffffffff
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50       0x1F040620,0x00040000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49       0x1F040620,0x00020000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48       0x1F040620,0x00010000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47       0x1F040620,0x00008000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46       0x1F040620,0x00004000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45       0x1F040620,0x00002000
+
+#define LPM_MEM_IDMAC_SC_CORD__ADDR                   0x1F040624
+#define LPM_MEM_IDMAC_SC_CORD__EMPTY       0x1F040624,0x00000000
+#define LPM_MEM_IDMAC_SC_CORD__FULL       0x1F040624,0xffffffff
+#define LPM_MEM_IDMAC_SC_CORD__SX0       0x1F040624,0x0FFF0000
+#define LPM_MEM_IDMAC_SC_CORD__SY0       0x1F040624,0x000007FF
+
+#define LPM_MEM_IPU_CONF__ADDR                   0x1F040628
+#define LPM_MEM_IPU_CONF__EMPTY       0x1F040628,0x00000000
+#define LPM_MEM_IPU_CONF__FULL       0x1F040628,0xffffffff
+#define LPM_MEM_IPU_CONF__IC_DMFC_SYNC       0x1F040628,0x04000000
+#define LPM_MEM_IPU_CONF__IC_DMFC_SEL       0x1F040628,0x02000000
+#define LPM_MEM_IPU_CONF__IDMAC_DISABLE       0x1F040628,0x00400000
+#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_ON       0x1F040628,0x00200000
+#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_MODE       0x1F040628,0x001F0000
+#define LPM_MEM_IPU_CONF__DMFC_EN       0x1F040628,0x00000400
+#define LPM_MEM_IPU_CONF__DC_EN       0x1F040628,0x00000200
+#define LPM_MEM_IPU_CONF__DI1_EN       0x1F040628,0x00000080
+#define LPM_MEM_IPU_CONF__DI0_EN       0x1F040628,0x00000040
+#define LPM_MEM_IPU_CONF__DP_EN       0x1F040628,0x00000020
+#define LPM_MEM_IPU_CONF__IRT_EN       0x1F040628,0x00000008
+#define LPM_MEM_IPU_CONF__IC_EN       0x1F040628,0x00000004
+
+#define LPM_MEM_IPU_INT_CTRL_1__ADDR                   0x1F040664
+#define LPM_MEM_IPU_INT_CTRL_1__EMPTY       0x1F040664,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_1__FULL       0x1F040664,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_31       0x1F040664,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_29       0x1F040664,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_28       0x1F040664,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_27       0x1F040664,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_24       0x1F040664,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_23       0x1F040664,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_22       0x1F040664,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_21       0x1F040664,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_20       0x1F040664,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_18       0x1F040664,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_17       0x1F040664,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_15       0x1F040664,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_14       0x1F040664,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_12       0x1F040664,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_11       0x1F040664,0x00000800
+
+#define LPM_MEM_IPU_INT_CTRL_2__ADDR                   0x1F040668
+#define LPM_MEM_IPU_INT_CTRL_2__EMPTY       0x1F040668,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_2__FULL       0x1F040668,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_52       0x1F040668,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_51       0x1F040668,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_50       0x1F040668,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_49       0x1F040668,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_48       0x1F040668,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_47       0x1F040668,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_46       0x1F040668,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_45       0x1F040668,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_44       0x1F040668,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_43       0x1F040668,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_42       0x1F040668,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_41       0x1F040668,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_40       0x1F040668,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_33       0x1F040668,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_3__ADDR                   0x1F04066C
+#define LPM_MEM_IPU_INT_CTRL_3__EMPTY       0x1F04066C,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_3__FULL       0x1F04066C,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31       0x1F04066C,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29       0x1F04066C,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28       0x1F04066C,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27       0x1F04066C,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24       0x1F04066C,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23       0x1F04066C,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22       0x1F04066C,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21       0x1F04066C,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20       0x1F04066C,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18       0x1F04066C,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17       0x1F04066C,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15       0x1F04066C,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14       0x1F04066C,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12       0x1F04066C,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11       0x1F04066C,0x00000800
+
+#define LPM_MEM_IPU_INT_CTRL_4__ADDR                   0x1F040670
+#define LPM_MEM_IPU_INT_CTRL_4__EMPTY       0x1F040670,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_4__FULL       0x1F040670,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52       0x1F040670,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51       0x1F040670,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50       0x1F040670,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49       0x1F040670,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48       0x1F040670,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47       0x1F040670,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46       0x1F040670,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45       0x1F040670,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44       0x1F040670,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43       0x1F040670,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42       0x1F040670,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41       0x1F040670,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40       0x1F040670,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33       0x1F040670,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_5__ADDR                   0x1F040674
+#define LPM_MEM_IPU_INT_CTRL_5__EMPTY       0x1F040674,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_5__FULL       0x1F040674,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31       0x1F040674,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29       0x1F040674,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28       0x1F040674,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27       0x1F040674,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24       0x1F040674,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23       0x1F040674,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22       0x1F040674,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21       0x1F040674,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20       0x1F040674,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18       0x1F040674,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17       0x1F040674,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15       0x1F040674,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14       0x1F040674,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12       0x1F040674,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11       0x1F040674,0x00000800
+
+#define LPM_MEM_IPU_INT_CTRL_6__ADDR                   0x1F040678
+#define LPM_MEM_IPU_INT_CTRL_6__EMPTY       0x1F040678,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_6__FULL       0x1F040678,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52       0x1F040678,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51       0x1F040678,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50       0x1F040678,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49       0x1F040678,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48       0x1F040678,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47       0x1F040678,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46       0x1F040678,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45       0x1F040678,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44       0x1F040678,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43       0x1F040678,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42       0x1F040678,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41       0x1F040678,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40       0x1F040678,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33       0x1F040678,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_7__ADDR                   0x1F04067C
+#define LPM_MEM_IPU_INT_CTRL_7__EMPTY       0x1F04067C,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_7__FULL       0x1F04067C,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_31       0x1F04067C,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_29       0x1F04067C,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_28       0x1F04067C,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_27       0x1F04067C,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_24       0x1F04067C,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_23       0x1F04067C,0x00800000
+
+#define LPM_MEM_IPU_INT_CTRL_8__ADDR                   0x1F040680
+#define LPM_MEM_IPU_INT_CTRL_8__EMPTY       0x1F040680,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_8__FULL       0x1F040680,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_52       0x1F040680,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_51       0x1F040680,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_44       0x1F040680,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_43       0x1F040680,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_42       0x1F040680,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_41       0x1F040680,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_33       0x1F040680,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_10__ADDR                   0x1F040688
+#define LPM_MEM_IPU_INT_CTRL_10__EMPTY       0x1F040688,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_10__FULL       0x1F040688,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_10__AXIR_ERR_EN       0x1F040688,0x40000000
+#define LPM_MEM_IPU_INT_CTRL_10__AXIW_ERR_EN       0x1F040688,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN       0x1F040688,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN       0x1F040688,0x04000000
+#define LPM_MEM_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN       0x1F040688,0x02000000
+#define LPM_MEM_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN       0x1F040688,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN       0x1F040688,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN       0x1F040688,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN       0x1F040688,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN       0x1F040688,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN       0x1F040688,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN       0x1F040688,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN       0x1F040688,0x00010000
+
+#define LPM_MEM_IPU_INT_CTRL_11__ADDR                   0x1F04068C
+#define LPM_MEM_IPU_INT_CTRL_11__EMPTY       0x1F04068C,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_11__FULL       0x1F04068C,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22       0x1F04068C,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21       0x1F04068C,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20       0x1F04068C,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12       0x1F04068C,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11       0x1F04068C,0x00000800
+
+#define LPM_MEM_IPU_INT_CTRL_12__ADDR                   0x1F040690
+#define LPM_MEM_IPU_INT_CTRL_12__EMPTY       0x1F040690,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_12__FULL       0x1F040690,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50       0x1F040690,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49       0x1F040690,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48       0x1F040690,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47       0x1F040690,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46       0x1F040690,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45       0x1F040690,0x00002000
+
+#define LPM_MEM_IPU_INT_CTRL_13__ADDR                   0x1F040694
+#define LPM_MEM_IPU_INT_CTRL_13__EMPTY       0x1F040694,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_13__FULL       0x1F040694,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_31       0x1F040694,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_29       0x1F040694,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_28       0x1F040694,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_27       0x1F040694,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_24       0x1F040694,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_23       0x1F040694,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_22       0x1F040694,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_21       0x1F040694,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_20       0x1F040694,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_18       0x1F040694,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_17       0x1F040694,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_15       0x1F040694,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_14       0x1F040694,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_12       0x1F040694,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_11       0x1F040694,0x00000800
+
+#define LPM_MEM_IPU_INT_CTRL_14__ADDR                   0x1F040698
+#define LPM_MEM_IPU_INT_CTRL_14__EMPTY       0x1F040698,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_14__FULL       0x1F040698,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_52       0x1F040698,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_51       0x1F040698,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_50       0x1F040698,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_49       0x1F040698,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_48       0x1F040698,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_47       0x1F040698,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_46       0x1F040698,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_45       0x1F040698,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_44       0x1F040698,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_43       0x1F040698,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_42       0x1F040698,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_41       0x1F040698,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_40       0x1F040698,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_33       0x1F040698,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_15__ADDR                   0x1F04069C
+#define LPM_MEM_IPU_INT_CTRL_15__EMPTY       0x1F04069C,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_15__FULL       0x1F04069C,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN       0x1F04069C,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN       0x1F04069C,0x40000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN       0x1F04069C,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN       0x1F04069C,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN       0x1F04069C,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN       0x1F04069C,0x04000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN       0x1F04069C,0x02000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN       0x1F04069C,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN       0x1F04069C,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN       0x1F04069C,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN       0x1F04069C,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN       0x1F04069C,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN       0x1F04069C,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN       0x1F04069C,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN       0x1F04069C,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_DP_START_EN       0x1F04069C,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN       0x1F04069C,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN       0x1F04069C,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_6_EN       0x1F04069C,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_4_EN       0x1F04069C,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_3_EN       0x1F04069C,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_2_EN       0x1F04069C,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_1_EN       0x1F04069C,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_0_EN       0x1F04069C,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN       0x1F04069C,0x00000080
+#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_BRAKE_EN       0x1F04069C,0x00000040
+#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_END_EN       0x1F04069C,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_START_EN       0x1F04069C,0x00000010
+#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_END_EN       0x1F04069C,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_START_EN       0x1F04069C,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN       0x1F04069C,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN       0x1F04069C,0x00000001
+
+#define LPM_MEM_IPU_SDMA_EVENT_1__ADDR                   0x1F0406A0
+#define LPM_MEM_IPU_SDMA_EVENT_1__EMPTY       0x1F0406A0,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__FULL       0x1F0406A0,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31       0x1F0406A0,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29       0x1F0406A0,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28       0x1F0406A0,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27       0x1F0406A0,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24       0x1F0406A0,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23       0x1F0406A0,0x00800000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22       0x1F0406A0,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21       0x1F0406A0,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20       0x1F0406A0,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18       0x1F0406A0,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17       0x1F0406A0,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15       0x1F0406A0,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14       0x1F0406A0,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12       0x1F0406A0,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11       0x1F0406A0,0x00000800
+
+#define LPM_MEM_IPU_SDMA_EVENT_2__ADDR                   0x1F0406A4
+#define LPM_MEM_IPU_SDMA_EVENT_2__EMPTY       0x1F0406A4,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_2__FULL       0x1F0406A4,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52       0x1F0406A4,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51       0x1F0406A4,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50       0x1F0406A4,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49       0x1F0406A4,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48       0x1F0406A4,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47       0x1F0406A4,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46       0x1F0406A4,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45       0x1F0406A4,0x00002000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44       0x1F0406A4,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43       0x1F0406A4,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42       0x1F0406A4,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41       0x1F0406A4,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40       0x1F0406A4,0x00000100
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33       0x1F0406A4,0x00000002
+
+#define LPM_MEM_IPU_SDMA_EVENT_3__ADDR                   0x1F0406A8
+#define LPM_MEM_IPU_SDMA_EVENT_3__EMPTY       0x1F0406A8,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__FULL       0x1F0406A8,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31       0x1F0406A8,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29       0x1F0406A8,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28       0x1F0406A8,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27       0x1F0406A8,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24       0x1F0406A8,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23       0x1F0406A8,0x00800000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22       0x1F0406A8,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21       0x1F0406A8,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20       0x1F0406A8,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18       0x1F0406A8,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17       0x1F0406A8,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15       0x1F0406A8,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14       0x1F0406A8,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12       0x1F0406A8,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11       0x1F0406A8,0x00000800
+
+#define LPM_MEM_IPU_SDMA_EVENT_4__ADDR                   0x1F0406AC
+#define LPM_MEM_IPU_SDMA_EVENT_4__EMPTY       0x1F0406AC,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_4__FULL       0x1F0406AC,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52       0x1F0406AC,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51       0x1F0406AC,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50       0x1F0406AC,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49       0x1F0406AC,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48       0x1F0406AC,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47       0x1F0406AC,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46       0x1F0406AC,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45       0x1F0406AC,0x00002000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44       0x1F0406AC,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43       0x1F0406AC,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42       0x1F0406AC,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41       0x1F0406AC,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40       0x1F0406AC,0x00000100
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33       0x1F0406AC,0x00000002
+
+#define LPM_MEM_IPU_SDMA_EVENT_7__ADDR                   0x1F0406B0
+#define LPM_MEM_IPU_SDMA_EVENT_7__EMPTY       0x1F0406B0,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__FULL       0x1F0406B0,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31       0x1F0406B0,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29       0x1F0406B0,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28       0x1F0406B0,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27       0x1F0406B0,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24       0x1F0406B0,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23       0x1F0406B0,0x00800000
+
+#define LPM_MEM_IPU_SDMA_EVENT_8__ADDR                   0x1F0406B4
+#define LPM_MEM_IPU_SDMA_EVENT_8__EMPTY       0x1F0406B4,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_8__FULL       0x1F0406B4,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52       0x1F0406B4,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51       0x1F0406B4,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44       0x1F0406B4,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43       0x1F0406B4,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42       0x1F0406B4,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41       0x1F0406B4,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32       0x1F0406B4,0x00000002
+
+#define LPM_MEM_IPU_SDMA_EVENT_11__ADDR                   0x1F0406B8
+#define LPM_MEM_IPU_SDMA_EVENT_11__EMPTY       0x1F0406B8,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_11__FULL       0x1F0406B8,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22       0x1F0406B8,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21       0x1F0406B8,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20       0x1F0406B8,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12       0x1F0406B8,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11       0x1F0406B8,0x00000800
+
+#define LPM_MEM_IPU_SDMA_EVENT_12__ADDR                   0x1F0406BC
+#define LPM_MEM_IPU_SDMA_EVENT_12__EMPTY       0x1F0406BC,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_12__FULL       0x1F0406BC,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50       0x1F0406BC,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49       0x1F0406BC,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48       0x1F0406BC,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47       0x1F0406BC,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46       0x1F0406BC,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45       0x1F0406BC,0x00002000
+
+#define LPM_MEM_IPU_SDMA_EVENT_13__ADDR                   0x1F0406C0
+#define LPM_MEM_IPU_SDMA_EVENT_13__EMPTY       0x1F0406C0,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__FULL       0x1F0406C0,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31       0x1F0406C0,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29       0x1F0406C0,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28       0x1F0406C0,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27       0x1F0406C0,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24       0x1F0406C0,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23       0x1F0406C0,0x00800000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22       0x1F0406C0,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21       0x1F0406C0,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20       0x1F0406C0,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18       0x1F0406C0,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17       0x1F0406C0,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15       0x1F0406C0,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14       0x1F0406C0,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12       0x1F0406C0,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11       0x1F0406C0,0x00000800
+
+#define LPM_MEM_IPU_SDMA_EVENT_14__ADDR                   0x1F0406C4
+#define LPM_MEM_IPU_SDMA_EVENT_14__EMPTY       0x1F0406C4,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_14__FULL       0x1F0406C4,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52       0x1F0406C4,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51       0x1F0406C4,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50       0x1F0406C4,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49       0x1F0406C4,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48       0x1F0406C4,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47       0x1F0406C4,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46       0x1F0406C4,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45       0x1F0406C4,0x00002000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44       0x1F0406C4,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43       0x1F0406C4,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42       0x1F0406C4,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41       0x1F0406C4,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40       0x1F0406C4,0x00000100
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33       0x1F0406C4,0x00000002
+
+#define LPM_MEM_IPU_SRM_PRI2__ADDR                   0x1F0006CC
+#define LPM_MEM_IPU_SRM_PRI2__EMPTY       0x1F0006CC,0x00000000
+#define LPM_MEM_IPU_SRM_PRI2__FULL       0x1F0006CC,0xffffffff
+#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_MODE       0x1F0006CC,0x18000000
+#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_PRI       0x1F0006CC,0x07000000
+#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_MODE       0x1F0006CC,0x00180000
+#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_PRI       0x1F0006CC,0x00070000
+#define LPM_MEM_IPU_SRM_PRI2__DC_6_SRM_MODE       0x1F0006CC,0x0000C000
+#define LPM_MEM_IPU_SRM_PRI2__DC_2_SRM_MODE       0x1F0006CC,0x00003000
+#define LPM_MEM_IPU_SRM_PRI2__DC_SRM_PRI       0x1F0006CC,0x00000E00
+#define LPM_MEM_IPU_SRM_PRI2__DP_A1_SRM_MODE       0x1F0006CC,0x00000180
+#define LPM_MEM_IPU_SRM_PRI2__DP_A0_SRM_MODE       0x1F0006CC,0x00000060
+#define LPM_MEM_IPU_SRM_PRI2__DP_S_SRM_MODE       0x1F0006CC,0x00000018
+#define LPM_MEM_IPU_SRM_PRI2__DP_SRM_PRI       0x1F0006CC,0x00000007
+
+#define LPM_MEM_IPU_FS_PROC_FLOW1__ADDR                   0x1F0406D0
+#define LPM_MEM_IPU_FS_PROC_FLOW1__EMPTY       0x1F0406D0,0x00000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__FULL       0x1F0406D0,0xffffffff
+#define LPM_MEM_IPU_FS_PROC_FLOW1__VF_IN_VALID        0x1F0406D0,0x80000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__ENC_IN_VALID       0x1F0406D0,0x40000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PRP_SRC_SEL       0x1F0406D0,0x0F000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL       0x1F0406D0,0x000F0000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_SRC_SEL       0x1F0406D0,0x0000F000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL       0x1F0406D0,0x00000F00
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL       0x1F0406D0,0x0000000F
+
+#define LPM_MEM_IPU_FS_PROC_FLOW2__ADDR                   0x1F0406D4
+#define LPM_MEM_IPU_FS_PROC_FLOW2__EMPTY       0x1F0406D4,0x00000000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__FULL       0x1F0406D4,0xffffffff
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL       0x1F0406D4,0x00F00000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL       0x1F0406D4,0x000F0000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_DEST_SEL       0x1F0406D4,0x0000F000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL       0x1F0406D4,0x00000F00
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL       0x1F0406D4,0x000000F0
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL       0x1F0406D4,0x0000000F
+
+#define LPM_MEM_IPU_FS_DISP_FLOW1__ADDR                   0x1F0406DC
+#define LPM_MEM_IPU_FS_DISP_FLOW1__EMPTY       0x1F0406DC,0x00000000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__FULL       0x1F0406DC,0xffffffff
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DC1_SRC_SEL       0x1F0406DC,0x00F00000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DC2_SRC_SEL       0x1F0406DC,0x000F0000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL       0x1F0406DC,0x0000F000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL       0x1F0406DC,0x00000F00
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL       0x1F0406DC,0x000000F0
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL       0x1F0406DC,0x0000000F
+
+#define LPM_MEM_IPU_FS_DISP_FLOW2__ADDR                   0x1F0406E0
+#define LPM_MEM_IPU_FS_DISP_FLOW2__EMPTY       0x1F0406E0,0x00000000
+#define LPM_MEM_IPU_FS_DISP_FLOW2__FULL       0x1F0406E0,0xffffffff
+#define LPM_MEM_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL       0x1F0406E0,0x000F0000
+#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL       0x1F0406E0,0x000000F0
+#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL       0x1F0406E0,0x0000000F
+
+#define LPM_MEM_IPU_DISP_GEN__ADDR                   0x1F0406EC
+#define LPM_MEM_IPU_DISP_GEN__EMPTY       0x1F0406EC,0x00000000
+#define LPM_MEM_IPU_DISP_GEN__FULL       0x1F0406EC,0xffffffff
+#define LPM_MEM_IPU_DISP_GEN__DI1_COUNTER_RELEASE       0x1F0406EC,0x02000000
+#define LPM_MEM_IPU_DISP_GEN__DI0_COUNTER_RELEASE       0x1F0406EC,0x01000000
+#define LPM_MEM_IPU_DISP_GEN__MCU_MAX_BURST_STOP       0x1F0406EC,0x00400000
+#define LPM_MEM_IPU_DISP_GEN__MCU_T       0x1F0406EC,0x003C0000
+#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_9       0x1F0406EC,0x00020000
+#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_8       0x1F0406EC,0x00010000
+#define LPM_MEM_IPU_DISP_GEN__DP_PIPE_CLR       0x1F0406EC,0x00000040
+#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC1       0x1F0406EC,0x00000020
+#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC0       0x1F0406EC,0x00000010
+#define LPM_MEM_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW       0x1F0406EC,0x00000008
+#define LPM_MEM_IPU_DISP_GEN__DC2_DOUBLE_FLOW       0x1F0406EC,0x00000004
+#define LPM_MEM_IPU_DISP_GEN__DI1_DUAL_MODE       0x1F0406EC,0x00000002
+#define LPM_MEM_IPU_DISP_GEN__DI0_DUAL_MODE       0x1F0406EC,0x00000001
+
+#define LPM_MEM_IPU_DISP_ALT1__ADDR                   0x1F0406F0
+#define LPM_MEM_IPU_DISP_ALT1__EMPTY       0x1F0406F0,0x00000000
+#define LPM_MEM_IPU_DISP_ALT1__FULL       0x1F0406F0,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT1__SEL_ALT_0       0x1F0406F0,0xF0000000
+#define LPM_MEM_IPU_DISP_ALT1__STEP_REPEAT_ALT_0       0x1F0406F0,0x0FFF0000
+#define LPM_MEM_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0       0x1F0406F0,0x00008000
+#define LPM_MEM_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0       0x1F0406F0,0x00007000
+#define LPM_MEM_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0       0x1F0406F0,0x00000FFF
+
+#define LPM_MEM_IPU_DISP_ALT2__ADDR                   0x1F0406F4
+#define LPM_MEM_IPU_DISP_ALT2__EMPTY       0x1F0406F4,0x00000000
+#define LPM_MEM_IPU_DISP_ALT2__FULL       0x1F0406F4,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0       0x1F0406F4,0x00070000
+#define LPM_MEM_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0       0x1F0406F4,0x00007000
+#define LPM_MEM_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0       0x1F0406F4,0x00000FFF
+
+#define LPM_MEM_IPU_DISP_ALT3__ADDR                   0x1F0406F8
+#define LPM_MEM_IPU_DISP_ALT3__EMPTY       0x1F0406F8,0x00000000
+#define LPM_MEM_IPU_DISP_ALT3__FULL       0x1F0406F8,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT3__SEL_ALT_1       0x1F0406F8,0xF0000000
+#define LPM_MEM_IPU_DISP_ALT3__STEP_REPEAT_ALT_1       0x1F0406F8,0x0FFF0000
+#define LPM_MEM_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1       0x1F0406F8,0x00008000
+#define LPM_MEM_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1       0x1F0406F8,0x00007000
+#define LPM_MEM_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1       0x1F0406F8,0x00000FFF
+
+#define LPM_MEM_IPU_DISP_ALT4__ADDR                   0x1F0406FC
+#define LPM_MEM_IPU_DISP_ALT4__EMPTY       0x1F0406FC,0x00000000
+#define LPM_MEM_IPU_DISP_ALT4__FULL       0x1F0406FC,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1       0x1F0406FC,0x00070000
+#define LPM_MEM_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1       0x1F0406FC,0x00007000
+#define LPM_MEM_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1       0x1F0406FC,0x00000FFF
+
+#define LPM_MEM_IPU_SNOOP__ADDR                   0x1F040700
+#define LPM_MEM_IPU_SNOOP__EMPTY       0x1F040700,0x00000000
+#define LPM_MEM_IPU_SNOOP__FULL       0x1F040700,0xffffffff
+#define LPM_MEM_IPU_SNOOP__SNOOP2_SYNC_BYP       0x1F040700,0x00010000
+#define LPM_MEM_IPU_SNOOP__AUTOREF_PER       0x1F040700,0x000003FF
+
+#define LPM_MEM_IPU_MEM_RST__ADDR                   0x1F040704
+#define LPM_MEM_IPU_MEM_RST__EMPTY       0x1F040704,0x00000000
+#define LPM_MEM_IPU_MEM_RST__FULL       0x1F040704,0xffffffff
+#define LPM_MEM_IPU_MEM_RST__RST_MEM_START       0x1F040704,0x80000000
+#define LPM_MEM_IPU_MEM_RST__RST_MEM_EN       0x1F040704,0x007FFFFF
+
+#define LPM_MEM_IPU_PM__ADDR                   0x1F040708
+#define LPM_MEM_IPU_PM__EMPTY       0x1F040708,0x00000000
+#define LPM_MEM_IPU_PM__FULL       0x1F040708,0xffffffff
+#define LPM_MEM_IPU_PM__LPSR_MODE       0x1F040708,0x80000000
+#define LPM_MEM_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE       0x1F040708,0x40000000
+#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_1       0x1F040708,0x3F800000
+#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_0       0x1F040708,0x007F0000
+#define LPM_MEM_IPU_PM__CLOCK_MODE_STAT       0x1F040708,0x00008000
+#define LPM_MEM_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE       0x1F040708,0x00004000
+#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_1       0x1F040708,0x00003F80
+#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_0       0x1F040708,0x0000007F
+
+#define LPM_MEM_IPU_GPR__ADDR                   0x1F04070C
+#define LPM_MEM_IPU_GPR__EMPTY       0x1F04070C,0x00000000
+#define LPM_MEM_IPU_GPR__FULL       0x1F04070C,0xffffffff
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY1_CLR       0x1F04070C,0x80000000
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY0_CLR       0x1F04070C,0x40000000
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY1_CLR       0x1F04070C,0x20000000
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY0_CLR       0x1F04070C,0x10000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR       0x1F04070C,0x08000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR       0x1F04070C,0x04000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR       0x1F04070C,0x02000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR       0x1F04070C,0x01000000
+#define LPM_MEM_IPU_GPR__IPU_DI1_CLK_CHANGE_ACK_DIS 0x1F04070C,0x00800000
+#define LPM_MEM_IPU_GPR__IPU_DI0_CLK_CHANGE_ACK_DIS 0x1F04070C,0x00400000
+#define LPM_MEM_IPU_GPR__IPU_GP21       0x1F04070C,0x00200000
+#define LPM_MEM_IPU_GPR__IPU_GP20       0x1F04070C,0x00100000
+#define LPM_MEM_IPU_GPR__IPU_GP19       0x1F04070C,0x00080000
+#define LPM_MEM_IPU_GPR__IPU_GP18       0x1F04070C,0x00040000
+#define LPM_MEM_IPU_GPR__IPU_GP17       0x1F04070C,0x00020000
+#define LPM_MEM_IPU_GPR__IPU_GP16       0x1F04070C,0x00010000
+#define LPM_MEM_IPU_GPR__IPU_GP15       0x1F04070C,0x00008000
+#define LPM_MEM_IPU_GPR__IPU_GP14       0x1F04070C,0x00004000
+#define LPM_MEM_IPU_GPR__IPU_GP13       0x1F04070C,0x00002000
+#define LPM_MEM_IPU_GPR__IPU_GP12       0x1F04070C,0x00001000
+#define LPM_MEM_IPU_GPR__IPU_GP11       0x1F04070C,0x00000800
+#define LPM_MEM_IPU_GPR__IPU_GP10       0x1F04070C,0x00000400
+#define LPM_MEM_IPU_GPR__IPU_GP9       0x1F04070C,0x00000200
+#define LPM_MEM_IPU_GPR__IPU_GP8       0x1F04070C,0x00000100
+#define LPM_MEM_IPU_GPR__IPU_GP7       0x1F04070C,0x00000080
+#define LPM_MEM_IPU_GPR__IPU_GP6       0x1F04070C,0x00000040
+#define LPM_MEM_IPU_GPR__IPU_GP5       0x1F04070C,0x00000020
+#define LPM_MEM_IPU_GPR__IPU_GP4       0x1F04070C,0x00000010
+#define LPM_MEM_IPU_GPR__IPU_GP3       0x1F04070C,0x00000008
+#define LPM_MEM_IPU_GPR__IPU_GP2       0x1F04070C,0x00000004
+#define LPM_MEM_IPU_GPR__IPU_GP1       0x1F04070C,0x00000002
+#define LPM_MEM_IPU_GPR__IPU_GP0       0x1F04070C,0x00000001
+
+#define LPM_MEM_IC_CONF__ADDR                   0x1F040710
+#define LPM_MEM_IC_CONF__EMPTY                  0x1F040710,0x00000000
+#define LPM_MEM_IC_CONF__FULL                   0x1F040710,0xffffffff
+#define LPM_MEM_IC_CONF__CSI_MEM_WR_EN   0x1F040710,0x80000000
+#define LPM_MEM_IC_CONF__RWS_EN          0x1F040710,0x40000000
+#define LPM_MEM_IC_CONF__IC_KEY_COLOR_EN               0x1F040710,0x20000000
+#define LPM_MEM_IC_CONF__IC_GLB_LOC_A          0x1F040710,0x10000000
+#define LPM_MEM_IC_CONF__PP_ROT_EN             0x1F040710,0x00100000
+#define LPM_MEM_IC_CONF__PP_CMB                0x1F040710,0x00080000
+#define LPM_MEM_IC_CONF__PP_CSC2                       0x1F040710,0x00040000
+#define LPM_MEM_IC_CONF__PP_CSC1                       0x1F040710,0x00020000
+#define LPM_MEM_IC_CONF__PP_EN                 0x1F040710,0x00010000
+#define LPM_MEM_IC_CONF__PRPVF_ROT_EN          0x1F040710,0x00001000
+#define LPM_MEM_IC_CONF__PRPVF_CMB             0x1F040710,0x00000800
+#define LPM_MEM_IC_CONF__PRPVF_CSC2            0x1F040710,0x00000400
+#define LPM_MEM_IC_CONF__PRPVF_CSC1            0x1F040710,0x00000200
+#define LPM_MEM_IC_CONF__PRPVF_EN              0x1F040710,0x00000100
+#define LPM_MEM_IC_CONF__PRPENC_ROT_EN         0x1F040710,0x00000004
+#define LPM_MEM_IC_CONF__PRPENC_CSC1           0x1F040710,0x00000002
+#define LPM_MEM_IC_CONF__PRPENC_EN             0x1F040710,0x00000001
+
+#define LPM_MEM_IC_PRP_ENC_RSC__ADDR            0x1F040714
+#define LPM_MEM_IC_PRP_ENC_RSC__EMPTY          0x1F040714,0x00000000
+#define LPM_MEM_IC_PRP_ENC_RSC__FULL           0x1F040714,0xffffffff
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_V   0x1F040714,0xC0000000
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_V   0x1F040714,0x3FFF0000
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_H   0x1F040714,0x0000C000
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_H   0x1F040714,0x00003FFF
+
+#define LPM_MEM_IC_PRP_VF_RSC__ADDR             0x1F040718
+#define LPM_MEM_IC_PRP_VF_RSC__EMPTY           0x1F040718,0x00000000
+#define LPM_MEM_IC_PRP_VF_RSC__FULL            0x1F040718,0xffffffff
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_V     0x1F040718,0xC0000000
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_V     0x1F040718,0x3FFF0000
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_H     0x1F040718,0x0000C000
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_H     0x1F040718,0x00003FFF
+
+#define LPM_MEM_IC_PP_RSC__ADDR                 0x1F04071C
+#define LPM_MEM_IC_PP_RSC__EMPTY                       0x1F04071C,0x00000000
+#define LPM_MEM_IC_PP_RSC__FULL                0x1F04071C,0xffffffff
+#define LPM_MEM_IC_PP_RSC__PP_DS_R_V           0x1F04071C,0xC0000000
+#define LPM_MEM_IC_PP_RSC__PP_RS_R_V           0x1F04071C,0x3FFF0000
+#define LPM_MEM_IC_PP_RSC__PP_DS_R_H           0x1F04071C,0x0000C000
+#define LPM_MEM_IC_PP_RSC__PP_RS_R_H           0x1F04071C,0x00003FFF
+
+#define LPM_MEM_IC_CMBP_1__ADDR                 0x1F040720
+#define LPM_MEM_IC_CMBP_1__EMPTY                       0x1F040720,0x00000000
+#define LPM_MEM_IC_CMBP_1__FULL                0x1F040720,0xffffffff
+#define LPM_MEM_IC_CMBP_1__IC_PP_ALPHA_V               0x1F040720,0x0000FF00
+#define LPM_MEM_IC_CMBP_1__IC_PRPVF_ALPHA_V     0x1F040720,0x000000FF
+
+#define LPM_MEM_IC_CMBP_2__ADDR                 0x1F040724
+#define LPM_MEM_IC_CMBP_2__EMPTY                       0x1F040724,0x00000000
+#define LPM_MEM_IC_CMBP_2__FULL                0x1F040724,0xffffffff
+#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_R       0x1F040724,0x00FF0000
+#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_G       0x1F040724,0x0000FF00
+#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_B       0x1F040724,0x000000FF
+
+#define LPM_MEM_IC_IDMAC_1__ADDR                0x1F040728
+#define LPM_MEM_IC_IDMAC_1__EMPTY              0x1F040728,0x00000000
+#define LPM_MEM_IC_IDMAC_1__FULL                       0x1F040728,0xffffffff
+#define LPM_MEM_IC_IDMAC_1__ALT_CB7_BURST_16    0x1F040728,0x02000000
+#define LPM_MEM_IC_IDMAC_1__ALT_CB6_BURST_16    0x1F040728,0x01000000
+#define LPM_MEM_IC_IDMAC_1__T3_FLIP_UD          0x1F040728,0x00080000
+#define LPM_MEM_IC_IDMAC_1__T3_FLIP_LR          0x1F040728,0x00040000
+#define LPM_MEM_IC_IDMAC_1__T3_ROT             0x1F040728,0x00020000
+#define LPM_MEM_IC_IDMAC_1__T2_FLIP_UD         0x1F040728,0x00010000
+#define LPM_MEM_IC_IDMAC_1__T2_FLIP_LR         0x1F040728,0x00008000
+#define LPM_MEM_IC_IDMAC_1__T2_ROT             0x1F040728,0x00004000
+#define LPM_MEM_IC_IDMAC_1__T1_FLIP_UD         0x1F040728,0x00002000
+#define LPM_MEM_IC_IDMAC_1__T1_FLIP_LR         0x1F040728,0x00001000
+#define LPM_MEM_IC_IDMAC_1__T1_ROT             0x1F040728,0x00000800
+#define LPM_MEM_IC_IDMAC_1__CB7_BURST_16               0x1F040728,0x00000080
+#define LPM_MEM_IC_IDMAC_1__CB6_BURST_16               0x1F040728,0x00000040
+#define LPM_MEM_IC_IDMAC_1__CB5_BURST_16               0x1F040728,0x00000020
+#define LPM_MEM_IC_IDMAC_1__CB4_BURST_16               0x1F040728,0x00000010
+#define LPM_MEM_IC_IDMAC_1__CB3_BURST_16               0x1F040728,0x00000008
+#define LPM_MEM_IC_IDMAC_1__CB2_BURST_16               0x1F040728,0x00000004
+#define LPM_MEM_IC_IDMAC_1__CB1_BURST_16               0x1F040728,0x00000002
+#define LPM_MEM_IC_IDMAC_1__CB0_BURST_16               0x1F040728,0x00000001
+
+#define LPM_MEM_IC_IDMAC_2__ADDR                0x1F04072C
+#define LPM_MEM_IC_IDMAC_2__EMPTY               0x1F04072C,0x00000000
+#define LPM_MEM_IC_IDMAC_2__FULL                0x1F04072C,0xffffffff
+#define LPM_MEM_IC_IDMAC_2__T3_FR_HEIGHT        0x1F04072C,0x3FF00000
+#define LPM_MEM_IC_IDMAC_2__T2_FR_HEIGHT        0x1F04072C,0x000FFC00
+#define LPM_MEM_IC_IDMAC_2__T1_FR_HEIGHT        0x1F04072C,0x000003FF
+
+#define LPM_MEM_IC_IDMAC_3__ADDR                0x1F040730
+#define LPM_MEM_IC_IDMAC_3__EMPTY               0x1F040730,0x00000000
+#define LPM_MEM_IC_IDMAC_3__FULL                       0x1F040730,0xffffffff
+#define LPM_MEM_IC_IDMAC_3__T3_FR_WIDTH        0x1F040730,0x3FF00000
+#define LPM_MEM_IC_IDMAC_3__T2_FR_WIDTH        0x1F040730,0x000FFC00
+#define LPM_MEM_IC_IDMAC_3__T1_FR_WIDTH        0x1F040730,0x000003FF
+
+#define LPM_MEM_IC_IDMAC_4__ADDR                  0x1F040734
+#define LPM_MEM_IC_IDMAC_4__EMPTY                0x1F040734,0x00000000
+#define LPM_MEM_IC_IDMAC_4__FULL                         0x1F040734,0xffffffff
+#define LPM_MEM_IC_IDMAC_4__RM_BRDG_MAX_RQ        0x1F040734,0x0000F000
+#define LPM_MEM_IC_IDMAC_4__IBM_BRDG_MAX_RQ       0x1F040734,0x00000F00
+#define LPM_MEM_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ  0x1F040734,0x000000F0
+#define LPM_MEM_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ    0x1F040734,0x0000000F
+
+#endif
diff --git a/packages/devs/ipu/arm/imx/v1_0/include/ipuv3ex_reg_def.h b/packages/devs/ipu/arm/imx/v1_0/include/ipuv3ex_reg_def.h
new file mode 100644 (file)
index 0000000..3734077
--- /dev/null
@@ -0,0 +1,14005 @@
+//==========================================================================
+//
+//      IPUV3ex_REG_DEF.h
+//
+//      regs definitions of IPUv3ex
+//
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       Ray Sun <Yanfei.Sun@freescale.com>
+// Create Date: 2008-07-31
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#ifndef _IPUV3E_REGS_DEF_H_
+#define _IPUV3E_REGS_DEF_H_
+
+// ================= Start of IPUV3EX Common Registers =====================
+
+#define IPU_IPU_CONF__ADDR            0x1E000000
+#define IPU_IPU_CONF__EMPTY           0x1E000000,0x00000000
+#define IPU_IPU_CONF__FULL            0x1E000000,0xffffffff
+#define IPU_IPU_CONF__CSI_SEL         0x1E000000,0x80000000
+#define IPU_IPU_CONF__IC_INPUT        0x1E000000,0x40000000
+#define IPU_IPU_CONF__CSI1_DATA_SOURCE 0x1E000000,0x20000000
+#define IPU_IPU_CONF__CSI0_DATA_SOURCE 0x1E000000,0x10000000
+#define IPU_IPU_CONF__IC_DMFC_SYNC     0x1E000000,0x04000000
+#define IPU_IPU_CONF__IC_DMFC_SEL      0x1E000000,0x02000000
+#define IPU_IPU_CONF__ISP_DOUBLE_FLOW  0x1E000000,0x01000000
+#define IPU_IPU_CONF__IDMAC_DISABLE    0x1E000000,0x00400000
+#define IPU_IPU_CONF__IPU_DIAGBUS_ON   0x1E000000,0x00200000
+#define IPU_IPU_CONF__IPU_DIAGBUS_MODE 0x1E000000,0x001F0000
+#define IPU_IPU_CONF__IPU_HSP_CLK_EN   0x1E000000,0x00008000
+#define IPU_IPU_CONF__SISG_EN         0x1E000000,0x00000800
+#define IPU_IPU_CONF__DMFC_EN         0x1E000000,0x00000400
+#define IPU_IPU_CONF__DC_EN           0x1E000000,0x00000200
+#define IPU_IPU_CONF__SMFC_EN         0x1E000000,0x00000100
+#define IPU_IPU_CONF__DI1_EN          0x1E000000,0x00000080
+#define IPU_IPU_CONF__DI0_EN          0x1E000000,0x00000040
+#define IPU_IPU_CONF__DP_EN           0x1E000000,0x00000020
+#define IPU_IPU_CONF__ISP_EN          0x1E000000,0x00000010
+#define IPU_IPU_CONF__IRT_EN          0x1E000000,0x00000008
+#define IPU_IPU_CONF__IC_EN           0x1E000000,0x00000004
+#define IPU_IPU_CONF__CSI1_EN         0x1E000000,0x00000002
+#define IPU_IPU_CONF__CSI0_EN         0x1E000000,0x00000001
+
+#define IPU_SISG_CTRL0__ADDR                 0x1E000004
+#define IPU_SISG_CTRL0__EMPTY                0x1E000004,0x00000000
+#define IPU_SISG_CTRL0__FULL                 0x1E000004,0xffffffff
+#define IPU_SISG_CTRL0__EXT_ACTV             0x1E000004,0x40000000
+#define IPU_SISG_CTRL0__MCU_ACTV_TRIG        0x1E000004,0x20000000
+#define IPU_SISG_CTRL0__VAL_STOP_SISG_COUNTER 0x1E000004,0x1FFFFFF0
+#define IPU_SISG_CTRL0__NO_OF_VSYNC          0x1E000004,0x0000000E
+#define IPU_SISG_CTRL0__VSYNC_RESET_COUNTER   0x1E000004,0x00000001
+
+#define IPU_SISG_CTRL1__ADDR           0x1E000008
+#define IPU_SISG_CTRL1__EMPTY          0x1E000008,0x00000000
+#define IPU_SISG_CTRL1__FULL           0x1E000008,0xffffffff
+#define IPU_SISG_CTRL1__SISG_OUT_POL   0x1E000008,0x00003F00
+#define IPU_SISG_CTRL1__SISG_STROBE_CNT 0x1E000008,0x0000001F
+
+#define IPU_SISG_SET_1__ADDR       0x1E00000C
+#define IPU_SISG_SET_1__EMPTY      0x1E00000C,0x00000000
+#define IPU_SISG_SET_1__FULL       0x1E00000C,0xffffffff
+#define IPU_SISG_SET_1__SISG_SET_1 0x1E00000C,0x01FFFFFF
+
+#define IPU_SISG_SET_2__ADDR       0x1E000010
+#define IPU_SISG_SET_2__EMPTY      0x1E000010,0x00000000
+#define IPU_SISG_SET_2__FULL       0x1E000010,0xffffffff
+#define IPU_SISG_SET_2__SISG_SET_2 0x1E000010,0x01FFFFFF
+
+#define IPU_SISG_SET_3__ADDR       0x1E000014
+#define IPU_SISG_SET_3__EMPTY      0x1E000014,0x00000000
+#define IPU_SISG_SET_3__FULL       0x1E000014,0xffffffff
+#define IPU_SISG_SET_3__SISG_SET_3 0x1E000014,0x01FFFFFF
+
+#define IPU_SISG_SET_4__ADDR       0x1E000018
+#define IPU_SISG_SET_4__EMPTY      0x1E000018,0x00000000
+#define IPU_SISG_SET_4__FULL       0x1E000018,0xffffffff
+#define IPU_SISG_SET_4__SISG_SET_4 0x1E000018,0x01FFFFFF
+
+#define IPU_SISG_SET_5__ADDR       0x1E00001C
+#define IPU_SISG_SET_5__EMPTY      0x1E00001C,0x00000000
+#define IPU_SISG_SET_5__FULL       0x1E00001C,0xffffffff
+#define IPU_SISG_SET_5__SISG_SET_5 0x1E00001C,0x01FFFFFF
+
+#define IPU_SISG_SET_6__ADDR       0x1E000020
+#define IPU_SISG_SET_6__EMPTY      0x1E000020,0x00000000
+#define IPU_SISG_SET_6__FULL       0x1E000020,0xffffffff
+#define IPU_SISG_SET_6__SISG_SET_6 0x1E000020,0x01FFFFFF
+
+#define IPU_SISG_CLR_1__ADDR        0x1E000024
+#define IPU_SISG_CLR_1__EMPTY       0x1E000024,0x00000000
+#define IPU_SISG_CLR_1__FULL        0x1E000024,0xffffffff
+#define IPU_SISG_CLR_1__SISG_CLEAR_1 0x1E000024,0x01FFFFFF
+
+#define IPU_SISG_CLR_2__ADDR        0x1E000028
+#define IPU_SISG_CLR_2__EMPTY       0x1E000028,0x00000000
+#define IPU_SISG_CLR_2__FULL        0x1E000028,0xffffffff
+#define IPU_SISG_CLR_2__SISG_CLEAR_2 0x1E000028,0x01FFFFFF
+
+#define IPU_SISG_CLR_3__ADDR        0x1E00002C
+#define IPU_SISG_CLR_3__EMPTY       0x1E00002C,0x00000000
+#define IPU_SISG_CLR_3__FULL        0x1E00002C,0xffffffff
+#define IPU_SISG_CLR_3__SISG_CLEAR_3 0x1E00002C,0x01FFFFFF
+
+#define IPU_SISG_CLR_4__ADDR        0x1E000030
+#define IPU_SISG_CLR_4__EMPTY       0x1E000030,0x00000000
+#define IPU_SISG_CLR_4__FULL        0x1E000030,0xffffffff
+#define IPU_SISG_CLR_4__SISG_CLEAR_4 0x1E000030,0x01FFFFFF
+
+#define IPU_SISG_CLR_5__ADDR        0x1E000034
+#define IPU_SISG_CLR_5__EMPTY       0x1E000034,0x00000000
+#define IPU_SISG_CLR_5__FULL        0x1E000034,0xffffffff
+#define IPU_SISG_CLR_5__SISG_CLEAR_5 0x1E000034,0x01FFFFFF
+
+#define IPU_SISG_CLR_6__ADDR        0x1E000038
+#define IPU_SISG_CLR_6__EMPTY       0x1E000038,0x00000000
+#define IPU_SISG_CLR_6__FULL        0x1E000038,0xffffffff
+#define IPU_SISG_CLR_6__SISG_CLEAR_6 0x1E000038,0x01FFFFFF
+
+#define IPU_IPU_INT_CTRL_1__ADDR           0x1E00003C
+#define IPU_IPU_INT_CTRL_1__EMPTY          0x1E00003C,0x00000000
+#define IPU_IPU_INT_CTRL_1__FULL           0x1E00003C,0xffffffff
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_31 0x1E00003C,0x80000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_29 0x1E00003C,0x20000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_28 0x1E00003C,0x10000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_27 0x1E00003C,0x08000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_24 0x1E00003C,0x01000000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_23 0x1E00003C,0x00800000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_22 0x1E00003C,0x00400000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_21 0x1E00003C,0x00200000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_20 0x1E00003C,0x00100000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_18 0x1E00003C,0x00040000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_17 0x1E00003C,0x00020000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_15 0x1E00003C,0x00008000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_14 0x1E00003C,0x00004000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_12 0x1E00003C,0x00001000
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_11 0x1E00003C,0x00000800
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_7  0x1E00003C,0x00000080
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_6  0x1E00003C,0x00000040
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_5  0x1E00003C,0x00000020
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_4  0x1E00003C,0x00000010
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_3  0x1E00003C,0x00000008
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_2  0x1E00003C,0x00000004
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_1  0x1E00003C,0x00000002
+#define IPU_IPU_INT_CTRL_1__IDMAC_EOF_EN_0  0x1E00003C,0x00000001
+
+#define IPU_IPU_INT_CTRL_2__ADDR           0x1E000040
+#define IPU_IPU_INT_CTRL_2__EMPTY          0x1E000040,0x00000000
+#define IPU_IPU_INT_CTRL_2__FULL           0x1E000040,0xffffffff
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_52 0x1E000040,0x00100000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_51 0x1E000040,0x00080000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_50 0x1E000040,0x00040000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_49 0x1E000040,0x00020000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_48 0x1E000040,0x00010000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_47 0x1E000040,0x00008000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_46 0x1E000040,0x00004000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_45 0x1E000040,0x00002000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_44 0x1E000040,0x00001000
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_43 0x1E000040,0x00000800
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_42 0x1E000040,0x00000400
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_41 0x1E000040,0x00000200
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_40 0x1E000040,0x00000100
+#define IPU_IPU_INT_CTRL_2__IDMAC_EOF_EN_33 0x1E000040,0x00000002
+
+#define IPU_IPU_INT_CTRL_3__ADDR             0x1E000044
+#define IPU_IPU_INT_CTRL_3__EMPTY            0x1E000044,0x00000000
+#define IPU_IPU_INT_CTRL_3__FULL             0x1E000044,0xffffffff
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31 0x1E000044,0x80000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29 0x1E000044,0x20000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28 0x1E000044,0x10000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27 0x1E000044,0x08000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24 0x1E000044,0x01000000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23 0x1E000044,0x00800000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22 0x1E000044,0x00400000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21 0x1E000044,0x00200000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20 0x1E000044,0x00100000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18 0x1E000044,0x00040000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17 0x1E000044,0x00020000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15 0x1E000044,0x00008000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14 0x1E000044,0x00004000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12 0x1E000044,0x00001000
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11 0x1E000044,0x00000800
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_7  0x1E000044,0x00000080
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_6  0x1E000044,0x00000040
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_5  0x1E000044,0x00000020
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_4  0x1E000044,0x00000010
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_3  0x1E000044,0x00000008
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_2  0x1E000044,0x00000004
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_1  0x1E000044,0x00000002
+#define IPU_IPU_INT_CTRL_3__IDMAC_NFACK_EN_0  0x1E000044,0x00000001
+
+#define IPU_IPU_INT_CTRL_4__ADDR             0x1E000048
+#define IPU_IPU_INT_CTRL_4__EMPTY            0x1E000048,0x00000000
+#define IPU_IPU_INT_CTRL_4__FULL             0x1E000048,0xffffffff
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52 0x1E000048,0x00100000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51 0x1E000048,0x00080000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50 0x1E000048,0x00040000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49 0x1E000048,0x00020000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48 0x1E000048,0x00010000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47 0x1E000048,0x00008000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46 0x1E000048,0x00004000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45 0x1E000048,0x00002000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44 0x1E000048,0x00001000
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43 0x1E000048,0x00000800
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42 0x1E000048,0x00000400
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41 0x1E000048,0x00000200
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40 0x1E000048,0x00000100
+#define IPU_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33 0x1E000048,0x00000002
+
+#define IPU_IPU_INT_CTRL_5__ADDR               0x1E00004C
+#define IPU_IPU_INT_CTRL_5__EMPTY              0x1E00004C,0x00000000
+#define IPU_IPU_INT_CTRL_5__FULL               0x1E00004C,0xffffffff
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31 0x1E00004C,0x80000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29 0x1E00004C,0x20000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28 0x1E00004C,0x10000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27 0x1E00004C,0x08000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24 0x1E00004C,0x01000000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23 0x1E00004C,0x00800000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22 0x1E00004C,0x00400000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21 0x1E00004C,0x00200000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20 0x1E00004C,0x00100000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18 0x1E00004C,0x00040000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17 0x1E00004C,0x00020000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15 0x1E00004C,0x00008000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14 0x1E00004C,0x00004000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12 0x1E00004C,0x00001000
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11 0x1E00004C,0x00000800
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_7 0x1E00004C,0x00000080
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_6 0x1E00004C,0x00000040
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_5 0x1E00004C,0x00000020
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_4 0x1E00004C,0x00000010
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_3 0x1E00004C,0x00000008
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_2 0x1E00004C,0x00000004
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_1 0x1E00004C,0x00000002
+#define IPU_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_0 0x1E00004C,0x00000001
+
+#define IPU_IPU_INT_CTRL_6__ADDR               0x1E000050
+#define IPU_IPU_INT_CTRL_6__EMPTY              0x1E000050,0x00000000
+#define IPU_IPU_INT_CTRL_6__FULL               0x1E000050,0xffffffff
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52 0x1E000050,0x00100000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51 0x1E000050,0x00080000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50 0x1E000050,0x00040000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49 0x1E000050,0x00020000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48 0x1E000050,0x00010000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47 0x1E000050,0x00008000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46 0x1E000050,0x00004000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45 0x1E000050,0x00002000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44 0x1E000050,0x00001000
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43 0x1E000050,0x00000800
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42 0x1E000050,0x00000400
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41 0x1E000050,0x00000200
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40 0x1E000050,0x00000100
+#define IPU_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33 0x1E000050,0x00000002
+
+#define IPU_IPU_INT_CTRL_7__ADDR           0x1E000054
+#define IPU_IPU_INT_CTRL_7__EMPTY          0x1E000054,0x00000000
+#define IPU_IPU_INT_CTRL_7__FULL           0x1E000054,0xffffffff
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1E000054,0x80000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1E000054,0x20000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1E000054,0x10000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1E000054,0x08000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1E000054,0x01000000
+#define IPU_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1E000054,0x00800000
+
+#define IPU_IPU_INT_CTRL_8__ADDR           0x1E000058
+#define IPU_IPU_INT_CTRL_8__EMPTY          0x1E000058,0x00000000
+#define IPU_IPU_INT_CTRL_8__FULL           0x1E000058,0xffffffff
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1E000058,0x00100000
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1E000058,0x00080000
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1E000058,0x00001000
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1E000058,0x00000800
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1E000058,0x00000400
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1E000058,0x00000200
+#define IPU_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1E000058,0x00000002
+
+#define IPU_IPU_INT_CTRL_9__ADDR               0x1E00005C
+#define IPU_IPU_INT_CTRL_9__EMPTY              0x1E00005C,0x00000000
+#define IPU_IPU_INT_CTRL_9__FULL               0x1E00005C,0xffffffff
+#define IPU_IPU_INT_CTRL_9__CSI1_PUPE_EN       0x1E00005C,0x80000000
+#define IPU_IPU_INT_CTRL_9__CSI0_PUPE_EN       0x1E00005C,0x40000000
+#define IPU_IPU_INT_CTRL_9__ISP_PUPE_EN                0x1E00005C,0x20000000
+#define IPU_IPU_INT_CTRL_9__IC_VF_BUF_OVF_EN   0x1E00005C,0x10000000
+#define IPU_IPU_INT_CTRL_9__IC_ENC_BUF_OVF_EN  0x1E00005C,0x08000000
+#define IPU_IPU_INT_CTRL_9__IC_BAYER_BUF_OVF_EN 0x1E00005C,0x04000000
+
+#define IPU_IPU_INT_CTRL_10__ADDR                     0x1E000060
+#define IPU_IPU_INT_CTRL_10__EMPTY                    0x1E000060,0x00000000
+#define IPU_IPU_INT_CTRL_10__FULL                     0x1E000060,0xffffffff
+#define IPU_IPU_INT_CTRL_10__AXIR_ERR_EN              0x1E000060,0x40000000
+#define IPU_IPU_INT_CTRL_10__AXIW_ERR_EN              0x1E000060,0x20000000
+#define IPU_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN 0x1E000060,0x10000000
+#define IPU_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN  0x1E000060,0x04000000
+#define IPU_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN    0x1E000060,0x02000000
+#define IPU_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN     0x1E000060,0x01000000
+#define IPU_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN       0x1E000060,0x00400000
+#define IPU_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN       0x1E000060,0x00200000
+#define IPU_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN      0x1E000060,0x00100000
+#define IPU_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN      0x1E000060,0x00080000
+#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN       0x1E000060,0x00040000
+#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN       0x1E000060,0x00020000
+#define IPU_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN       0x1E000060,0x00010000
+#define IPU_IPU_INT_CTRL_10__ISP_RAM_HIST_OF_EN               0x1E000060,0x00000020
+#define IPU_IPU_INT_CTRL_10__ISP_RAM_ST_OF_EN         0x1E000060,0x00000010
+#define IPU_IPU_INT_CTRL_10__SMFC3_FRM_LOST_EN        0x1E000060,0x00000008
+#define IPU_IPU_INT_CTRL_10__SMFC2_FRM_LOST_EN        0x1E000060,0x00000004
+#define IPU_IPU_INT_CTRL_10__SMFC1_FRM_LOST_EN        0x1E000060,0x00000002
+#define IPU_IPU_INT_CTRL_10__SMFC0_FRM_LOST_EN        0x1E000060,0x00000001
+
+#define IPU_IPU_INT_CTRL_11__ADDR             0x1E000064
+#define IPU_IPU_INT_CTRL_11__EMPTY            0x1E000064,0x00000000
+#define IPU_IPU_INT_CTRL_11__FULL             0x1E000064,0xffffffff
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22 0x1E000064,0x00400000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21 0x1E000064,0x00200000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20 0x1E000064,0x00100000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12 0x1E000064,0x00001000
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11 0x1E000064,0x00000800
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_5  0x1E000064,0x00000020
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_3  0x1E000064,0x00000008
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_2  0x1E000064,0x00000004
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_1  0x1E000064,0x00000002
+#define IPU_IPU_INT_CTRL_11__IDMAC_EOBND_EN_0  0x1E000064,0x00000001
+
+#define IPU_IPU_INT_CTRL_12__ADDR             0x1E000068
+#define IPU_IPU_INT_CTRL_12__EMPTY            0x1E000068,0x00000000
+#define IPU_IPU_INT_CTRL_12__FULL             0x1E000068,0xffffffff
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50 0x1E000068,0x00040000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49 0x1E000068,0x00020000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48 0x1E000068,0x00010000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47 0x1E000068,0x00008000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46 0x1E000068,0x00004000
+#define IPU_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45 0x1E000068,0x00002000
+
+#define IPU_IPU_INT_CTRL_13__ADDR          0x1E00006C
+#define IPU_IPU_INT_CTRL_13__EMPTY         0x1E00006C,0x00000000
+#define IPU_IPU_INT_CTRL_13__FULL          0x1E00006C,0xffffffff
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_31 0x1E00006C,0x80000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_29 0x1E00006C,0x20000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_28 0x1E00006C,0x10000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_27 0x1E00006C,0x08000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_24 0x1E00006C,0x01000000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_23 0x1E00006C,0x00800000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_22 0x1E00006C,0x00400000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_21 0x1E00006C,0x00200000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_20 0x1E00006C,0x00100000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_18 0x1E00006C,0x00040000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_17 0x1E00006C,0x00020000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_15 0x1E00006C,0x00008000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_14 0x1E00006C,0x00004000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_12 0x1E00006C,0x00001000
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_11 0x1E00006C,0x00000800
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_7  0x1E00006C,0x00000080
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_6  0x1E00006C,0x00000040
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_5  0x1E00006C,0x00000020
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_4  0x1E00006C,0x00000010
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_3  0x1E00006C,0x00000008
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_2  0x1E00006C,0x00000004
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_1  0x1E00006C,0x00000002
+#define IPU_IPU_INT_CTRL_13__IDMAC_TH_EN_0  0x1E00006C,0x00000001
+
+#define IPU_IPU_INT_CTRL_14__ADDR          0x1E000070
+#define IPU_IPU_INT_CTRL_14__EMPTY         0x1E000070,0x00000000
+#define IPU_IPU_INT_CTRL_14__FULL          0x1E000070,0xffffffff
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_52 0x1E000070,0x00100000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_51 0x1E000070,0x00080000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_50 0x1E000070,0x00040000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_49 0x1E000070,0x00020000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_48 0x1E000070,0x00010000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_47 0x1E000070,0x00008000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_46 0x1E000070,0x00004000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_45 0x1E000070,0x00002000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_44 0x1E000070,0x00001000
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_43 0x1E000070,0x00000800
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_42 0x1E000070,0x00000400
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_41 0x1E000070,0x00000200
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_40 0x1E000070,0x00000100
+#define IPU_IPU_INT_CTRL_14__IDMAC_TH_EN_33 0x1E000070,0x00000002
+
+#define IPU_IPU_INT_CTRL_15__ADDR                  0x1E000074
+#define IPU_IPU_INT_CTRL_15__EMPTY                 0x1E000074,0x00000000
+#define IPU_IPU_INT_CTRL_15__FULL                  0x1E000074,0xffffffff
+#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN    0x1E000074,0x80000000
+#define IPU_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN    0x1E000074,0x40000000
+#define IPU_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN 0x1E000074,0x20000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN   0x1E000074,0x10000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN    0x1E000074,0x08000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN    0x1E000074,0x04000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN    0x1E000074,0x02000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN    0x1E000074,0x01000000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN    0x1E000074,0x00800000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN    0x1E000074,0x00400000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN    0x1E000074,0x00200000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN    0x1E000074,0x00100000
+#define IPU_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN    0x1E000074,0x00080000
+#define IPU_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN 0x1E000074,0x00040000
+#define IPU_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN      0x1E000074,0x00020000
+#define IPU_IPU_INT_CTRL_15__DC_DP_START_EN        0x1E000074,0x00010000
+#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN     0x1E000074,0x00008000
+#define IPU_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN     0x1E000074,0x00004000
+#define IPU_IPU_INT_CTRL_15__DC_FC_6_EN                    0x1E000074,0x00002000
+#define IPU_IPU_INT_CTRL_15__DC_FC_4_EN                    0x1E000074,0x00001000
+#define IPU_IPU_INT_CTRL_15__DC_FC_3_EN                    0x1E000074,0x00000800
+#define IPU_IPU_INT_CTRL_15__DC_FC_2_EN                    0x1E000074,0x00000400
+#define IPU_IPU_INT_CTRL_15__DC_FC_1_EN                    0x1E000074,0x00000200
+#define IPU_IPU_INT_CTRL_15__DC_FC_0_EN                    0x1E000074,0x00000100
+#define IPU_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN       0x1E000074,0x00000080
+#define IPU_IPU_INT_CTRL_15__DP_SF_BRAKE_EN        0x1E000074,0x00000040
+#define IPU_IPU_INT_CTRL_15__DP_ASF_END_EN         0x1E000074,0x00000020
+#define IPU_IPU_INT_CTRL_15__DP_ASF_START_EN       0x1E000074,0x00000010
+#define IPU_IPU_INT_CTRL_15__DP_SF_END_EN          0x1E000074,0x00000008
+#define IPU_IPU_INT_CTRL_15__DP_SF_START_EN        0x1E000074,0x00000004
+#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN   0x1E000074,0x00000002
+#define IPU_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN   0x1E000074,0x00000001
+
+#define IPU_IPU_SDMA_EVENT_1__ADDR                0x1E000078
+#define IPU_IPU_SDMA_EVENT_1__EMPTY               0x1E000078,0x00000000
+#define IPU_IPU_SDMA_EVENT_1__FULL                0x1E000078,0xffffffff
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31 0x1E000078,0x80000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29 0x1E000078,0x20000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28 0x1E000078,0x10000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27 0x1E000078,0x08000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24 0x1E000078,0x01000000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23 0x1E000078,0x00800000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22 0x1E000078,0x00400000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21 0x1E000078,0x00200000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20 0x1E000078,0x00100000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18 0x1E000078,0x00040000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17 0x1E000078,0x00020000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15 0x1E000078,0x00008000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14 0x1E000078,0x00004000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12 0x1E000078,0x00001000
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11 0x1E000078,0x00000800
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_7  0x1E000078,0x00000080
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_6  0x1E000078,0x00000040
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_5  0x1E000078,0x00000020
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_4  0x1E000078,0x00000010
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_3  0x1E000078,0x00000008
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_2  0x1E000078,0x00000004
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_1  0x1E000078,0x00000002
+#define IPU_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_0  0x1E000078,0x00000001
+
+#define IPU_IPU_SDMA_EVENT_2__ADDR                0x1E00007C
+#define IPU_IPU_SDMA_EVENT_2__EMPTY               0x1E00007C,0x00000000
+#define IPU_IPU_SDMA_EVENT_2__FULL                0x1E00007C,0xffffffff
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52 0x1E00007C,0x00100000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51 0x1E00007C,0x00080000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50 0x1E00007C,0x00040000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49 0x1E00007C,0x00020000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48 0x1E00007C,0x00010000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47 0x1E00007C,0x00008000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46 0x1E00007C,0x00004000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45 0x1E00007C,0x00002000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44 0x1E00007C,0x00001000
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43 0x1E00007C,0x00000800
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42 0x1E00007C,0x00000400
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41 0x1E00007C,0x00000200
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40 0x1E00007C,0x00000100
+#define IPU_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33 0x1E00007C,0x00000002
+
+#define IPU_IPU_SDMA_EVENT_3__ADDR                  0x1E000080
+#define IPU_IPU_SDMA_EVENT_3__EMPTY                 0x1E000080,0x00000000
+#define IPU_IPU_SDMA_EVENT_3__FULL                  0x1E000080,0xffffffff
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31 0x1E000080,0x80000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29 0x1E000080,0x20000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28 0x1E000080,0x10000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27 0x1E000080,0x08000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24 0x1E000080,0x01000000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23 0x1E000080,0x00800000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22 0x1E000080,0x00400000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21 0x1E000080,0x00200000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20 0x1E000080,0x00100000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18 0x1E000080,0x00040000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17 0x1E000080,0x00020000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15 0x1E000080,0x00008000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14 0x1E000080,0x00004000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12 0x1E000080,0x00001000
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11 0x1E000080,0x00000800
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_7  0x1E000080,0x00000080
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_6  0x1E000080,0x00000040
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_5  0x1E000080,0x00000020
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_4  0x1E000080,0x00000010
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_3  0x1E000080,0x00000008
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_2  0x1E000080,0x00000004
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_1  0x1E000080,0x00000002
+#define IPU_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_0  0x1E000080,0x00000001
+
+#define IPU_IPU_SDMA_EVENT_4__ADDR                  0x1E000084
+#define IPU_IPU_SDMA_EVENT_4__EMPTY                 0x1E000084,0x00000000
+#define IPU_IPU_SDMA_EVENT_4__FULL                  0x1E000084,0xffffffff
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52 0x1E000084,0x00100000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51 0x1E000084,0x00080000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50 0x1E000084,0x00040000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49 0x1E000084,0x00020000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48 0x1E000084,0x00010000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47 0x1E000084,0x00008000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46 0x1E000084,0x00004000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45 0x1E000084,0x00002000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44 0x1E000084,0x00001000
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43 0x1E000084,0x00000800
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42 0x1E000084,0x00000400
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41 0x1E000084,0x00000200
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40 0x1E000084,0x00000100
+#define IPU_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33 0x1E000084,0x00000002
+
+#define IPU_IPU_SDMA_EVENT_7__ADDR                0x1E000088
+#define IPU_IPU_SDMA_EVENT_7__EMPTY               0x1E000088,0x00000000
+#define IPU_IPU_SDMA_EVENT_7__FULL                0x1E000088,0xffffffff
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1E000088,0x80000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1E000088,0x20000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1E000088,0x10000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1E000088,0x08000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1E000088,0x01000000
+#define IPU_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1E000088,0x00800000
+
+#define IPU_IPU_SDMA_EVENT_8__ADDR                0x1E00008C
+#define IPU_IPU_SDMA_EVENT_8__EMPTY               0x1E00008C,0x00000000
+#define IPU_IPU_SDMA_EVENT_8__FULL                0x1E00008C,0xffffffff
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1E00008C,0x00100000
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1E00008C,0x00080000
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1E00008C,0x00001000
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1E00008C,0x00000800
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1E00008C,0x00000400
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1E00008C,0x00000200
+#define IPU_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1E00008C,0x00000002
+
+#define IPU_IPU_SDMA_EVENT_11__ADDR                  0x1E000090
+#define IPU_IPU_SDMA_EVENT_11__EMPTY                 0x1E000090,0x00000000
+#define IPU_IPU_SDMA_EVENT_11__FULL                  0x1E000090,0xffffffff
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22 0x1E000090,0x00400000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21 0x1E000090,0x00200000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20 0x1E000090,0x00100000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12 0x1E000090,0x00001000
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11 0x1E000090,0x00000800
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_5  0x1E000090,0x00000020
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_3  0x1E000090,0x00000008
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_2  0x1E000090,0x00000004
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_1  0x1E000090,0x00000002
+#define IPU_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_0  0x1E000090,0x00000001
+
+#define IPU_IPU_SDMA_EVENT_12__ADDR                  0x1E000094
+#define IPU_IPU_SDMA_EVENT_12__EMPTY                 0x1E000094,0x00000000
+#define IPU_IPU_SDMA_EVENT_12__FULL                  0x1E000094,0xffffffff
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50 0x1E000094,0x00040000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49 0x1E000094,0x00020000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48 0x1E000094,0x00010000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47 0x1E000094,0x00008000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46 0x1E000094,0x00004000
+#define IPU_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45 0x1E000094,0x00002000
+
+#define IPU_IPU_SDMA_EVENT_13__ADDR               0x1E000098
+#define IPU_IPU_SDMA_EVENT_13__EMPTY              0x1E000098,0x00000000
+#define IPU_IPU_SDMA_EVENT_13__FULL               0x1E000098,0xffffffff
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31 0x1E000098,0x80000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29 0x1E000098,0x20000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28 0x1E000098,0x10000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27 0x1E000098,0x08000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24 0x1E000098,0x01000000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23 0x1E000098,0x00800000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22 0x1E000098,0x00400000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21 0x1E000098,0x00200000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20 0x1E000098,0x00100000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18 0x1E000098,0x00040000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17 0x1E000098,0x00020000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15 0x1E000098,0x00008000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14 0x1E000098,0x00004000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12 0x1E000098,0x00001000
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11 0x1E000098,0x00000800
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_7  0x1E000098,0x00000080
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_6  0x1E000098,0x00000040
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_5  0x1E000098,0x00000020
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_4  0x1E000098,0x00000010
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_3  0x1E000098,0x00000008
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_2  0x1E000098,0x00000004
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_1  0x1E000098,0x00000002
+#define IPU_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_0  0x1E000098,0x00000001
+
+#define IPU_IPU_SDMA_EVENT_14__ADDR               0x1E00009C
+#define IPU_IPU_SDMA_EVENT_14__EMPTY              0x1E00009C,0x00000000
+#define IPU_IPU_SDMA_EVENT_14__FULL               0x1E00009C,0xffffffff
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52 0x1E00009C,0x00100000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51 0x1E00009C,0x00080000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50 0x1E00009C,0x00040000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49 0x1E00009C,0x00020000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48 0x1E00009C,0x00010000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47 0x1E00009C,0x00008000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46 0x1E00009C,0x00004000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45 0x1E00009C,0x00002000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44 0x1E00009C,0x00001000
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43 0x1E00009C,0x00000800
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42 0x1E00009C,0x00000400
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41 0x1E00009C,0x00000200
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40 0x1E00009C,0x00000100
+#define IPU_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33 0x1E00009C,0x00000002
+
+#define IPU_IPU_SRM_PRI1__ADDR         0x1E0000A0
+#define IPU_IPU_SRM_PRI1__EMPTY                0x1E0000A0,0x00000000
+#define IPU_IPU_SRM_PRI1__FULL         0x1E0000A0,0xffffffff
+#define IPU_IPU_SRM_PRI1__ISP_SRM_MODE 0x1E0000A0,0x00180000
+#define IPU_IPU_SRM_PRI1__ISP_SRM_PRI  0x1E0000A0,0x00070000
+#define IPU_IPU_SRM_PRI1__CSI0_SRM_MODE 0x1E0000A0,0x00001800
+#define IPU_IPU_SRM_PRI1__CSI0_SRM_PRI 0x1E0000A0,0x00000700
+#define IPU_IPU_SRM_PRI1__CSI1_SRM_MODE 0x1E0000A0,0x00000018
+#define IPU_IPU_SRM_PRI1__CSI1_SRM_PRI 0x1E0000A0,0x00000007
+
+#define IPU_IPU_SRM_PRI2__ADDR          0x1E0000A4
+#define IPU_IPU_SRM_PRI2__EMPTY                 0x1E0000A4,0x00000000
+#define IPU_IPU_SRM_PRI2__FULL          0x1E0000A4,0xffffffff
+#define IPU_IPU_SRM_PRI2__DI1_SRM_MODE  0x1E0000A4,0x18000000
+#define IPU_IPU_SRM_PRI2__DI1_SRM_PRI   0x1E0000A4,0x07000000
+#define IPU_IPU_SRM_PRI2__DI0_SRM_MODE  0x1E0000A4,0x00180000
+#define IPU_IPU_SRM_PRI2__DI0_SRM_PRI   0x1E0000A4,0x00070000
+#define IPU_IPU_SRM_PRI2__DC_6_SRM_MODE         0x1E0000A4,0x0000C000
+#define IPU_IPU_SRM_PRI2__DC_2_SRM_MODE         0x1E0000A4,0x00003000
+#define IPU_IPU_SRM_PRI2__DC_SRM_PRI    0x1E0000A4,0x00000E00
+#define IPU_IPU_SRM_PRI2__DP_A1_SRM_MODE 0x1E0000A4,0x00000180
+#define IPU_IPU_SRM_PRI2__DP_A0_SRM_MODE 0x1E0000A4,0x00000060
+#define IPU_IPU_SRM_PRI2__DP_S_SRM_MODE         0x1E0000A4,0x00000018
+#define IPU_IPU_SRM_PRI2__DP_SRM_PRI    0x1E0000A4,0x00000007
+
+#define IPU_IPU_FS_PROC_FLOW1__ADDR              0x1E0000A8
+#define IPU_IPU_FS_PROC_FLOW1__EMPTY             0x1E0000A8,0x00000000
+#define IPU_IPU_FS_PROC_FLOW1__FULL              0x1E0000A8,0xffffffff
+#define IPU_IPU_FS_PROC_FLOW1__VF_IN_VALID       0x1E0000A8,0x80000000
+#define IPU_IPU_FS_PROC_FLOW1__ENC_IN_VALID      0x1E0000A8,0x40000000
+#define IPU_IPU_FS_PROC_FLOW1__PRP_SRC_SEL       0x1E0000A8,0x0F000000
+#define IPU_IPU_FS_PROC_FLOW1__ISP_SRC_SEL       0x1E0000A8,0x00F00000
+#define IPU_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL    0x1E0000A8,0x000F0000
+#define IPU_IPU_FS_PROC_FLOW1__PP_SRC_SEL        0x1E0000A8,0x0000F000
+#define IPU_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL  0x1E0000A8,0x00000F00
+#define IPU_IPU_FS_PROC_FLOW1__ALT_ISP_SRC_SEL   0x1E0000A8,0x000000F0
+#define IPU_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL 0x1E0000A8,0x0000000F
+
+#define IPU_IPU_FS_PROC_FLOW2__ADDR               0x1E0000AC
+#define IPU_IPU_FS_PROC_FLOW2__EMPTY              0x1E0000AC,0x00000000
+#define IPU_IPU_FS_PROC_FLOW2__FULL               0x1E0000AC,0xffffffff
+#define IPU_IPU_FS_PROC_FLOW2__PRP_ALT_DEST_SEL           0x1E0000AC,0xF0000000
+#define IPU_IPU_FS_PROC_FLOW2__PRP_DEST_SEL       0x1E0000AC,0x0F000000
+#define IPU_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL 0x1E0000AC,0x00F00000
+#define IPU_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL    0x1E0000AC,0x000F0000
+#define IPU_IPU_FS_PROC_FLOW2__PP_DEST_SEL        0x1E0000AC,0x0000F000
+#define IPU_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL  0x1E0000AC,0x00000F00
+#define IPU_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL     0x1E0000AC,0x000000F0
+#define IPU_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL           0x1E0000AC,0x0000000F
+
+#define IPU_IPU_FS_PROC_FLOW3__ADDR          0x1E0000B0
+#define IPU_IPU_FS_PROC_FLOW3__EMPTY         0x1E0000B0,0x00000000
+#define IPU_IPU_FS_PROC_FLOW3__FULL          0x1E0000B0,0xffffffff
+#define IPU_IPU_FS_PROC_FLOW3__SMFC3_DEST_SEL 0x1E0000B0,0x00003800
+#define IPU_IPU_FS_PROC_FLOW3__SMFC2_DEST_SEL 0x1E0000B0,0x00000780
+#define IPU_IPU_FS_PROC_FLOW3__SMFC1_DEST_SEL 0x1E0000B0,0x00000070
+#define IPU_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL 0x1E0000B0,0x0000000F
+
+#define IPU_IPU_FS_DISP_FLOW1__ADDR             0x1E0000B4
+#define IPU_IPU_FS_DISP_FLOW1__EMPTY            0x1E0000B4,0x00000000
+#define IPU_IPU_FS_DISP_FLOW1__FULL             0x1E0000B4,0xffffffff
+#define IPU_IPU_FS_DISP_FLOW1__DC1_SRC_SEL      0x1E0000B4,0x00F00000
+#define IPU_IPU_FS_DISP_FLOW1__DC2_SRC_SEL      0x1E0000B4,0x000F0000
+#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL 0x1E0000B4,0x0000F000
+#define IPU_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL 0x1E0000B4,0x00000F00
+#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL         0x1E0000B4,0x000000F0
+#define IPU_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL         0x1E0000B4,0x0000000F
+
+#define IPU_IPU_FS_DISP_FLOW2__ADDR                 0x1E0000B8
+#define IPU_IPU_FS_DISP_FLOW2__EMPTY                0x1E0000B8,0x00000000
+#define IPU_IPU_FS_DISP_FLOW2__FULL                 0x1E0000B8,0xffffffff
+#define IPU_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL      0x1E0000B8,0x000F0000
+#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL 0x1E0000B8,0x000000F0
+#define IPU_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL 0x1E0000B8,0x0000000F
+
+#define IPU_IPU_SKIP__ADDR                     0x1E0000BC
+#define IPU_IPU_SKIP__EMPTY                    0x1E0000BC,0x00000000
+#define IPU_IPU_SKIP__FULL                     0x1E0000BC,0xffffffff
+#define IPU_IPU_SKIP__CSI_SKIP_IC_VF           0x1E0000BC,0x0000F800
+#define IPU_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_VF 0x1E0000BC,0x00000700
+#define IPU_IPU_SKIP__CSI_SKIP_IC_ENC          0x1E0000BC,0x000000F8
+#define IPU_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_ENC 0x1E0000BC,0x00000007
+
+#define IPU_IPU_DISP_ALT_CONF__ADDR  0x1E0000C0
+#define IPU_IPU_DISP_ALT_CONF__EMPTY 0x1E0000C0,0x00000000
+#define IPU_IPU_DISP_ALT_CONF__FULL  0x1E0000C0,0xffffffff
+
+#define IPU_IPU_DISP_GEN__ADDR                0x1E0000C4
+#define IPU_IPU_DISP_GEN__EMPTY                       0x1E0000C4,0x00000000
+#define IPU_IPU_DISP_GEN__FULL                0x1E0000C4,0xffffffff
+#define IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE  0x1E0000C4,0x02000000
+#define IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE  0x1E0000C4,0x01000000
+#define IPU_IPU_DISP_GEN__CSI_VSYNC_DEST       0x1E0000C4,0x00800000
+#define IPU_IPU_DISP_GEN__MCU_MAX_BURST_STOP   0x1E0000C4,0x00400000
+#define IPU_IPU_DISP_GEN__MCU_T                       0x1E0000C4,0x003C0000
+#define IPU_IPU_DISP_GEN__MCU_DI_ID_9         0x1E0000C4,0x00020000
+#define IPU_IPU_DISP_GEN__MCU_DI_ID_8         0x1E0000C4,0x00010000
+#define IPU_IPU_DISP_GEN__DP_PIPE_CLR         0x1E0000C4,0x00000040
+#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC1      0x1E0000C4,0x00000020
+#define IPU_IPU_DISP_GEN__DP_FG_EN_ASYNC0      0x1E0000C4,0x00000010
+#define IPU_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW 0x1E0000C4,0x00000008
+#define IPU_IPU_DISP_GEN__DC2_DOUBLE_FLOW      0x1E0000C4,0x00000004
+#define IPU_IPU_DISP_GEN__DI1_DUAL_MODE               0x1E0000C4,0x00000002
+#define IPU_IPU_DISP_GEN__DI0_DUAL_MODE               0x1E0000C4,0x00000001
+
+#define IPU_IPU_DISP_ALT1__ADDR                         0x1E0000C8
+#define IPU_IPU_DISP_ALT1__EMPTY                0x1E0000C8,0x00000000
+#define IPU_IPU_DISP_ALT1__FULL                         0x1E0000C8,0xffffffff
+#define IPU_IPU_DISP_ALT1__SEL_ALT_0            0x1E0000C8,0xF0000000
+#define IPU_IPU_DISP_ALT1__STEP_REPEAT_ALT_0    0x1E0000C8,0x0FFF0000
+#define IPU_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0 0x1E0000C8,0x00008000
+#define IPU_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0    0x1E0000C8,0x00007000
+#define IPU_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0   0x1E0000C8,0x00000FFF
+
+#define IPU_IPU_DISP_ALT2__ADDR                           0x1E0000CC
+#define IPU_IPU_DISP_ALT2__EMPTY                  0x1E0000CC,0x00000000
+#define IPU_IPU_DISP_ALT2__FULL                           0x1E0000CC,0xffffffff
+#define IPU_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0           0x1E0000CC,0x00070000
+#define IPU_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0 0x1E0000CC,0x00007000
+#define IPU_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0     0x1E0000CC,0x00000FFF
+
+#define IPU_IPU_DISP_ALT3__ADDR                         0x1E0000D0
+#define IPU_IPU_DISP_ALT3__EMPTY                0x1E0000D0,0x00000000
+#define IPU_IPU_DISP_ALT3__FULL                         0x1E0000D0,0xffffffff
+#define IPU_IPU_DISP_ALT3__SEL_ALT_1            0x1E0000D0,0xF0000000
+#define IPU_IPU_DISP_ALT3__STEP_REPEAT_ALT_1    0x1E0000D0,0x0FFF0000
+#define IPU_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1 0x1E0000D0,0x00008000
+#define IPU_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1    0x1E0000D0,0x00007000
+#define IPU_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1   0x1E0000D0,0x00000FFF
+
+#define IPU_IPU_DISP_ALT4__ADDR                           0x1E0000D4
+#define IPU_IPU_DISP_ALT4__EMPTY                  0x1E0000D4,0x00000000
+#define IPU_IPU_DISP_ALT4__FULL                           0x1E0000D4,0xffffffff
+#define IPU_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1           0x1E0000D4,0x00070000
+#define IPU_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1 0x1E0000D4,0x00007000
+#define IPU_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1     0x1E0000D4,0x00000FFF
+
+#define IPU_IPU_SNOOP__ADDR           0x1E0000D8
+#define IPU_IPU_SNOOP__EMPTY          0x1E0000D8,0x00000000
+#define IPU_IPU_SNOOP__FULL           0x1E0000D8,0xffffffff
+#define IPU_IPU_SNOOP__SNOOP2_SYNC_BYP 0x1E0000D8,0x00010000
+#define IPU_IPU_SNOOP__AUTOREF_PER     0x1E0000D8,0x000003FF
+
+#define IPU_IPU_MEM_RST__ADDR         0x1E0000DC
+#define IPU_IPU_MEM_RST__EMPTY        0x1E0000DC,0x00000000
+#define IPU_IPU_MEM_RST__FULL         0x1E0000DC,0xffffffff
+#define IPU_IPU_MEM_RST__RST_MEM_START 0x1E0000DC,0x80000000
+#define IPU_IPU_MEM_RST__RST_MEM_EN    0x1E0000DC,0x007FFFFF
+
+#define IPU_IPU_PM__ADDR                     0x1E0000E0
+#define IPU_IPU_PM__EMPTY                    0x1E0000E0,0x00000000
+#define IPU_IPU_PM__FULL                     0x1E0000E0,0xffffffff
+#define IPU_IPU_PM__LPSR_MODE                0x1E0000E0,0x80000000
+#define IPU_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x40000000
+#define IPU_IPU_PM__DI1_CLK_PERIOD_1         0x1E0000E0,0x3F800000
+#define IPU_IPU_PM__DI1_CLK_PERIOD_0         0x1E0000E0,0x007F0000
+#define IPU_IPU_PM__CLOCK_MODE_STAT          0x1E0000E0,0x00008000
+#define IPU_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE 0x1E0000E0,0x00004000
+#define IPU_IPU_PM__DI0_CLK_PERIOD_1         0x1E0000E0,0x00003F80
+#define IPU_IPU_PM__DI0_CLK_PERIOD_0         0x1E0000E0,0x0000007F
+
+#define IPU_IPU_GPR__ADDR                      0x1E0000E4
+#define IPU_IPU_GPR__EMPTY                     0x1E0000E4,0x00000000
+#define IPU_IPU_GPR__FULL                      0x1E0000E4,0xffffffff
+#define IPU_IPU_GPR__IPU_CH_BUF1_RDY1_CLR      0x1E0000E4,0x80000000
+#define IPU_IPU_GPR__IPU_CH_BUF1_RDY0_CLR      0x1E0000E4,0x40000000
+#define IPU_IPU_GPR__IPU_CH_BUF0_RDY1_CLR      0x1E0000E4,0x20000000
+#define IPU_IPU_GPR__IPU_CH_BUF0_RDY0_CLR      0x1E0000E4,0x10000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR  0x1E0000E4,0x08000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR  0x1E0000E4,0x04000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR  0x1E0000E4,0x02000000
+#define IPU_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR  0x1E0000E4,0x01000000
+#define IPU_IPU_GPR__IPU_DI1_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00800000
+#define IPU_IPU_GPR__IPU_DI0_CLK_CHANGE_ACK_DIS 0x1E0000E4,0x00400000
+#define IPU_IPU_GPR__IPU_GP21                  0x1E0000E4,0x00200000
+#define IPU_IPU_GPR__IPU_GP20                  0x1E0000E4,0x00100000
+#define IPU_IPU_GPR__IPU_GP19                  0x1E0000E4,0x00080000
+#define IPU_IPU_GPR__IPU_GP18                  0x1E0000E4,0x00040000
+#define IPU_IPU_GPR__IPU_GP17                  0x1E0000E4,0x00020000
+#define IPU_IPU_GPR__IPU_GP16                  0x1E0000E4,0x00010000
+#define IPU_IPU_GPR__IPU_GP15                  0x1E0000E4,0x00008000
+#define IPU_IPU_GPR__IPU_GP14                  0x1E0000E4,0x00004000
+#define IPU_IPU_GPR__IPU_GP13                  0x1E0000E4,0x00002000
+#define IPU_IPU_GPR__IPU_GP12                  0x1E0000E4,0x00001000
+#define IPU_IPU_GPR__IPU_GP11                  0x1E0000E4,0x00000800
+#define IPU_IPU_GPR__IPU_GP10                  0x1E0000E4,0x00000400
+#define IPU_IPU_GPR__IPU_GP9                   0x1E0000E4,0x00000200
+#define IPU_IPU_GPR__IPU_GP8                   0x1E0000E4,0x00000100
+#define IPU_IPU_GPR__IPU_GP7                   0x1E0000E4,0x00000080
+#define IPU_IPU_GPR__IPU_GP6                   0x1E0000E4,0x00000040
+#define IPU_IPU_GPR__IPU_GP5                   0x1E0000E4,0x00000020
+#define IPU_IPU_GPR__IPU_GP4                   0x1E0000E4,0x00000010
+#define IPU_IPU_GPR__IPU_GP3                   0x1E0000E4,0x00000008
+#define IPU_IPU_GPR__IPU_GP2                   0x1E0000E4,0x00000004
+#define IPU_IPU_GPR__IPU_GP1                   0x1E0000E4,0x00000002
+#define IPU_IPU_GPR__IPU_GP0                   0x1E0000E4,0x00000001
+
+#define IPU_IPU_CH_DB_MODE_SEL_0__ADDR                 0x1E000150
+#define IPU_IPU_CH_DB_MODE_SEL_0__EMPTY                        0x1E000150,0x00000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__FULL                 0x1E000150,0xffffffff
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_31 0x1E000150,0x80000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_29 0x1E000150,0x20000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_28 0x1E000150,0x10000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_27 0x1E000150,0x08000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_24 0x1E000150,0x01000000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_23 0x1E000150,0x00800000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_22 0x1E000150,0x00400000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_21 0x1E000150,0x00200000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_20 0x1E000150,0x00100000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_18 0x1E000150,0x00040000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_17 0x1E000150,0x00020000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_15 0x1E000150,0x00008000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_14 0x1E000150,0x00004000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_12 0x1E000150,0x00001000
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_11 0x1E000150,0x00000800
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_7 0x1E000150,0x00000080
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_6 0x1E000150,0x00000040
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_5 0x1E000150,0x00000020
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_4 0x1E000150,0x00000010
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_3 0x1E000150,0x00000008
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_2 0x1E000150,0x00000004
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_1 0x1E000150,0x00000002
+#define IPU_IPU_CH_DB_MODE_SEL_0__DMA_CH_DB_MODE_SEL_0 0x1E000150,0x00000001
+
+#define IPU_IPU_CH_DB_MODE_SEL_1__ADDR                 0x1E000154
+#define IPU_IPU_CH_DB_MODE_SEL_1__EMPTY                        0x1E000154,0x00000000
+#define IPU_IPU_CH_DB_MODE_SEL_1__FULL                 0x1E000154,0xffffffff
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_52 0x1E000154,0x00100000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_51 0x1E000154,0x00080000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_50 0x1E000154,0x00040000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_49 0x1E000154,0x00020000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_48 0x1E000154,0x00010000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_47 0x1E000154,0x00008000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_46 0x1E000154,0x00004000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_45 0x1E000154,0x00002000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_44 0x1E000154,0x00001000
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_43 0x1E000154,0x00000800
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_42 0x1E000154,0x00000400
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_41 0x1E000154,0x00000200
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_40 0x1E000154,0x00000100
+#define IPU_IPU_CH_DB_MODE_SEL_1__DMA_CH_DB_MODE_SEL_33 0x1E000154,0x00000002
+
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__ADDR                     0x1E000168
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__EMPTY                    0x1E000168,0x00000000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__FULL                     0x1E000168,0xffffffff
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_29 0x1E000168,0x20000000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_24 0x1E000168,0x01000000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_7 0x1E000168,0x00000080
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_6 0x1E000168,0x00000040
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_5 0x1E000168,0x00000020
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_0__DMA_CH_ALT_DB_MODE_SEL_4 0x1E000168,0x00000010
+
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__ADDR                     0x1E00016C
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__EMPTY                    0x1E00016C,0x00000000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__FULL                     0x1E00016C,0xffffffff
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_52 0x1E00016C,0x00100000
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_41 0x1E00016C,0x00000200
+#define IPU_IPU_ALT_CH_DB_MODE_SEL_1__DMA_CH_ALT_DB_MODE_SEL_33 0x1E00016C,0x00000002
+
+#define IPU_IPU_CH_TRB_MODE_SEL_0__ADDR                             0x1E000178
+#define IPU_IPU_CH_TRB_MODE_SEL_1__ADDR                             0x1E00017C
+
+// ================== End of IPUV3EX Common Registers ======================
+
+// ================= Start of IPUV3EX Status Registers =====================
+
+#define IPU_IPU_INT_STAT_1__ADDR        0x1E000200
+#define IPU_IPU_INT_STAT_1__EMPTY       0x1E000200,0x00000000
+#define IPU_IPU_INT_STAT_1__FULL        0x1E000200,0xffffffff
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_31 0x1E000200,0x80000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_29 0x1E000200,0x20000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_28 0x1E000200,0x10000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_27 0x1E000200,0x08000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_24 0x1E000200,0x01000000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_23 0x1E000200,0x00800000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_22 0x1E000200,0x00400000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_21 0x1E000200,0x00200000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_20 0x1E000200,0x00100000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_18 0x1E000200,0x00040000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_17 0x1E000200,0x00020000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_15 0x1E000200,0x00008000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_14 0x1E000200,0x00004000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_12 0x1E000200,0x00001000
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_11 0x1E000200,0x00000800
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_7         0x1E000200,0x00000080
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_6         0x1E000200,0x00000040
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_5         0x1E000200,0x00000020
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_4         0x1E000200,0x00000010
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_3         0x1E000200,0x00000008
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_2         0x1E000200,0x00000004
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_1         0x1E000200,0x00000002
+#define IPU_IPU_INT_STAT_1__IDMAC_EOF_0         0x1E000200,0x00000001
+
+#define IPU_IPU_INT_STAT_2__ADDR        0x1E000204
+#define IPU_IPU_INT_STAT_2__EMPTY       0x1E000204,0x00000000
+#define IPU_IPU_INT_STAT_2__FULL        0x1E000204,0xffffffff
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_52 0x1E000204,0x00100000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_51 0x1E000204,0x00080000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_50 0x1E000204,0x00040000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_49 0x1E000204,0x00020000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_48 0x1E000204,0x00010000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_47 0x1E000204,0x00008000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_46 0x1E000204,0x00004000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_45 0x1E000204,0x00002000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_44 0x1E000204,0x00001000
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_43 0x1E000204,0x00000800
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_42 0x1E000204,0x00000400
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_41 0x1E000204,0x00000200
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_40 0x1E000204,0x00000100
+#define IPU_IPU_INT_STAT_2__IDMAC_EOF_33 0x1E000204,0x00000002
+
+#define IPU_IPU_INT_STAT_3__ADDR          0x1E000208
+#define IPU_IPU_INT_STAT_3__EMPTY         0x1E000208,0x00000000
+#define IPU_IPU_INT_STAT_3__FULL          0x1E000208,0xffffffff
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_31 0x1E000208,0x80000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_29 0x1E000208,0x20000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_28 0x1E000208,0x10000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_27 0x1E000208,0x08000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_24 0x1E000208,0x01000000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_23 0x1E000208,0x00800000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_22 0x1E000208,0x00400000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_21 0x1E000208,0x00200000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_20 0x1E000208,0x00100000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_18 0x1E000208,0x00040000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_17 0x1E000208,0x00020000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_15 0x1E000208,0x00008000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_14 0x1E000208,0x00004000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_12 0x1E000208,0x00001000
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_11 0x1E000208,0x00000800
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_7  0x1E000208,0x00000080
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_6  0x1E000208,0x00000040
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_5  0x1E000208,0x00000020
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_4  0x1E000208,0x00000010
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_3  0x1E000208,0x00000008
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_2  0x1E000208,0x00000004
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_1  0x1E000208,0x00000002
+#define IPU_IPU_INT_STAT_3__IDMAC_NFACK_0  0x1E000208,0x00000001
+
+#define IPU_IPU_INT_STAT_4__ADDR          0x1E00020C
+#define IPU_IPU_INT_STAT_4__EMPTY         0x1E00020C,0x00000000
+#define IPU_IPU_INT_STAT_4__FULL          0x1E00020C,0xffffffff
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_52 0x1E00020C,0x00100000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_51 0x1E00020C,0x00080000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_50 0x1E00020C,0x00040000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_49 0x1E00020C,0x00020000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_48 0x1E00020C,0x00010000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_47 0x1E00020C,0x00008000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_46 0x1E00020C,0x00004000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_45 0x1E00020C,0x00002000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_44 0x1E00020C,0x00001000
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_43 0x1E00020C,0x00000800
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_42 0x1E00020C,0x00000400
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_41 0x1E00020C,0x00000200
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_40 0x1E00020C,0x00000100
+#define IPU_IPU_INT_STAT_4__IDMAC_NFACK_33 0x1E00020C,0x00000002
+
+#define IPU_IPU_INT_STAT_5__ADDR                0x1E000210
+#define IPU_IPU_INT_STAT_5__EMPTY               0x1E000210,0x00000000
+#define IPU_IPU_INT_STAT_5__FULL                0x1E000210,0xffffffff
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_31 0x1E000210,0x80000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_29 0x1E000210,0x20000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_28 0x1E000210,0x10000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_27 0x1E000210,0x08000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_24 0x1E000210,0x01000000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_23 0x1E000210,0x00800000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_22 0x1E000210,0x00400000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_21 0x1E000210,0x00200000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_20 0x1E000210,0x00100000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_18 0x1E000210,0x00040000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_17 0x1E000210,0x00020000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_15 0x1E000210,0x00008000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_14 0x1E000210,0x00004000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_12 0x1E000210,0x00001000
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_11 0x1E000210,0x00000800
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_7         0x1E000210,0x00000080
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_6         0x1E000210,0x00000040
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_5         0x1E000210,0x00000020
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_4         0x1E000210,0x00000010
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_3         0x1E000210,0x00000008
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_2         0x1E000210,0x00000004
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_1         0x1E000210,0x00000002
+#define IPU_IPU_INT_STAT_5__IDMAC_NFB4EOF_ERR_0         0x1E000210,0x00000001
+
+#define IPU_IPU_INT_STAT_6__ADDR                0x1E000214
+#define IPU_IPU_INT_STAT_6__EMPTY               0x1E000214,0x00000000
+#define IPU_IPU_INT_STAT_6__FULL                0x1E000214,0xffffffff
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_52 0x1E000214,0x00100000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_51 0x1E000214,0x00080000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_50 0x1E000214,0x00040000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_49 0x1E000214,0x00020000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_48 0x1E000214,0x00010000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_47 0x1E000214,0x00008000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_46 0x1E000214,0x00004000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_45 0x1E000214,0x00002000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_44 0x1E000214,0x00001000
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_43 0x1E000214,0x00000800
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_42 0x1E000214,0x00000400
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_41 0x1E000214,0x00000200
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_40 0x1E000214,0x00000100
+#define IPU_IPU_INT_STAT_6__IDMAC_NFB4EOF_ERR_33 0x1E000214,0x00000002
+
+#define IPU_IPU_INT_STAT_7__ADDR        0x1E000218
+#define IPU_IPU_INT_STAT_7__EMPTY       0x1E000218,0x00000000
+#define IPU_IPU_INT_STAT_7__FULL        0x1E000218,0xffffffff
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_31 0x1E000218,0x80000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_29 0x1E000218,0x20000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_28 0x1E000218,0x10000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_27 0x1E000218,0x08000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_24 0x1E000218,0x01000000
+#define IPU_IPU_INT_STAT_7__IDMAC_EOS_23 0x1E000218,0x00800000
+
+#define IPU_IPU_INT_STAT_8__ADDR        0x1E00021C
+#define IPU_IPU_INT_STAT_8__EMPTY       0x1E00021C,0x00000000
+#define IPU_IPU_INT_STAT_8__FULL        0x1E00021C,0xffffffff
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_52 0x1E00021C,0x00100000
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_51 0x1E00021C,0x00080000
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_44 0x1E00021C,0x00001000
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_43 0x1E00021C,0x00000800
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_42 0x1E00021C,0x00000400
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_41 0x1E00021C,0x00000200
+#define IPU_IPU_INT_STAT_8__IDMAC_EOS_32 0x1E00021C,0x00000002
+
+#define IPU_IPU_INT_STAT_9__ADDR            0x1E000220
+#define IPU_IPU_INT_STAT_9__EMPTY           0x1E000220,0x00000000
+#define IPU_IPU_INT_STAT_9__FULL            0x1E000220,0xffffffff
+#define IPU_IPU_INT_STAT_9__CSI1_PUPE       0x1E000220,0x80000000
+#define IPU_IPU_INT_STAT_9__CSI0_PUPE       0x1E000220,0x40000000
+#define IPU_IPU_INT_STAT_9__ISP_PUPE        0x1E000220,0x20000000
+#define IPU_IPU_INT_STAT_9__IC_VF_BUF_OVF    0x1E000220,0x10000000
+#define IPU_IPU_INT_STAT_9__IC_ENC_BUF_OVF   0x1E000220,0x08000000
+#define IPU_IPU_INT_STAT_9__IC_BAYER_BUF_OVF 0x1E000220,0x04000000
+
+#define IPU_IPU_INT_STAT_10__ADDR                  0x1E000224
+#define IPU_IPU_INT_STAT_10__EMPTY                 0x1E000224,0x00000000
+#define IPU_IPU_INT_STAT_10__FULL                  0x1E000224,0xffffffff
+#define IPU_IPU_INT_STAT_10__AXIR_ERR              0x1E000224,0x40000000
+#define IPU_IPU_INT_STAT_10__AXIW_ERR              0x1E000224,0x20000000
+#define IPU_IPU_INT_STAT_10__NON_PRIVILEGED_ACC_ERR 0x1E000224,0x10000000
+#define IPU_IPU_INT_STAT_10__IC_BAYER_FRM_LOST_ERR  0x1E000224,0x04000000
+#define IPU_IPU_INT_STAT_10__IC_ENC_FRM_LOST_ERR    0x1E000224,0x02000000
+#define IPU_IPU_INT_STAT_10__IC_VF_FRM_LOST_ERR            0x1E000224,0x01000000
+#define IPU_IPU_INT_STAT_10__DI1_TIME_OUT_ERR      0x1E000224,0x00400000
+#define IPU_IPU_INT_STAT_10__DI0_TIME_OUT_ERR      0x1E000224,0x00200000
+#define IPU_IPU_INT_STAT_10__DI1_SYNC_DISP_ERR     0x1E000224,0x00100000
+#define IPU_IPU_INT_STAT_10__DI0_SYNC_DISP_ERR     0x1E000224,0x00080000
+#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_6      0x1E000224,0x00040000
+#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_2      0x1E000224,0x00020000
+#define IPU_IPU_INT_STAT_10__DC_TEARING_ERR_1      0x1E000224,0x00010000
+#define IPU_IPU_INT_STAT_10__ISP_RAM_HIST_OF       0x1E000224,0x00000020
+#define IPU_IPU_INT_STAT_10__ISP_RAM_ST_OF         0x1E000224,0x00000010
+#define IPU_IPU_INT_STAT_10__SMFC3_FRM_LOST        0x1E000224,0x00000008
+#define IPU_IPU_INT_STAT_10__SMFC2_FRM_LOST        0x1E000224,0x00000004
+#define IPU_IPU_INT_STAT_10__SMFC1_FRM_LOST        0x1E000224,0x00000002
+#define IPU_IPU_INT_STAT_10__SMFC0_FRM_LOST        0x1E000224,0x00000001
+
+#define IPU_IPU_INT_STAT_11__ADDR          0x1E000228
+#define IPU_IPU_INT_STAT_11__EMPTY         0x1E000228,0x00000000
+#define IPU_IPU_INT_STAT_11__FULL          0x1E000228,0xffffffff
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_22 0x1E000228,0x00400000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_21 0x1E000228,0x00200000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_20 0x1E000228,0x00100000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_12 0x1E000228,0x00001000
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_11 0x1E000228,0x00000800
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_5  0x1E000228,0x00000020
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_3  0x1E000228,0x00000008
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_2  0x1E000228,0x00000004
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_1  0x1E000228,0x00000002
+#define IPU_IPU_INT_STAT_11__IDMAC_EOBND_0  0x1E000228,0x00000001
+
+#define IPU_IPU_INT_STAT_12__ADDR          0x1E00022C
+#define IPU_IPU_INT_STAT_12__EMPTY         0x1E00022C,0x00000000
+#define IPU_IPU_INT_STAT_12__FULL          0x1E00022C,0xffffffff
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_50 0x1E00022C,0x00040000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_49 0x1E00022C,0x00020000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_48 0x1E00022C,0x00010000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_47 0x1E00022C,0x00008000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_46 0x1E00022C,0x00004000
+#define IPU_IPU_INT_STAT_12__IDMAC_EOBND_45 0x1E00022C,0x00002000
+
+#define IPU_IPU_INT_STAT_13__ADDR       0x1E000230
+#define IPU_IPU_INT_STAT_13__EMPTY      0x1E000230,0x00000000
+#define IPU_IPU_INT_STAT_13__FULL       0x1E000230,0xffffffff
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_31 0x1E000230,0x80000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_29 0x1E000230,0x20000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_28 0x1E000230,0x10000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_27 0x1E000230,0x08000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_24 0x1E000230,0x01000000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_23 0x1E000230,0x00800000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_22 0x1E000230,0x00400000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_21 0x1E000230,0x00200000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_20 0x1E000230,0x00100000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_18 0x1E000230,0x00040000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_17 0x1E000230,0x00020000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_15 0x1E000230,0x00008000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_14 0x1E000230,0x00004000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_12 0x1E000230,0x00001000
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_11 0x1E000230,0x00000800
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_7         0x1E000230,0x00000080
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_6         0x1E000230,0x00000040
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_5         0x1E000230,0x00000020
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_4         0x1E000230,0x00000010
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_3         0x1E000230,0x00000008
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_2         0x1E000230,0x00000004
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_1         0x1E000230,0x00000002
+#define IPU_IPU_INT_STAT_13__IDMAC_TH_0         0x1E000230,0x00000001
+
+#define IPU_IPU_INT_STAT_14__ADDR       0x1E000234
+#define IPU_IPU_INT_STAT_14__EMPTY      0x1E000234,0x00000000
+#define IPU_IPU_INT_STAT_14__FULL       0x1E000234,0xffffffff
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_52 0x1E000234,0x00100000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_51 0x1E000234,0x00080000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_50 0x1E000234,0x00040000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_49 0x1E000234,0x00020000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_48 0x1E000234,0x00010000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_47 0x1E000234,0x00008000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_46 0x1E000234,0x00004000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_45 0x1E000234,0x00002000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_44 0x1E000234,0x00001000
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_43 0x1E000234,0x00000800
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_42 0x1E000234,0x00000400
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_41 0x1E000234,0x00000200
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_40 0x1E000234,0x00000100
+#define IPU_IPU_INT_STAT_14__IDMAC_TH_33 0x1E000234,0x00000002
+
+#define IPU_IPU_INT_STAT_15__ADDR               0x1E000238
+#define IPU_IPU_INT_STAT_15__EMPTY              0x1E000238,0x00000000
+#define IPU_IPU_INT_STAT_15__FULL               0x1E000238,0xffffffff
+#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_8   0x1E000238,0x80000000
+#define IPU_IPU_INT_STAT_15__DI1_CNT_EN_PRE_3   0x1E000238,0x40000000
+#define IPU_IPU_INT_STAT_15__DI1_DISP_CLK_EN_PRE 0x1E000238,0x20000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_10  0x1E000238,0x10000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_9   0x1E000238,0x08000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_8   0x1E000238,0x04000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_7   0x1E000238,0x02000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_6   0x1E000238,0x01000000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_5   0x1E000238,0x00800000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_4   0x1E000238,0x00400000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_3   0x1E000238,0x00200000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_2   0x1E000238,0x00100000
+#define IPU_IPU_INT_STAT_15__DI0_CNT_EN_PRE_1   0x1E000238,0x00080000
+#define IPU_IPU_INT_STAT_15__DI0_DISP_CLK_EN_PRE 0x1E000238,0x00040000
+#define IPU_IPU_INT_STAT_15__DC_ASYNC_STOP      0x1E000238,0x00020000
+#define IPU_IPU_INT_STAT_15__DC_DP_START        0x1E000238,0x00010000
+#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_1     0x1E000238,0x00008000
+#define IPU_IPU_INT_STAT_15__DI_VSYNC_PRE_0     0x1E000238,0x00004000
+#define IPU_IPU_INT_STAT_15__DC_FC_6            0x1E000238,0x00002000
+#define IPU_IPU_INT_STAT_15__DC_FC_4            0x1E000238,0x00001000
+#define IPU_IPU_INT_STAT_15__DC_FC_3            0x1E000238,0x00000800
+#define IPU_IPU_INT_STAT_15__DC_FC_2            0x1E000238,0x00000400
+#define IPU_IPU_INT_STAT_15__DC_FC_1            0x1E000238,0x00000200
+#define IPU_IPU_INT_STAT_15__DC_FC_0            0x1E000238,0x00000100
+#define IPU_IPU_INT_STAT_15__DP_ASF_BRAKE       0x1E000238,0x00000080
+#define IPU_IPU_INT_STAT_15__DP_SF_BRAKE        0x1E000238,0x00000040
+#define IPU_IPU_INT_STAT_15__DP_ASF_END                 0x1E000238,0x00000020
+#define IPU_IPU_INT_STAT_15__DP_ASF_START       0x1E000238,0x00000010
+#define IPU_IPU_INT_STAT_15__DP_SF_END          0x1E000238,0x00000008
+#define IPU_IPU_INT_STAT_15__DP_SF_START        0x1E000238,0x00000004
+#define IPU_IPU_INT_STAT_15__IPU_SNOOPING2_INT  0x1E000238,0x00000002
+#define IPU_IPU_INT_STAT_15__IPU_SNOOPING1_INT  0x1E000238,0x00000001
+
+#define IPU_IPU_CUR_BUF_0__ADDR                     0x1E00023C
+#define IPU_IPU_CUR_BUF_0__EMPTY            0x1E00023C,0x00000000
+#define IPU_IPU_CUR_BUF_0__FULL                     0x1E00023C,0xffffffff
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_31 0x1E00023C,0x80000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_29 0x1E00023C,0x20000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_28 0x1E00023C,0x10000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_27 0x1E00023C,0x08000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_24 0x1E00023C,0x01000000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_23 0x1E00023C,0x00800000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_22 0x1E00023C,0x00400000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_21 0x1E00023C,0x00200000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_20 0x1E00023C,0x00100000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_18 0x1E00023C,0x00040000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_17 0x1E00023C,0x00020000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_15 0x1E00023C,0x00008000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_14 0x1E00023C,0x00004000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_12 0x1E00023C,0x00001000
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_11 0x1E00023C,0x00000800
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_7  0x1E00023C,0x00000080
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_6  0x1E00023C,0x00000040
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_5  0x1E00023C,0x00000020
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_4  0x1E00023C,0x00000010
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_3  0x1E00023C,0x00000008
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_2  0x1E00023C,0x00000004
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_1  0x1E00023C,0x00000002
+#define IPU_IPU_CUR_BUF_0__DMA_CH_CUR_BUF_0  0x1E00023C,0x00000001
+
+#define IPU_IPU_CUR_BUF_1__ADDR                     0x1E000240
+#define IPU_IPU_CUR_BUF_1__EMPTY            0x1E000240,0x00000000
+#define IPU_IPU_CUR_BUF_1__FULL                     0x1E000240,0xffffffff
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_52 0x1E000240,0x00100000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_51 0x1E000240,0x00080000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_50 0x1E000240,0x00040000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_49 0x1E000240,0x00020000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_48 0x1E000240,0x00010000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_47 0x1E000240,0x00008000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_46 0x1E000240,0x00004000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_45 0x1E000240,0x00002000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_44 0x1E000240,0x00001000
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_43 0x1E000240,0x00000800
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_42 0x1E000240,0x00000400
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_41 0x1E000240,0x00000200
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_40 0x1E000240,0x00000100
+#define IPU_IPU_CUR_BUF_1__DMA_CH_CUR_BUF_33 0x1E000240,0x00000002
+
+#define IPU_IPU_ALT_CUR_BUF_0__ADDR                 0x1E000244
+#define IPU_IPU_ALT_CUR_BUF_0__EMPTY                0x1E000244,0x00000000
+#define IPU_IPU_ALT_CUR_BUF_0__FULL                 0x1E000244,0xffffffff
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_29 0x1E000244,0x20000000
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_24 0x1E000244,0x01000000
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_7  0x1E000244,0x00000080
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_6  0x1E000244,0x00000040
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_5  0x1E000244,0x00000020
+#define IPU_IPU_ALT_CUR_BUF_0__DMA_CH_ALT_CUR_BUF_4  0x1E000244,0x00000010
+
+#define IPU_IPU_ALT_CUR_BUF_1__ADDR                 0x1E000248
+#define IPU_IPU_ALT_CUR_BUF_1__EMPTY                0x1E000248,0x00000000
+#define IPU_IPU_ALT_CUR_BUF_1__FULL                 0x1E000248,0xffffffff
+#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_52 0x1E000248,0x00100000
+#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_41 0x1E000248,0x00000200
+#define IPU_IPU_ALT_CUR_BUF_1__DMA_CH_ALT_CUR_BUF_33 0x1E000248,0x00000002
+
+#define IPU_IPU_SRM_STAT__ADDR          0x1E00024C
+#define IPU_IPU_SRM_STAT__EMPTY                 0x1E00024C,0x00000000
+#define IPU_IPU_SRM_STAT__FULL          0x1E00024C,0xffffffff
+#define IPU_IPU_SRM_STAT__DI1_SRM_STAT  0x1E00024C,0x00000200
+#define IPU_IPU_SRM_STAT__DI0_SRM_STAT  0x1E00024C,0x00000100
+#define IPU_IPU_SRM_STAT__CSI1_SRM_STAT         0x1E00024C,0x00000080
+#define IPU_IPU_SRM_STAT__CSI0_SRM_STAT         0x1E00024C,0x00000040
+#define IPU_IPU_SRM_STAT__DC_6_SRM_STAT         0x1E00024C,0x00000020
+#define IPU_IPU_SRM_STAT__DC_2_SRM_STAT         0x1E00024C,0x00000010
+#define IPU_IPU_SRM_STAT__ISP_SRM_STAT  0x1E00024C,0x00000008
+#define IPU_IPU_SRM_STAT__DP_A1_SRM_STAT 0x1E00024C,0x00000004
+#define IPU_IPU_SRM_STAT__DP_A0_SRM_STAT 0x1E00024C,0x00000002
+#define IPU_IPU_SRM_STAT__DP_S_SRM_STAT         0x1E00024C,0x00000001
+
+#define IPU_IPU_PROC_TASKS_STAT__ADDR               0x1E000250
+#define IPU_IPU_PROC_TASKS_STAT__EMPTY              0x1E000250,0x00000000
+#define IPU_IPU_PROC_TASKS_STAT__FULL               0x1E000250,0xffffffff
+#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC3_TSTAT 0x1E000250,0x00C00000
+#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC2_TSTAT 0x1E000250,0x00300000
+#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC1_TSTAT 0x1E000250,0x000C0000
+#define IPU_IPU_PROC_TASKS_STAT__CSI2MEM_SMFC0_TSTAT 0x1E000250,0x00030000
+#define IPU_IPU_PROC_TASKS_STAT__MEM2PRP_TSTAT      0x1E000250,0x00007000
+#define IPU_IPU_PROC_TASKS_STAT__PP_ROT_TSTAT       0x1E000250,0x00000C00
+#define IPU_IPU_PROC_TASKS_STAT__VF_ROT_TSTAT       0x1E000250,0x00000300
+#define IPU_IPU_PROC_TASKS_STAT__ENC_ROT_TSTAT      0x1E000250,0x000000C0
+#define IPU_IPU_PROC_TASKS_STAT__PP_TSTAT           0x1E000250,0x00000030
+#define IPU_IPU_PROC_TASKS_STAT__VF_TSTAT           0x1E000250,0x0000000C
+#define IPU_IPU_PROC_TASKS_STAT__ENC_TSTAT          0x1E000250,0x00000003
+
+#define IPU_IPU_DISP_TASKS_STAT__ADDR              0x1E000254
+#define IPU_IPU_DISP_TASKS_STAT__EMPTY             0x1E000254,0x00000000
+#define IPU_IPU_DISP_TASKS_STAT__FULL              0x1E000254,0xffffffff
+#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC2_CUR_FLOW 0x1E000254,0x00000800
+#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC2_STAT            0x1E000254,0x00000700
+#define IPU_IPU_DISP_TASKS_STAT__DC_ASYNC1_STAT            0x1E000254,0x00000030
+#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_CUR_FLOW  0x1E000254,0x00000008
+#define IPU_IPU_DISP_TASKS_STAT__DP_ASYNC_STAT     0x1E000254,0x00000007
+
+#define IPU_IPU_TRB_CUR_BUF_REG0__ADDR                 0x0E000258
+#define IPU_IPU_TRB_CUR_BUF_REG1__ADDR                 0x0E00025C
+#define IPU_IPU_TRB_CUR_BUF_REG2__ADDR                 0x0E000260
+#define IPU_IPU_TRB_CUR_BUF_REG3__ADDR                 0x0E000264
+
+#define IPU_IPU_CH_BUF0_RDY0__ADDR              0x1E000268
+#define IPU_IPU_CH_BUF0_RDY0__EMPTY             0x1E000268,0x00000000
+#define IPU_IPU_CH_BUF0_RDY0__FULL              0x1E000268,0xffffffff
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_31 0x1E000268,0x80000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_29 0x1E000268,0x20000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_28 0x1E000268,0x10000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_27 0x1E000268,0x08000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_24 0x1E000268,0x01000000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_23 0x1E000268,0x00800000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_22 0x1E000268,0x00400000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_21 0x1E000268,0x00200000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_20 0x1E000268,0x00100000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_18 0x1E000268,0x00040000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_17 0x1E000268,0x00020000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_15 0x1E000268,0x00008000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_14 0x1E000268,0x00004000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_12 0x1E000268,0x00001000
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_11 0x1E000268,0x00000800
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_7         0x1E000268,0x00000080
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_6         0x1E000268,0x00000040
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_5         0x1E000268,0x00000020
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_4         0x1E000268,0x00000010
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_3         0x1E000268,0x00000008
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_2         0x1E000268,0x00000004
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_1         0x1E000268,0x00000002
+#define IPU_IPU_CH_BUF0_RDY0__DMA_CH_BUF0_RDY_0         0x1E000268,0x00000001
+
+#define IPU_IPU_CH_BUF0_RDY1__ADDR              0x1E00026C
+#define IPU_IPU_CH_BUF0_RDY1__EMPTY             0x1E00026C,0x00000000
+#define IPU_IPU_CH_BUF0_RDY1__FULL              0x1E00026C,0xffffffff
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_52 0x1E00026C,0x00100000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_51 0x1E00026C,0x00080000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_50 0x1E00026C,0x00040000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_49 0x1E00026C,0x00020000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_48 0x1E00026C,0x00010000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_47 0x1E00026C,0x00008000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_46 0x1E00026C,0x00004000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_45 0x1E00026C,0x00002000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_44 0x1E00026C,0x00001000
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_43 0x1E00026C,0x00000800
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_42 0x1E00026C,0x00000400
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_41 0x1E00026C,0x00000200
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_40 0x1E00026C,0x00000100
+#define IPU_IPU_CH_BUF0_RDY1__DMA_CH_BUF0_RDY_33 0x1E00026C,0x00000002
+
+#define IPU_IPU_CH_BUF1_RDY0__ADDR              0x1E000270
+#define IPU_IPU_CH_BUF1_RDY0__EMPTY             0x1E000270,0x00000000
+#define IPU_IPU_CH_BUF1_RDY0__FULL              0x1E000270,0xffffffff
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_31 0x1E000270,0x80000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_29 0x1E000270,0x20000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_28 0x1E000270,0x10000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_27 0x1E000270,0x08000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_24 0x1E000270,0x01000000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_23 0x1E000270,0x00800000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_22 0x1E000270,0x00400000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_21 0x1E000270,0x00200000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_20 0x1E000270,0x00100000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_18 0x1E000270,0x00040000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_17 0x1E000270,0x00020000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_15 0x1E000270,0x00008000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_14 0x1E000270,0x00004000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_12 0x1E000270,0x00001000
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_11 0x1E000270,0x00000800
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_7         0x1E000270,0x00000080
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_6         0x1E000270,0x00000040
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_5         0x1E000270,0x00000020
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_4         0x1E000270,0x00000010
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_3         0x1E000270,0x00000008
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_2         0x1E000270,0x00000004
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_1         0x1E000270,0x00000002
+#define IPU_IPU_CH_BUF1_RDY0__DMA_CH_BUF1_RDY_0         0x1E000270,0x00000001
+
+#define IPU_IPU_CH_BUF1_RDY1__ADDR              0x1E000274
+#define IPU_IPU_CH_BUF1_RDY1__EMPTY             0x1E000274,0x00000000
+#define IPU_IPU_CH_BUF1_RDY1__FULL              0x1E000274,0xffffffff
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_52 0x1E000274,0x00100000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_51 0x1E000274,0x00080000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_50 0x1E000274,0x00040000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_49 0x1E000274,0x00020000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_48 0x1E000274,0x00010000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_47 0x1E000274,0x00008000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_46 0x1E000274,0x00004000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_45 0x1E000274,0x00002000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_44 0x1E000274,0x00001000
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_43 0x1E000274,0x00000800
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_42 0x1E000274,0x00000400
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_41 0x1E000274,0x00000200
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_40 0x1E000274,0x00000100
+#define IPU_IPU_CH_BUF1_RDY1__DMA_CH_BUF1_RDY_33 0x1E000274,0x00000002
+
+#define IPU_IPU_ALT_CH_BUF0_RDY0__ADDR                  0x1E000278
+#define IPU_IPU_ALT_CH_BUF0_RDY0__EMPTY                         0x1E000278,0x00000000
+#define IPU_IPU_ALT_CH_BUF0_RDY0__FULL                  0x1E000278,0xffffffff
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_29 0x1E000278,0x20000000
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_24 0x1E000278,0x01000000
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_7         0x1E000278,0x00000080
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_6         0x1E000278,0x00000040
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_5         0x1E000278,0x00000020
+#define IPU_IPU_ALT_CH_BUF0_RDY0__DMA_CH_ALT_BUF0_RDY_4         0x1E000278,0x00000010
+
+#define IPU_IPU_ALT_CH_BUF0_RDY1__ADDR                  0x1E00027C
+#define IPU_IPU_ALT_CH_BUF0_RDY1__EMPTY                         0x1E00027C,0x00000000
+#define IPU_IPU_ALT_CH_BUF0_RDY1__FULL                  0x1E00027C,0xffffffff
+#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_52 0x1E00027C,0x00100000
+#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_41 0x1E00027C,0x00000200
+#define IPU_IPU_ALT_CH_BUF0_RDY1__DMA_CH_ALT_BUF0_RDY_33 0x1E00027C,0x00000002
+
+#define IPU_IPU_ALT_CH_BUF1_RDY0__ADDR                  0x1E000280
+#define IPU_IPU_ALT_CH_BUF1_RDY0__EMPTY                         0x1E000280,0x00000000
+#define IPU_IPU_ALT_CH_BUF1_RDY0__FULL                  0x1E000280,0xffffffff
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_29 0x1E000280,0x20000000
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_24 0x1E000280,0x01000000
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_7         0x1E000280,0x00000080
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_6         0x1E000280,0x00000040
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_5         0x1E000280,0x00000020
+#define IPU_IPU_ALT_CH_BUF1_RDY0__DMA_CH_ALT_BUF1_RDY_4         0x1E000280,0x00000010
+
+#define IPU_IPU_ALT_CH_BUF1_RDY1__ADDR                  0x1E000284
+#define IPU_IPU_ALT_CH_BUF1_RDY1__EMPTY                         0x1E000284,0x00000000
+#define IPU_IPU_ALT_CH_BUF1_RDY1__FULL                  0x1E000284,0xffffffff
+#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_52 0x1E000284,0x00100000
+#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_41 0x1E000284,0x00000200
+#define IPU_IPU_ALT_CH_BUF1_RDY1__DMA_CH_ALT_BUF1_RDY_33 0x1E000284,0x00000002
+
+#define IPU_IPU_CH_BUF2_RDY0__ADDR              0x1E000288
+#define IPU_IPU_CH_BUF2_RDY1__ADDR              0x1E00028C
+
+// ================== End of IPUV3EX Status Registers ======================
+
+// ================= Start of IPUV3EX IDMAC Registers =====================
+#define IPU_IDMAC_CONF__ADDR        0x1E008000
+#define IPU_IDMAC_CONF__EMPTY       0x1E008000,0x00000000
+#define IPU_IDMAC_CONF__FULL        0x1E008000,0xffffffff
+#define IPU_IDMAC_CONF__P_ENDIAN     0x1E008000,0x00010000
+#define IPU_IDMAC_CONF__RDI         0x1E008000,0x00000020
+#define IPU_IDMAC_CONF__WIDPT       0x1E008000,0x00000018
+#define IPU_IDMAC_CONF__MAX_REQ_READ 0x1E008000,0x00000007
+
+#define IPU_IDMAC_CH_EN_1__ADDR                  0x1E008004
+#define IPU_IDMAC_CH_EN_1__EMPTY         0x1E008004,0x00000000
+#define IPU_IDMAC_CH_EN_1__FULL                  0x1E008004,0xffffffff
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_31 0x1E008004,0x80000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_29 0x1E008004,0x20000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_28 0x1E008004,0x10000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_27 0x1E008004,0x08000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_24 0x1E008004,0x01000000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_23 0x1E008004,0x00800000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_22 0x1E008004,0x00400000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_21 0x1E008004,0x00200000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_20 0x1E008004,0x00100000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_18 0x1E008004,0x00040000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_17 0x1E008004,0x00020000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_15 0x1E008004,0x00008000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_14 0x1E008004,0x00004000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_12 0x1E008004,0x00001000
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_11 0x1E008004,0x00000800
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_7  0x1E008004,0x00000080
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_6  0x1E008004,0x00000040
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_5  0x1E008004,0x00000020
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_4  0x1E008004,0x00000010
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_3  0x1E008004,0x00000008
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_2  0x1E008004,0x00000004
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_1  0x1E008004,0x00000002
+#define IPU_IDMAC_CH_EN_1__IDMAC_CH_EN_0  0x1E008004,0x00000001
+
+#define IPU_IDMAC_CH_EN_2__ADDR                  0x1E008008
+#define IPU_IDMAC_CH_EN_2__EMPTY         0x1E008008,0x00000000
+#define IPU_IDMAC_CH_EN_2__FULL                  0x1E008008,0xffffffff
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_52 0x1E008008,0x00100000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_51 0x1E008008,0x00080000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_50 0x1E008008,0x00040000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_49 0x1E008008,0x00020000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_48 0x1E008008,0x00010000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_47 0x1E008008,0x00008000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_46 0x1E008008,0x00004000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_45 0x1E008008,0x00002000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_44 0x1E008008,0x00001000
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_43 0x1E008008,0x00000800
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_42 0x1E008008,0x00000400
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_41 0x1E008008,0x00000200
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_40 0x1E008008,0x00000100
+#define IPU_IDMAC_CH_EN_2__IDMAC_CH_EN_33 0x1E008008,0x00000002
+
+#define IPU_IDMAC_SEP_ALPHA__ADDR           0x1E00800C
+#define IPU_IDMAC_SEP_ALPHA__EMPTY          0x1E00800C,0x00000000
+#define IPU_IDMAC_SEP_ALPHA__FULL           0x1E00800C,0xffffffff
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29 0x1E00800C,0x20000000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27 0x1E00800C,0x08000000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24 0x1E00800C,0x01000000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23 0x1E00800C,0x00800000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15 0x1E00800C,0x00008000
+#define IPU_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14 0x1E00800C,0x00004000
+
+#define IPU_IDMAC_ALT_SEP_ALPHA__ADDR               0x1E008010
+#define IPU_IDMAC_ALT_SEP_ALPHA__EMPTY              0x1E008010,0x00000000
+#define IPU_IDMAC_ALT_SEP_ALPHA__FULL               0x1E008010,0xffffffff
+#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29 0x1E008010,0x20000000
+#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24 0x1E008010,0x01000000
+#define IPU_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23 0x1E008010,0x00800000
+
+#define IPU_IDMAC_CH_PRI_1__ADDR           0x1E008014
+#define IPU_IDMAC_CH_PRI_1__EMPTY          0x1E008014,0x00000000
+#define IPU_IDMAC_CH_PRI_1__FULL           0x1E008014,0xffffffff
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29 0x1E008014,0x20000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28 0x1E008014,0x10000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27 0x1E008014,0x08000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24 0x1E008014,0x01000000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23 0x1E008014,0x00800000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22 0x1E008014,0x00400000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21 0x1E008014,0x00200000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20 0x1E008014,0x00100000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15 0x1E008014,0x00008000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14 0x1E008014,0x00004000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12 0x1E008014,0x00001000
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11 0x1E008014,0x00000800
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_7  0x1E008014,0x00000080
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_6  0x1E008014,0x00000040
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_5  0x1E008014,0x00000020
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_4  0x1E008014,0x00000010
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_3  0x1E008014,0x00000008
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_2  0x1E008014,0x00000004
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_1  0x1E008014,0x00000002
+#define IPU_IDMAC_CH_PRI_1__IDMAC_CH_PRI_0  0x1E008014,0x00000001
+
+#define IPU_IDMAC_CH_PRI_2__ADDR           0x1E008018
+#define IPU_IDMAC_CH_PRI_2__EMPTY          0x1E008018,0x00000000
+#define IPU_IDMAC_CH_PRI_2__FULL           0x1E008018,0xffffffff
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50 0x1E008018,0x00040000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49 0x1E008018,0x00020000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48 0x1E008018,0x00010000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47 0x1E008018,0x00008000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46 0x1E008018,0x00004000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45 0x1E008018,0x00002000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44 0x1E008018,0x00001000
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43 0x1E008018,0x00000800
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42 0x1E008018,0x00000400
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41 0x1E008018,0x00000200
+#define IPU_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40 0x1E008018,0x00000100
+
+#define IPU_IDMAC_WM_EN_1__ADDR                  0x1E00801C
+#define IPU_IDMAC_WM_EN_1__EMPTY         0x1E00801C,0x00000000
+#define IPU_IDMAC_WM_EN_1__FULL                  0x1E00801C,0xffffffff
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_29 0x1E00801C,0x20000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_28 0x1E00801C,0x10000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_27 0x1E00801C,0x08000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_24 0x1E00801C,0x01000000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_23 0x1E00801C,0x00800000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_14 0x1E00801C,0x00004000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_12 0x1E00801C,0x00001000
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_3  0x1E00801C,0x00000008
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_2  0x1E00801C,0x00000004
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_1  0x1E00801C,0x00000002
+#define IPU_IDMAC_WM_EN_1__IDMAC_WM_EN_0  0x1E00801C,0x00000001
+
+#define IPU_IDMAC_WM_EN_2__ADDR                  0x1E008020
+#define IPU_IDMAC_WM_EN_2__EMPTY         0x1E008020,0x00000000
+#define IPU_IDMAC_WM_EN_2__FULL                  0x1E008020,0xffffffff
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_44 0x1E008020,0x00001000
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_43 0x1E008020,0x00000800
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_42 0x1E008020,0x00000400
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_41 0x1E008020,0x00000200
+#define IPU_IDMAC_WM_EN_2__IDMAC_WM_EN_40 0x1E008020,0x00000100
+
+#define IPU_IDMAC_LOCK_EN_1__ADDR            0x1E008024
+
+#define IPU_IDMAC_LOCK_EN_2__ADDR            0x1E008028
+#define IPU_IDMAC_LOCK_EN_2__EMPTY           0x1E008028,0x00000000
+#define IPU_IDMAC_LOCK_EN_2__FULL            0x1E008028,0xffffffff
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50 0x1E008028,0x00040000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49 0x1E008028,0x00020000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48 0x1E008028,0x00010000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47 0x1E008028,0x00008000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46 0x1E008028,0x00004000
+#define IPU_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45 0x1E008028,0x00002000
+
+#define IPU_IDMAC_SUB_ADDR_0__ADDR            0x1E00802C
+#define IPU_IDMAC_SUB_ADDR_0__EMPTY           0x1E00802C,0x00000000
+#define IPU_IDMAC_SUB_ADDR_0__FULL            0x1E00802C,0xffffffff
+#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_7 0x1E00802C,0x7F000000
+#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_6 0x1E00802C,0x007F0000
+#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_5 0x1E00802C,0x00007F00
+#define IPU_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_4 0x1E00802C,0x0000007F
+
+#define IPU_IDMAC_SUB_ADDR_1__ADDR             0x1E008030
+#define IPU_IDMAC_SUB_ADDR_1__EMPTY            0x1E008030,0x00000000
+#define IPU_IDMAC_SUB_ADDR_1__FULL             0x1E008030,0xffffffff
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33 0x1E008030,0x7F000000
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29 0x1E008030,0x007F0000
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24 0x1E008030,0x00007F00
+#define IPU_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23 0x1E008030,0x0000007F
+
+#define IPU_IDMAC_SUB_ADDR_2__ADDR             0x1E008034
+#define IPU_IDMAC_SUB_ADDR_2__EMPTY            0x1E008034,0x00000000
+#define IPU_IDMAC_SUB_ADDR_2__FULL             0x1E008034,0xffffffff
+#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52 0x1E008034,0x007F0000
+#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51 0x1E008034,0x00007F00
+#define IPU_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41 0x1E008034,0x0000007F
+
+#define IPU_IDMAC_SUB_ADDR_3__ADDR             0x1E008038
+#define IPU_IDMAC_SUB_ADDR_4__ADDR             0x1E00803C
+
+#define IPU_IDMAC_BNDM_EN_1__ADDR            0x1E008040
+#define IPU_IDMAC_BNDM_EN_1__EMPTY           0x1E008040,0x00000000
+#define IPU_IDMAC_BNDM_EN_1__FULL            0x1E008040,0xffffffff
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22 0x1E008040,0x00400000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21 0x1E008040,0x00200000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20 0x1E008040,0x00100000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12 0x1E008040,0x00001000
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11 0x1E008040,0x00000800
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_5  0x1E008040,0x00000020
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_3  0x1E008040,0x00000008
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_2  0x1E008040,0x00000004
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_1  0x1E008040,0x00000002
+#define IPU_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_0  0x1E008040,0x00000001
+
+#define IPU_IDMAC_BNDM_EN_2__ADDR            0x1E008044
+#define IPU_IDMAC_BNDM_EN_2__EMPTY           0x1E008044,0x00000000
+#define IPU_IDMAC_BNDM_EN_2__FULL            0x1E008044,0xffffffff
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50 0x1E008044,0x00040000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49 0x1E008044,0x00020000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48 0x1E008044,0x00010000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47 0x1E008044,0x00008000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46 0x1E008044,0x00004000
+#define IPU_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45 0x1E008044,0x00002000
+
+#define IPU_IDMAC_SC_CORD__ADDR         0x1E008048
+#define IPU_IDMAC_SC_CORD__EMPTY 0x1E008048,0x00000000
+#define IPU_IDMAC_SC_CORD__FULL         0x1E008048,0xffffffff
+#define IPU_IDMAC_SC_CORD__SX0  0x1E008048,0x0FFF0000
+#define IPU_IDMAC_SC_CORD__SY0  0x1E008048,0x000007FF
+
+#define IPU_IDMAC_SC_CORD2__ADDR  0x1E00804C
+
+#define IPU_IDMAC_CH_BUSY_1__ADDR            0x1E008100
+#define IPU_IDMAC_CH_BUSY_1__EMPTY           0x1E008100,0x00000000
+#define IPU_IDMAC_CH_BUSY_1__FULL            0x1E008100,0xffffffff
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_31 0x1E008100,0x80000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_29 0x1E008100,0x20000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_28 0x1E008100,0x10000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_27 0x1E008100,0x08000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_24 0x1E008100,0x01000000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_23 0x1E008100,0x00800000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_22 0x1E008100,0x00400000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_21 0x1E008100,0x00200000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_20 0x1E008100,0x00100000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_18 0x1E008100,0x00040000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_17 0x1E008100,0x00020000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_15 0x1E008100,0x00008000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_14 0x1E008100,0x00004000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_12 0x1E008100,0x00001000
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_11 0x1E008100,0x00000800
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_7  0x1E008100,0x00000080
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_6  0x1E008100,0x00000040
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_5  0x1E008100,0x00000020
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_4  0x1E008100,0x00000010
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_3  0x1E008100,0x00000008
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_2  0x1E008100,0x00000004
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_1  0x1E008100,0x00000002
+#define IPU_IDMAC_CH_BUSY_1__IDMAC_CH_BUSY_0  0x1E008100,0x00000001
+
+#define IPU_IDMAC_CH_BUSY_2__ADDR            0x1E008104
+#define IPU_IDMAC_CH_BUSY_2__EMPTY           0x1E008104,0x00000000
+#define IPU_IDMAC_CH_BUSY_2__FULL            0x1E008104,0xffffffff
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_52 0x1E008104,0x00100000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_51 0x1E008104,0x00080000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_50 0x1E008104,0x00040000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_49 0x1E008104,0x00020000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_48 0x1E008104,0x00010000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_47 0x1E008104,0x00008000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_46 0x1E008104,0x00004000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_45 0x1E008104,0x00002000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_44 0x1E008104,0x00001000
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_43 0x1E008104,0x00000800
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_42 0x1E008104,0x00000400
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_41 0x1E008104,0x00000200
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_40 0x1E008104,0x00000100
+#define IPU_IDMAC_CH_BUSY_2__IDMAC_CH_BUSY_33 0x1E008104,0x00000002
+
+// ================== End of IPUV3EX IDMAC Registers ======================
+
+// ================= Start of IPUV3EX ISP Registers =====================
+#define IPU_ISP_C0__ADDR             0x1E010000
+#define IPU_ISP_C0__EMPTY            0x1E010000,0x00000000
+#define IPU_ISP_C0__FULL             0x1E010000,0xffffffff
+#define IPU_ISP_C0__ISP_BURST_SIZE    0x1E010000,0x001C0000
+#define IPU_ISP_C0__ISP_RED_ROW_BEGIN 0x1E010000,0x00020000
+#define IPU_ISP_C0__ISP_GREEN_P_BEGIN 0x1E010000,0x00010000
+#define IPU_ISP_C0__LINEARCCM_ON      0x1E010000,0x00004000
+#define IPU_ISP_C0__LLF_G_EN         0x1E010000,0x00002000
+#define IPU_ISP_C0__LLF_RB_EN        0x1E010000,0x00001000
+#define IPU_ISP_C0__AD_EN            0x1E010000,0x00000800
+#define IPU_ISP_C0__STS_EN           0x1E010000,0x00000400
+#define IPU_ISP_C0__CL_EN            0x1E010000,0x00000200
+#define IPU_ISP_C0__CS_EN            0x1E010000,0x00000100
+#define IPU_ISP_C0__CCA_EN           0x1E010000,0x00000080
+#define IPU_ISP_C0__HFE_EN           0x1E010000,0x00000040
+#define IPU_ISP_C0__CNS_EN           0x1E010000,0x00000020
+#define IPU_ISP_C0__MTF_ROC_EN       0x1E010000,0x00000010
+#define IPU_ISP_C0__GAMMA_EN         0x1E010000,0x00000008
+#define IPU_ISP_C0__CROC_EN          0x1E010000,0x00000004
+#define IPU_ISP_C0__TBPR_EN          0x1E010000,0x00000002
+#define IPU_ISP_C0__BPR_EN           0x1E010000,0x00000001
+
+#define IPU_ISP_C1__ADDR            0x1E010004
+#define IPU_ISP_C1__EMPTY           0x1E010004,0x00000000
+#define IPU_ISP_C1__FULL            0x1E010004,0xffffffff
+#define IPU_ISP_C1__YUV_EN          0x1E010004,0x20000000
+#define IPU_ISP_C1__CSC_SAT_MODE     0x1E010004,0x10000000
+#define IPU_ISP_C1__BOTTOM_CROP             0x1E010004,0x0E000000
+#define IPU_ISP_C1__TOP_CROP        0x1E010004,0x01C00000
+#define IPU_ISP_C1__RIGHT_CROP      0x1E010004,0x00380000
+#define IPU_ISP_C1__LEFT_CROP       0x1E010004,0x00070000
+#define IPU_ISP_C1__MTF_ROC_SH_M     0x1E010004,0x00006000
+#define IPU_ISP_C1__MTF_ROC_SH_N     0x1E010004,0x00001800
+#define IPU_ISP_C1__MTF_ROC_SH_QA    0x1E010004,0x00000700
+#define IPU_ISP_C1__MTF_ROC_SH_SHARP 0x1E010004,0x000000E0
+#define IPU_ISP_C1__WIDEASPECT      0x1E010004,0x00000010
+#define IPU_ISP_C1__APP_SEL         0x1E010004,0x0000000C
+#define IPU_ISP_C1__INT_MODE        0x1E010004,0x00000003
+
+#define IPU_ISP_FS__ADDR    0x1E010008
+#define IPU_ISP_FS__EMPTY   0x1E010008,0x00000000
+#define IPU_ISP_FS__FULL    0x1E010008,0xffffffff
+#define IPU_ISP_FS__FWIDTH  0x1E010008,0x0FFF0000
+#define IPU_ISP_FS__FHEIGHT 0x1E010008,0x00000FFF
+
+#define IPU_ISP_BI__ADDR   0x1E01000C
+#define IPU_ISP_BI__EMPTY  0x1E01000C,0x00000000
+#define IPU_ISP_BI__FULL   0x1E01000C,0xffffffff
+#define IPU_ISP_BI__HBLANK 0x1E01000C,0x0FFF0000
+#define IPU_ISP_BI__VBLANK 0x1E01000C,0x00000FFF
+
+#define IPU_ISP_OCO__ADDR    0x1E010010
+#define IPU_ISP_OCO__EMPTY   0x1E010010,0x00000000
+#define IPU_ISP_OCO__FULL    0x1E010010,0xffffffff
+#define IPU_ISP_OCO__HOFFSET 0x1E010010,0x1FFF0000
+#define IPU_ISP_OCO__VOFFSET 0x1E010010,0x00001FFF
+
+#define IPU_ISP_BPR1__ADDR  0x1E010014
+#define IPU_ISP_BPR1__EMPTY 0x1E010014,0x00000000
+#define IPU_ISP_BPR1__FULL  0x1E010014,0xffffffff
+#define IPU_ISP_BPR1__TB    0x1E010014,0xFF000000
+#define IPU_ISP_BPR1__TDR   0x1E010014,0x00FF0000
+#define IPU_ISP_BPR1__TR    0x1E010014,0x0000FF00
+#define IPU_ISP_BPR1__DKR   0x1E010014,0x000000FF
+
+#define IPU_ISP_BPR2__ADDR  0x1E010018
+#define IPU_ISP_BPR2__EMPTY 0x1E010018,0x00000000
+#define IPU_ISP_BPR2__FULL  0x1E010018,0xffffffff
+#define IPU_ISP_BPR2__BRB   0x1E010018,0xFF000000
+#define IPU_ISP_BPR2__TT    0x1E010018,0x00FF0000
+#define IPU_ISP_BPR2__TVDB  0x1E010018,0x0000FF00
+#define IPU_ISP_BPR2__TDB   0x1E010018,0x000000FF
+
+#define IPU_ISP_BPR3__ADDR  0x1E01001C
+#define IPU_ISP_BPR3__EMPTY 0x1E01001C,0x00000000
+#define IPU_ISP_BPR3__FULL  0x1E01001C,0xffffffff
+#define IPU_ISP_BPR3__TG    0x1E01001C,0xFF000000
+#define IPU_ISP_BPR3__TGF   0x1E01001C,0x00FF0000
+#define IPU_ISP_BPR3__DKB   0x1E01001C,0x0000FF00
+#define IPU_ISP_BPR3__TG2   0x1E01001C,0x000000FF
+
+#define IPU_ISP_BPR4__ADDR  0x1E010020
+#define IPU_ISP_BPR4__EMPTY 0x1E010020,0x00000000
+#define IPU_ISP_BPR4__FULL  0x1E010020,0xffffffff
+#define IPU_ISP_BPR4__DKRCL 0x1E010020,0xFF000000
+#define IPU_ISP_BPR4__TGFCL 0x1E010020,0x00FF0000
+#define IPU_ISP_BPR4__TCL2  0x1E010020,0x0000FF00
+#define IPU_ISP_BPR4__TCL   0x1E010020,0x000000FF
+
+#define IPU_ISP_BPR5__ADDR  0x1E010024
+#define IPU_ISP_BPR5__EMPTY 0x1E010024,0x00000000
+#define IPU_ISP_BPR5__FULL  0x1E010024,0xffffffff
+#define IPU_ISP_BPR5__TGL2  0x1E010024,0x0000FF00
+#define IPU_ISP_BPR5__TBC   0x1E010024,0x000000FF
+
+#define IPU_ISP_CCMLIN0__ADDR    0x1E010028
+#define IPU_ISP_CCMLIN0__EMPTY   0x1E010028,0x00000000
+#define IPU_ISP_CCMLIN0__FULL    0x1E010028,0xffffffff
+#define IPU_ISP_CCMLIN0__CCMLIN12 0x1E010028,0x7C000000
+#define IPU_ISP_CCMLIN0__CCMLIN11 0x1E010028,0x03E00000
+#define IPU_ISP_CCMLIN0__CCMLIN10 0x1E010028,0x001F0000
+#define IPU_ISP_CCMLIN0__CCMLIN02 0x1E010028,0x00007C00
+#define IPU_ISP_CCMLIN0__CCMLIN01 0x1E010028,0x000003E0
+#define IPU_ISP_CCMLIN0__CCMLIN00 0x1E010028,0x0000001F
+
+#define IPU_ISP_CCMLIN1__ADDR    0x1E01002C
+#define IPU_ISP_CCMLIN1__EMPTY   0x1E01002C,0x00000000
+#define IPU_ISP_CCMLIN1__FULL    0x1E01002C,0xffffffff
+#define IPU_ISP_CCMLIN1__CCMLIN22 0x1E01002C,0x00007C00
+#define IPU_ISP_CCMLIN1__CCMLIN21 0x1E01002C,0x000003E0
+#define IPU_ISP_CCMLIN1__CCMLIN20 0x1E01002C,0x0000001F
+
+#define IPU_ISP_CG_0__ADDR   0x1E010030
+#define IPU_ISP_CG_0__EMPTY  0x1E010030,0x00000000
+#define IPU_ISP_CG_0__FULL   0x1E010030,0xffffffff
+#define IPU_ISP_CG_0__BGAIN  0x1E010030,0xFF000000
+#define IPU_ISP_CG_0__GBGAIN 0x1E010030,0x00FF0000
+#define IPU_ISP_CG_0__GRGAIN 0x1E010030,0x0000FF00
+#define IPU_ISP_CG_0__RGAIN  0x1E010030,0x000000FF
+
+#define IPU_ISP_CG_1__ADDR   0x1E010034
+#define IPU_ISP_CG_1__EMPTY  0x1E010034,0x00000000
+#define IPU_ISP_CG_1__FULL   0x1E010034,0xffffffff
+#define IPU_ISP_CG_1__BSHIFT 0x1E010034,0x00000030
+#define IPU_ISP_CG_1__GSHIFT 0x1E010034,0x0000000C
+#define IPU_ISP_CG_1__RSHIFT 0x1E010034,0x00000003
+
+#define IPU_ISP_ROC_0__ADDR        0x1E010038
+#define IPU_ISP_ROC_0__EMPTY       0x1E010038,0x00000000
+#define IPU_ISP_ROC_0__FULL        0x1E010038,0xffffffff
+#define IPU_ISP_ROC_0__CROC_Q_BLIN  0x1E010038,0x01C00000
+#define IPU_ISP_ROC_0__CROC_Q_GLIN  0x1E010038,0x00380000
+#define IPU_ISP_ROC_0__CROC_Q_RLIN  0x1E010038,0x00070000
+#define IPU_ISP_ROC_0__CROC_SH_QR   0x1E010038,0x00007000
+#define IPU_ISP_ROC_0__CROC_SH_QRGB 0x1E010038,0x00000E00
+#define IPU_ISP_ROC_0__CROC_SH_QB   0x1E010038,0x000001C0
+#define IPU_ISP_ROC_0__CROC_R_APP   0x1E010038,0x00000030
+#define IPU_ISP_ROC_0__CROC_G_APP   0x1E010038,0x0000000C
+#define IPU_ISP_ROC_0__CROC_B_APP   0x1E010038,0x00000003
+
+#define IPU_ISP_ROC_1__ADDR    0x1E01003C
+#define IPU_ISP_ROC_1__EMPTY   0x1E01003C,0x00000000
+#define IPU_ISP_ROC_1__FULL    0x1E01003C,0xffffffff
+#define IPU_ISP_ROC_1__CROC_MYB 0x1E01003C,0xFF000000
+#define IPU_ISP_ROC_1__CROC_MXB 0x1E01003C,0x00FF0000
+#define IPU_ISP_ROC_1__CROC_MYG 0x1E01003C,0x0000FF00
+#define IPU_ISP_ROC_1__CROC_MXG 0x1E01003C,0x000000FF
+
+#define IPU_ISP_ROC_2__ADDR    0x1E010040
+#define IPU_ISP_ROC_2__EMPTY   0x1E010040,0x00000000
+#define IPU_ISP_ROC_2__FULL    0x1E010040,0xffffffff
+#define IPU_ISP_ROC_2__CROC_MYR 0x1E010040,0x0000FF00
+#define IPU_ISP_ROC_2__CROC_MXR 0x1E010040,0x000000FF
+
+#define IPU_ISP_ROC_3__ADDR    0x1E010044
+
+/*not all IPS regs defined here*/
+// ================= End of IPUV3EX ISP Registers =====================
+
+// ================= Start of IPUV3EX DP Registers =====================
+#define IPU_DP_COM_CONF_SYNC__ADDR                    0x1E018000
+#define IPU_DP_COM_CONF_SYNC__EMPTY                   0x1E018000,0x00000000
+#define IPU_DP_COM_CONF_SYNC__FULL                    0x1E018000,0xffffffff
+#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC     0x1E018000,0x00002000
+#define IPU_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC        0x1E018000,0x00001000
+#define IPU_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1E018000,0x00000800
+#define IPU_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1E018000,0x00000400
+#define IPU_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC         0x1E018000,0x00000300
+#define IPU_DP_COM_CONF_SYNC__DP_COC_SYNC             0x1E018000,0x00000070
+#define IPU_DP_COM_CONF_SYNC__DP_GWCKE_SYNC           0x1E018000,0x00000008
+#define IPU_DP_COM_CONF_SYNC__DP_GWAM_SYNC            0x1E018000,0x00000004
+#define IPU_DP_COM_CONF_SYNC__DP_GWSEL_SYNC           0x1E018000,0x00000002
+#define IPU_DP_COM_CONF_SYNC__DP_FG_EN_SYNC           0x1E018000,0x00000001
+
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__ADDR         0x1E018004
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__EMPTY        0x1E018004,0x00000000
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__FULL         0x1E018004,0xffffffff
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC  0x1E018004,0xFF000000
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1E018004,0x00FF0000
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1E018004,0x0000FF00
+#define IPU_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1E018004,0x000000FF
+
+#define IPU_DP_FG_POS_SYNC__ADDR        0x1E018008
+#define IPU_DP_FG_POS_SYNC__EMPTY       0x1E018008,0x00000000
+#define IPU_DP_FG_POS_SYNC__FULL        0x1E018008,0xffffffff
+#define IPU_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1E018008,0x07FF0000
+#define IPU_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1E018008,0x000007FF
+
+#define IPU_DP_CUR_POS_SYNC__ADDR       0x1E01800C
+#define IPU_DP_CUR_POS_SYNC__EMPTY      0x1E01800C,0x00000000
+#define IPU_DP_CUR_POS_SYNC__FULL       0x1E01800C,0xffffffff
+#define IPU_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1E01800C,0xF8000000
+#define IPU_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1E01800C,0x07FF0000
+#define IPU_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1E01800C,0x0000F800
+#define IPU_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1E01800C,0x000007FF
+
+#define IPU_DP_CUR_MAP_SYNC__ADDR             0x1E018010
+#define IPU_DP_CUR_MAP_SYNC__EMPTY            0x1E018010,0x00000000
+#define IPU_DP_CUR_MAP_SYNC__FULL             0x1E018010,0xffffffff
+#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1E018010,0x00FF0000
+#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1E018010,0x0000FF00
+#define IPU_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1E018010,0x000000FF
+
+#define IPU_DP_GAMMA_C_SYNC_0__ADDR             0x1E018014
+#define IPU_DP_GAMMA_C_SYNC_0__EMPTY            0x1E018014,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_0__FULL             0x1E018014,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1E018014,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1E018014,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_1__ADDR             0x1E018018
+#define IPU_DP_GAMMA_C_SYNC_1__EMPTY            0x1E018018,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_1__FULL             0x1E018018,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1E018018,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1E018018,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_2__ADDR             0x1E01801C
+#define IPU_DP_GAMMA_C_SYNC_2__EMPTY            0x1E01801C,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_2__FULL             0x1E01801C,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1E01801C,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1E01801C,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_3__ADDR             0x1E018020
+#define IPU_DP_GAMMA_C_SYNC_3__EMPTY            0x1E018020,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_3__FULL             0x1E018020,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1E018020,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1E018020,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_4__ADDR             0x1E018024
+#define IPU_DP_GAMMA_C_SYNC_4__EMPTY            0x1E018024,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_4__FULL             0x1E018024,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1E018024,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1E018024,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_5__ADDR              0x1E018028
+#define IPU_DP_GAMMA_C_SYNC_5__EMPTY             0x1E018028,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_5__FULL              0x1E018028,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1E018028,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1E018028,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_6__ADDR              0x1E01802C
+#define IPU_DP_GAMMA_C_SYNC_6__EMPTY             0x1E01802C,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_6__FULL              0x1E01802C,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1E01802C,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1E01802C,0x000001FF
+
+#define IPU_DP_GAMMA_C_SYNC_7__ADDR              0x1E018030
+#define IPU_DP_GAMMA_C_SYNC_7__EMPTY             0x1E018030,0x00000000
+#define IPU_DP_GAMMA_C_SYNC_7__FULL              0x1E018030,0xffffffff
+#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1E018030,0x01FF0000
+#define IPU_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1E018030,0x000001FF
+
+#define IPU_DP_GAMMA_S_SYNC_0__ADDR             0x1E018034
+#define IPU_DP_GAMMA_S_SYNC_0__EMPTY            0x1E018034,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_0__FULL             0x1E018034,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1E018034,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1E018034,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1E018034,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1E018034,0x000000FF
+
+#define IPU_DP_GAMMA_S_SYNC_1__ADDR             0x1E018038
+#define IPU_DP_GAMMA_S_SYNC_1__EMPTY            0x1E018038,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_1__FULL             0x1E018038,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1E018038,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1E018038,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1E018038,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1E018038,0x000000FF
+
+#define IPU_DP_GAMMA_S_SYNC_2__ADDR              0x1E01803C
+#define IPU_DP_GAMMA_S_SYNC_2__EMPTY             0x1E01803C,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_2__FULL              0x1E01803C,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1E01803C,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1E01803C,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9  0x1E01803C,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8  0x1E01803C,0x000000FF
+
+#define IPU_DP_GAMMA_S_SYNC_3__ADDR              0x1E018040
+#define IPU_DP_GAMMA_S_SYNC_3__EMPTY             0x1E018040,0x00000000
+#define IPU_DP_GAMMA_S_SYNC_3__FULL              0x1E018040,0xffffffff
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1E018040,0xFF000000
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1E018040,0x00FF0000
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1E018040,0x0000FF00
+#define IPU_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1E018040,0x000000FF
+
+#define IPU_DP_CSCA_SYNC_0__ADDR           0x1E018044
+#define IPU_DP_CSCA_SYNC_0__EMPTY          0x1E018044,0x00000000
+#define IPU_DP_CSCA_SYNC_0__FULL           0x1E018044,0xffffffff
+#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1E018044,0x03FF0000
+#define IPU_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1E018044,0x000003FF
+
+#define IPU_DP_CSCA_SYNC_1__ADDR           0x1E018048
+#define IPU_DP_CSCA_SYNC_1__EMPTY          0x1E018048,0x00000000
+#define IPU_DP_CSCA_SYNC_1__FULL           0x1E018048,0xffffffff
+#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1E018048,0x03FF0000
+#define IPU_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1E018048,0x000003FF
+
+#define IPU_DP_CSCA_SYNC_2__ADDR           0x1E01804C
+#define IPU_DP_CSCA_SYNC_2__EMPTY          0x1E01804C,0x00000000
+#define IPU_DP_CSCA_SYNC_2__FULL           0x1E01804C,0xffffffff
+#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1E01804C,0x03FF0000
+#define IPU_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1E01804C,0x000003FF
+
+#define IPU_DP_CSCA_SYNC_3__ADDR           0x1E018050
+#define IPU_DP_CSCA_SYNC_3__EMPTY          0x1E018050,0x00000000
+#define IPU_DP_CSCA_SYNC_3__FULL           0x1E018050,0xffffffff
+#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1E018050,0x03FF0000
+#define IPU_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1E018050,0x000003FF
+
+#define IPU_DP_CSC_SYNC_0__ADDR                  0x1E018054
+#define IPU_DP_CSC_SYNC_0__EMPTY         0x1E018054,0x00000000
+#define IPU_DP_CSC_SYNC_0__FULL                  0x1E018054,0xffffffff
+#define IPU_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1E018054,0xC0000000
+#define IPU_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1E018054,0x3FFF0000
+#define IPU_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1E018054,0x000003FF
+
+#define IPU_DP_CSC_SYNC_1__ADDR                  0x1E018058
+#define IPU_DP_CSC_SYNC_1__EMPTY         0x1E018058,0x00000000
+#define IPU_DP_CSC_SYNC_1__FULL                  0x1E018058,0xffffffff
+#define IPU_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1E018058,0xC0000000
+#define IPU_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1E018058,0x3FFF0000
+#define IPU_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1E018058,0x0000C000
+#define IPU_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1E018058,0x00003FFF
+
+#define IPU_DP_CUR_POS_ALT__ADDR           0x1E01805C
+#define IPU_DP_CUR_POS_ALT__EMPTY          0x1E01805C,0x00000000
+#define IPU_DP_CUR_POS_ALT__FULL           0x1E01805C,0xffffffff
+#define IPU_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1E01805C,0xF8000000
+#define IPU_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1E01805C,0x07FF0000
+#define IPU_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1E01805C,0x0000F800
+#define IPU_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1E01805C,0x000007FF
+
+#define IPU_DP_COM_CONF_ASYNC__ADDR                      0x1E018060
+#define IPU_DP_COM_CONF_ASYNC__EMPTY                     0x1E018060,0x00000000
+#define IPU_DP_COM_CONF_ASYNC__FULL                      0x1E018060,0xffffffff
+#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_YUV_EN_ASYNC    0x1E018060,0x00002000
+#define IPU_DP_COM_CONF_ASYNC__DP_GAMMA_EN_ASYNC        0x1E018060,0x00001000
+#define IPU_DP_COM_CONF_ASYNC__DP_CSC_YUV_SAT_MODE_ASYNC 0x1E018060,0x00000800
+#define IPU_DP_COM_CONF_ASYNC__DP_CSC_GAMUT_SAT_EN_ASYNC 0x1E018060,0x00000400
+#define IPU_DP_COM_CONF_ASYNC__DP_CSC_DEF_ASYNC                 0x1E018060,0x00000300
+#define IPU_DP_COM_CONF_ASYNC__DP_COC_ASYNC             0x1E018060,0x00000070
+#define IPU_DP_COM_CONF_ASYNC__DP_GWCKE_ASYNC           0x1E018060,0x00000008
+#define IPU_DP_COM_CONF_ASYNC__DP_GWAM_ASYNC            0x1E018060,0x00000004
+#define IPU_DP_COM_CONF_ASYNC__DP_GWSEL_ASYNC           0x1E018060,0x00000002
+
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__ADDR           0x1E018064
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__EMPTY          0x1E018064,0x00000000
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__FULL           0x1E018064,0xffffffff
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWAV_ASYNC  0x1E018064,0xFF000000
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKR_ASYNC 0x1E018064,0x00FF0000
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKG_ASYNC 0x1E018064,0x0000FF00
+#define IPU_DP_GRAPH_WIND_CTRL_ASYNC__DP_GWCKB_ASYNC 0x1E018064,0x000000FF
+
+#define IPU_DP_FG_POS_ASYNC__ADDR          0x1E018068
+#define IPU_DP_FG_POS_ASYNC__EMPTY         0x1E018068,0x00000000
+#define IPU_DP_FG_POS_ASYNC__FULL          0x1E018068,0xffffffff
+#define IPU_DP_FG_POS_ASYNC__DP_FGXP_ASYNC 0x1E018068,0x07FF0000
+#define IPU_DP_FG_POS_ASYNC__DP_FGYP_ASYNC 0x1E018068,0x000007FF
+
+#define IPU_DP_CUR_POS_ASYNC__ADDR         0x1E01806C
+#define IPU_DP_CUR_POS_ASYNC__EMPTY        0x1E01806C,0x00000000
+#define IPU_DP_CUR_POS_ASYNC__FULL         0x1E01806C,0xffffffff
+#define IPU_DP_CUR_POS_ASYNC__DP_CXW_ASYNC 0x1E01806C,0xF8000000
+#define IPU_DP_CUR_POS_ASYNC__DP_CXP_ASYNC 0x1E01806C,0x07FF0000
+#define IPU_DP_CUR_POS_ASYNC__DP_CYH_ASYNC 0x1E01806C,0x0000F800
+#define IPU_DP_CUR_POS_ASYNC__DP_CYP_ASYNC 0x1E01806C,0x000007FF
+
+#define IPU_DP_CUR_MAP_ASYNC__ADDR            0x1E018070
+#define IPU_DP_CUR_MAP_ASYNC__EMPTY           0x1E018070,0x00000000
+#define IPU_DP_CUR_MAP_ASYNC__FULL            0x1E018070,0xffffffff
+#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_R_ASYNC 0x1E018070,0x00FF0000
+#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_G_ASYNC 0x1E018070,0x0000FF00
+#define IPU_DP_CUR_MAP_ASYNC__CUR_COL_B_ASYNC 0x1E018070,0x000000FF
+
+#define IPU_DP_GAMMA_C_ASYNC_0__ADDR               0x1E018074
+#define IPU_DP_GAMMA_C_ASYNC_0__EMPTY              0x1E018074,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_0__FULL               0x1E018074,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_1 0x1E018074,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_0__DP_GAMMA_C_ASYNC_0 0x1E018074,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_1__ADDR               0x1E018078
+#define IPU_DP_GAMMA_C_ASYNC_1__EMPTY              0x1E018078,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_1__FULL               0x1E018078,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_3 0x1E018078,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_1__DP_GAMMA_C_ASYNC_2 0x1E018078,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_2__ADDR               0x1E01807C
+#define IPU_DP_GAMMA_C_ASYNC_2__EMPTY              0x1E01807C,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_2__FULL               0x1E01807C,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_5 0x1E01807C,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_2__DP_GAMMA_C_ASYNC_4 0x1E01807C,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_3__ADDR               0x1E018080
+#define IPU_DP_GAMMA_C_ASYNC_3__EMPTY              0x1E018080,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_3__FULL               0x1E018080,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_7 0x1E018080,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_3__DP_GAMMA_C_ASYNC_6 0x1E018080,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_4__ADDR               0x1E018084
+#define IPU_DP_GAMMA_C_ASYNC_4__EMPTY              0x1E018084,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_4__FULL               0x1E018084,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_9 0x1E018084,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_4__DP_GAMMA_C_ASYNC_8 0x1E018084,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_5__ADDR                0x1E018088
+#define IPU_DP_GAMMA_C_ASYNC_5__EMPTY               0x1E018088,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_5__FULL                0x1E018088,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_11 0x1E018088,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_5__DP_GAMMA_C_ASYNC_10 0x1E018088,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_6__ADDR                0x1E01808C
+#define IPU_DP_GAMMA_C_ASYNC_6__EMPTY               0x1E01808C,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_6__FULL                0x1E01808C,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_13 0x1E01808C,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_6__DP_GAMMA_C_ASYNC_12 0x1E01808C,0x000001FF
+
+#define IPU_DP_GAMMA_C_ASYNC_7__ADDR                0x1E018090
+#define IPU_DP_GAMMA_C_ASYNC_7__EMPTY               0x1E018090,0x00000000
+#define IPU_DP_GAMMA_C_ASYNC_7__FULL                0x1E018090,0xffffffff
+#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_15 0x1E018090,0x01FF0000
+#define IPU_DP_GAMMA_C_ASYNC_7__DP_GAMMA_C_ASYNC_14 0x1E018090,0x000001FF
+
+#define IPU_DP_GAMMA_S_ASYNC_0__ADDR               0x1E018094
+#define IPU_DP_GAMMA_S_ASYNC_0__EMPTY              0x1E018094,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_0__FULL               0x1E018094,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_3 0x1E018094,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_2 0x1E018094,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_1 0x1E018094,0x0000FF00
+#define IPU_DP_GAMMA_S_ASYNC_0__DP_GAMMA_S_ASYNC_0 0x1E018094,0x000000FF
+
+#define IPU_DP_GAMMA_S_ASYNC_1__ADDR               0x1E018098
+#define IPU_DP_GAMMA_S_ASYNC_1__EMPTY              0x1E018098,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_1__FULL               0x1E018098,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_7 0x1E018098,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_6 0x1E018098,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_5 0x1E018098,0x0000FF00
+#define IPU_DP_GAMMA_S_ASYNC_1__DP_GAMMA_S_ASYNC_4 0x1E018098,0x000000FF
+
+#define IPU_DP_GAMMA_S_ASYNC_2__ADDR                0x1E01809C
+#define IPU_DP_GAMMA_S_ASYNC_2__EMPTY               0x1E01809C,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_2__FULL                0x1E01809C,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_11 0x1E01809C,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_10 0x1E01809C,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_9  0x1E01809C,0x0000FF00
+#define IPU_DP_GAMMA_S_ASYNC_2__DP_GAMMA_S_ASYNC_8  0x1E01809C,0x000000FF
+
+#define IPU_DP_GAMMA_S_ASYNC_3__ADDR                0x1E0180A0
+#define IPU_DP_GAMMA_S_ASYNC_3__EMPTY               0x1E0180A0,0x00000000
+#define IPU_DP_GAMMA_S_ASYNC_3__FULL                0x1E0180A0,0xffffffff
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_15 0x1E0180A0,0xFF000000
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_14 0x1E0180A0,0x00FF0000
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_13 0x1E0180A0,0x0000FF00
+#define IPU_DP_GAMMA_S_ASYNC_3__DP_GAMMA_S_ASYNC_12 0x1E0180A0,0x000000FF
+
+#define IPU_DP_CSCA_ASYNC_0__ADDR             0x1E0180A4
+#define IPU_DP_CSCA_ASYNC_0__EMPTY            0x1E0180A4,0x00000000
+#define IPU_DP_CSCA_ASYNC_0__FULL             0x1E0180A4,0xffffffff
+#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_1 0x1E0180A4,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_0__DP_CSC_A_ASYNC_0 0x1E0180A4,0x000003FF
+
+#define IPU_DP_CSCA_ASYNC_1__ADDR             0x1E0180A8
+#define IPU_DP_CSCA_ASYNC_1__EMPTY            0x1E0180A8,0x00000000
+#define IPU_DP_CSCA_ASYNC_1__FULL             0x1E0180A8,0xffffffff
+#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_3 0x1E0180A8,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_1__DP_CSC_A_ASYNC_2 0x1E0180A8,0x000003FF
+
+#define IPU_DP_CSCA_ASYNC_2__ADDR             0x1E0180AC
+#define IPU_DP_CSCA_ASYNC_2__EMPTY            0x1E0180AC,0x00000000
+#define IPU_DP_CSCA_ASYNC_2__FULL             0x1E0180AC,0xffffffff
+#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_5 0x1E0180AC,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_2__DP_CSC_A_ASYNC_4 0x1E0180AC,0x000003FF
+
+#define IPU_DP_CSCA_ASYNC_3__ADDR             0x1E0180B0
+#define IPU_DP_CSCA_ASYNC_3__EMPTY            0x1E0180B0,0x00000000
+#define IPU_DP_CSCA_ASYNC_3__FULL             0x1E0180B0,0xffffffff
+#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_7 0x1E0180B0,0x03FF0000
+#define IPU_DP_CSCA_ASYNC_3__DP_CSC_A_ASYNC_6 0x1E0180B0,0x000003FF
+
+#define IPU_DP_CSC_ASYNC_0__ADDR            0x1E0180B4
+#define IPU_DP_CSC_ASYNC_0__EMPTY           0x1E0180B4,0x00000000
+#define IPU_DP_CSC_ASYNC_0__FULL            0x1E0180B4,0xffffffff
+#define IPU_DP_CSC_ASYNC_0__DP_CSC_S0_ASYNC 0x1E0180B4,0xC0000000
+#define IPU_DP_CSC_ASYNC_0__DP_CSC_B0_ASYNC 0x1E0180B4,0x3FFF0000
+#define IPU_DP_CSC_ASYNC_0__DP_CSC_A8_ASYNC 0x1E0180B4,0x000003FF
+
+#define IPU_DP_CSC_ASYNC_1__ADDR            0x1E0180B8
+#define IPU_DP_CSC_ASYNC_1__EMPTY           0x1E0180B8,0x00000000
+#define IPU_DP_CSC_ASYNC_1__FULL            0x1E0180B8,0xffffffff
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_S2_ASYNC 0x1E0180B8,0xC0000000
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_B2_ASYNC 0x1E0180B8,0x3FFF0000
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_S1_ASYNC 0x1E0180B8,0x0000C000
+#define IPU_DP_CSC_ASYNC_1__DP_CSC_B1_ASYNC 0x1E0180B8,0x00003FFF
+
+#define IPU_DP_DEBUG_CNT__ADDR             0x1E0180BC
+#define IPU_DP_DEBUG_CNT__EMPTY                    0x1E0180BC,0x00000000
+#define IPU_DP_DEBUG_CNT__FULL             0x1E0180BC,0xffffffff
+#define IPU_DP_DEBUG_CNT__BRAKE_CNT_1      0x1E0180BC,0x000000E0
+#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_1 0x1E0180BC,0x00000010
+#define IPU_DP_DEBUG_CNT__BRAKE_CNT_0      0x1E0180BC,0x0000000E
+#define IPU_DP_DEBUG_CNT__BRAKE_STATUS_EN_0 0x1E0180BC,0x00000001
+
+#define IPU_DP_DEBUG_STAT__ADDR                   0x1E0180C0
+#define IPU_DP_DEBUG_STAT__EMPTY          0x1E0180C0,0x00000000
+#define IPU_DP_DEBUG_STAT__FULL                   0x1E0180C0,0xffffffff
+#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_1           0x1E0180C0,0x20000000
+#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_1 0x1E0180C0,0x10000000
+#define IPU_DP_DEBUG_STAT__FG_ACTIVE_1    0x1E0180C0,0x08000000
+#define IPU_DP_DEBUG_STAT__V_CNT_OLD_1    0x1E0180C0,0x07FF0000
+#define IPU_DP_DEBUG_STAT__CYP_EN_OLD_0           0x1E0180C0,0x00002000
+#define IPU_DP_DEBUG_STAT__COMBYP_EN_OLD_0 0x1E0180C0,0x00001000
+#define IPU_DP_DEBUG_STAT__FG_ACTIVE_0    0x1E0180C0,0x00000800
+#define IPU_DP_DEBUG_STAT__V_CNT_OLD_0    0x1E0180C0,0x000007FF
+
+// ================= Start of IPUV3EX SRM DP Registers =====================
+
+// ================= Start of IPUV3EX IC Registers =====================
+#define IPU_IC_CONF__ADDR           0x1E020000
+#define IPU_IC_CONF__EMPTY          0x1E020000,0x00000000
+#define IPU_IC_CONF__FULL           0x1E020000,0xffffffff
+#define IPU_IC_CONF__CSI_MEM_WR_EN   0x1E020000,0x80000000
+#define IPU_IC_CONF__RWS_EN         0x1E020000,0x40000000
+#define IPU_IC_CONF__IC_KEY_COLOR_EN 0x1E020000,0x20000000
+#define IPU_IC_CONF__IC_GLB_LOC_A    0x1E020000,0x10000000
+#define IPU_IC_CONF__PP_ROT_EN      0x1E020000,0x00100000
+#define IPU_IC_CONF__PP_CMB         0x1E020000,0x00080000
+#define IPU_IC_CONF__PP_CSC2        0x1E020000,0x00040000
+#define IPU_IC_CONF__PP_CSC1        0x1E020000,0x00020000
+#define IPU_IC_CONF__PP_EN          0x1E020000,0x00010000
+#define IPU_IC_CONF__PRPVF_ROT_EN    0x1E020000,0x00001000
+#define IPU_IC_CONF__PRPVF_CMB      0x1E020000,0x00000800
+#define IPU_IC_CONF__PRPVF_CSC2             0x1E020000,0x00000400
+#define IPU_IC_CONF__PRPVF_CSC1             0x1E020000,0x00000200
+#define IPU_IC_CONF__PRPVF_EN       0x1E020000,0x00000100
+#define IPU_IC_CONF__PRPENC_ROT_EN   0x1E020000,0x00000004
+#define IPU_IC_CONF__PRPENC_CSC1     0x1E020000,0x00000002
+#define IPU_IC_CONF__PRPENC_EN      0x1E020000,0x00000001
+
+#define IPU_IC_PRP_ENC_RSC__ADDR         0x1E020004
+#define IPU_IC_PRP_ENC_RSC__EMPTY        0x1E020004,0x00000000
+#define IPU_IC_PRP_ENC_RSC__FULL         0x1E020004,0xffffffff
+#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_V 0x1E020004,0xC0000000
+#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_V 0x1E020004,0x3FFF0000
+#define IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_H 0x1E020004,0x0000C000
+#define IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_H 0x1E020004,0x00003FFF
+
+#define IPU_IC_PRP_VF_RSC__ADDR                0x1E020008
+#define IPU_IC_PRP_VF_RSC__EMPTY       0x1E020008,0x00000000
+#define IPU_IC_PRP_VF_RSC__FULL                0x1E020008,0xffffffff
+#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_V 0x1E020008,0xC0000000
+#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_V 0x1E020008,0x3FFF0000
+#define IPU_IC_PRP_VF_RSC__PRPVF_DS_R_H 0x1E020008,0x0000C000
+#define IPU_IC_PRP_VF_RSC__PRPVF_RS_R_H 0x1E020008,0x00003FFF
+
+#define IPU_IC_PP_RSC__ADDR     0x1E02000C
+#define IPU_IC_PP_RSC__EMPTY    0x1E02000C,0x00000000
+#define IPU_IC_PP_RSC__FULL     0x1E02000C,0xffffffff
+#define IPU_IC_PP_RSC__PP_DS_R_V 0x1E02000C,0xC0000000
+#define IPU_IC_PP_RSC__PP_RS_R_V 0x1E02000C,0x3FFF0000
+#define IPU_IC_PP_RSC__PP_DS_R_H 0x1E02000C,0x0000C000
+#define IPU_IC_PP_RSC__PP_RS_R_H 0x1E02000C,0x00003FFF
+
+#define IPU_IC_CMBP_1__ADDR            0x1E020010
+#define IPU_IC_CMBP_1__EMPTY           0x1E020010,0x00000000
+#define IPU_IC_CMBP_1__FULL            0x1E020010,0xffffffff
+#define IPU_IC_CMBP_1__IC_PP_ALPHA_V   0x1E020010,0x0000FF00
+#define IPU_IC_CMBP_1__IC_PRPVF_ALPHA_V 0x1E020010,0x000000FF
+
+#define IPU_IC_CMBP_2__ADDR          0x1E020014
+#define IPU_IC_CMBP_2__EMPTY         0x1E020014,0x00000000
+#define IPU_IC_CMBP_2__FULL          0x1E020014,0xffffffff
+#define IPU_IC_CMBP_2__IC_KEY_COLOR_R 0x1E020014,0x00FF0000
+#define IPU_IC_CMBP_2__IC_KEY_COLOR_G 0x1E020014,0x0000FF00
+#define IPU_IC_CMBP_2__IC_KEY_COLOR_B 0x1E020014,0x000000FF
+
+#define IPU_IC_IDMAC_1__ADDR            0x1E020018
+#define IPU_IC_IDMAC_1__EMPTY           0x1E020018,0x00000000
+#define IPU_IC_IDMAC_1__FULL            0x1E020018,0xffffffff
+#define IPU_IC_IDMAC_1__ALT_CB7_BURST_16 0x1E020018,0x02000000
+#define IPU_IC_IDMAC_1__ALT_CB6_BURST_16 0x1E020018,0x01000000
+#define IPU_IC_IDMAC_1__T3_FLIP_RS      0x1E020018,0x00400000
+#define IPU_IC_IDMAC_1__T2_FLIP_RS      0x1E020018,0x00200000
+#define IPU_IC_IDMAC_1__T1_FLIP_RS      0x1E020018,0x00100000
+#define IPU_IC_IDMAC_1__T3_FLIP_UD      0x1E020018,0x00080000
+#define IPU_IC_IDMAC_1__T3_FLIP_LR      0x1E020018,0x00040000
+#define IPU_IC_IDMAC_1__T3_ROT          0x1E020018,0x00020000
+#define IPU_IC_IDMAC_1__T2_FLIP_UD      0x1E020018,0x00010000
+#define IPU_IC_IDMAC_1__T2_FLIP_LR      0x1E020018,0x00008000
+#define IPU_IC_IDMAC_1__T2_ROT          0x1E020018,0x00004000
+#define IPU_IC_IDMAC_1__T1_FLIP_UD      0x1E020018,0x00002000
+#define IPU_IC_IDMAC_1__T1_FLIP_LR      0x1E020018,0x00001000
+#define IPU_IC_IDMAC_1__T1_ROT          0x1E020018,0x00000800
+#define IPU_IC_IDMAC_1__CB7_BURST_16    0x1E020018,0x00000080
+#define IPU_IC_IDMAC_1__CB6_BURST_16    0x1E020018,0x00000040
+#define IPU_IC_IDMAC_1__CB5_BURST_16    0x1E020018,0x00000020
+#define IPU_IC_IDMAC_1__CB4_BURST_16    0x1E020018,0x00000010
+#define IPU_IC_IDMAC_1__CB3_BURST_16    0x1E020018,0x00000008
+#define IPU_IC_IDMAC_1__CB2_BURST_16    0x1E020018,0x00000004
+#define IPU_IC_IDMAC_1__CB1_BURST_16    0x1E020018,0x00000002
+#define IPU_IC_IDMAC_1__CB0_BURST_16    0x1E020018,0x00000001
+
+#define IPU_IC_IDMAC_2__ADDR        0x1E02001C
+#define IPU_IC_IDMAC_2__EMPTY       0x1E02001C,0x00000000
+#define IPU_IC_IDMAC_2__FULL        0x1E02001C,0xffffffff
+#define IPU_IC_IDMAC_2__T3_FR_HEIGHT 0x1E02001C,0x3FF00000
+#define IPU_IC_IDMAC_2__T2_FR_HEIGHT 0x1E02001C,0x000FFC00
+#define IPU_IC_IDMAC_2__T1_FR_HEIGHT 0x1E02001C,0x000003FF
+
+#define IPU_IC_IDMAC_3__ADDR       0x1E020020
+#define IPU_IC_IDMAC_3__EMPTY      0x1E020020,0x00000000
+#define IPU_IC_IDMAC_3__FULL       0x1E020020,0xffffffff
+#define IPU_IC_IDMAC_3__T3_FR_WIDTH 0x1E020020,0x3FF00000
+#define IPU_IC_IDMAC_3__T2_FR_WIDTH 0x1E020020,0x000FFC00
+#define IPU_IC_IDMAC_3__T1_FR_WIDTH 0x1E020020,0x000003FF
+
+#define IPU_IC_IDMAC_4__ADDR                0x1E020024
+#define IPU_IC_IDMAC_4__EMPTY               0x1E020024,0x00000000
+#define IPU_IC_IDMAC_4__FULL                0x1E020024,0xffffffff
+#define IPU_IC_IDMAC_4__RM_BRDG_MAX_RQ      0x1E020024,0x0000F000
+#define IPU_IC_IDMAC_4__IBM_BRDG_MAX_RQ             0x1E020024,0x00000F00
+#define IPU_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ 0x1E020024,0x000000F0
+#define IPU_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ   0x1E020024,0x0000000F
+// ================= End of IPUV3EX IC Registers =====================
+
+// ================= Start of IPUV3EX CSI Registers =====================
+#define IPU_CSI0_SENS_CONF__ADDR                 0x1E030000
+#define IPU_CSI0_SENS_CONF__EMPTY                0x1E030000,0x00000000
+#define IPU_CSI0_SENS_CONF__FULL                 0x1E030000,0xffffffff
+#define IPU_CSI0_SENS_CONF__CSI0_FORCE_EOF       0x1E030000,0x20000000
+#define IPU_CSI0_SENS_CONF__CSI0_JPEG_MODE       0x1E030000,0x10000000
+#define IPU_CSI0_SENS_CONF__CSI0_JPEG8_EN        0x1E030000,0x08000000
+#define IPU_CSI0_SENS_CONF__CSI0_DATA_DEST       0x1E030000,0x07000000
+#define IPU_CSI0_SENS_CONF__CSI0_DIV_RATIO       0x1E030000,0x00FF0000
+#define IPU_CSI0_SENS_CONF__CSI0_EXT_VSYNC       0x1E030000,0x00008000
+#define IPU_CSI0_SENS_CONF__CSI0_DATA_WIDTH      0x1E030000,0x00007800
+#define IPU_CSI0_SENS_CONF__CSI0_SENS_DATA_FORMAT 0x1E030000,0x00000700
+#define IPU_CSI0_SENS_CONF__CSI0_PACK_TIGHT      0x1E030000,0x00000080
+#define IPU_CSI0_SENS_CONF__CSI0_SENS_PRTCL      0x1E030000,0x00000070
+#define IPU_CSI0_SENS_CONF__CSI0_SENS_PIX_CLK_POL 0x1E030000,0x00000008
+#define IPU_CSI0_SENS_CONF__CSI0_DATA_POL        0x1E030000,0x00000004
+#define IPU_CSI0_SENS_CONF__CSI0_HSYNC_POL       0x1E030000,0x00000002
+#define IPU_CSI0_SENS_CONF__CSI0_VSYNC_POL       0x1E030000,0x00000001
+
+#define IPU_CSI0_SENS_FRM_SIZE__ADDR                0x1E030004
+#define IPU_CSI0_SENS_FRM_SIZE__EMPTY               0x1E030004,0x00000000
+#define IPU_CSI0_SENS_FRM_SIZE__FULL                0x1E030004,0xffffffff
+#define IPU_CSI0_SENS_FRM_SIZE__CSI0_SENS_FRM_HEIGHT 0x1E030004,0x0FFF0000
+#define IPU_CSI0_SENS_FRM_SIZE__CSI0_SENS_FRM_WIDTH  0x1E030004,0x00001FFF
+
+#define IPU_CSI0_ACT_FRM_SIZE__ADDR               0x1E030008
+#define IPU_CSI0_ACT_FRM_SIZE__EMPTY              0x1E030008,0x00000000
+#define IPU_CSI0_ACT_FRM_SIZE__FULL               0x1E030008,0xffffffff
+#define IPU_CSI0_ACT_FRM_SIZE__CSI0_ACT_FRM_HEIGHT 0x1E030008,0x0FFF0000
+#define IPU_CSI0_ACT_FRM_SIZE__CSI0_ACT_FRM_WIDTH  0x1E030008,0x00001FFF
+
+#define IPU_CSI0_OUT_FRM_CTRL__ADDR          0x1E03000C
+#define IPU_CSI0_OUT_FRM_CTRL__EMPTY         0x1E03000C,0x00000000
+#define IPU_CSI0_OUT_FRM_CTRL__FULL          0x1E03000C,0xffffffff
+#define IPU_CSI0_OUT_FRM_CTRL__CSI0_HORZ_DWNS 0x1E03000C,0x80000000
+#define IPU_CSI0_OUT_FRM_CTRL__CSI0_VERT_DWNS 0x1E03000C,0x40000000
+#define IPU_CSI0_OUT_FRM_CTRL__CSI0_HSC              0x1E03000C,0x1FFF0000
+#define IPU_CSI0_OUT_FRM_CTRL__CSI0_VSC              0x1E03000C,0x00000FFF
+
+#define IPU_CSI0_TST_CTRL__ADDR                      0x1E030010
+#define IPU_CSI0_TST_CTRL__EMPTY             0x1E030010,0x00000000
+#define IPU_CSI0_TST_CTRL__FULL                      0x1E030010,0xffffffff
+#define IPU_CSI0_TST_CTRL__CSI0_TEST_GEN_MODE 0x1E030010,0x01000000
+#define IPU_CSI0_TST_CTRL__CSI0_PG_B_VALUE    0x1E030010,0x00FF0000
+#define IPU_CSI0_TST_CTRL__CSI0_PG_G_VALUE    0x1E030010,0x0000FF00
+#define IPU_CSI0_TST_CTRL__CSI0_PG_R_VALUE    0x1E030010,0x000000FF
+
+#define IPU_CSI0_CCIR_CODE_1__ADDR                   0x1E030014
+#define IPU_CSI0_CCIR_CODE_1__EMPTY                  0x1E030014,0x00000000
+#define IPU_CSI0_CCIR_CODE_1__FULL                   0x1E030014,0xffffffff
+#define IPU_CSI0_CCIR_CODE_1__CSI0_CCIR_ERR_DET_EN    0x1E030014,0x01000000
+#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_ACTV     0x1E030014,0x00380000
+#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_ACTV      0x1E030014,0x00070000
+#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_BLNK_2ND 0x1E030014,0x00000E00
+#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_BLNK_2ND  0x1E030014,0x000001C0
+#define IPU_CSI0_CCIR_CODE_1__CSI0_STRT_FLD0_BLNK_1ST 0x1E030014,0x00000038
+#define IPU_CSI0_CCIR_CODE_1__CSI0_END_FLD0_BLNK_1ST  0x1E030014,0x00000007
+
+#define IPU_CSI0_CCIR_CODE_2__ADDR                   0x1E030018
+#define IPU_CSI0_CCIR_CODE_2__EMPTY                  0x1E030018,0x00000000
+#define IPU_CSI0_CCIR_CODE_2__FULL                   0x1E030018,0xffffffff
+#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_ACTV     0x1E030018,0x00380000
+#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_ACTV      0x1E030018,0x00070000
+#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_BLNK_2ND 0x1E030018,0x00000E00
+#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_BLNK_2ND  0x1E030018,0x000001C0
+#define IPU_CSI0_CCIR_CODE_2__CSI0_STRT_FLD1_BLNK_1ST 0x1E030018,0x00000038
+#define IPU_CSI0_CCIR_CODE_2__CSI0_END_FLD1_BLNK_1ST  0x1E030018,0x00000007
+
+#define IPU_CSI0_CCIR_CODE_3__ADDR            0x1E03001C
+#define IPU_CSI0_CCIR_CODE_3__EMPTY           0x1E03001C,0x00000000
+#define IPU_CSI0_CCIR_CODE_3__FULL            0x1E03001C,0xffffffff
+#define IPU_CSI0_CCIR_CODE_3__CSI0_CCIR_PRECOM 0x1E03001C,0x3FFFFFFF
+
+#define IPU_CSI0_DI__ADDR         0x1E030020
+#define IPU_CSI0_DI__EMPTY        0x1E030020,0x00000000
+#define IPU_CSI0_DI__FULL         0x1E030020,0xffffffff
+#define IPU_CSI0_DI__CSI0_MIPI_DI3 0x1E030020,0xFF000000
+#define IPU_CSI0_DI__CSI0_MIPI_DI2 0x1E030020,0x00FF0000
+#define IPU_CSI0_DI__CSI0_MIPI_DI1 0x1E030020,0x0000FF00
+#define IPU_CSI0_DI__CSI0_MIPI_DI0 0x1E030020,0x000000FF
+
+#define IPU_CSI0_SKIP__ADDR                    0x1E030024
+#define IPU_CSI0_SKIP__EMPTY                   0x1E030024,0x00000000
+#define IPU_CSI0_SKIP__FULL                    0x1E030024,0xffffffff
+#define IPU_CSI0_SKIP__CSI0_SKIP_ISP           0x1E030024,0x00F80000
+#define IPU_CSI0_SKIP__CSI0_MAX_RATIO_SKIP_ISP 0x1E030024,0x00070000
+#define IPU_CSI0_SKIP__CSI0_ID_2_SKIP          0x1E030024,0x00000300
+#define IPU_CSI0_SKIP__CSI0_SKIP_SMFC          0x1E030024,0x000000F8
+#define IPU_CSI0_SKIP__CSI0_MAX_RATIO_SKIP_SMFC 0x1E030024,0x00000007
+
+#define IPU_CSI0_CPD_CTRL__ADDR                      0x1E030028
+#define IPU_CSI0_CPD_CTRL__EMPTY             0x1E030028,0x00000000
+#define IPU_CSI0_CPD_CTRL__FULL                      0x1E030028,0xffffffff
+#define IPU_CSI0_CPD_CTRL__CSI0_CPD          0x1E030028,0x0000001C
+#define IPU_CSI0_CPD_CTRL__CSI0_RED_ROW_BEGIN 0x1E030028,0x00000002
+#define IPU_CSI0_CPD_CTRL__CSI0_GREEN_P_BEGIN 0x1E030028,0x00000001
+
+#define IPU_CSI0_CPD_RC_0__ADDR                 0x1E03002C
+#define IPU_CSI0_CPD_RC_0__EMPTY        0x1E03002C,0x00000000
+#define IPU_CSI0_CPD_RC_0__FULL                 0x1E03002C,0xffffffff
+#define IPU_CSI0_CPD_RC_0__CSI0_CPD_RC_1 0x1E03002C,0x01FF0000
+#define IPU_CSI0_CPD_RC_0__CSI0_CPD_RC_0 0x1E03002C,0x000001FF
+
+#define IPU_CSI0_CPD_RC_1__ADDR                 0x1E030030
+#define IPU_CSI0_CPD_RC_1__EMPTY        0x1E030030,0x00000000
+#define IPU_CSI0_CPD_RC_1__FULL                 0x1E030030,0xffffffff
+#define IPU_CSI0_CPD_RC_1__CSI0_CPD_RC_3 0x1E030030,0x01FF0000
+#define IPU_CSI0_CPD_RC_1__CSI0_CPD_RC_2 0x1E030030,0x000001FF
+
+#define IPU_CSI0_CPD_RC_2__ADDR                 0x1E030034
+#define IPU_CSI0_CPD_RC_2__EMPTY        0x1E030034,0x00000000
+#define IPU_CSI0_CPD_RC_2__FULL                 0x1E030034,0xffffffff
+#define IPU_CSI0_CPD_RC_2__CSI0_CPD_RC_5 0x1E030034,0x01FF0000
+#define IPU_CSI0_CPD_RC_2__CSI0_CPD_RC_4 0x1E030034,0x000001FF
+
+#define IPU_CSI0_CPD_RC_3__ADDR                 0x1E030038
+#define IPU_CSI0_CPD_RC_3__EMPTY        0x1E030038,0x00000000
+#define IPU_CSI0_CPD_RC_3__FULL                 0x1E030038,0xffffffff
+#define IPU_CSI0_CPD_RC_3__CSI0_CPD_RC_7 0x1E030038,0x01FF0000
+#define IPU_CSI0_CPD_RC_3__CSI0_CPD_RC_6 0x1E030038,0x000001FF
+
+#define IPU_CSI0_CPD_RC_4__ADDR                 0x1E03003C
+#define IPU_CSI0_CPD_RC_4__EMPTY        0x1E03003C,0x00000000
+#define IPU_CSI0_CPD_RC_4__FULL                 0x1E03003C,0xffffffff
+#define IPU_CSI0_CPD_RC_4__CSI0_CPD_RC_9 0x1E03003C,0x01FF0000
+#define IPU_CSI0_CPD_RC_4__CSI0_CPD_RC_8 0x1E03003C,0x000001FF
+
+#define IPU_CSI0_CPD_RC_5__ADDR                  0x1E030040
+#define IPU_CSI0_CPD_RC_5__EMPTY         0x1E030040,0x00000000
+#define IPU_CSI0_CPD_RC_5__FULL                  0x1E030040,0xffffffff
+#define IPU_CSI0_CPD_RC_5__CSI0_CPD_RC_11 0x1E030040,0x01FF0000
+#define IPU_CSI0_CPD_RC_5__CSI0_CPD_RC_10 0x1E030040,0x000001FF
+
+#define IPU_CSI0_CPD_RC_6__ADDR                  0x1E030044
+#define IPU_CSI0_CPD_RC_6__EMPTY         0x1E030044,0x00000000
+#define IPU_CSI0_CPD_RC_6__FULL                  0x1E030044,0xffffffff
+#define IPU_CSI0_CPD_RC_6__CSI0_CPD_RC_13 0x1E030044,0x01FF0000
+#define IPU_CSI0_CPD_RC_6__CSI0_CPD_RC_12 0x1E030044,0x000001FF
+
+#define IPU_CSI0_CPD_RC_7__ADDR                  0x1E030048
+#define IPU_CSI0_CPD_RC_7__EMPTY         0x1E030048,0x00000000
+#define IPU_CSI0_CPD_RC_7__FULL                  0x1E030048,0xffffffff
+#define IPU_CSI0_CPD_RC_7__CSI0_CPD_RC_15 0x1E030048,0x01FF0000
+#define IPU_CSI0_CPD_RC_7__CSI0_CPD_RC_14 0x1E030048,0x000001FF
+
+#define IPU_CSI0_CPD_RS_0__ADDR                0x1E03004C
+#define IPU_CSI0_CPD_RS_0__EMPTY       0x1E03004C,0x00000000
+#define IPU_CSI0_CPD_RS_0__FULL                0x1E03004C,0xffffffff
+#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS3 0x1E03004C,0xFF000000
+#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS2 0x1E03004C,0x00FF0000
+#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS1 0x1E03004C,0x0000FF00
+#define IPU_CSI0_CPD_RS_0__CSI0_CPD_RS0 0x1E03004C,0x000000FF
+
+#define IPU_CSI0_CPD_RS_1__ADDR                0x1E030050
+#define IPU_CSI0_CPD_RS_1__EMPTY       0x1E030050,0x00000000
+#define IPU_CSI0_CPD_RS_1__FULL                0x1E030050,0xffffffff
+#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS7 0x1E030050,0xFF000000
+#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS6 0x1E030050,0x00FF0000
+#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS5 0x1E030050,0x0000FF00
+#define IPU_CSI0_CPD_RS_1__CSI0_CPD_RS4 0x1E030050,0x000000FF
+
+#define IPU_CSI0_CPD_RS_2__ADDR                 0x1E030054
+#define IPU_CSI0_CPD_RS_2__EMPTY        0x1E030054,0x00000000
+#define IPU_CSI0_CPD_RS_2__FULL                 0x1E030054,0xffffffff
+#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS11 0x1E030054,0xFF000000
+#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS10 0x1E030054,0x00FF0000
+#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS9         0x1E030054,0x0000FF00
+#define IPU_CSI0_CPD_RS_2__CSI0_CPD_RS8         0x1E030054,0x000000FF
+
+#define IPU_CSI0_CPD_RS_3__ADDR                 0x1E030058
+#define IPU_CSI0_CPD_RS_3__EMPTY        0x1E030058,0x00000000
+#define IPU_CSI0_CPD_RS_3__FULL                 0x1E030058,0xffffffff
+#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS15 0x1E030058,0xFF000000
+#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS14 0x1E030058,0x00FF0000
+#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS13 0x1E030058,0x0000FF00
+#define IPU_CSI0_CPD_RS_3__CSI0_CPD_RS12 0x1E030058,0x000000FF
+
+#define IPU_CSI0_CPD_GRC_0__ADDR         0x1E03005C
+#define IPU_CSI0_CPD_GRC_0__EMPTY        0x1E03005C,0x00000000
+#define IPU_CSI0_CPD_GRC_0__FULL         0x1E03005C,0xffffffff
+#define IPU_CSI0_CPD_GRC_0__CSI0_CPD_GRC1 0x1E03005C,0x01FF0000
+#define IPU_CSI0_CPD_GRC_0__CSI0_CPD_GRC0 0x1E03005C,0x000001FF
+
+#define IPU_CSI0_CPD_GRC_1__ADDR         0x1E030060
+#define IPU_CSI0_CPD_GRC_1__EMPTY        0x1E030060,0x00000000
+#define IPU_CSI0_CPD_GRC_1__FULL         0x1E030060,0xffffffff
+#define IPU_CSI0_CPD_GRC_1__CSI0_CPD_GRC3 0x1E030060,0x01FF0000
+#define IPU_CSI0_CPD_GRC_1__CSI0_CPD_GRC2 0x1E030060,0x000001FF
+
+#define IPU_CSI0_CPD_GRC_2__ADDR         0x1E030064
+#define IPU_CSI0_CPD_GRC_2__EMPTY        0x1E030064,0x00000000
+#define IPU_CSI0_CPD_GRC_2__FULL         0x1E030064,0xffffffff
+#define IPU_CSI0_CPD_GRC_2__CSI0_CPD_GRC5 0x1E030064,0x01FF0000
+#define IPU_CSI0_CPD_GRC_2__CSI0_CPD_GRC4 0x1E030064,0x000001FF
+
+#define IPU_CSI0_CPD_GRC_3__ADDR         0x1E030068
+#define IPU_CSI0_CPD_GRC_3__EMPTY        0x1E030068,0x00000000
+#define IPU_CSI0_CPD_GRC_3__FULL         0x1E030068,0xffffffff
+#define IPU_CSI0_CPD_GRC_3__CSI0_CPD_GRC7 0x1E030068,0x01FF0000
+#define IPU_CSI0_CPD_GRC_3__CSI0_CPD_GRC6 0x1E030068,0x000001FF
+
+#define IPU_CSI0_CPD_GRC_4__ADDR         0x1E03006C
+#define IPU_CSI0_CPD_GRC_4__EMPTY        0x1E03006C,0x00000000
+#define IPU_CSI0_CPD_GRC_4__FULL         0x1E03006C,0xffffffff
+#define IPU_CSI0_CPD_GRC_4__CSI0_CPD_GRC9 0x1E03006C,0x01FF0000
+#define IPU_CSI0_CPD_GRC_4__CSI0_CPD_GRC8 0x1E03006C,0x000001FF
+
+#define IPU_CSI0_CPD_GRC_5__ADDR          0x1E030070
+#define IPU_CSI0_CPD_GRC_5__EMPTY         0x1E030070,0x00000000
+#define IPU_CSI0_CPD_GRC_5__FULL          0x1E030070,0xffffffff
+#define IPU_CSI0_CPD_GRC_5__CSI0_CPD_GRC11 0x1E030070,0x01FF0000
+#define IPU_CSI0_CPD_GRC_5__CSI0_CPD_GRC10 0x1E030070,0x000001FF
+
+#define IPU_CSI0_CPD_GRC_6__ADDR          0x1E030074
+#define IPU_CSI0_CPD_GRC_6__EMPTY         0x1E030074,0x00000000
+#define IPU_CSI0_CPD_GRC_6__FULL          0x1E030074,0xffffffff
+#define IPU_CSI0_CPD_GRC_6__CSI0_CPD_GRC13 0x1E030074,0x01FF0000
+#define IPU_CSI0_CPD_GRC_6__CSI0_CPD_GRC12 0x1E030074,0x000001FF
+
+#define IPU_CSI0_CPD_GRC_7__ADDR          0x1E030078
+#define IPU_CSI0_CPD_GRC_7__EMPTY         0x1E030078,0x00000000
+#define IPU_CSI0_CPD_GRC_7__FULL          0x1E030078,0xffffffff
+#define IPU_CSI0_CPD_GRC_7__CSI0_CPD_GRC15 0x1E030078,0x01FF0000
+#define IPU_CSI0_CPD_GRC_7__CSI0_CPD_GRC14 0x1E030078,0x000001FF
+
+#define IPU_CSI0_CPD_GRS_0__ADDR         0x1E03007C
+#define IPU_CSI0_CPD_GRS_0__EMPTY        0x1E03007C,0x00000000
+#define IPU_CSI0_CPD_GRS_0__FULL         0x1E03007C,0xffffffff
+#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS3 0x1E03007C,0xFF000000
+#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS2 0x1E03007C,0x00FF0000
+#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS1 0x1E03007C,0x0000FF00
+#define IPU_CSI0_CPD_GRS_0__CSI0_CPD_GRS0 0x1E03007C,0x000000FF
+
+#define IPU_CSI0_CPD_GRS_1__ADDR         0x1E030080
+#define IPU_CSI0_CPD_GRS_1__EMPTY        0x1E030080,0x00000000
+#define IPU_CSI0_CPD_GRS_1__FULL         0x1E030080,0xffffffff
+#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS7 0x1E030080,0xFF000000
+#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS6 0x1E030080,0x00FF0000
+#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS5 0x1E030080,0x0000FF00
+#define IPU_CSI0_CPD_GRS_1__CSI0_CPD_GRS4 0x1E030080,0x000000FF
+
+#define IPU_CSI0_CPD_GRS_2__ADDR          0x1E030084
+#define IPU_CSI0_CPD_GRS_2__EMPTY         0x1E030084,0x00000000
+#define IPU_CSI0_CPD_GRS_2__FULL          0x1E030084,0xffffffff
+#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS11 0x1E030084,0xFF000000
+#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS10 0x1E030084,0x00FF0000
+#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS9  0x1E030084,0x0000FF00
+#define IPU_CSI0_CPD_GRS_2__CSI0_CPD_GRS8  0x1E030084,0x000000FF
+
+#define IPU_CSI0_CPD_GRS_3__ADDR          0x1E030088
+#define IPU_CSI0_CPD_GRS_3__EMPTY         0x1E030088,0x00000000
+#define IPU_CSI0_CPD_GRS_3__FULL          0x1E030088,0xffffffff
+#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS15 0x1E030088,0xFF000000
+#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS14 0x1E030088,0x00FF0000
+#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS13 0x1E030088,0x0000FF00
+#define IPU_CSI0_CPD_GRS_3__CSI0_CPD_GRS12 0x1E030088,0x000000FF
+
+#define IPU_CSI0_CPD_GBC_0__ADDR         0x1E03008C
+#define IPU_CSI0_CPD_GBC_0__EMPTY        0x1E03008C,0x00000000
+#define IPU_CSI0_CPD_GBC_0__FULL         0x1E03008C,0xffffffff
+#define IPU_CSI0_CPD_GBC_0__CSI0_CPD_GBC1 0x1E03008C,0x01FF0000
+#define IPU_CSI0_CPD_GBC_0__CSI0_CPD_GBC0 0x1E03008C,0x000001FF
+
+#define IPU_CSI0_CPD_GBC_1__ADDR         0x1E030090
+#define IPU_CSI0_CPD_GBC_1__EMPTY        0x1E030090,0x00000000
+#define IPU_CSI0_CPD_GBC_1__FULL         0x1E030090,0xffffffff
+#define IPU_CSI0_CPD_GBC_1__CSI0_CPD_GBC3 0x1E030090,0x01FF0000
+#define IPU_CSI0_CPD_GBC_1__CSI0_CPD_GBC2 0x1E030090,0x000001FF
+
+#define IPU_CSI0_CPD_GBC_2__ADDR         0x1E030094
+#define IPU_CSI0_CPD_GBC_2__EMPTY        0x1E030094,0x00000000
+#define IPU_CSI0_CPD_GBC_2__FULL         0x1E030094,0xffffffff
+#define IPU_CSI0_CPD_GBC_2__CSI0_CPD_GBC5 0x1E030094,0x01FF0000
+#define IPU_CSI0_CPD_GBC_2__CSI0_CPD_GBC4 0x1E030094,0x000001FF
+
+#define IPU_CSI0_CPD_GBC_3__ADDR         0x1E030098
+#define IPU_CSI0_CPD_GBC_3__EMPTY        0x1E030098,0x00000000
+#define IPU_CSI0_CPD_GBC_3__FULL         0x1E030098,0xffffffff
+#define IPU_CSI0_CPD_GBC_3__CSI0_CPD_GBC7 0x1E030098,0x01FF0000
+#define IPU_CSI0_CPD_GBC_3__CSI0_CPD_GBC6 0x1E030098,0x000001FF
+
+#define IPU_CSI0_CPD_GBC_4__ADDR         0x1E03009C
+#define IPU_CSI0_CPD_GBC_4__EMPTY        0x1E03009C,0x00000000
+#define IPU_CSI0_CPD_GBC_4__FULL         0x1E03009C,0xffffffff
+#define IPU_CSI0_CPD_GBC_4__CSI0_CPD_GBC9 0x1E03009C,0x01FF0000
+#define IPU_CSI0_CPD_GBC_4__CSI0_CPD_GBC8 0x1E03009C,0x000001FF
+
+#define IPU_CSI0_CPD_GBC_5__ADDR          0x1E0300A0
+#define IPU_CSI0_CPD_GBC_5__EMPTY         0x1E0300A0,0x00000000
+#define IPU_CSI0_CPD_GBC_5__FULL          0x1E0300A0,0xffffffff
+#define IPU_CSI0_CPD_GBC_5__CSI0_CPD_GBC11 0x1E0300A0,0x01FF0000
+#define IPU_CSI0_CPD_GBC_5__CSI0_CPD_GBC10 0x1E0300A0,0x000001FF
+
+#define IPU_CSI0_CPD_GBC_6__ADDR          0x1E0300A4
+#define IPU_CSI0_CPD_GBC_6__EMPTY         0x1E0300A4,0x00000000
+#define IPU_CSI0_CPD_GBC_6__FULL          0x1E0300A4,0xffffffff
+#define IPU_CSI0_CPD_GBC_6__CSI0_CPD_GBC13 0x1E0300A4,0x01FF0000
+#define IPU_CSI0_CPD_GBC_6__CSI0_CPD_GBC12 0x1E0300A4,0x000001FF
+
+#define IPU_CSI0_CPD_GBC_7__ADDR          0x1E0300A8
+#define IPU_CSI0_CPD_GBC_7__EMPTY         0x1E0300A8,0x00000000
+#define IPU_CSI0_CPD_GBC_7__FULL          0x1E0300A8,0xffffffff
+#define IPU_CSI0_CPD_GBC_7__CSI0_CPD_GBC15 0x1E0300A8,0x01FF0000
+#define IPU_CSI0_CPD_GBC_7__CSI0_CPD_GBC14 0x1E0300A8,0x000001FF
+
+#define IPU_CSI0_CPD_GBS_0__ADDR         0x1E0300AC
+#define IPU_CSI0_CPD_GBS_0__EMPTY        0x1E0300AC,0x00000000
+#define IPU_CSI0_CPD_GBS_0__FULL         0x1E0300AC,0xffffffff
+#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS3 0x1E0300AC,0xFF000000
+#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS2 0x1E0300AC,0x00FF0000
+#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS1 0x1E0300AC,0x0000FF00
+#define IPU_CSI0_CPD_GBS_0__CSI0_CPD_GBS0 0x1E0300AC,0x000000FF
+
+#define IPU_CSI0_CPD_GBS_1__ADDR         0x1E0300B0
+#define IPU_CSI0_CPD_GBS_1__EMPTY        0x1E0300B0,0x00000000
+#define IPU_CSI0_CPD_GBS_1__FULL         0x1E0300B0,0xffffffff
+#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS7 0x1E0300B0,0xFF000000
+#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS6 0x1E0300B0,0x00FF0000
+#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS5 0x1E0300B0,0x0000FF00
+#define IPU_CSI0_CPD_GBS_1__CSI0_CPD_GBS4 0x1E0300B0,0x000000FF
+
+#define IPU_CSI0_CPD_GBS_2__ADDR          0x1E0300B4
+#define IPU_CSI0_CPD_GBS_2__EMPTY         0x1E0300B4,0x00000000
+#define IPU_CSI0_CPD_GBS_2__FULL          0x1E0300B4,0xffffffff
+#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS11 0x1E0300B4,0xFF000000
+#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS10 0x1E0300B4,0x00FF0000
+#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS9  0x1E0300B4,0x0000FF00
+#define IPU_CSI0_CPD_GBS_2__CSI0_CPD_GBS8  0x1E0300B4,0x000000FF
+
+#define IPU_CSI0_CPD_GBS_3__ADDR          0x1E0300B8
+#define IPU_CSI0_CPD_GBS_3__EMPTY         0x1E0300B8,0x00000000
+#define IPU_CSI0_CPD_GBS_3__FULL          0x1E0300B8,0xffffffff
+#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS15 0x1E0300B8,0xFF000000
+#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS14 0x1E0300B8,0x00FF0000
+#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS13 0x1E0300B8,0x0000FF00
+#define IPU_CSI0_CPD_GBS_3__CSI0_CPD_GBS12 0x1E0300B8,0x000000FF
+
+#define IPU_CSI0_CPD_BC_0__ADDR                0x1E0300BC
+#define IPU_CSI0_CPD_BC_0__EMPTY       0x1E0300BC,0x00000000
+#define IPU_CSI0_CPD_BC_0__FULL                0x1E0300BC,0xffffffff
+#define IPU_CSI0_CPD_BC_0__CSI0_CPD_BC1 0x1E0300BC,0x01FF0000
+#define IPU_CSI0_CPD_BC_0__CSI0_CPD_BC0 0x1E0300BC,0x000001FF
+
+#define IPU_CSI0_CPD_BC_1__ADDR                0x1E0300C0
+#define IPU_CSI0_CPD_BC_1__EMPTY       0x1E0300C0,0x00000000
+#define IPU_CSI0_CPD_BC_1__FULL                0x1E0300C0,0xffffffff
+#define IPU_CSI0_CPD_BC_1__CSI0_CPD_BC3 0x1E0300C0,0x01FF0000
+#define IPU_CSI0_CPD_BC_1__CSI0_CPD_BC2 0x1E0300C0,0x000001FF
+
+#define IPU_CSI0_CPD_BC_2__ADDR                0x1E0300C4
+#define IPU_CSI0_CPD_BC_2__EMPTY       0x1E0300C4,0x00000000
+#define IPU_CSI0_CPD_BC_2__FULL                0x1E0300C4,0xffffffff
+#define IPU_CSI0_CPD_BC_2__CSI0_CPD_BC5 0x1E0300C4,0x01FF0000
+#define IPU_CSI0_CPD_BC_2__CSI0_CPD_BC4 0x1E0300C4,0x000001FF
+
+#define IPU_CSI0_CPD_BC_3__ADDR                0x1E0300C8
+#define IPU_CSI0_CPD_BC_3__EMPTY       0x1E0300C8,0x00000000
+#define IPU_CSI0_CPD_BC_3__FULL                0x1E0300C8,0xffffffff
+#define IPU_CSI0_CPD_BC_3__CSI0_CPD_BC7 0x1E0300C8,0x01FF0000
+#define IPU_CSI0_CPD_BC_3__CSI0_CPD_BC6 0x1E0300C8,0x000001FF
+
+#define IPU_CSI0_CPD_BC_4__ADDR                0x1E0300CC
+#define IPU_CSI0_CPD_BC_4__EMPTY       0x1E0300CC,0x00000000
+#define IPU_CSI0_CPD_BC_4__FULL                0x1E0300CC,0xffffffff
+#define IPU_CSI0_CPD_BC_4__CSI0_CPD_BC9 0x1E0300CC,0x01FF0000
+#define IPU_CSI0_CPD_BC_4__CSI0_CPD_BC8 0x1E0300CC,0x000001FF
+
+#define IPU_CSI0_CPD_BC_5__ADDR                 0x1E0300D0
+#define IPU_CSI0_CPD_BC_5__EMPTY        0x1E0300D0,0x00000000
+#define IPU_CSI0_CPD_BC_5__FULL                 0x1E0300D0,0xffffffff
+#define IPU_CSI0_CPD_BC_5__CSI0_CPD_BC11 0x1E0300D0,0x01FF0000
+#define IPU_CSI0_CPD_BC_5__CSI0_CPD_BC10 0x1E0300D0,0x000001FF
+
+#define IPU_CSI0_CPD_BC_6__ADDR                 0x1E0300D4
+#define IPU_CSI0_CPD_BC_6__EMPTY        0x1E0300D4,0x00000000
+#define IPU_CSI0_CPD_BC_6__FULL                 0x1E0300D4,0xffffffff
+#define IPU_CSI0_CPD_BC_6__CSI0_CPD_BC13 0x1E0300D4,0x01FF0000
+#define IPU_CSI0_CPD_BC_6__CSI0_CPD_BC12 0x1E0300D4,0x000001FF
+
+#define IPU_CSI0_CPD_BC_7__ADDR                 0x1E0300D8
+#define IPU_CSI0_CPD_BC_7__EMPTY        0x1E0300D8,0x00000000
+#define IPU_CSI0_CPD_BC_7__FULL                 0x1E0300D8,0xffffffff
+#define IPU_CSI0_CPD_BC_7__CSI0_CPD_BC15 0x1E0300D8,0x01FF0000
+#define IPU_CSI0_CPD_BC_7__CSI0_CPD_BC14 0x1E0300D8,0x000001FF
+
+#define IPU_CSI0_CPD_BS_0__ADDR                0x1E0300DC
+#define IPU_CSI0_CPD_BS_0__EMPTY       0x1E0300DC,0x00000000
+#define IPU_CSI0_CPD_BS_0__FULL                0x1E0300DC,0xffffffff
+#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS3 0x1E0300DC,0xFF000000
+#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS2 0x1E0300DC,0x00FF0000
+#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS1 0x1E0300DC,0x0000FF00
+#define IPU_CSI0_CPD_BS_0__CSI0_CPD_BS0 0x1E0300DC,0x000000FF
+
+#define IPU_CSI0_CPD_BS_1__ADDR                0x1E0300E0
+#define IPU_CSI0_CPD_BS_1__EMPTY       0x1E0300E0,0x00000000
+#define IPU_CSI0_CPD_BS_1__FULL                0x1E0300E0,0xffffffff
+#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS7 0x1E0300E0,0xFF000000
+#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS6 0x1E0300E0,0x00FF0000
+#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS5 0x1E0300E0,0x0000FF00
+#define IPU_CSI0_CPD_BS_1__CSI0_CPD_BS4 0x1E0300E0,0x000000FF
+
+#define IPU_CSI0_CPD_BS_2__ADDR                 0x1E0300E4
+#define IPU_CSI0_CPD_BS_2__EMPTY        0x1E0300E4,0x00000000
+#define IPU_CSI0_CPD_BS_2__FULL                 0x1E0300E4,0xffffffff
+#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS11 0x1E0300E4,0xFF000000
+#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS10 0x1E0300E4,0x00FF0000
+#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS9         0x1E0300E4,0x0000FF00
+#define IPU_CSI0_CPD_BS_2__CSI0_CPD_BS8         0x1E0300E4,0x000000FF
+
+#define IPU_CSI0_CPD_BS_3__ADDR                 0x1E0300E8
+#define IPU_CSI0_CPD_BS_3__EMPTY        0x1E0300E8,0x00000000
+#define IPU_CSI0_CPD_BS_3__FULL                 0x1E0300E8,0xffffffff
+#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS15 0x1E0300E8,0xFF000000
+#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS14 0x1E0300E8,0x00FF0000
+#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS13 0x1E0300E8,0x0000FF00
+#define IPU_CSI0_CPD_BS_3__CSI0_CPD_BS12 0x1E0300E8,0x000000FF
+
+#define IPU_CSI0_CPD_OFFSET1__ADDR              0x1E0300EC
+#define IPU_CSI0_CPD_OFFSET1__EMPTY             0x1E0300EC,0x00000000
+#define IPU_CSI0_CPD_OFFSET1__FULL              0x1E0300EC,0xffffffff
+#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_B_OFFSET         0x1E0300EC,0x3FF00000
+#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_GB_OFFSET 0x1E0300EC,0x000FFC00
+#define IPU_CSI0_CPD_OFFSET1__CSI0_CPD_GR_OFFSET 0x1E0300EC,0x000003FF
+
+#define IPU_CSI0_CPD_OFFSET2__ADDR             0x1E0300F0
+#define IPU_CSI0_CPD_OFFSET2__EMPTY            0x1E0300F0,0x00000000
+#define IPU_CSI0_CPD_OFFSET2__FULL             0x1E0300F0,0xffffffff
+#define IPU_CSI0_CPD_OFFSET2__CSI0_CPD_R_OFFSET 0x1E0300F0,0x000003FF
+
+#define IPU_CSI1_SENS_CONF__ADDR                 0x1E038000
+#define IPU_CSI1_SENS_CONF__EMPTY                0x1E038000,0x00000000
+#define IPU_CSI1_SENS_CONF__FULL                 0x1E038000,0xffffffff
+#define IPU_CSI1_SENS_CONF__CSI1_DATA_EN_POL     0x1E038000,0x80000000
+#define IPU_CSI1_SENS_CONF__CSI1_FORCE_EOF       0x1E038000,0x20000000
+#define IPU_CSI1_SENS_CONF__CSI1_JPEG_MODE       0x1E038000,0x10000000
+#define IPU_CSI1_SENS_CONF__CSI1_JPEG8_EN        0x1E038000,0x08000000
+#define IPU_CSI1_SENS_CONF__CSI1_DATA_DEST       0x1E038000,0x07000000
+#define IPU_CSI1_SENS_CONF__CSI1_DIV_RATIO       0x1E038000,0x00FF0000
+#define IPU_CSI1_SENS_CONF__CSI1_EXT_VSYNC       0x1E038000,0x00008000
+#define IPU_CSI1_SENS_CONF__CSI1_DATA_WIDTH      0x1E038000,0x00007800
+#define IPU_CSI1_SENS_CONF__CSI1_SENS_DATA_FORMAT 0x1E038000,0x00000700
+#define IPU_CSI1_SENS_CONF__CSI1_PACK_TIGHT      0x1E038000,0x00000080
+#define IPU_CSI1_SENS_CONF__CSI1_SENS_PRTCL      0x1E038000,0x00000070
+#define IPU_CSI1_SENS_CONF__CSI1_SENS_PIX_CLK_POL 0x1E038000,0x00000008
+#define IPU_CSI1_SENS_CONF__CSI1_DATA_POL        0x1E038000,0x00000004
+#define IPU_CSI1_SENS_CONF__CSI1_HSYNC_POL       0x1E038000,0x00000002
+#define IPU_CSI1_SENS_CONF__CSI1_VSYNC_POL       0x1E038000,0x00000001
+
+#define IPU_CSI1_SENS_FRM_SIZE__ADDR                0x1E038004
+#define IPU_CSI1_SENS_FRM_SIZE__EMPTY               0x1E038004,0x00000000
+#define IPU_CSI1_SENS_FRM_SIZE__FULL                0x1E038004,0xffffffff
+#define IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_HEIGHT 0x1E038004,0x0FFF0000
+#define IPU_CSI1_SENS_FRM_SIZE__CSI1_SENS_FRM_WIDTH  0x1E038004,0x00001FFF
+
+#define IPU_CSI1_ACT_FRM_SIZE__ADDR               0x1E038008
+#define IPU_CSI1_ACT_FRM_SIZE__EMPTY              0x1E038008,0x00000000
+#define IPU_CSI1_ACT_FRM_SIZE__FULL               0x1E038008,0xffffffff
+#define IPU_CSI1_ACT_FRM_SIZE__CSI1_ACT_FRM_HEIGHT 0x1E038008,0x0FFF0000
+#define IPU_CSI1_ACT_FRM_SIZE__CSI1_ACT_FRM_WIDTH  0x1E038008,0x00001FFF
+
+#define IPU_CSI1_OUT_FRM_CTRL__ADDR          0x1E03800C
+#define IPU_CSI1_OUT_FRM_CTRL__EMPTY         0x1E03800C,0x00000000
+#define IPU_CSI1_OUT_FRM_CTRL__FULL          0x1E03800C,0xffffffff
+#define IPU_CSI1_OUT_FRM_CTRL__CSI1_HORZ_DWNS 0x1E03800C,0x80000000
+#define IPU_CSI1_OUT_FRM_CTRL__CSI1_VERT_DWNS 0x1E03800C,0x40000000
+#define IPU_CSI1_OUT_FRM_CTRL__CSI1_HSC              0x1E03800C,0x1FFF0000
+#define IPU_CSI1_OUT_FRM_CTRL__CSI1_VSC              0x1E03800C,0x00000FFF
+
+#define IPU_CSI1_TST_CTRL__ADDR                      0x1E038010
+#define IPU_CSI1_TST_CTRL__EMPTY             0x1E038010,0x00000000
+#define IPU_CSI1_TST_CTRL__FULL                      0x1E038010,0xffffffff
+#define IPU_CSI1_TST_CTRL__CSI1_TEST_GEN_MODE 0x1E038010,0x01000000
+#define IPU_CSI1_TST_CTRL__CSI1_PG_B_VALUE    0x1E038010,0x00FF0000
+#define IPU_CSI1_TST_CTRL__CSI1_PG_G_VALUE    0x1E038010,0x0000FF00
+#define IPU_CSI1_TST_CTRL__CSI1_PG_R_VALUE    0x1E038010,0x000000FF
+
+#define IPU_CSI1_CCIR_CODE_1__ADDR                   0x1E038014
+#define IPU_CSI1_CCIR_CODE_1__EMPTY                  0x1E038014,0x00000000
+#define IPU_CSI1_CCIR_CODE_1__FULL                   0x1E038014,0xffffffff
+#define IPU_CSI1_CCIR_CODE_1__CSI1_CCIR_ERR_DET_EN    0x1E038014,0x01000000
+#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_ACTV     0x1E038014,0x00380000
+#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_ACTV      0x1E038014,0x00070000
+#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_BLNK_2ND 0x1E038014,0x00000E00
+#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_BLNK_2ND  0x1E038014,0x000001C0
+#define IPU_CSI1_CCIR_CODE_1__CSI1_STRT_FLD0_BLNK_1ST 0x1E038014,0x00000038
+#define IPU_CSI1_CCIR_CODE_1__CSI1_END_FLD0_BLNK_1ST  0x1E038014,0x00000007
+
+#define IPU_CSI1_CCIR_CODE_2__ADDR                   0x1E038018
+#define IPU_CSI1_CCIR_CODE_2__EMPTY                  0x1E038018,0x00000000
+#define IPU_CSI1_CCIR_CODE_2__FULL                   0x1E038018,0xffffffff
+#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_ACTV     0x1E038018,0x00380000
+#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_ACTV      0x1E038018,0x00070000
+#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_BLNK_2ND 0x1E038018,0x00000E00
+#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_BLNK_2ND  0x1E038018,0x000001C0
+#define IPU_CSI1_CCIR_CODE_2__CSI1_STRT_FLD1_BLNK_1ST 0x1E038018,0x00000038
+#define IPU_CSI1_CCIR_CODE_2__CSI1_END_FLD1_BLNK_1ST  0x1E038018,0x00000007
+
+#define IPU_CSI1_CCIR_CODE_3__ADDR            0x1E03801C
+#define IPU_CSI1_CCIR_CODE_3__EMPTY           0x1E03801C,0x00000000
+#define IPU_CSI1_CCIR_CODE_3__FULL            0x1E03801C,0xffffffff
+#define IPU_CSI1_CCIR_CODE_3__CSI1_CCIR_PRECOM 0x1E03801C,0x3FFFFFFF
+
+#define IPU_CSI1_DI__ADDR         0x1E038020
+#define IPU_CSI1_DI__EMPTY        0x1E038020,0x00000000
+#define IPU_CSI1_DI__FULL         0x1E038020,0xffffffff
+#define IPU_CSI1_DI__CSI1_MIPI_DI3 0x1E038020,0xFF000000
+#define IPU_CSI1_DI__CSI1_MIPI_DI2 0x1E038020,0x00FF0000
+#define IPU_CSI1_DI__CSI1_MIPI_DI1 0x1E038020,0x0000FF00
+#define IPU_CSI1_DI__CSI1_MIPI_DI0 0x1E038020,0x000000FF
+
+#define IPU_CSI1_SKIP__ADDR                    0x1E038024
+#define IPU_CSI1_SKIP__EMPTY                   0x1E038024,0x00000000
+#define IPU_CSI1_SKIP__FULL                    0x1E038024,0xffffffff
+#define IPU_CSI1_SKIP__CSI1_SKIP_ISP           0x1E038024,0x00F80000
+#define IPU_CSI1_SKIP__CSI1_MAX_RATIO_SKIP_ISP 0x1E038024,0x00070000
+#define IPU_CSI1_SKIP__CSI1_ID_2_SKIP          0x1E038024,0x00000300
+#define IPU_CSI1_SKIP__CSI1_SKIP_SMFC          0x1E038024,0x000000F8
+#define IPU_CSI1_SKIP__CSI1_MAX_RATIO_SKIP_SMFC 0x1E038024,0x00000007
+
+#define IPU_CSI1_CPD_CTRL__ADDR                      0x1E038028
+#define IPU_CSI1_CPD_CTRL__EMPTY             0x1E038028,0x00000000
+#define IPU_CSI1_CPD_CTRL__FULL                      0x1E038028,0xffffffff
+#define IPU_CSI1_CPD_CTRL__CSI1_CPD          0x1E038028,0x0000001C
+#define IPU_CSI1_CPD_CTRL__CSI1_RED_ROW_BEGIN 0x1E038028,0x00000002
+#define IPU_CSI1_CPD_CTRL__CSI1_GREEN_P_BEGIN 0x1E038028,0x00000001
+
+#define IPU_CSI1_CPD_RC_0__ADDR                 0x1E03802C
+#define IPU_CSI1_CPD_RC_0__EMPTY        0x1E03802C,0x00000000
+#define IPU_CSI1_CPD_RC_0__FULL                 0x1E03802C,0xffffffff
+#define IPU_CSI1_CPD_RC_0__CSI1_CPD_RC_1 0x1E03802C,0x01FF0000
+#define IPU_CSI1_CPD_RC_0__CSI1_CPD_RC_0 0x1E03802C,0x000001FF
+
+#define IPU_CSI1_CPD_RC_1__ADDR                 0x1E038030
+#define IPU_CSI1_CPD_RC_1__EMPTY        0x1E038030,0x00000000
+#define IPU_CSI1_CPD_RC_1__FULL                 0x1E038030,0xffffffff
+#define IPU_CSI1_CPD_RC_1__CSI1_CPD_RC_3 0x1E038030,0x01FF0000
+#define IPU_CSI1_CPD_RC_1__CSI1_CPD_RC_2 0x1E038030,0x000001FF
+
+#define IPU_CSI1_CPD_RC_2__ADDR                 0x1E038034
+#define IPU_CSI1_CPD_RC_2__EMPTY        0x1E038034,0x00000000
+#define IPU_CSI1_CPD_RC_2__FULL                 0x1E038034,0xffffffff
+#define IPU_CSI1_CPD_RC_2__CSI1_CPD_RC_5 0x1E038034,0x01FF0000
+#define IPU_CSI1_CPD_RC_2__CSI1_CPD_RC_4 0x1E038034,0x000001FF
+
+#define IPU_CSI1_CPD_RC_3__ADDR                 0x1E038038
+#define IPU_CSI1_CPD_RC_3__EMPTY        0x1E038038,0x00000000
+#define IPU_CSI1_CPD_RC_3__FULL                 0x1E038038,0xffffffff
+#define IPU_CSI1_CPD_RC_3__CSI1_CPD_RC_7 0x1E038038,0x01FF0000
+#define IPU_CSI1_CPD_RC_3__CSI1_CPD_RC_6 0x1E038038,0x000001FF
+
+#define IPU_CSI1_CPD_RC_4__ADDR                 0x1E03803C
+#define IPU_CSI1_CPD_RC_4__EMPTY        0x1E03803C,0x00000000
+#define IPU_CSI1_CPD_RC_4__FULL                 0x1E03803C,0xffffffff
+#define IPU_CSI1_CPD_RC_4__CSI1_CPD_RC_9 0x1E03803C,0x01FF0000
+#define IPU_CSI1_CPD_RC_4__CSI1_CPD_RC_8 0x1E03803C,0x000001FF
+
+#define IPU_CSI1_CPD_RC_5__ADDR                  0x1E038040
+#define IPU_CSI1_CPD_RC_5__EMPTY         0x1E038040,0x00000000
+#define IPU_CSI1_CPD_RC_5__FULL                  0x1E038040,0xffffffff
+#define IPU_CSI1_CPD_RC_5__CSI1_CPD_RC_11 0x1E038040,0x01FF0000
+#define IPU_CSI1_CPD_RC_5__CSI1_CPD_RC_10 0x1E038040,0x000001FF
+
+#define IPU_CSI1_CPD_RC_6__ADDR                  0x1E038044
+#define IPU_CSI1_CPD_RC_6__EMPTY         0x1E038044,0x00000000
+#define IPU_CSI1_CPD_RC_6__FULL                  0x1E038044,0xffffffff
+#define IPU_CSI1_CPD_RC_6__CSI1_CPD_RC_13 0x1E038044,0x01FF0000
+#define IPU_CSI1_CPD_RC_6__CSI1_CPD_RC_12 0x1E038044,0x000001FF
+
+#define IPU_CSI1_CPD_RC_7__ADDR                  0x1E038048
+#define IPU_CSI1_CPD_RC_7__EMPTY         0x1E038048,0x00000000
+#define IPU_CSI1_CPD_RC_7__FULL                  0x1E038048,0xffffffff
+#define IPU_CSI1_CPD_RC_7__CSI1_CPD_RC_15 0x1E038048,0x01FF0000
+#define IPU_CSI1_CPD_RC_7__CSI1_CPD_RC_14 0x1E038048,0x000001FF
+
+#define IPU_CSI1_CPD_RS_0__ADDR                0x1E03804C
+#define IPU_CSI1_CPD_RS_0__EMPTY       0x1E03804C,0x00000000
+#define IPU_CSI1_CPD_RS_0__FULL                0x1E03804C,0xffffffff
+#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS3 0x1E03804C,0xFF000000
+#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS2 0x1E03804C,0x00FF0000
+#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS1 0x1E03804C,0x0000FF00
+#define IPU_CSI1_CPD_RS_0__CSI1_CPD_RS0 0x1E03804C,0x000000FF
+
+#define IPU_CSI1_CPD_RS_1__ADDR                0x1E038050
+#define IPU_CSI1_CPD_RS_1__EMPTY       0x1E038050,0x00000000
+#define IPU_CSI1_CPD_RS_1__FULL                0x1E038050,0xffffffff
+#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS7 0x1E038050,0xFF000000
+#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS6 0x1E038050,0x00FF0000
+#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS5 0x1E038050,0x0000FF00
+#define IPU_CSI1_CPD_RS_1__CSI1_CPD_RS4 0x1E038050,0x000000FF
+
+#define IPU_CSI1_CPD_RS_2__ADDR                 0x1E038054
+#define IPU_CSI1_CPD_RS_2__EMPTY        0x1E038054,0x00000000
+#define IPU_CSI1_CPD_RS_2__FULL                 0x1E038054,0xffffffff
+#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS11 0x1E038054,0xFF000000
+#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS10 0x1E038054,0x00FF0000
+#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS9         0x1E038054,0x0000FF00
+#define IPU_CSI1_CPD_RS_2__CSI1_CPD_RS8         0x1E038054,0x000000FF
+
+#define IPU_CSI1_CPD_RS_3__ADDR                 0x1E038058
+#define IPU_CSI1_CPD_RS_3__EMPTY        0x1E038058,0x00000000
+#define IPU_CSI1_CPD_RS_3__FULL                 0x1E038058,0xffffffff
+#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS15 0x1E038058,0xFF000000
+#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS14 0x1E038058,0x00FF0000
+#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS13 0x1E038058,0x0000FF00
+#define IPU_CSI1_CPD_RS_3__CSI1_CPD_RS12 0x1E038058,0x000000FF
+
+#define IPU_CSI1_CPD_GRC_0__ADDR         0x1E03805C
+#define IPU_CSI1_CPD_GRC_0__EMPTY        0x1E03805C,0x00000000
+#define IPU_CSI1_CPD_GRC_0__FULL         0x1E03805C,0xffffffff
+#define IPU_CSI1_CPD_GRC_0__CSI1_CPD_GRC1 0x1E03805C,0x01FF0000
+#define IPU_CSI1_CPD_GRC_0__CSI1_CPD_GRC0 0x1E03805C,0x000001FF
+
+#define IPU_CSI1_CPD_GRC_1__ADDR         0x1E038060
+#define IPU_CSI1_CPD_GRC_1__EMPTY        0x1E038060,0x00000000
+#define IPU_CSI1_CPD_GRC_1__FULL         0x1E038060,0xffffffff
+#define IPU_CSI1_CPD_GRC_1__CSI1_CPD_GRC3 0x1E038060,0x01FF0000
+#define IPU_CSI1_CPD_GRC_1__CSI1_CPD_GRC2 0x1E038060,0x000001FF
+
+#define IPU_CSI1_CPD_GRC_2__ADDR         0x1E038064
+#define IPU_CSI1_CPD_GRC_2__EMPTY        0x1E038064,0x00000000
+#define IPU_CSI1_CPD_GRC_2__FULL         0x1E038064,0xffffffff
+#define IPU_CSI1_CPD_GRC_2__CSI1_CPD_GRC5 0x1E038064,0x01FF0000
+#define IPU_CSI1_CPD_GRC_2__CSI1_CPD_GRC4 0x1E038064,0x000001FF
+
+#define IPU_CSI1_CPD_GRC_3__ADDR         0x1E038068
+#define IPU_CSI1_CPD_GRC_3__EMPTY        0x1E038068,0x00000000
+#define IPU_CSI1_CPD_GRC_3__FULL         0x1E038068,0xffffffff
+#define IPU_CSI1_CPD_GRC_3__CSI1_CPD_GRC7 0x1E038068,0x01FF0000
+#define IPU_CSI1_CPD_GRC_3__CSI1_CPD_GRC6 0x1E038068,0x000001FF
+
+#define IPU_CSI1_CPD_GRC_4__ADDR         0x1E03806C
+#define IPU_CSI1_CPD_GRC_4__EMPTY        0x1E03806C,0x00000000
+#define IPU_CSI1_CPD_GRC_4__FULL         0x1E03806C,0xffffffff
+#define IPU_CSI1_CPD_GRC_4__CSI1_CPD_GRC9 0x1E03806C,0x01FF0000
+#define IPU_CSI1_CPD_GRC_4__CSI1_CPD_GRC8 0x1E03806C,0x000001FF
+
+#define IPU_CSI1_CPD_GRC_5__ADDR          0x1E038070
+#define IPU_CSI1_CPD_GRC_5__EMPTY         0x1E038070,0x00000000
+#define IPU_CSI1_CPD_GRC_5__FULL          0x1E038070,0xffffffff
+#define IPU_CSI1_CPD_GRC_5__CSI1_CPD_GRC11 0x1E038070,0x01FF0000
+#define IPU_CSI1_CPD_GRC_5__CSI1_CPD_GRC10 0x1E038070,0x000001FF
+
+#define IPU_CSI1_CPD_GRC_6__ADDR          0x1E038074
+#define IPU_CSI1_CPD_GRC_6__EMPTY         0x1E038074,0x00000000
+#define IPU_CSI1_CPD_GRC_6__FULL          0x1E038074,0xffffffff
+#define IPU_CSI1_CPD_GRC_6__CSI1_CPD_GRC13 0x1E038074,0x01FF0000
+#define IPU_CSI1_CPD_GRC_6__CSI1_CPD_GRC12 0x1E038074,0x000001FF
+
+#define IPU_CSI1_CPD_GRC_7__ADDR          0x1E038078
+#define IPU_CSI1_CPD_GRC_7__EMPTY         0x1E038078,0x00000000
+#define IPU_CSI1_CPD_GRC_7__FULL          0x1E038078,0xffffffff
+#define IPU_CSI1_CPD_GRC_7__CSI1_CPD_GRC15 0x1E038078,0x01FF0000
+#define IPU_CSI1_CPD_GRC_7__CSI1_CPD_GRC14 0x1E038078,0x000001FF
+
+#define IPU_CSI1_CPD_GRS_0__ADDR         0x1E03807C
+#define IPU_CSI1_CPD_GRS_0__EMPTY        0x1E03807C,0x00000000
+#define IPU_CSI1_CPD_GRS_0__FULL         0x1E03807C,0xffffffff
+#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS3 0x1E03807C,0xFF000000
+#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS2 0x1E03807C,0x00FF0000
+#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS1 0x1E03807C,0x0000FF00
+#define IPU_CSI1_CPD_GRS_0__CSI1_CPD_GRS0 0x1E03807C,0x000000FF
+
+#define IPU_CSI1_CPD_GRS_1__ADDR         0x1E038080
+#define IPU_CSI1_CPD_GRS_1__EMPTY        0x1E038080,0x00000000
+#define IPU_CSI1_CPD_GRS_1__FULL         0x1E038080,0xffffffff
+#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS7 0x1E038080,0xFF000000
+#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS6 0x1E038080,0x00FF0000
+#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS5 0x1E038080,0x0000FF00
+#define IPU_CSI1_CPD_GRS_1__CSI1_CPD_GRS4 0x1E038080,0x000000FF
+
+#define IPU_CSI1_CPD_GRS_2__ADDR          0x1E038084
+#define IPU_CSI1_CPD_GRS_2__EMPTY         0x1E038084,0x00000000
+#define IPU_CSI1_CPD_GRS_2__FULL          0x1E038084,0xffffffff
+#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS11 0x1E038084,0xFF000000
+#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS10 0x1E038084,0x00FF0000
+#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS9  0x1E038084,0x0000FF00
+#define IPU_CSI1_CPD_GRS_2__CSI1_CPD_GRS8  0x1E038084,0x000000FF
+
+#define IPU_CSI1_CPD_GRS_3__ADDR          0x1E038088
+#define IPU_CSI1_CPD_GRS_3__EMPTY         0x1E038088,0x00000000
+#define IPU_CSI1_CPD_GRS_3__FULL          0x1E038088,0xffffffff
+#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS15 0x1E038088,0xFF000000
+#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS14 0x1E038088,0x00FF0000
+#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS13 0x1E038088,0x0000FF00
+#define IPU_CSI1_CPD_GRS_3__CSI1_CPD_GRS12 0x1E038088,0x000000FF
+
+#define IPU_CSI1_CPD_GBC_0__ADDR         0x1E03808C
+#define IPU_CSI1_CPD_GBC_0__EMPTY        0x1E03808C,0x00000000
+#define IPU_CSI1_CPD_GBC_0__FULL         0x1E03808C,0xffffffff
+#define IPU_CSI1_CPD_GBC_0__CSI1_CPD_GBC1 0x1E03808C,0x01FF0000
+#define IPU_CSI1_CPD_GBC_0__CSI1_CPD_GBC0 0x1E03808C,0x000001FF
+
+#define IPU_CSI1_CPD_GBC_1__ADDR         0x1E038090
+#define IPU_CSI1_CPD_GBC_1__EMPTY        0x1E038090,0x00000000
+#define IPU_CSI1_CPD_GBC_1__FULL         0x1E038090,0xffffffff
+#define IPU_CSI1_CPD_GBC_1__CSI1_CPD_GBC3 0x1E038090,0x01FF0000
+#define IPU_CSI1_CPD_GBC_1__CSI1_CPD_GBC2 0x1E038090,0x000001FF
+
+#define IPU_CSI1_CPD_GBC_2__ADDR         0x1E038094
+#define IPU_CSI1_CPD_GBC_2__EMPTY        0x1E038094,0x00000000
+#define IPU_CSI1_CPD_GBC_2__FULL         0x1E038094,0xffffffff
+#define IPU_CSI1_CPD_GBC_2__CSI1_CPD_GBC5 0x1E038094,0x01FF0000
+#define IPU_CSI1_CPD_GBC_2__CSI1_CPD_GBC4 0x1E038094,0x000001FF
+
+#define IPU_CSI1_CPD_GBC_3__ADDR         0x1E038098
+#define IPU_CSI1_CPD_GBC_3__EMPTY        0x1E038098,0x00000000
+#define IPU_CSI1_CPD_GBC_3__FULL         0x1E038098,0xffffffff
+#define IPU_CSI1_CPD_GBC_3__CSI1_CPD_GBC7 0x1E038098,0x01FF0000
+#define IPU_CSI1_CPD_GBC_3__CSI1_CPD_GBC6 0x1E038098,0x000001FF
+
+#define IPU_CSI1_CPD_GBC_4__ADDR         0x1E03809C
+#define IPU_CSI1_CPD_GBC_4__EMPTY        0x1E03809C,0x00000000
+#define IPU_CSI1_CPD_GBC_4__FULL         0x1E03809C,0xffffffff
+#define IPU_CSI1_CPD_GBC_4__CSI1_CPD_GBC9 0x1E03809C,0x01FF0000
+#define IPU_CSI1_CPD_GBC_4__CSI1_CPD_GBC8 0x1E03809C,0x000001FF
+
+#define IPU_CSI1_CPD_GBC_5__ADDR          0x1E0380A0
+#define IPU_CSI1_CPD_GBC_5__EMPTY         0x1E0380A0,0x00000000
+#define IPU_CSI1_CPD_GBC_5__FULL          0x1E0380A0,0xffffffff
+#define IPU_CSI1_CPD_GBC_5__CSI1_CPD_GBC11 0x1E0380A0,0x01FF0000
+#define IPU_CSI1_CPD_GBC_5__CSI1_CPD_GBC10 0x1E0380A0,0x000001FF
+
+#define IPU_CSI1_CPD_GBC_6__ADDR          0x1E0380A4
+#define IPU_CSI1_CPD_GBC_6__EMPTY         0x1E0380A4,0x00000000
+#define IPU_CSI1_CPD_GBC_6__FULL          0x1E0380A4,0xffffffff
+#define IPU_CSI1_CPD_GBC_6__CSI1_CPD_GBC13 0x1E0380A4,0x01FF0000
+#define IPU_CSI1_CPD_GBC_6__CSI1_CPD_GBC12 0x1E0380A4,0x000001FF
+
+#define IPU_CSI1_CPD_GBC_7__ADDR          0x1E0380A8
+#define IPU_CSI1_CPD_GBC_7__EMPTY         0x1E0380A8,0x00000000
+#define IPU_CSI1_CPD_GBC_7__FULL          0x1E0380A8,0xffffffff
+#define IPU_CSI1_CPD_GBC_7__CSI1_CPD_GBC15 0x1E0380A8,0x01FF0000
+#define IPU_CSI1_CPD_GBC_7__CSI1_CPD_GBC14 0x1E0380A8,0x000001FF
+
+#define IPU_CSI1_CPD_GBS_0__ADDR         0x1E0380AC
+#define IPU_CSI1_CPD_GBS_0__EMPTY        0x1E0380AC,0x00000000
+#define IPU_CSI1_CPD_GBS_0__FULL         0x1E0380AC,0xffffffff
+#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS3 0x1E0380AC,0xFF000000
+#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS2 0x1E0380AC,0x00FF0000
+#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS1 0x1E0380AC,0x0000FF00
+#define IPU_CSI1_CPD_GBS_0__CSI1_CPD_GBS0 0x1E0380AC,0x000000FF
+
+#define IPU_CSI1_CPD_GBS_1__ADDR         0x1E0380B0
+#define IPU_CSI1_CPD_GBS_1__EMPTY        0x1E0380B0,0x00000000
+#define IPU_CSI1_CPD_GBS_1__FULL         0x1E0380B0,0xffffffff
+#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS7 0x1E0380B0,0xFF000000
+#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS6 0x1E0380B0,0x00FF0000
+#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS5 0x1E0380B0,0x0000FF00
+#define IPU_CSI1_CPD_GBS_1__CSI1_CPD_GBS4 0x1E0380B0,0x000000FF
+
+#define IPU_CSI1_CPD_GBS_2__ADDR          0x1E0380B4
+#define IPU_CSI1_CPD_GBS_2__EMPTY         0x1E0380B4,0x00000000
+#define IPU_CSI1_CPD_GBS_2__FULL          0x1E0380B4,0xffffffff
+#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS11 0x1E0380B4,0xFF000000
+#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS10 0x1E0380B4,0x00FF0000
+#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS9  0x1E0380B4,0x0000FF00
+#define IPU_CSI1_CPD_GBS_2__CSI1_CPD_GBS8  0x1E0380B4,0x000000FF
+
+#define IPU_CSI1_CPD_GBS_3__ADDR          0x1E0380B8
+#define IPU_CSI1_CPD_GBS_3__EMPTY         0x1E0380B8,0x00000000
+#define IPU_CSI1_CPD_GBS_3__FULL          0x1E0380B8,0xffffffff
+#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS15 0x1E0380B8,0xFF000000
+#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS14 0x1E0380B8,0x00FF0000
+#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS13 0x1E0380B8,0x0000FF00
+#define IPU_CSI1_CPD_GBS_3__CSI1_CPD_GBS12 0x1E0380B8,0x000000FF
+
+#define IPU_CSI1_CPD_BC_0__ADDR                0x1E0380BC
+#define IPU_CSI1_CPD_BC_0__EMPTY       0x1E0380BC,0x00000000
+#define IPU_CSI1_CPD_BC_0__FULL                0x1E0380BC,0xffffffff
+#define IPU_CSI1_CPD_BC_0__CSI1_CPD_BC1 0x1E0380BC,0x01FF0000
+#define IPU_CSI1_CPD_BC_0__CSI1_CPD_BC0 0x1E0380BC,0x000001FF
+
+#define IPU_CSI1_CPD_BC_1__ADDR                0x1E0380C0
+#define IPU_CSI1_CPD_BC_1__EMPTY       0x1E0380C0,0x00000000
+#define IPU_CSI1_CPD_BC_1__FULL                0x1E0380C0,0xffffffff
+#define IPU_CSI1_CPD_BC_1__CSI1_CPD_BC3 0x1E0380C0,0x01FF0000
+#define IPU_CSI1_CPD_BC_1__CSI1_CPD_BC2 0x1E0380C0,0x000001FF
+
+#define IPU_CSI1_CPD_BC_2__ADDR                0x1E0380C4
+#define IPU_CSI1_CPD_BC_2__EMPTY       0x1E0380C4,0x00000000
+#define IPU_CSI1_CPD_BC_2__FULL                0x1E0380C4,0xffffffff
+#define IPU_CSI1_CPD_BC_2__CSI1_CPD_BC5 0x1E0380C4,0x01FF0000
+#define IPU_CSI1_CPD_BC_2__CSI1_CPD_BC4 0x1E0380C4,0x000001FF
+
+#define IPU_CSI1_CPD_BC_3__ADDR                0x1E0380C8
+#define IPU_CSI1_CPD_BC_3__EMPTY       0x1E0380C8,0x00000000
+#define IPU_CSI1_CPD_BC_3__FULL                0x1E0380C8,0xffffffff
+#define IPU_CSI1_CPD_BC_3__CSI1_CPD_BC7 0x1E0380C8,0x01FF0000
+#define IPU_CSI1_CPD_BC_3__CSI1_CPD_BC6 0x1E0380C8,0x000001FF
+
+#define IPU_CSI1_CPD_BC_4__ADDR                0x1E0380CC
+#define IPU_CSI1_CPD_BC_4__EMPTY       0x1E0380CC,0x00000000
+#define IPU_CSI1_CPD_BC_4__FULL                0x1E0380CC,0xffffffff
+#define IPU_CSI1_CPD_BC_4__CSI1_CPD_BC9 0x1E0380CC,0x01FF0000
+#define IPU_CSI1_CPD_BC_4__CSI1_CPD_BC8 0x1E0380CC,0x000001FF
+
+#define IPU_CSI1_CPD_BC_5__ADDR                 0x1E0380D0
+#define IPU_CSI1_CPD_BC_5__EMPTY        0x1E0380D0,0x00000000
+#define IPU_CSI1_CPD_BC_5__FULL                 0x1E0380D0,0xffffffff
+#define IPU_CSI1_CPD_BC_5__CSI1_CPD_BC11 0x1E0380D0,0x01FF0000
+#define IPU_CSI1_CPD_BC_5__CSI1_CPD_BC10 0x1E0380D0,0x000001FF
+
+#define IPU_CSI1_CPD_BC_6__ADDR                 0x1E0380D4
+#define IPU_CSI1_CPD_BC_6__EMPTY        0x1E0380D4,0x00000000
+#define IPU_CSI1_CPD_BC_6__FULL                 0x1E0380D4,0xffffffff
+#define IPU_CSI1_CPD_BC_6__CSI1_CPD_BC13 0x1E0380D4,0x01FF0000
+#define IPU_CSI1_CPD_BC_6__CSI1_CPD_BC12 0x1E0380D4,0x000001FF
+
+#define IPU_CSI1_CPD_BC_7__ADDR                 0x1E0380D8
+#define IPU_CSI1_CPD_BC_7__EMPTY        0x1E0380D8,0x00000000
+#define IPU_CSI1_CPD_BC_7__FULL                 0x1E0380D8,0xffffffff
+#define IPU_CSI1_CPD_BC_7__CSI1_CPD_BC15 0x1E0380D8,0x01FF0000
+#define IPU_CSI1_CPD_BC_7__CSI1_CPD_BC14 0x1E0380D8,0x000001FF
+
+#define IPU_CSI1_CPD_BS_0__ADDR                0x1E0380DC
+#define IPU_CSI1_CPD_BS_0__EMPTY       0x1E0380DC,0x00000000
+#define IPU_CSI1_CPD_BS_0__FULL                0x1E0380DC,0xffffffff
+#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS3 0x1E0380DC,0xFF000000
+#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS2 0x1E0380DC,0x00FF0000
+#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS1 0x1E0380DC,0x0000FF00
+#define IPU_CSI1_CPD_BS_0__CSI1_CPD_BS0 0x1E0380DC,0x000000FF
+
+#define IPU_CSI1_CPD_BS_1__ADDR                0x1E0380E0
+#define IPU_CSI1_CPD_BS_1__EMPTY       0x1E0380E0,0x00000000
+#define IPU_CSI1_CPD_BS_1__FULL                0x1E0380E0,0xffffffff
+#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS7 0x1E0380E0,0xFF000000
+#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS6 0x1E0380E0,0x00FF0000
+#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS5 0x1E0380E0,0x0000FF00
+#define IPU_CSI1_CPD_BS_1__CSI1_CPD_BS4 0x1E0380E0,0x000000FF
+
+#define IPU_CSI1_CPD_BS_2__ADDR                 0x1E0380E4
+#define IPU_CSI1_CPD_BS_2__EMPTY        0x1E0380E4,0x00000000
+#define IPU_CSI1_CPD_BS_2__FULL                 0x1E0380E4,0xffffffff
+#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS11 0x1E0380E4,0xFF000000
+#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS10 0x1E0380E4,0x00FF0000
+#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS9         0x1E0380E4,0x0000FF00
+#define IPU_CSI1_CPD_BS_2__CSI1_CPD_BS8         0x1E0380E4,0x000000FF
+
+#define IPU_CSI1_CPD_BS_3__ADDR                 0x1E0380E8
+#define IPU_CSI1_CPD_BS_3__EMPTY        0x1E0380E8,0x00000000
+#define IPU_CSI1_CPD_BS_3__FULL                 0x1E0380E8,0xffffffff
+#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS15 0x1E0380E8,0xFF000000
+#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS14 0x1E0380E8,0x00FF0000
+#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS13 0x1E0380E8,0x0000FF00
+#define IPU_CSI1_CPD_BS_3__CSI1_CPD_BS12 0x1E0380E8,0x000000FF
+
+#define IPU_CSI1_CPD_OFFSET1__ADDR              0x1E0380EC
+#define IPU_CSI1_CPD_OFFSET1__EMPTY             0x1E0380EC,0x00000000
+#define IPU_CSI1_CPD_OFFSET1__FULL              0x1E0380EC,0xffffffff
+#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_B_OFFSET         0x1E0380EC,0x3FF00000
+#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_GB_OFFSET 0x1E0380EC,0x000FFC00
+#define IPU_CSI1_CPD_OFFSET1__CSI1_CPD_GR_OFFSET 0x1E0380EC,0x000003FF
+
+#define IPU_CSI1_CPD_OFFSET2__ADDR             0x1E0380F0
+#define IPU_CSI1_CPD_OFFSET2__EMPTY            0x1E0380F0,0x00000000
+#define IPU_CSI1_CPD_OFFSET2__FULL             0x1E0380F0,0xffffffff
+#define IPU_CSI1_CPD_OFFSET2__CSI1_CPD_R_OFFSET 0x1E0380F0,0x000003FF
+// ================= End of IPUV3EX CSI Registers =====================
+
+// ================= Start of IPUV3EX DI Registers =====================
+#define IPU_DI0_GENERAL__ADDR                     0x1E040000
+#define IPU_DI0_GENERAL__EMPTY                    0x1E040000,0x00000000
+#define IPU_DI0_GENERAL__FULL                     0x1E040000,0xffffffff
+#define IPU_DI0_GENERAL__DI0_DISP_Y_SEL                   0x1E040000,0x70000000
+#define IPU_DI0_GENERAL__DI0_CLOCK_STOP_MODE   0x1E040000,0x0F000000
+#define IPU_DI0_GENERAL__DI0_DISP_CLOCK_INIT   0x1E040000,0x00800000
+#define IPU_DI0_GENERAL__DI0_MASK_SEL             0x1E040000,0x00400000
+#define IPU_DI0_GENERAL__DI0_VSYNC_EXT            0x1E040000,0x00200000
+#define IPU_DI0_GENERAL__DI0_CLK_EXT              0x1E040000,0x00100000
+#define IPU_DI0_GENERAL__DI0_WATCHDOG_MODE        0x1E040000,0x000C0000
+#define IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK 0x1E040000,0x00020000
+#define IPU_DI0_GENERAL__DI0_SYNC_COUNT_SEL       0x1E040000,0x0000F000
+#define IPU_DI0_GENERAL__DI0_ERR_TREATMENT        0x1E040000,0x00000800
+#define IPU_DI0_GENERAL__DI0_ERM_VSYNC_SEL        0x1E040000,0x00000400
+#define IPU_DI0_GENERAL__DI0_POLARITY_CS1         0x1E040000,0x00000200
+#define IPU_DI0_GENERAL__DI0_POLARITY_CS0         0x1E040000,0x00000100
+#define IPU_DI0_GENERAL__DI0_POLARITY_8                   0x1E040000,0x00000080
+#define IPU_DI0_GENERAL__DI0_POLARITY_7                   0x1E040000,0x00000040
+#define IPU_DI0_GENERAL__DI0_POLARITY_6                   0x1E040000,0x00000020
+#define IPU_DI0_GENERAL__DI0_POLARITY_5                   0x1E040000,0x00000010
+#define IPU_DI0_GENERAL__DI0_POLARITY_4                   0x1E040000,0x00000008
+#define IPU_DI0_GENERAL__DI0_POLARITY_3                   0x1E040000,0x00000004
+#define IPU_DI0_GENERAL__DI0_POLARITY_2                   0x1E040000,0x00000002
+#define IPU_DI0_GENERAL__DI0_POLARITY_1                   0x1E040000,0x00000001
+
+#define IPU_DI0_BS_CLKGEN0__ADDR               0x1E040004
+#define IPU_DI0_BS_CLKGEN0__EMPTY              0x1E040004,0x00000000
+#define IPU_DI0_BS_CLKGEN0__FULL               0x1E040004,0xffffffff
+#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET 0x1E040004,0x01FF0000
+#define IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD 0x1E040004,0x00000FFF
+
+#define IPU_DI0_BS_CLKGEN1__ADDR                 0x1E040008
+#define IPU_DI0_BS_CLKGEN1__EMPTY                0x1E040008,0x00000000
+#define IPU_DI0_BS_CLKGEN1__FULL                 0x1E040008,0xffffffff
+#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN 0x1E040008,0x01FF0000
+#define IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP      0x1E040008,0x000001FF
+
+#define DI_SWGEN0_ADDR(di, pointer)                            (IPU_DI0_GENERAL__ADDR + \
+                                                                                       di *0x8000 +                            \
+                                                                                       (pointer-1) * 0x4 + 0x000C)
+#define DI_SWGEN0_EMPTY(di, pointer)                                           DI_SWGEN0_ADDR(di, pointer), 0x00000000
+#define DI_SWGEN0_FULL(di, pointer)                                                    DI_SWGEN0_ADDR(di, pointer), 0xFFFFFFFF
+
+#define DI_SWGEN0_RUN_VALUE_M1(di, pointer)            DI_SWGEN0_ADDR(di, pointer), 0x7FF80000
+#define DI_SWGEN0_RUN_RESOL(di, pointer)                               DI_SWGEN0_ADDR(di, pointer), 0x00070000
+#define DI_SWGEN0_OFFSET_VALUE(di, pointer)                    DI_SWGEN0_ADDR(di, pointer), 0x00007FF8
+#define DI_SWGEN0_OFFSET_RESOL(di, pointer)                    DI_SWGEN0_ADDR(di, pointer), 0x00000007
+
+#define DI_SWGEN1_ADDR(di, pointer)                                                    (IPU_DI0_GENERAL__ADDR + \
+                                                                                                                                                                                       di *0x8000 + \
+                                                                                                                                                                                       (pointer-1) * 0x4 + 0x0030)
+#define DI_SWGEN1_EMPTY(di, pointer)                                           DI_SWGEN1_ADDR(di, pointer), 0x00000000
+#define DI_SWGEN1_FULL(di, pointer)                                                    DI_SWGEN1_ADDR(di, pointer), 0xFFFFFFFF
+
+#define DI_SWGEN1_CNT_POL_GEN_EN(di, pointer)  DI_SWGEN1_ADDR(di, pointer), 0x60000000
+#define DI_SWGEN1_CNT_AUTOLOAD(di, pointer)            DI_SWGEN1_ADDR(di, pointer), 0x10000000
+#define DI_SWGEN1_CNT_CLR_SEL(di, pointer)                     DI_SWGEN1_ADDR(di, pointer), 0x0E000000
+#define DI_SWGEN1_CNT_DOW(di, pointer)                                 DI_SWGEN1_ADDR(di, pointer), 0x01FF0000
+#define DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00007000
+#define DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer) DI_SWGEN1_ADDR(di, pointer), 0x00000E00
+#define DI_SWGEN1_CNT_CNT_UP(di, pointer)                              DI_SWGEN1_ADDR(di, pointer), 0x000001FF
+
+/*sync waveform generator 9 is special*/
+#define IPU_DI0_SW_GEN0_9__ADDR                           0x1E04002C
+#define IPU_DI0_SW_GEN0_9__EMPTY                  0x1E04002C,0x00000000
+#define IPU_DI0_SW_GEN0_9__FULL                           0x1E04002C,0xffffffff
+#define IPU_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9     0x1E04002C,0x7FF80000
+#define IPU_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9           0x1E04002C,0x00070000
+#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9     0x1E04002C,0x00007FF8
+#define IPU_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9 0x1E04002C,0x00000007
+
+#define IPU_DI0_SW_GEN1_9__ADDR                         0x1E040050
+#define IPU_DI0_SW_GEN1_9__EMPTY                0x1E040050,0x00000000
+#define IPU_DI0_SW_GEN1_9__FULL                         0x1E040050,0xffffffff
+#define IPU_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9    0x1E040050,0xE0000000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9 0x1E040050,0x10000000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9    0x1E040050,0x0E000000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_DOWN_9       0x1E040050,0x01FF0000
+#define IPU_DI0_SW_GEN1_9__DI0_TAG_SEL_9        0x1E040050,0x00008000
+#define IPU_DI0_SW_GEN1_9__DI0_CNT_UP_9                 0x1E040050,0x000001FF
+
+#define IPU_DI0_SYNC_AS_GEN__ADDR             0x1E040054
+#define IPU_DI0_SYNC_AS_GEN__EMPTY            0x1E040054,0x00000000
+#define IPU_DI0_SYNC_AS_GEN__FULL             0x1E040054,0xffffffff
+#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN 0x1E040054,0x10000000
+#define IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL     0x1E040054,0x0000E000
+#define IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START    0x1E040054,0x00000FFF
+
+#define IPU_DI0_DW_GEN_0__ADDR                 0x1E040058
+#define IPU_DI0_DW_GEN_0__EMPTY                        0x1E040058,0x00000000
+#define IPU_DI0_DW_GEN_0__FULL                 0x1E040058,0xffffffff
+#define IPU_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0    0x1E040058,0xFF000000
+#define IPU_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1E040058,0x00FF0000
+#define IPU_DI0_DW_GEN_0__DI0_CST_0            0x1E040058,0x0000C000
+#define IPU_DI0_DW_GEN_0__DI0_PT_6_0           0x1E040058,0x00003000
+#define IPU_DI0_DW_GEN_0__DI0_PT_5_0           0x1E040058,0x00000C00
+#define IPU_DI0_DW_GEN_0__DI0_PT_4_0           0x1E040058,0x00000300
+#define IPU_DI0_DW_GEN_0__DI0_PT_3_0           0x1E040058,0x000000C0
+#define IPU_DI0_DW_GEN_0__DI0_PT_2_0           0x1E040058,0x00000030
+#define IPU_DI0_DW_GEN_0__DI0_PT_1_0           0x1E040058,0x0000000C
+#define IPU_DI0_DW_GEN_0__DI0_PT_0_0           0x1E040058,0x00000003
+
+#define IPU_DI0_DW_GEN_0__ADDR                   0x1E040058
+#define IPU_DI0_DW_GEN_0__EMPTY                          0x1E040058,0x00000000
+#define IPU_DI0_DW_GEN_0__FULL                   0x1E040058,0xffffffff
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0    0x1E040058,0xFF000000
+#define IPU_DI0_DW_GEN_0__DI0_START_PERIOD_0     0x1E040058,0x00FF0000
+#define IPU_DI0_DW_GEN_0__DI0_CST_0              0x1E040058,0x0000C000
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1E040058,0x000001F0
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_RS_0        0x1E040058,0x0000000C
+#define IPU_DI0_DW_GEN_0__DI0_SERIAL_CLK_0       0x1E040058,0x00000003
+
+#define IPU_DI0_DW_GEN_1__ADDR                 0x1E04005C
+#define IPU_DI0_DW_GEN_1__EMPTY                        0x1E04005C,0x00000000
+#define IPU_DI0_DW_GEN_1__FULL                 0x1E04005C,0xffffffff
+#define IPU_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1    0x1E04005C,0xFF000000
+#define IPU_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1E04005C,0x00FF0000
+#define IPU_DI0_DW_GEN_1__DI0_CST_1            0x1E04005C,0x0000C000
+#define IPU_DI0_DW_GEN_1__DI0_PT_6_1           0x1E04005C,0x00003000
+#define IPU_DI0_DW_GEN_1__DI0_PT_5_1           0x1E04005C,0x00000C00
+#define IPU_DI0_DW_GEN_1__DI0_PT_4_1           0x1E04005C,0x00000300
+#define IPU_DI0_DW_GEN_1__DI0_PT_3_1           0x1E04005C,0x000000C0
+#define IPU_DI0_DW_GEN_1__DI0_PT_2_1           0x1E04005C,0x00000030
+#define IPU_DI0_DW_GEN_1__DI0_PT_1_1           0x1E04005C,0x0000000C
+#define IPU_DI0_DW_GEN_1__DI0_PT_0_1           0x1E04005C,0x00000003
+
+#define IPU_DI0_DW_GEN_1__ADDR                   0x1E04005C
+#define IPU_DI0_DW_GEN_1__EMPTY                          0x1E04005C,0x00000000
+#define IPU_DI0_DW_GEN_1__FULL                   0x1E04005C,0xffffffff
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1    0x1E04005C,0xFF000000
+#define IPU_DI0_DW_GEN_1__DI0_START_PERIOD_1     0x1E04005C,0x00FF0000
+#define IPU_DI0_DW_GEN_1__DI0_CST_1              0x1E04005C,0x0000C000
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1E04005C,0x000001F0
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_RS_1        0x1E04005C,0x0000000C
+#define IPU_DI0_DW_GEN_1__DI0_SERIAL_CLK_1       0x1E04005C,0x00000003
+
+#define IPU_DI0_DW_GEN_2__ADDR                 0x1E040060
+#define IPU_DI0_DW_GEN_2__EMPTY                        0x1E040060,0x00000000
+#define IPU_DI0_DW_GEN_2__FULL                 0x1E040060,0xffffffff
+#define IPU_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2    0x1E040060,0xFF000000
+#define IPU_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1E040060,0x00FF0000
+#define IPU_DI0_DW_GEN_2__DI0_CST_2            0x1E040060,0x0000C000
+#define IPU_DI0_DW_GEN_2__DI0_PT_6_2           0x1E040060,0x00003000
+#define IPU_DI0_DW_GEN_2__DI0_PT_5_2           0x1E040060,0x00000C00
+#define IPU_DI0_DW_GEN_2__DI0_PT_4_2           0x1E040060,0x00000300
+#define IPU_DI0_DW_GEN_2__DI0_PT_3_2           0x1E040060,0x000000C0
+#define IPU_DI0_DW_GEN_2__DI0_PT_2_2           0x1E040060,0x00000030
+#define IPU_DI0_DW_GEN_2__DI0_PT_1_2           0x1E040060,0x0000000C
+#define IPU_DI0_DW_GEN_2__DI0_PT_0_2           0x1E040060,0x00000003
+
+#define IPU_DI0_DW_GEN_2__ADDR                   0x1E040060
+#define IPU_DI0_DW_GEN_2__EMPTY                          0x1E040060,0x00000000
+#define IPU_DI0_DW_GEN_2__FULL                   0x1E040060,0xffffffff
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2    0x1E040060,0xFF000000
+#define IPU_DI0_DW_GEN_2__DI0_START_PERIOD_2     0x1E040060,0x00FF0000
+#define IPU_DI0_DW_GEN_2__DI0_CST_2              0x1E040060,0x0000C000
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1E040060,0x000001F0
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_RS_2        0x1E040060,0x0000000C
+#define IPU_DI0_DW_GEN_2__DI0_SERIAL_CLK_2       0x1E040060,0x00000003
+
+#define IPU_DI0_DW_GEN_3__ADDR                 0x1E040064
+#define IPU_DI0_DW_GEN_3__EMPTY                        0x1E040064,0x00000000
+#define IPU_DI0_DW_GEN_3__FULL                 0x1E040064,0xffffffff
+#define IPU_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3    0x1E040064,0xFF000000
+#define IPU_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1E040064,0x00FF0000
+#define IPU_DI0_DW_GEN_3__DI0_CST_3            0x1E040064,0x0000C000
+#define IPU_DI0_DW_GEN_3__DI0_PT_6_3           0x1E040064,0x00003000
+#define IPU_DI0_DW_GEN_3__DI0_PT_5_3           0x1E040064,0x00000C00
+#define IPU_DI0_DW_GEN_3__DI0_PT_4_3           0x1E040064,0x00000300
+#define IPU_DI0_DW_GEN_3__DI0_PT_3_3           0x1E040064,0x000000C0
+#define IPU_DI0_DW_GEN_3__DI0_PT_2_3           0x1E040064,0x00000030
+#define IPU_DI0_DW_GEN_3__DI0_PT_1_3           0x1E040064,0x0000000C
+#define IPU_DI0_DW_GEN_3__DI0_PT_0_3           0x1E040064,0x00000003
+
+#define IPU_DI0_DW_GEN_3__ADDR                   0x1E040064
+#define IPU_DI0_DW_GEN_3__EMPTY                          0x1E040064,0x00000000
+#define IPU_DI0_DW_GEN_3__FULL                   0x1E040064,0xffffffff
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3    0x1E040064,0xFF000000
+#define IPU_DI0_DW_GEN_3__DI0_START_PERIOD_3     0x1E040064,0x00FF0000
+#define IPU_DI0_DW_GEN_3__DI0_CST_3              0x1E040064,0x0000C000
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1E040064,0x000001F0
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_RS_3        0x1E040064,0x0000000C
+#define IPU_DI0_DW_GEN_3__DI0_SERIAL_CLK_3       0x1E040064,0x00000003
+
+#define IPU_DI0_DW_GEN_4__ADDR                 0x1E040068
+#define IPU_DI0_DW_GEN_4__EMPTY                        0x1E040068,0x00000000
+#define IPU_DI0_DW_GEN_4__FULL                 0x1E040068,0xffffffff
+#define IPU_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4    0x1E040068,0xFF000000
+#define IPU_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1E040068,0x00FF0000
+#define IPU_DI0_DW_GEN_4__DI0_CST_4            0x1E040068,0x0000C000
+#define IPU_DI0_DW_GEN_4__DI0_PT_6_4           0x1E040068,0x00003000
+#define IPU_DI0_DW_GEN_4__DI0_PT_5_4           0x1E040068,0x00000C00
+#define IPU_DI0_DW_GEN_4__DI0_PT_4_4           0x1E040068,0x00000300
+#define IPU_DI0_DW_GEN_4__DI0_PT_3_4           0x1E040068,0x000000C0
+#define IPU_DI0_DW_GEN_4__DI0_PT_2_4           0x1E040068,0x00000030
+#define IPU_DI0_DW_GEN_4__DI0_PT_1_4           0x1E040068,0x0000000C
+#define IPU_DI0_DW_GEN_4__DI0_PT_0_4           0x1E040068,0x00000003
+
+#define IPU_DI0_DW_GEN_4__ADDR                   0x1E040068
+#define IPU_DI0_DW_GEN_4__EMPTY                          0x1E040068,0x00000000
+#define IPU_DI0_DW_GEN_4__FULL                   0x1E040068,0xffffffff
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4    0x1E040068,0xFF000000
+#define IPU_DI0_DW_GEN_4__DI0_START_PERIOD_4     0x1E040068,0x00FF0000
+#define IPU_DI0_DW_GEN_4__DI0_CST_4              0x1E040068,0x0000C000
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1E040068,0x000001F0
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_RS_4        0x1E040068,0x0000000C
+#define IPU_DI0_DW_GEN_4__DI0_SERIAL_CLK_4       0x1E040068,0x00000003
+
+#define IPU_DI0_DW_GEN_5__ADDR                 0x1E04006C
+#define IPU_DI0_DW_GEN_5__EMPTY                        0x1E04006C,0x00000000
+#define IPU_DI0_DW_GEN_5__FULL                 0x1E04006C,0xffffffff
+#define IPU_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5    0x1E04006C,0xFF000000
+#define IPU_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1E04006C,0x00FF0000
+#define IPU_DI0_DW_GEN_5__DI0_CST_5            0x1E04006C,0x0000C000
+#define IPU_DI0_DW_GEN_5__DI0_PT_6_5           0x1E04006C,0x00003000
+#define IPU_DI0_DW_GEN_5__DI0_PT_5_5           0x1E04006C,0x00000C00
+#define IPU_DI0_DW_GEN_5__DI0_PT_4_5           0x1E04006C,0x00000300
+#define IPU_DI0_DW_GEN_5__DI0_PT_3_5           0x1E04006C,0x000000C0
+#define IPU_DI0_DW_GEN_5__DI0_PT_2_5           0x1E04006C,0x00000030
+#define IPU_DI0_DW_GEN_5__DI0_PT_1_5           0x1E04006C,0x0000000C
+#define IPU_DI0_DW_GEN_5__DI0_PT_0_5           0x1E04006C,0x00000003
+
+#define IPU_DI0_DW_GEN_5__ADDR                   0x1E04006C
+#define IPU_DI0_DW_GEN_5__EMPTY                          0x1E04006C,0x00000000
+#define IPU_DI0_DW_GEN_5__FULL                   0x1E04006C,0xffffffff
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5    0x1E04006C,0xFF000000
+#define IPU_DI0_DW_GEN_5__DI0_START_PERIOD_5     0x1E04006C,0x00FF0000
+#define IPU_DI0_DW_GEN_5__DI0_CST_5              0x1E04006C,0x0000C000
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1E04006C,0x000001F0
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_RS_5        0x1E04006C,0x0000000C
+#define IPU_DI0_DW_GEN_5__DI0_SERIAL_CLK_5       0x1E04006C,0x00000003
+
+#define IPU_DI0_DW_GEN_6__ADDR                 0x1E040070
+#define IPU_DI0_DW_GEN_6__EMPTY                        0x1E040070,0x00000000
+#define IPU_DI0_DW_GEN_6__FULL                 0x1E040070,0xffffffff
+#define IPU_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6    0x1E040070,0xFF000000
+#define IPU_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1E040070,0x00FF0000
+#define IPU_DI0_DW_GEN_6__DI0_CST_6            0x1E040070,0x0000C000
+#define IPU_DI0_DW_GEN_6__DI0_PT_6_6           0x1E040070,0x00003000
+#define IPU_DI0_DW_GEN_6__DI0_PT_5_6           0x1E040070,0x00000C00
+#define IPU_DI0_DW_GEN_6__DI0_PT_4_6           0x1E040070,0x00000300
+#define IPU_DI0_DW_GEN_6__DI0_PT_3_6           0x1E040070,0x000000C0
+#define IPU_DI0_DW_GEN_6__DI0_PT_2_6           0x1E040070,0x00000030
+#define IPU_DI0_DW_GEN_6__DI0_PT_1_6           0x1E040070,0x0000000C
+#define IPU_DI0_DW_GEN_6__DI0_PT_0_6           0x1E040070,0x00000003
+
+#define IPU_DI0_DW_GEN_6__ADDR                   0x1E040070
+#define IPU_DI0_DW_GEN_6__EMPTY                          0x1E040070,0x00000000
+#define IPU_DI0_DW_GEN_6__FULL                   0x1E040070,0xffffffff
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6    0x1E040070,0xFF000000
+#define IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6     0x1E040070,0x00FF0000
+#define IPU_DI0_DW_GEN_6__DI0_CST_6              0x1E040070,0x0000C000
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1E040070,0x000001F0
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6        0x1E040070,0x0000000C
+#define IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6       0x1E040070,0x00000003
+
+#define IPU_DI0_DW_GEN_7__ADDR                 0x1E040074
+#define IPU_DI0_DW_GEN_7__EMPTY                        0x1E040074,0x00000000
+#define IPU_DI0_DW_GEN_7__FULL                 0x1E040074,0xffffffff
+#define IPU_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7    0x1E040074,0xFF000000
+#define IPU_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1E040074,0x00FF0000
+#define IPU_DI0_DW_GEN_7__DI0_CST_7            0x1E040074,0x0000C000
+#define IPU_DI0_DW_GEN_7__DI0_PT_6_7           0x1E040074,0x00003000
+#define IPU_DI0_DW_GEN_7__DI0_PT_5_7           0x1E040074,0x00000C00
+#define IPU_DI0_DW_GEN_7__DI0_PT_4_7           0x1E040074,0x00000300
+#define IPU_DI0_DW_GEN_7__DI0_PT_3_7           0x1E040074,0x000000C0
+#define IPU_DI0_DW_GEN_7__DI0_PT_2_7           0x1E040074,0x00000030
+#define IPU_DI0_DW_GEN_7__DI0_PT_1_7           0x1E040074,0x0000000C
+#define IPU_DI0_DW_GEN_7__DI0_PT_0_7           0x1E040074,0x00000003
+
+#define IPU_DI0_DW_GEN_7__ADDR                   0x1E040074
+#define IPU_DI0_DW_GEN_7__EMPTY                          0x1E040074,0x00000000
+#define IPU_DI0_DW_GEN_7__FULL                   0x1E040074,0xffffffff
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7    0x1E040074,0xFF000000
+#define IPU_DI0_DW_GEN_7__DI0_START_PERIOD_7     0x1E040074,0x00FF0000
+#define IPU_DI0_DW_GEN_7__DI0_CST_7              0x1E040074,0x0000C000
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1E040074,0x000001F0
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_RS_7        0x1E040074,0x0000000C
+#define IPU_DI0_DW_GEN_7__DI0_SERIAL_CLK_7       0x1E040074,0x00000003
+
+#define IPU_DI0_DW_GEN_8__ADDR                 0x1E040078
+#define IPU_DI0_DW_GEN_8__EMPTY                        0x1E040078,0x00000000
+#define IPU_DI0_DW_GEN_8__FULL                 0x1E040078,0xffffffff
+#define IPU_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8    0x1E040078,0xFF000000
+#define IPU_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1E040078,0x00FF0000
+#define IPU_DI0_DW_GEN_8__DI0_CST_8            0x1E040078,0x0000C000
+#define IPU_DI0_DW_GEN_8__DI0_PT_6_8           0x1E040078,0x00003000
+#define IPU_DI0_DW_GEN_8__DI0_PT_5_8           0x1E040078,0x00000C00
+#define IPU_DI0_DW_GEN_8__DI0_PT_4_8           0x1E040078,0x00000300
+#define IPU_DI0_DW_GEN_8__DI0_PT_3_8           0x1E040078,0x000000C0
+#define IPU_DI0_DW_GEN_8__DI0_PT_2_8           0x1E040078,0x00000030
+#define IPU_DI0_DW_GEN_8__DI0_PT_1_8           0x1E040078,0x0000000C
+#define IPU_DI0_DW_GEN_8__DI0_PT_0_8           0x1E040078,0x00000003
+
+#define IPU_DI0_DW_GEN_8__ADDR                   0x1E040078
+#define IPU_DI0_DW_GEN_8__EMPTY                          0x1E040078,0x00000000
+#define IPU_DI0_DW_GEN_8__FULL                   0x1E040078,0xffffffff
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8    0x1E040078,0xFF000000
+#define IPU_DI0_DW_GEN_8__DI0_START_PERIOD_8     0x1E040078,0x00FF0000
+#define IPU_DI0_DW_GEN_8__DI0_CST_8              0x1E040078,0x0000C000
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1E040078,0x000001F0
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_RS_8        0x1E040078,0x0000000C
+#define IPU_DI0_DW_GEN_8__DI0_SERIAL_CLK_8       0x1E040078,0x00000003
+
+#define IPU_DI0_DW_GEN_9__ADDR                 0x1E04007C
+#define IPU_DI0_DW_GEN_9__EMPTY                        0x1E04007C,0x00000000
+#define IPU_DI0_DW_GEN_9__FULL                 0x1E04007C,0xffffffff
+#define IPU_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9    0x1E04007C,0xFF000000
+#define IPU_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1E04007C,0x00FF0000
+#define IPU_DI0_DW_GEN_9__DI0_CST_9            0x1E04007C,0x0000C000
+#define IPU_DI0_DW_GEN_9__DI0_PT_6_9           0x1E04007C,0x00003000
+#define IPU_DI0_DW_GEN_9__DI0_PT_5_9           0x1E04007C,0x00000C00
+#define IPU_DI0_DW_GEN_9__DI0_PT_4_9           0x1E04007C,0x00000300
+#define IPU_DI0_DW_GEN_9__DI0_PT_3_9           0x1E04007C,0x000000C0
+#define IPU_DI0_DW_GEN_9__DI0_PT_2_9           0x1E04007C,0x00000030
+#define IPU_DI0_DW_GEN_9__DI0_PT_1_9           0x1E04007C,0x0000000C
+#define IPU_DI0_DW_GEN_9__DI0_PT_0_9           0x1E04007C,0x00000003
+
+#define IPU_DI0_DW_GEN_9__ADDR                   0x1E04007C
+#define IPU_DI0_DW_GEN_9__EMPTY                          0x1E04007C,0x00000000
+#define IPU_DI0_DW_GEN_9__FULL                   0x1E04007C,0xffffffff
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9    0x1E04007C,0xFF000000
+#define IPU_DI0_DW_GEN_9__DI0_START_PERIOD_9     0x1E04007C,0x00FF0000
+#define IPU_DI0_DW_GEN_9__DI0_CST_9              0x1E04007C,0x0000C000
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1E04007C,0x000001F0
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_RS_9        0x1E04007C,0x0000000C
+#define IPU_DI0_DW_GEN_9__DI0_SERIAL_CLK_9       0x1E04007C,0x00000003
+
+#define IPU_DI0_DW_GEN_10__ADDR                          0x1E040080
+#define IPU_DI0_DW_GEN_10__EMPTY                 0x1E040080,0x00000000
+#define IPU_DI0_DW_GEN_10__FULL                          0x1E040080,0xffffffff
+#define IPU_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10    0x1E040080,0xFF000000
+#define IPU_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1E040080,0x00FF0000
+#define IPU_DI0_DW_GEN_10__DI0_CST_10            0x1E040080,0x0000C000
+#define IPU_DI0_DW_GEN_10__DI0_PT_6_10           0x1E040080,0x00003000
+#define IPU_DI0_DW_GEN_10__DI0_PT_5_10           0x1E040080,0x00000C00
+#define IPU_DI0_DW_GEN_10__DI0_PT_4_10           0x1E040080,0x00000300
+#define IPU_DI0_DW_GEN_10__DI0_PT_3_10           0x1E040080,0x000000C0
+#define IPU_DI0_DW_GEN_10__DI0_PT_2_10           0x1E040080,0x00000030
+#define IPU_DI0_DW_GEN_10__DI0_PT_1_10           0x1E040080,0x0000000C
+#define IPU_DI0_DW_GEN_10__DI0_PT_0_10           0x1E040080,0x00000003
+
+#define IPU_DI0_DW_GEN_10__ADDR                            0x1E040080
+#define IPU_DI0_DW_GEN_10__EMPTY                   0x1E040080,0x00000000
+#define IPU_DI0_DW_GEN_10__FULL                            0x1E040080,0xffffffff
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10            0x1E040080,0xFF000000
+#define IPU_DI0_DW_GEN_10__DI0_START_PERIOD_10     0x1E040080,0x00FF0000
+#define IPU_DI0_DW_GEN_10__DI0_CST_10              0x1E040080,0x0000C000
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E040080,0x000001F0
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_RS_10        0x1E040080,0x0000000C
+#define IPU_DI0_DW_GEN_10__DI0_SERIAL_CLK_10       0x1E040080,0x00000003
+
+#define IPU_DI0_DW_GEN_11__ADDR                          0x1E040084
+#define IPU_DI0_DW_GEN_11__EMPTY                 0x1E040084,0x00000000
+#define IPU_DI0_DW_GEN_11__FULL                          0x1E040084,0xffffffff
+#define IPU_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11    0x1E040084,0xFF000000
+#define IPU_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1E040084,0x00FF0000
+#define IPU_DI0_DW_GEN_11__DI0_CST_11            0x1E040084,0x0000C000
+#define IPU_DI0_DW_GEN_11__DI0_PT_6_11           0x1E040084,0x00003000
+#define IPU_DI0_DW_GEN_11__DI0_PT_5_11           0x1E040084,0x00000C00
+#define IPU_DI0_DW_GEN_11__DI0_PT_4_11           0x1E040084,0x00000300
+#define IPU_DI0_DW_GEN_11__DI0_PT_3_11           0x1E040084,0x000000C0
+#define IPU_DI0_DW_GEN_11__DI0_PT_2_11           0x1E040084,0x00000030
+#define IPU_DI0_DW_GEN_11__DI0_PT_1_11           0x1E040084,0x0000000C
+#define IPU_DI0_DW_GEN_11__DI0_PT_0_11           0x1E040084,0x00000003
+
+#define IPU_DI0_DW_GEN_11__ADDR                            0x1E040084
+#define IPU_DI0_DW_GEN_11__EMPTY                   0x1E040084,0x00000000
+#define IPU_DI0_DW_GEN_11__FULL                            0x1E040084,0xffffffff
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11            0x1E040084,0xFF000000
+#define IPU_DI0_DW_GEN_11__DI0_START_PERIOD_11     0x1E040084,0x00FF0000
+#define IPU_DI0_DW_GEN_11__DI0_CST_11              0x1E040084,0x0000C000
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E040084,0x000001F0
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_RS_11        0x1E040084,0x0000000C
+#define IPU_DI0_DW_GEN_11__DI0_SERIAL_CLK_11       0x1E040084,0x00000003
+
+#define IPU_DI_DW_OFFSET                                                               0x0088
+#define DI_WAVESET_ADDR(di, pointer, set)              (IPU_DI0_GENERAL__ADDR + \
+                                                                                                                                                               di*0x8000 + IPU_DI_DW_OFFSET + \
+                                                                                                                                                               pointer*0x4 + set * 0x30)
+#define DI_WAVESET_UP(di, pointer, set)                                DI_WAVESET_ADDR(di, pointer, set), 0x000001FF
+#define DI_WAVESET_DOWN(di, pointer, set)      DI_WAVESET_ADDR(di, pointer, set), 0x01FF0000
+
+#define IPU_DI_STEP_RPT_OFFSET                                 0x0148
+#define DI_STEP_RPT_ADDR(di, pointer)                  (IPU_DI0_GENERAL__ADDR + \
+                                                                                                                                                               di*0x8000 + IPU_DI_STEP_RPT_OFFSET + \
+                                                                                                                                                               ((pointer-1) / 2)*0x4 )
+#define DI_STEP_RPT(di, pointer)                                               DI_STEP_RPT_ADDR(di, pointer), 0x0FFF<<((pointer-1)%2)*16
+
+#define IPU_DI0_STP_REP_9__ADDR                     0x1E040158
+#define IPU_DI0_STP_REP_9__EMPTY            0x1E040158,0x00000000
+#define IPU_DI0_STP_REP_9__FULL                     0x1E040158,0xffffffff
+#define IPU_DI0_STP_REP_9__DI0_STEP_REPEAT_9 0x1E040158,0x00000FFF
+
+#define IPU_DI0_SER_CONF__ADDR                      0x1E04015C
+#define IPU_DI0_SER_CONF__EMPTY                             0x1E04015C,0x00000000
+#define IPU_DI0_SER_CONF__FULL                      0x1E04015C,0xffffffff
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1 0x1E04015C,0xF0000000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0 0x1E04015C,0x0F000000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1 0x1E04015C,0x00F00000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0 0x1E04015C,0x000F0000
+#define IPU_DI0_SER_CONF__DI0_SERIAL_LATCH          0x1E04015C,0x0000FF00
+#define IPU_DI0_SER_CONF__DI0_LLA_SER_ACCESS        0x1E04015C,0x00000020
+#define IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY      0x1E04015C,0x00000010
+#define IPU_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY   0x1E04015C,0x00000008
+#define IPU_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY     0x1E04015C,0x00000004
+#define IPU_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY     0x1E04015C,0x00000002
+#define IPU_DI0_SER_CONF__DI0_WAIT4SERIAL           0x1E04015C,0x00000001
+
+#define IPU_DI0_SSC__ADDR             0x1E040160
+#define IPU_DI0_SSC__EMPTY            0x1E040160,0x00000000
+#define IPU_DI0_SSC__FULL             0x1E040160,0xffffffff
+#define IPU_DI0_SSC__DI0_PIN17_ERM     0x1E040160,0x00800000
+#define IPU_DI0_SSC__DI0_PIN16_ERM     0x1E040160,0x00400000
+#define IPU_DI0_SSC__DI0_PIN15_ERM     0x1E040160,0x00200000
+#define IPU_DI0_SSC__DI0_PIN14_ERM     0x1E040160,0x00100000
+#define IPU_DI0_SSC__DI0_PIN13_ERM     0x1E040160,0x00080000
+#define IPU_DI0_SSC__DI0_PIN12_ERM     0x1E040160,0x00040000
+#define IPU_DI0_SSC__DI0_PIN11_ERM     0x1E040160,0x00020000
+#define IPU_DI0_SSC__DI0_CS_ERM               0x1E040160,0x00010000
+#define IPU_DI0_SSC__DI0_WAIT_ON       0x1E040160,0x00000020
+#define IPU_DI0_SSC__DI0_BYTE_EN_RD_IN 0x1E040160,0x00000008
+#define IPU_DI0_SSC__DI0_BYTE_EN_PNTR  0x1E040160,0x00000007
+
+#define IPU_DI0_POL__ADDR                    0x1E040164
+#define IPU_DI0_POL__EMPTY                   0x1E040164,0x00000000
+#define IPU_DI0_POL__FULL                    0x1E040164,0xffffffff
+#define IPU_DI0_POL__DI0_WAIT_POLARITY       0x1E040164,0x04000000
+#define IPU_DI0_POL__DI0_CS1_BYTE_EN_POLARITY 0x1E040164,0x02000000
+#define IPU_DI0_POL__DI0_CS0_BYTE_EN_POLARITY 0x1E040164,0x01000000
+#define IPU_DI0_POL__DI0_CS1_DATA_POLARITY    0x1E040164,0x00800000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_17      0x1E040164,0x00400000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_16      0x1E040164,0x00200000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_15      0x1E040164,0x00100000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_14      0x1E040164,0x00080000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_13      0x1E040164,0x00040000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_12      0x1E040164,0x00020000
+#define IPU_DI0_POL__DI0_CS1_POLARITY_11      0x1E040164,0x00010000
+#define IPU_DI0_POL__DI0_CS0_DATA_POLARITY    0x1E040164,0x00008000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_17      0x1E040164,0x00004000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_16      0x1E040164,0x00002000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_15      0x1E040164,0x00001000
+#define IPU_DI0_POL__DI0_CS0_POLARITY_14      0x1E040164,0x00000800
+#define IPU_DI0_POL__DI0_CS0_POLARITY_13      0x1E040164,0x00000400
+#define IPU_DI0_POL__DI0_CS0_POLARITY_12      0x1E040164,0x00000200
+#define IPU_DI0_POL__DI0_CS0_POLARITY_11      0x1E040164,0x00000100
+#define IPU_DI0_POL__DI0_DRDY_DATA_POLARITY   0x1E040164,0x00000080
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_17     0x1E040164,0x00000040
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_16     0x1E040164,0x00000020
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_15     0x1E040164,0x00000010
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_14     0x1E040164,0x00000008
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_13     0x1E040164,0x00000004
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_12     0x1E040164,0x00000002
+#define IPU_DI0_POL__DI0_DRDY_POLARITY_11     0x1E040164,0x00000001
+
+#define IPU_DI0_AW0__ADDR             0x1E040168
+#define IPU_DI0_AW0__EMPTY            0x1E040168,0x00000000
+#define IPU_DI0_AW0__FULL             0x1E040168,0xffffffff
+#define IPU_DI0_AW0__DI0_AW_TRIG_SEL   0x1E040168,0xF0000000
+#define IPU_DI0_AW0__DI0_AW_HEND       0x1E040168,0x0FFF0000
+#define IPU_DI0_AW0__DI0_AW_HCOUNT_SEL 0x1E040168,0x0000F000
+#define IPU_DI0_AW0__DI0_AW_HSTART     0x1E040168,0x00000FFF
+
+#define IPU_DI0_AW1__ADDR             0x1E04016C
+#define IPU_DI0_AW1__EMPTY            0x1E04016C,0x00000000
+#define IPU_DI0_AW1__FULL             0x1E04016C,0xffffffff
+#define IPU_DI0_AW1__DI0_AW_VEND       0x1E04016C,0x0FFF0000
+#define IPU_DI0_AW1__DI0_AW_VCOUNT_SEL 0x1E04016C,0x0000F000
+#define IPU_DI0_AW1__DI0_AW_VSTART     0x1E04016C,0x00000FFF
+
+#define IPU_DI0_SCR_CONF__ADDR             0x1E040170
+#define IPU_DI0_SCR_CONF__EMPTY                    0x1E040170,0x00000000
+#define IPU_DI0_SCR_CONF__FULL             0x1E040170,0xffffffff
+#define IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT 0x1E040170,0x00000FFF
+
+#define IPU_DI0_STAT__ADDR               0x1E040174
+#define IPU_DI0_STAT__EMPTY              0x1E040174,0x00000000
+#define IPU_DI0_STAT__FULL               0x1E040174,0xffffffff
+#define IPU_DI0_STAT__DI0_CNTR_FIFO_FULL  0x1E040174,0x00000008
+#define IPU_DI0_STAT__DI0_CNTR_FIFO_EMPTY 0x1E040174,0x00000004
+#define IPU_DI0_STAT__DI0_READ_FIFO_FULL  0x1E040174,0x00000002
+#define IPU_DI0_STAT__DI0_READ_FIFO_EMPTY 0x1E040174,0x00000001
+
+#define IPU_DI1_GENERAL__ADDR                 0x1E048000
+#define IPU_DI1_GENERAL__EMPTY                0x1E048000,0x00000000
+#define IPU_DI1_GENERAL__FULL                 0x1E048000,0xffffffff
+#define IPU_DI1_GENERAL__DI1_DISP_Y_SEL               0x1E048000,0x70000000
+#define IPU_DI1_GENERAL__DI1_CLOCK_STOP_MODE   0x1E048000,0x0F000000
+#define IPU_DI1_GENERAL__DI1_DISP_CLOCK_INIT   0x1E048000,0x00800000
+#define IPU_DI1_GENERAL__DI1_MASK_SEL         0x1E048000,0x00400000
+#define IPU_DI1_GENERAL__DI1_VSYNC_EXT        0x1E048000,0x00200000
+#define IPU_DI1_GENERAL__DI1_CLK_EXT          0x1E048000,0x00100000
+#define IPU_DI1_GENERAL__DI1_WATCHDOG_MODE     0x1E048000,0x000C0000
+#define IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK 0x1E048000,0x00020000
+#define IPU_DI1_GENERAL__DI1_SYNC_COUNT_SEL    0x1E048000,0x0000F000
+#define IPU_DI1_GENERAL__DI1_ERR_TREATMENT     0x1E048000,0x00000800
+#define IPU_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1E048000,0x00000400
+#define IPU_DI1_GENERAL__DI1_POLARITY_CS1      0x1E048000,0x00000200
+#define IPU_DI1_GENERAL__DI1_POLARITY_CS0      0x1E048000,0x00000100
+#define IPU_DI1_GENERAL__DI1_POLARITY_8               0x1E048000,0x00000080
+#define IPU_DI1_GENERAL__DI1_POLARITY_7               0x1E048000,0x00000040
+#define IPU_DI1_GENERAL__DI1_POLARITY_6               0x1E048000,0x00000020
+#define IPU_DI1_GENERAL__DI1_POLARITY_5               0x1E048000,0x00000010
+#define IPU_DI1_GENERAL__DI1_POLARITY_4               0x1E048000,0x00000008
+#define IPU_DI1_GENERAL__DI1_POLARITY_3               0x1E048000,0x00000004
+#define IPU_DI1_GENERAL__DI1_POLARITY_2               0x1E048000,0x00000002
+#define IPU_DI1_GENERAL__DI1_POLARITY_1               0x1E048000,0x00000001
+
+#define IPU_DI1_BS_CLKGEN0__ADDR               0x1E048004
+#define IPU_DI1_BS_CLKGEN0__EMPTY              0x1E048004,0x00000000
+#define IPU_DI1_BS_CLKGEN0__FULL               0x1E048004,0xffffffff
+#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET 0x1E048004,0x01FF0000
+#define IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD 0x1E048004,0x00000FFF
+
+#define IPU_DI1_BS_CLKGEN1__ADDR             0x1E048008
+#define IPU_DI1_BS_CLKGEN1__EMPTY            0x1E048008,0x00000000
+#define IPU_DI1_BS_CLKGEN1__FULL             0x1E048008,0xffffffff
+#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN 0x1E048008,0x01FF0000
+#define IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP   0x1E048008,0x000001FF
+
+#define IPU_DI1_SW_GEN0_9__ADDR                           0x1E04802C
+#define IPU_DI1_SW_GEN0_9__EMPTY                  0x1E04802C,0x00000000
+#define IPU_DI1_SW_GEN0_9__FULL                           0x1E04802C,0xffffffff
+#define IPU_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9     0x1E04802C,0x7FF80000
+#define IPU_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9           0x1E04802C,0x00070000
+#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9     0x1E04802C,0x00007FF8
+#define IPU_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9 0x1E04802C,0x00000007
+
+#define IPU_DI1_SW_GEN1_9__ADDR                         0x1E048050
+#define IPU_DI1_SW_GEN1_9__EMPTY                0x1E048050,0x00000000
+#define IPU_DI1_SW_GEN1_9__FULL                         0x1E048050,0xffffffff
+#define IPU_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9    0x1E048050,0xE0000000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9 0x1E048050,0x10000000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9    0x1E048050,0x0E000000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_DOWN_9       0x1E048050,0x01FF0000
+#define IPU_DI1_SW_GEN1_9__DI1_TAG_SEL_9        0x1E048050,0x00008000
+#define IPU_DI1_SW_GEN1_9__DI1_CNT_UP_9                 0x1E048050,0x000001FF
+
+#define IPU_DI1_SYNC_AS_GEN__ADDR             0x1E048054
+#define IPU_DI1_SYNC_AS_GEN__EMPTY            0x1E048054,0x00000000
+#define IPU_DI1_SYNC_AS_GEN__FULL             0x1E048054,0xffffffff
+#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN 0x1E048054,0x10000000
+#define IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL     0x1E048054,0x0000E000
+#define IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START    0x1E048054,0x00000FFF
+
+#define IPU_DI1_DW_GEN_0__ADDR                 0x1E048058
+#define IPU_DI1_DW_GEN_0__EMPTY                        0x1E048058,0x00000000
+#define IPU_DI1_DW_GEN_0__FULL                 0x1E048058,0xffffffff
+#define IPU_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0    0x1E048058,0xFF000000
+#define IPU_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1E048058,0x00FF0000
+#define IPU_DI1_DW_GEN_0__DI1_CST_0            0x1E048058,0x0000C000
+#define IPU_DI1_DW_GEN_0__DI1_PT_6_0           0x1E048058,0x00003000
+#define IPU_DI1_DW_GEN_0__DI1_PT_5_0           0x1E048058,0x00000C00
+#define IPU_DI1_DW_GEN_0__DI1_PT_4_0           0x1E048058,0x00000300
+#define IPU_DI1_DW_GEN_0__DI1_PT_3_0           0x1E048058,0x000000C0
+#define IPU_DI1_DW_GEN_0__DI1_PT_2_0           0x1E048058,0x00000030
+#define IPU_DI1_DW_GEN_0__DI1_PT_1_0           0x1E048058,0x0000000C
+#define IPU_DI1_DW_GEN_0__DI1_PT_0_0           0x1E048058,0x00000003
+
+#define IPU_DI1_DW_GEN_0__ADDR                   0x1E048058
+#define IPU_DI1_DW_GEN_0__EMPTY                          0x1E048058,0x00000000
+#define IPU_DI1_DW_GEN_0__FULL                   0x1E048058,0xffffffff
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0    0x1E048058,0xFF000000
+#define IPU_DI1_DW_GEN_0__DI1_START_PERIOD_0     0x1E048058,0x00FF0000
+#define IPU_DI1_DW_GEN_0__DI1_CST_0              0x1E048058,0x0000C000
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1E048058,0x000001F0
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_RS_0        0x1E048058,0x0000000C
+#define IPU_DI1_DW_GEN_0__DI1_SERIAL_CLK_0       0x1E048058,0x00000003
+
+#define IPU_DI1_DW_GEN_1__ADDR                 0x1E04805C
+#define IPU_DI1_DW_GEN_1__EMPTY                        0x1E04805C,0x00000000
+#define IPU_DI1_DW_GEN_1__FULL                 0x1E04805C,0xffffffff
+#define IPU_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1    0x1E04805C,0xFF000000
+#define IPU_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1E04805C,0x00FF0000
+#define IPU_DI1_DW_GEN_1__DI1_CST_1            0x1E04805C,0x0000C000
+#define IPU_DI1_DW_GEN_1__DI1_PT_6_1           0x1E04805C,0x00003000
+#define IPU_DI1_DW_GEN_1__DI1_PT_5_1           0x1E04805C,0x00000C00
+#define IPU_DI1_DW_GEN_1__DI1_PT_4_1           0x1E04805C,0x00000300
+#define IPU_DI1_DW_GEN_1__DI1_PT_3_1           0x1E04805C,0x000000C0
+#define IPU_DI1_DW_GEN_1__DI1_PT_2_1           0x1E04805C,0x00000030
+#define IPU_DI1_DW_GEN_1__DI1_PT_1_1           0x1E04805C,0x0000000C
+#define IPU_DI1_DW_GEN_1__DI1_PT_0_1           0x1E04805C,0x00000003
+
+#define IPU_DI1_DW_GEN_1__ADDR                   0x1E04805C
+#define IPU_DI1_DW_GEN_1__EMPTY                          0x1E04805C,0x00000000
+#define IPU_DI1_DW_GEN_1__FULL                   0x1E04805C,0xffffffff
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1    0x1E04805C,0xFF000000
+#define IPU_DI1_DW_GEN_1__DI1_START_PERIOD_1     0x1E04805C,0x00FF0000
+#define IPU_DI1_DW_GEN_1__DI1_CST_1              0x1E04805C,0x0000C000
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1E04805C,0x000001F0
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_RS_1        0x1E04805C,0x0000000C
+#define IPU_DI1_DW_GEN_1__DI1_SERIAL_CLK_1       0x1E04805C,0x00000003
+
+#define IPU_DI1_DW_GEN_2__ADDR                 0x1E048060
+#define IPU_DI1_DW_GEN_2__EMPTY                        0x1E048060,0x00000000
+#define IPU_DI1_DW_GEN_2__FULL                 0x1E048060,0xffffffff
+#define IPU_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2    0x1E048060,0xFF000000
+#define IPU_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1E048060,0x00FF0000
+#define IPU_DI1_DW_GEN_2__DI1_CST_2            0x1E048060,0x0000C000
+#define IPU_DI1_DW_GEN_2__DI1_PT_6_2           0x1E048060,0x00003000
+#define IPU_DI1_DW_GEN_2__DI1_PT_5_2           0x1E048060,0x00000C00
+#define IPU_DI1_DW_GEN_2__DI1_PT_4_2           0x1E048060,0x00000300
+#define IPU_DI1_DW_GEN_2__DI1_PT_3_2           0x1E048060,0x000000C0
+#define IPU_DI1_DW_GEN_2__DI1_PT_2_2           0x1E048060,0x00000030
+#define IPU_DI1_DW_GEN_2__DI1_PT_1_2           0x1E048060,0x0000000C
+#define IPU_DI1_DW_GEN_2__DI1_PT_0_2           0x1E048060,0x00000003
+
+#define IPU_DI1_DW_GEN_2__ADDR                   0x1E048060
+#define IPU_DI1_DW_GEN_2__EMPTY                          0x1E048060,0x00000000
+#define IPU_DI1_DW_GEN_2__FULL                   0x1E048060,0xffffffff
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2    0x1E048060,0xFF000000
+#define IPU_DI1_DW_GEN_2__DI1_START_PERIOD_2     0x1E048060,0x00FF0000
+#define IPU_DI1_DW_GEN_2__DI1_CST_2              0x1E048060,0x0000C000
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1E048060,0x000001F0
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_RS_2        0x1E048060,0x0000000C
+#define IPU_DI1_DW_GEN_2__DI1_SERIAL_CLK_2       0x1E048060,0x00000003
+
+#define IPU_DI1_DW_GEN_3__ADDR                 0x1E048064
+#define IPU_DI1_DW_GEN_3__EMPTY                        0x1E048064,0x00000000
+#define IPU_DI1_DW_GEN_3__FULL                 0x1E048064,0xffffffff
+#define IPU_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3    0x1E048064,0xFF000000
+#define IPU_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1E048064,0x00FF0000
+#define IPU_DI1_DW_GEN_3__DI1_CST_3            0x1E048064,0x0000C000
+#define IPU_DI1_DW_GEN_3__DI1_PT_6_3           0x1E048064,0x00003000
+#define IPU_DI1_DW_GEN_3__DI1_PT_5_3           0x1E048064,0x00000C00
+#define IPU_DI1_DW_GEN_3__DI1_PT_4_3           0x1E048064,0x00000300
+#define IPU_DI1_DW_GEN_3__DI1_PT_3_3           0x1E048064,0x000000C0
+#define IPU_DI1_DW_GEN_3__DI1_PT_2_3           0x1E048064,0x00000030
+#define IPU_DI1_DW_GEN_3__DI1_PT_1_3           0x1E048064,0x0000000C
+#define IPU_DI1_DW_GEN_3__DI1_PT_0_3           0x1E048064,0x00000003
+
+#define IPU_DI1_DW_GEN_3__ADDR                   0x1E048064
+#define IPU_DI1_DW_GEN_3__EMPTY                          0x1E048064,0x00000000
+#define IPU_DI1_DW_GEN_3__FULL                   0x1E048064,0xffffffff
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3    0x1E048064,0xFF000000
+#define IPU_DI1_DW_GEN_3__DI1_START_PERIOD_3     0x1E048064,0x00FF0000
+#define IPU_DI1_DW_GEN_3__DI1_CST_3              0x1E048064,0x0000C000
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1E048064,0x000001F0
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_RS_3        0x1E048064,0x0000000C
+#define IPU_DI1_DW_GEN_3__DI1_SERIAL_CLK_3       0x1E048064,0x00000003
+
+#define IPU_DI1_DW_GEN_4__ADDR                 0x1E048068
+#define IPU_DI1_DW_GEN_4__EMPTY                        0x1E048068,0x00000000
+#define IPU_DI1_DW_GEN_4__FULL                 0x1E048068,0xffffffff
+#define IPU_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4    0x1E048068,0xFF000000
+#define IPU_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1E048068,0x00FF0000
+#define IPU_DI1_DW_GEN_4__DI1_CST_4            0x1E048068,0x0000C000
+#define IPU_DI1_DW_GEN_4__DI1_PT_6_4           0x1E048068,0x00003000
+#define IPU_DI1_DW_GEN_4__DI1_PT_5_4           0x1E048068,0x00000C00
+#define IPU_DI1_DW_GEN_4__DI1_PT_4_4           0x1E048068,0x00000300
+#define IPU_DI1_DW_GEN_4__DI1_PT_3_4           0x1E048068,0x000000C0
+#define IPU_DI1_DW_GEN_4__DI1_PT_2_4           0x1E048068,0x00000030
+#define IPU_DI1_DW_GEN_4__DI1_PT_1_4           0x1E048068,0x0000000C
+#define IPU_DI1_DW_GEN_4__DI1_PT_0_4           0x1E048068,0x00000003
+
+#define IPU_DI1_DW_GEN_4__ADDR                   0x1E048068
+#define IPU_DI1_DW_GEN_4__EMPTY                          0x1E048068,0x00000000
+#define IPU_DI1_DW_GEN_4__FULL                   0x1E048068,0xffffffff
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4    0x1E048068,0xFF000000
+#define IPU_DI1_DW_GEN_4__DI1_START_PERIOD_4     0x1E048068,0x00FF0000
+#define IPU_DI1_DW_GEN_4__DI1_CST_4              0x1E048068,0x0000C000
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1E048068,0x000001F0
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_RS_4        0x1E048068,0x0000000C
+#define IPU_DI1_DW_GEN_4__DI1_SERIAL_CLK_4       0x1E048068,0x00000003
+
+#define IPU_DI1_DW_GEN_5__ADDR                 0x1E04806C
+#define IPU_DI1_DW_GEN_5__EMPTY                        0x1E04806C,0x00000000
+#define IPU_DI1_DW_GEN_5__FULL                 0x1E04806C,0xffffffff
+#define IPU_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5    0x1E04806C,0xFF000000
+#define IPU_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1E04806C,0x00FF0000
+#define IPU_DI1_DW_GEN_5__DI1_CST_5            0x1E04806C,0x0000C000
+#define IPU_DI1_DW_GEN_5__DI1_PT_6_5           0x1E04806C,0x00003000
+#define IPU_DI1_DW_GEN_5__DI1_PT_5_5           0x1E04806C,0x00000C00
+#define IPU_DI1_DW_GEN_5__DI1_PT_4_5           0x1E04806C,0x00000300
+#define IPU_DI1_DW_GEN_5__DI1_PT_3_5           0x1E04806C,0x000000C0
+#define IPU_DI1_DW_GEN_5__DI1_PT_2_5           0x1E04806C,0x00000030
+#define IPU_DI1_DW_GEN_5__DI1_PT_1_5           0x1E04806C,0x0000000C
+#define IPU_DI1_DW_GEN_5__DI1_PT_0_5           0x1E04806C,0x00000003
+
+#define IPU_DI1_DW_GEN_5__ADDR                   0x1E04806C
+#define IPU_DI1_DW_GEN_5__EMPTY                          0x1E04806C,0x00000000
+#define IPU_DI1_DW_GEN_5__FULL                   0x1E04806C,0xffffffff
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5    0x1E04806C,0xFF000000
+#define IPU_DI1_DW_GEN_5__DI1_START_PERIOD_5     0x1E04806C,0x00FF0000
+#define IPU_DI1_DW_GEN_5__DI1_CST_5              0x1E04806C,0x0000C000
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1E04806C,0x000001F0
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_RS_5        0x1E04806C,0x0000000C
+#define IPU_DI1_DW_GEN_5__DI1_SERIAL_CLK_5       0x1E04806C,0x00000003
+
+#define IPU_DI1_DW_GEN_6__ADDR                 0x1E048070
+#define IPU_DI1_DW_GEN_6__EMPTY                        0x1E048070,0x00000000
+#define IPU_DI1_DW_GEN_6__FULL                 0x1E048070,0xffffffff
+#define IPU_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6    0x1E048070,0xFF000000
+#define IPU_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1E048070,0x00FF0000
+#define IPU_DI1_DW_GEN_6__DI1_CST_6            0x1E048070,0x0000C000
+#define IPU_DI1_DW_GEN_6__DI1_PT_6_6           0x1E048070,0x00003000
+#define IPU_DI1_DW_GEN_6__DI1_PT_5_6           0x1E048070,0x00000C00
+#define IPU_DI1_DW_GEN_6__DI1_PT_4_6           0x1E048070,0x00000300
+#define IPU_DI1_DW_GEN_6__DI1_PT_3_6           0x1E048070,0x000000C0
+#define IPU_DI1_DW_GEN_6__DI1_PT_2_6           0x1E048070,0x00000030
+#define IPU_DI1_DW_GEN_6__DI1_PT_1_6           0x1E048070,0x0000000C
+#define IPU_DI1_DW_GEN_6__DI1_PT_0_6           0x1E048070,0x00000003
+
+#define IPU_DI1_DW_GEN_6__ADDR                   0x1E048070
+#define IPU_DI1_DW_GEN_6__EMPTY                          0x1E048070,0x00000000
+#define IPU_DI1_DW_GEN_6__FULL                   0x1E048070,0xffffffff
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6    0x1E048070,0xFF000000
+#define IPU_DI1_DW_GEN_6__DI1_START_PERIOD_6     0x1E048070,0x00FF0000
+#define IPU_DI1_DW_GEN_6__DI1_CST_6              0x1E048070,0x0000C000
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1E048070,0x000001F0
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_RS_6        0x1E048070,0x0000000C
+#define IPU_DI1_DW_GEN_6__DI1_SERIAL_CLK_6       0x1E048070,0x00000003
+
+#define IPU_DI1_DW_GEN_7__ADDR                 0x1E048074
+#define IPU_DI1_DW_GEN_7__EMPTY                        0x1E048074,0x00000000
+#define IPU_DI1_DW_GEN_7__FULL                 0x1E048074,0xffffffff
+#define IPU_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7    0x1E048074,0xFF000000
+#define IPU_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1E048074,0x00FF0000
+#define IPU_DI1_DW_GEN_7__DI1_CST_7            0x1E048074,0x0000C000
+#define IPU_DI1_DW_GEN_7__DI1_PT_6_7           0x1E048074,0x00003000
+#define IPU_DI1_DW_GEN_7__DI1_PT_5_7           0x1E048074,0x00000C00
+#define IPU_DI1_DW_GEN_7__DI1_PT_4_7           0x1E048074,0x00000300
+#define IPU_DI1_DW_GEN_7__DI1_PT_3_7           0x1E048074,0x000000C0
+#define IPU_DI1_DW_GEN_7__DI1_PT_2_7           0x1E048074,0x00000030
+#define IPU_DI1_DW_GEN_7__DI1_PT_1_7           0x1E048074,0x0000000C
+#define IPU_DI1_DW_GEN_7__DI1_PT_0_7           0x1E048074,0x00000003
+
+#define IPU_DI1_DW_GEN_7__ADDR                   0x1E048074
+#define IPU_DI1_DW_GEN_7__EMPTY                          0x1E048074,0x00000000
+#define IPU_DI1_DW_GEN_7__FULL                   0x1E048074,0xffffffff
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7    0x1E048074,0xFF000000
+#define IPU_DI1_DW_GEN_7__DI1_START_PERIOD_7     0x1E048074,0x00FF0000
+#define IPU_DI1_DW_GEN_7__DI1_CST_7              0x1E048074,0x0000C000
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1E048074,0x000001F0
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_RS_7        0x1E048074,0x0000000C
+#define IPU_DI1_DW_GEN_7__DI1_SERIAL_CLK_7       0x1E048074,0x00000003
+
+#define IPU_DI1_DW_GEN_8__ADDR                 0x1E048078
+#define IPU_DI1_DW_GEN_8__EMPTY                        0x1E048078,0x00000000
+#define IPU_DI1_DW_GEN_8__FULL                 0x1E048078,0xffffffff
+#define IPU_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8    0x1E048078,0xFF000000
+#define IPU_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1E048078,0x00FF0000
+#define IPU_DI1_DW_GEN_8__DI1_CST_8            0x1E048078,0x0000C000
+#define IPU_DI1_DW_GEN_8__DI1_PT_6_8           0x1E048078,0x00003000
+#define IPU_DI1_DW_GEN_8__DI1_PT_5_8           0x1E048078,0x00000C00
+#define IPU_DI1_DW_GEN_8__DI1_PT_4_8           0x1E048078,0x00000300
+#define IPU_DI1_DW_GEN_8__DI1_PT_3_8           0x1E048078,0x000000C0
+#define IPU_DI1_DW_GEN_8__DI1_PT_2_8           0x1E048078,0x00000030
+#define IPU_DI1_DW_GEN_8__DI1_PT_1_8           0x1E048078,0x0000000C
+#define IPU_DI1_DW_GEN_8__DI1_PT_0_8           0x1E048078,0x00000003
+
+#define IPU_DI1_DW_GEN_8__ADDR                   0x1E048078
+#define IPU_DI1_DW_GEN_8__EMPTY                          0x1E048078,0x00000000
+#define IPU_DI1_DW_GEN_8__FULL                   0x1E048078,0xffffffff
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8    0x1E048078,0xFF000000
+#define IPU_DI1_DW_GEN_8__DI1_START_PERIOD_8     0x1E048078,0x00FF0000
+#define IPU_DI1_DW_GEN_8__DI1_CST_8              0x1E048078,0x0000C000
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1E048078,0x000001F0
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_RS_8        0x1E048078,0x0000000C
+#define IPU_DI1_DW_GEN_8__DI1_SERIAL_CLK_8       0x1E048078,0x00000003
+
+#define IPU_DI1_DW_GEN_9__ADDR                 0x1E04807C
+#define IPU_DI1_DW_GEN_9__EMPTY                        0x1E04807C,0x00000000
+#define IPU_DI1_DW_GEN_9__FULL                 0x1E04807C,0xffffffff
+#define IPU_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9    0x1E04807C,0xFF000000
+#define IPU_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1E04807C,0x00FF0000
+#define IPU_DI1_DW_GEN_9__DI1_CST_9            0x1E04807C,0x0000C000
+#define IPU_DI1_DW_GEN_9__DI1_PT_6_9           0x1E04807C,0x00003000
+#define IPU_DI1_DW_GEN_9__DI1_PT_5_9           0x1E04807C,0x00000C00
+#define IPU_DI1_DW_GEN_9__DI1_PT_4_9           0x1E04807C,0x00000300
+#define IPU_DI1_DW_GEN_9__DI1_PT_3_9           0x1E04807C,0x000000C0
+#define IPU_DI1_DW_GEN_9__DI1_PT_2_9           0x1E04807C,0x00000030
+#define IPU_DI1_DW_GEN_9__DI1_PT_1_9           0x1E04807C,0x0000000C
+#define IPU_DI1_DW_GEN_9__DI1_PT_0_9           0x1E04807C,0x00000003
+
+#define IPU_DI1_DW_GEN_9__ADDR                   0x1E04807C
+#define IPU_DI1_DW_GEN_9__EMPTY                          0x1E04807C,0x00000000
+#define IPU_DI1_DW_GEN_9__FULL                   0x1E04807C,0xffffffff
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9    0x1E04807C,0xFF000000
+#define IPU_DI1_DW_GEN_9__DI1_START_PERIOD_9     0x1E04807C,0x00FF0000
+#define IPU_DI1_DW_GEN_9__DI1_CST_9              0x1E04807C,0x0000C000
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1E04807C,0x000001F0
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_RS_9        0x1E04807C,0x0000000C
+#define IPU_DI1_DW_GEN_9__DI1_SERIAL_CLK_9       0x1E04807C,0x00000003
+
+#define IPU_DI1_DW_GEN_10__ADDR                          0x1E048080
+#define IPU_DI1_DW_GEN_10__EMPTY                 0x1E048080,0x00000000
+#define IPU_DI1_DW_GEN_10__FULL                          0x1E048080,0xffffffff
+#define IPU_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10    0x1E048080,0xFF000000
+#define IPU_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1E048080,0x00FF0000
+#define IPU_DI1_DW_GEN_10__DI1_CST_10            0x1E048080,0x0000C000
+#define IPU_DI1_DW_GEN_10__DI1_PT_6_10           0x1E048080,0x00003000
+#define IPU_DI1_DW_GEN_10__DI1_PT_5_10           0x1E048080,0x00000C00
+#define IPU_DI1_DW_GEN_10__DI1_PT_4_10           0x1E048080,0x00000300
+#define IPU_DI1_DW_GEN_10__DI1_PT_3_10           0x1E048080,0x000000C0
+#define IPU_DI1_DW_GEN_10__DI1_PT_2_10           0x1E048080,0x00000030
+#define IPU_DI1_DW_GEN_10__DI1_PT_1_10           0x1E048080,0x0000000C
+#define IPU_DI1_DW_GEN_10__DI1_PT_0_10           0x1E048080,0x00000003
+
+#define IPU_DI1_DW_GEN_10__ADDR                            0x1E048080
+#define IPU_DI1_DW_GEN_10__EMPTY                   0x1E048080,0x00000000
+#define IPU_DI1_DW_GEN_10__FULL                            0x1E048080,0xffffffff
+#define IPU_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10            0x1E048080,0xFF000000
+#define IPU_DI1_DW_GEN_10__DI1_START_PERIOD_10     0x1E048080,0x00FF0000
+#define IPU_DI1_DW_GEN_10__DI1_CST_10              0x1E048080,0x0000C000
+#define IPU_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1E048080,0x000001F0
+#define IPU_DI1_DW_GEN_10__DI1_SERIAL_RS_10        0x1E048080,0x0000000C
+#define IPU_DI1_DW_GEN_10__DI1_SERIAL_CLK_10       0x1E048080,0x00000003
+
+#define IPU_DI1_DW_GEN_11__ADDR                          0x1E048084
+#define IPU_DI1_DW_GEN_11__EMPTY                 0x1E048084,0x00000000
+#define IPU_DI1_DW_GEN_11__FULL                          0x1E048084,0xffffffff
+#define IPU_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11    0x1E048084,0xFF000000
+#define IPU_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1E048084,0x00FF0000
+#define IPU_DI1_DW_GEN_11__DI1_CST_11            0x1E048084,0x0000C000
+#define IPU_DI1_DW_GEN_11__DI1_PT_6_11           0x1E048084,0x00003000
+#define IPU_DI1_DW_GEN_11__DI1_PT_5_11           0x1E048084,0x00000C00
+#define IPU_DI1_DW_GEN_11__DI1_PT_4_11           0x1E048084,0x00000300
+#define IPU_DI1_DW_GEN_11__DI1_PT_3_11           0x1E048084,0x000000C0
+#define IPU_DI1_DW_GEN_11__DI1_PT_2_11           0x1E048084,0x00000030
+#define IPU_DI1_DW_GEN_11__DI1_PT_1_11           0x1E048084,0x0000000C
+#define IPU_DI1_DW_GEN_11__DI1_PT_0_11           0x1E048084,0x00000003
+
+#define IPU_DI1_DW_GEN_11__ADDR                            0x1E048084
+#define IPU_DI1_DW_GEN_11__EMPTY                   0x1E048084,0x00000000
+#define IPU_DI1_DW_GEN_11__FULL                            0x1E048084,0xffffffff
+#define IPU_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11            0x1E048084,0xFF000000
+#define IPU_DI1_DW_GEN_11__DI1_START_PERIOD_11     0x1E048084,0x00FF0000
+#define IPU_DI1_DW_GEN_11__DI1_CST_11              0x1E048084,0x0000C000
+#define IPU_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1E048084,0x000001F0
+#define IPU_DI1_DW_GEN_11__DI1_SERIAL_RS_11        0x1E048084,0x0000000C
+#define IPU_DI1_DW_GEN_11__DI1_SERIAL_CLK_11       0x1E048084,0x00000003
+
+#define IPU_DI1_STP_REP_9__ADDR                     0x1E048158
+#define IPU_DI1_STP_REP_9__EMPTY            0x1E048158,0x00000000
+#define IPU_DI1_STP_REP_9__FULL                     0x1E048158,0xffffffff
+#define IPU_DI1_STP_REP_9__DI1_STEP_REPEAT_9 0x1E048158,0x00000FFF
+
+#define IPU_DI1_SER_CONF__ADDR                      0x1E04815C
+#define IPU_DI1_SER_CONF__EMPTY                             0x1E04815C,0x00000000
+#define IPU_DI1_SER_CONF__FULL                      0x1E04815C,0xffffffff
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1 0x1E04815C,0xF0000000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0 0x1E04815C,0x0F000000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1 0x1E04815C,0x00F00000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0 0x1E04815C,0x000F0000
+#define IPU_DI1_SER_CONF__DI1_SERIAL_LATCH          0x1E04815C,0x0000FF00
+#define IPU_DI1_SER_CONF__DI1_LLA_SER_ACCESS        0x1E04815C,0x00000020
+#define IPU_DI1_SER_CONF__DI1_SER_CLK_POLARITY      0x1E04815C,0x00000010
+#define IPU_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY   0x1E04815C,0x00000008
+#define IPU_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY     0x1E04815C,0x00000004
+#define IPU_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY     0x1E04815C,0x00000002
+#define IPU_DI1_SER_CONF__DI1_WAIT4SERIAL           0x1E04815C,0x00000001
+
+#define IPU_DI1_SSC__ADDR             0x1E048160
+#define IPU_DI1_SSC__EMPTY            0x1E048160,0x00000000
+#define IPU_DI1_SSC__FULL             0x1E048160,0xffffffff
+#define IPU_DI1_SSC__DI1_PIN17_ERM     0x1E048160,0x00800000
+#define IPU_DI1_SSC__DI1_PIN16_ERM     0x1E048160,0x00400000
+#define IPU_DI1_SSC__DI1_PIN15_ERM     0x1E048160,0x00200000
+#define IPU_DI1_SSC__DI1_PIN14_ERM     0x1E048160,0x00100000
+#define IPU_DI1_SSC__DI1_PIN13_ERM     0x1E048160,0x00080000
+#define IPU_DI1_SSC__DI1_PIN12_ERM     0x1E048160,0x00040000
+#define IPU_DI1_SSC__DI1_PIN11_ERM     0x1E048160,0x00020000
+#define IPU_DI1_SSC__DI1_CS_ERM               0x1E048160,0x00010000
+#define IPU_DI1_SSC__DI1_WAIT_ON       0x1E048160,0x00000020
+#define IPU_DI1_SSC__DI1_BYTE_EN_RD_IN 0x1E048160,0x00000008
+#define IPU_DI1_SSC__DI1_BYTE_EN_PNTR  0x1E048160,0x00000007
+
+#define IPU_DI1_POL__ADDR                    0x1E048164
+#define IPU_DI1_POL__EMPTY                   0x1E048164,0x00000000
+#define IPU_DI1_POL__FULL                    0x1E048164,0xffffffff
+#define IPU_DI1_POL__DI1_WAIT_POLARITY       0x1E048164,0x04000000
+#define IPU_DI1_POL__DI1_CS1_BYTE_EN_POLARITY 0x1E048164,0x02000000
+#define IPU_DI1_POL__DI1_CS0_BYTE_EN_POLARITY 0x1E048164,0x01000000
+#define IPU_DI1_POL__DI1_CS1_DATA_POLARITY    0x1E048164,0x00800000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_17      0x1E048164,0x00400000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_16      0x1E048164,0x00200000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_15      0x1E048164,0x00100000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_14      0x1E048164,0x00080000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_13      0x1E048164,0x00040000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_12      0x1E048164,0x00020000
+#define IPU_DI1_POL__DI1_CS1_POLARITY_11      0x1E048164,0x00010000
+#define IPU_DI1_POL__DI1_CS0_DATA_POLARITY    0x1E048164,0x00008000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_17      0x1E048164,0x00004000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_16      0x1E048164,0x00002000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_15      0x1E048164,0x00001000
+#define IPU_DI1_POL__DI1_CS0_POLARITY_14      0x1E048164,0x00000800
+#define IPU_DI1_POL__DI1_CS0_POLARITY_13      0x1E048164,0x00000400
+#define IPU_DI1_POL__DI1_CS0_POLARITY_12      0x1E048164,0x00000200
+#define IPU_DI1_POL__DI1_CS0_POLARITY_11      0x1E048164,0x00000100
+#define IPU_DI1_POL__DI1_DRDY_DATA_POLARITY   0x1E048164,0x00000080
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_17     0x1E048164,0x00000040
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_16     0x1E048164,0x00000020
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_15     0x1E048164,0x00000010
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_14     0x1E048164,0x00000008
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_13     0x1E048164,0x00000004
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_12     0x1E048164,0x00000002
+#define IPU_DI1_POL__DI1_DRDY_POLARITY_11     0x1E048164,0x00000001
+
+#define IPU_DI1_AW0__ADDR             0x1E048168
+#define IPU_DI1_AW0__EMPTY            0x1E048168,0x00000000
+#define IPU_DI1_AW0__FULL             0x1E048168,0xffffffff
+#define IPU_DI1_AW0__DI1_AW_TRIG_SEL   0x1E048168,0xF0000000
+#define IPU_DI1_AW0__DI1_AW_HEND       0x1E048168,0x0FFF0000
+#define IPU_DI1_AW0__DI1_AW_HCOUNT_SEL 0x1E048168,0x0000F000
+#define IPU_DI1_AW0__DI1_AW_HSTART     0x1E048168,0x00000FFF
+
+#define IPU_DI1_AW1__ADDR             0x1E04816C
+#define IPU_DI1_AW1__EMPTY            0x1E04816C,0x00000000
+#define IPU_DI1_AW1__FULL             0x1E04816C,0xffffffff
+#define IPU_DI1_AW1__DI1_AW_VEND       0x1E04816C,0x0FFF0000
+#define IPU_DI1_AW1__DI1_AW_VCOUNT_SEL 0x1E04816C,0x0000F000
+#define IPU_DI1_AW1__DI1_AW_VSTART     0x1E04816C,0x00000FFF
+
+#define IPU_DI1_SCR_CONF__ADDR             0x1E048170
+#define IPU_DI1_SCR_CONF__EMPTY                    0x1E048170,0x00000000
+#define IPU_DI1_SCR_CONF__FULL             0x1E048170,0xffffffff
+#define IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT 0x1E048170,0x00000FFF
+
+#define IPU_DI1_STAT__ADDR               0x1E048174
+#define IPU_DI1_STAT__EMPTY              0x1E048174,0x00000000
+#define IPU_DI1_STAT__FULL               0x1E048174,0xffffffff
+#define IPU_DI1_STAT__DI1_CNTR_FIFO_FULL  0x1E048174,0x00000008
+#define IPU_DI1_STAT__DI1_CNTR_FIFO_EMPTY 0x1E048174,0x00000004
+#define IPU_DI1_STAT__DI1_READ_FIFO_FULL  0x1E048174,0x00000002
+#define IPU_DI1_STAT__DI1_READ_FIFO_EMPTY 0x1E048174,0x00000001
+// ================= End of IPUV3EX DI Registers =====================
+
+// ================= Start of IPUV3EX SMFC Registers =====================
+#define IPU_SMFC_MAP__ADDR    0x1E050000
+#define IPU_SMFC_MAP__EMPTY   0x1E050000,0x00000000
+#define IPU_SMFC_MAP__FULL    0x1E050000,0xffffffff
+#define IPU_SMFC_MAP__MAP_CH3 0x1E050000,0x00000E00
+#define IPU_SMFC_MAP__MAP_CH2 0x1E050000,0x000001C0
+#define IPU_SMFC_MAP__MAP_CH1 0x1E050000,0x00000038
+#define IPU_SMFC_MAP__MAP_CH0 0x1E050000,0x00000007
+
+#define IPU_SMFC_WMC__ADDR    0x1E050004
+#define IPU_SMFC_WMC__EMPTY   0x1E050004,0x00000000
+#define IPU_SMFC_WMC__FULL    0x1E050004,0xffffffff
+#define IPU_SMFC_WMC__WM3_CLR 0x1E050004,0x0E000000
+#define IPU_SMFC_WMC__WM3_SET 0x1E050004,0x01C00000
+#define IPU_SMFC_WMC__WM2_CLR 0x1E050004,0x00380000
+#define IPU_SMFC_WMC__WM2_SET 0x1E050004,0x00070000
+#define IPU_SMFC_WMC__WM1_CLR 0x1E050004,0x00000E00
+#define IPU_SMFC_WMC__WM1_SET 0x1E050004,0x000001C0
+#define IPU_SMFC_WMC__WM0_CLR 0x1E050004,0x00000038
+#define IPU_SMFC_WMC__WM0_SET 0x1E050004,0x00000007
+
+#define IPU_SMFC_BS__ADDR       0x1E050008
+#define IPU_SMFC_BS__EMPTY      0x1E050008,0x00000000
+#define IPU_SMFC_BS__FULL       0x1E050008,0xffffffff
+#define IPU_SMFC_BS__BURST3_SIZE 0x1E050008,0x0000F000
+#define IPU_SMFC_BS__BURST2_SIZE 0x1E050008,0x00000F00
+#define IPU_SMFC_BS__BURST1_SIZE 0x1E050008,0x000000F0
+#define IPU_SMFC_BS__BURST0_SIZE 0x1E050008,0x0000000F
+// ================= End of IPUV3EX SMFC Registers =====================
+
+// ================= Start of IPUV3EX DC Registers =====================
+#define IPU_DC_READ_CH_CONF__ADDR               0x1E058000
+#define IPU_DC_READ_CH_CONF__EMPTY              0x1E058000,0x00000000
+#define IPU_DC_READ_CH_CONF__FULL               0x1E058000,0xffffffff
+#define IPU_DC_READ_CH_CONF__TIME_OUT_VALUE     0x1E058000,0xFFFF0000
+#define IPU_DC_READ_CH_CONF__CS_ID_3            0x1E058000,0x00000800
+#define IPU_DC_READ_CH_CONF__CS_ID_2            0x1E058000,0x00000400
+#define IPU_DC_READ_CH_CONF__CS_ID_1            0x1E058000,0x00000200
+#define IPU_DC_READ_CH_CONF__CS_ID_0            0x1E058000,0x00000100
+#define IPU_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0 0x1E058000,0x00000040
+#define IPU_DC_READ_CH_CONF__W_SIZE_0           0x1E058000,0x00000030
+#define IPU_DC_READ_CH_CONF__PROG_DISP_ID_0     0x1E058000,0x0000000C
+#define IPU_DC_READ_CH_CONF__PROG_DI_ID_0       0x1E058000,0x00000002
+#define IPU_DC_READ_CH_CONF__RD_CHANNEL_EN      0x1E058000,0x00000001
+
+#define IPU_DC_READ_CH_ADDR__ADDR      0x1E058004
+#define IPU_DC_READ_CH_ADDR__EMPTY     0x1E058004,0x00000000
+#define IPU_DC_READ_CH_ADDR__FULL      0x1E058004,0xffffffff
+#define IPU_DC_READ_CH_ADDR__ST_ADDR_0 0x1E058004,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_0__ADDR                  0x1E058008
+#define IPU_DC_RL0_CH_0__EMPTY                 0x1E058008,0x00000000
+#define IPU_DC_RL0_CH_0__FULL                  0x1E058008,0xffffffff
+#define IPU_DC_RL0_CH_0__COD_NL_START_CHAN_0   0x1E058008,0xFF000000
+#define IPU_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0 0x1E058008,0x000F0000
+#define IPU_DC_RL0_CH_0__COD_NF_START_CHAN_0   0x1E058008,0x0000FF00
+#define IPU_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0 0x1E058008,0x0000000F
+
+#define IPU_DC_RL1_CH_0__ADDR                      0x1E05800C
+#define IPU_DC_RL1_CH_0__EMPTY                     0x1E05800C,0x00000000
+#define IPU_DC_RL1_CH_0__FULL                      0x1E05800C,0xffffffff
+#define IPU_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0    0x1E05800C,0xFF000000
+#define IPU_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0 0x1E05800C,0x000F0000
+#define IPU_DC_RL1_CH_0__COD_EOF_START_CHAN_0      0x1E05800C,0x0000FF00
+#define IPU_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0    0x1E05800C,0x0000000F
+
+#define IPU_DC_RL2_CH_0__ADDR                       0x1E058010
+#define IPU_DC_RL2_CH_0__EMPTY                      0x1E058010,0x00000000
+#define IPU_DC_RL2_CH_0__FULL                       0x1E058010,0xffffffff
+#define IPU_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0    0x1E058010,0xFF000000
+#define IPU_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0 0x1E058010,0x000F0000
+#define IPU_DC_RL2_CH_0__COD_EOL_START_CHAN_0       0x1E058010,0x0000FF00
+#define IPU_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0     0x1E058010,0x0000000F
+
+#define IPU_DC_RL3_CH_0__ADDR                        0x1E058014
+#define IPU_DC_RL3_CH_0__EMPTY                       0x1E058014,0x00000000
+#define IPU_DC_RL3_CH_0__FULL                        0x1E058014,0xffffffff
+#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0    0x1E058014,0xFF000000
+#define IPU_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0 0x1E058014,0x000F0000
+#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0    0x1E058014,0x0000FF00
+#define IPU_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0 0x1E058014,0x0000000F
+
+#define IPU_DC_RL4_CH_0__ADDR                        0x1E058018
+#define IPU_DC_RL4_CH_0__EMPTY                       0x1E058018,0x00000000
+#define IPU_DC_RL4_CH_0__FULL                        0x1E058018,0xffffffff
+#define IPU_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0    0x1E058018,0x0000FF00
+#define IPU_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0 0x1E058018,0x0000000F
+
+#define IPU_DC_WR_CH_CONF_1__ADDR               0x1E05801C
+#define IPU_DC_WR_CH_CONF_1__EMPTY              0x1E05801C,0x00000000
+#define IPU_DC_WR_CH_CONF_1__FULL               0x1E05801C,0xffffffff
+#define IPU_DC_WR_CH_CONF_1__PROG_START_TIME_1  0x1E05801C,0x07FF0000
+#define IPU_DC_WR_CH_CONF_1__FIELD_MODE_1       0x1E05801C,0x00000200
+#define IPU_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1 0x1E05801C,0x00000100
+#define IPU_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1    0x1E05801C,0x000000E0
+#define IPU_DC_WR_CH_CONF_1__PROG_DISP_ID_1     0x1E05801C,0x00000018
+#define IPU_DC_WR_CH_CONF_1__PROG_DI_ID_1       0x1E05801C,0x00000004
+#define IPU_DC_WR_CH_CONF_1__W_SIZE_1           0x1E05801C,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_1__ADDR      0x1E058020
+#define IPU_DC_WR_CH_ADDR_1__EMPTY     0x1E058020,0x00000000
+#define IPU_DC_WR_CH_ADDR_1__FULL      0x1E058020,0xffffffff
+#define IPU_DC_WR_CH_ADDR_1__ST_ADDR_1 0x1E058020,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_1__ADDR                  0x1E058024
+#define IPU_DC_RL0_CH_1__EMPTY                 0x1E058024,0x00000000
+#define IPU_DC_RL0_CH_1__FULL                  0x1E058024,0xffffffff
+#define IPU_DC_RL0_CH_1__COD_NL_START_CHAN_1   0x1E058024,0xFF000000
+#define IPU_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1 0x1E058024,0x000F0000
+#define IPU_DC_RL0_CH_1__COD_NF_START_CHAN_1   0x1E058024,0x0000FF00
+#define IPU_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1 0x1E058024,0x0000000F
+
+#define IPU_DC_RL1_CH_1__ADDR                      0x1E058028
+#define IPU_DC_RL1_CH_1__EMPTY                     0x1E058028,0x00000000
+#define IPU_DC_RL1_CH_1__FULL                      0x1E058028,0xffffffff
+#define IPU_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1    0x1E058028,0xFF000000
+#define IPU_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1 0x1E058028,0x000F0000
+#define IPU_DC_RL1_CH_1__COD_EOF_START_CHAN_1      0x1E058028,0x0000FF00
+#define IPU_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1    0x1E058028,0x0000000F
+
+#define IPU_DC_RL2_CH_1__ADDR                       0x1E05802C
+#define IPU_DC_RL2_CH_1__EMPTY                      0x1E05802C,0x00000000
+#define IPU_DC_RL2_CH_1__FULL                       0x1E05802C,0xffffffff
+#define IPU_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1    0x1E05802C,0xFF000000
+#define IPU_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1 0x1E05802C,0x000F0000
+#define IPU_DC_RL2_CH_1__COD_EOL_START_CHAN_1       0x1E05802C,0x0000FF00
+#define IPU_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1     0x1E05802C,0x0000000F
+
+#define IPU_DC_RL3_CH_1__ADDR                        0x1E058030
+#define IPU_DC_RL3_CH_1__EMPTY                       0x1E058030,0x00000000
+#define IPU_DC_RL3_CH_1__FULL                        0x1E058030,0xffffffff
+#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1    0x1E058030,0xFF000000
+#define IPU_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1 0x1E058030,0x000F0000
+#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1    0x1E058030,0x0000FF00
+#define IPU_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1 0x1E058030,0x0000000F
+
+#define IPU_DC_RL4_CH_1__ADDR                        0x1E058034
+#define IPU_DC_RL4_CH_1__EMPTY                       0x1E058034,0x00000000
+#define IPU_DC_RL4_CH_1__FULL                        0x1E058034,0xffffffff
+#define IPU_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1    0x1E058034,0x0000FF00
+#define IPU_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1 0x1E058034,0x0000000F
+
+#define IPU_DC_WR_CH_CONF_2__ADDR               0x1E058038
+#define IPU_DC_WR_CH_CONF_2__EMPTY              0x1E058038,0x00000000
+#define IPU_DC_WR_CH_CONF_2__FULL               0x1E058038,0xffffffff
+#define IPU_DC_WR_CH_CONF_2__PROG_START_TIME_2  0x1E058038,0x07FF0000
+#define IPU_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2 0x1E058038,0x00000100
+#define IPU_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2    0x1E058038,0x000000E0
+#define IPU_DC_WR_CH_CONF_2__PROG_DISP_ID_2     0x1E058038,0x00000018
+#define IPU_DC_WR_CH_CONF_2__PROG_DI_ID_2       0x1E058038,0x00000004
+#define IPU_DC_WR_CH_CONF_2__W_SIZE_2           0x1E058038,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_2__ADDR      0x1E05803C
+#define IPU_DC_WR_CH_ADDR_2__EMPTY     0x1E05803C,0x00000000
+#define IPU_DC_WR_CH_ADDR_2__FULL      0x1E05803C,0xffffffff
+#define IPU_DC_WR_CH_ADDR_2__ST_ADDR_2 0x1E05803C,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_2__ADDR                  0x1E058040
+#define IPU_DC_RL0_CH_2__EMPTY                 0x1E058040,0x00000000
+#define IPU_DC_RL0_CH_2__FULL                  0x1E058040,0xffffffff
+#define IPU_DC_RL0_CH_2__COD_NL_START_CHAN_2   0x1E058040,0xFF000000
+#define IPU_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2 0x1E058040,0x000F0000
+#define IPU_DC_RL0_CH_2__COD_NF_START_CHAN_2   0x1E058040,0x0000FF00
+#define IPU_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2 0x1E058040,0x0000000F
+
+#define IPU_DC_RL1_CH_2__ADDR                      0x1E058044
+#define IPU_DC_RL1_CH_2__EMPTY                     0x1E058044,0x00000000
+#define IPU_DC_RL1_CH_2__FULL                      0x1E058044,0xffffffff
+#define IPU_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2    0x1E058044,0xFF000000
+#define IPU_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2 0x1E058044,0x000F0000
+#define IPU_DC_RL1_CH_2__COD_EOF_START_CHAN_2      0x1E058044,0x0000FF00
+#define IPU_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2    0x1E058044,0x0000000F
+
+#define IPU_DC_RL2_CH_2__ADDR                       0x1E058048
+#define IPU_DC_RL2_CH_2__EMPTY                      0x1E058048,0x00000000
+#define IPU_DC_RL2_CH_2__FULL                       0x1E058048,0xffffffff
+#define IPU_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2    0x1E058048,0xFF000000
+#define IPU_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2 0x1E058048,0x000F0000
+#define IPU_DC_RL2_CH_2__COD_EOL_START_CHAN_2       0x1E058048,0x0000FF00
+#define IPU_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2     0x1E058048,0x0000000F
+
+#define IPU_DC_RL3_CH_2__ADDR                        0x1E05804C
+#define IPU_DC_RL3_CH_2__EMPTY                       0x1E05804C,0x00000000
+#define IPU_DC_RL3_CH_2__FULL                        0x1E05804C,0xffffffff
+#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2    0x1E05804C,0xFF000000
+#define IPU_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2 0x1E05804C,0x000F0000
+#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2    0x1E05804C,0x0000FF00
+#define IPU_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2 0x1E05804C,0x0000000F
+
+#define IPU_DC_RL4_CH_2__ADDR                        0x1E058050
+#define IPU_DC_RL4_CH_2__EMPTY                       0x1E058050,0x00000000
+#define IPU_DC_RL4_CH_2__FULL                        0x1E058050,0xffffffff
+#define IPU_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2    0x1E058050,0x0000FF00
+#define IPU_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2 0x1E058050,0x0000000F
+
+#define IPU_DC_CMD_CH_CONF_3__ADDR                     0x1E058054
+#define IPU_DC_CMD_CH_CONF_3__EMPTY                    0x1E058054,0x00000000
+#define IPU_DC_CMD_CH_CONF_3__FULL                     0x1E058054,0xffffffff
+#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3 0x1E058054,0xFF000000
+#define IPU_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3 0x1E058054,0x0000FF00
+#define IPU_DC_CMD_CH_CONF_3__W_SIZE_3                 0x1E058054,0x00000003
+
+#define IPU_DC_CMD_CH_CONF_4__ADDR                     0x1E058058
+#define IPU_DC_CMD_CH_CONF_4__EMPTY                    0x1E058058,0x00000000
+#define IPU_DC_CMD_CH_CONF_4__FULL                     0x1E058058,0xffffffff
+#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4 0x1E058058,0xFF000000
+#define IPU_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4 0x1E058058,0x0000FF00
+#define IPU_DC_CMD_CH_CONF_4__W_SIZE_4                 0x1E058058,0x00000003
+
+#define IPU_DC_WR_CH_CONF_5__ADDR               0x1E05805C
+#define IPU_DC_WR_CH_CONF_5__EMPTY              0x1E05805C,0x00000000
+#define IPU_DC_WR_CH_CONF_5__FULL               0x1E05805C,0xffffffff
+#define IPU_DC_WR_CH_CONF_5__PROG_START_TIME_5  0x1E05805C,0x07FF0000
+#define IPU_DC_WR_CH_CONF_5__FIELD_MODE_5       0x1E05805C,0x00000200
+#define IPU_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5 0x1E05805C,0x00000100
+#define IPU_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5    0x1E05805C,0x000000E0
+#define IPU_DC_WR_CH_CONF_5__PROG_DISP_ID_5     0x1E05805C,0x00000018
+#define IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5       0x1E05805C,0x00000004
+#define IPU_DC_WR_CH_CONF_5__W_SIZE_5           0x1E05805C,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_5__ADDR      0x1E058060
+#define IPU_DC_WR_CH_ADDR_5__EMPTY     0x1E058060,0x00000000
+#define IPU_DC_WR_CH_ADDR_5__FULL      0x1E058060,0xffffffff
+#define IPU_DC_WR_CH_ADDR_5__ST_ADDR_5 0x1E058060,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_5__ADDR                  0x1E058064
+#define IPU_DC_RL0_CH_5__EMPTY                 0x1E058064,0x00000000
+#define IPU_DC_RL0_CH_5__FULL                  0x1E058064,0xffffffff
+#define IPU_DC_RL0_CH_5__COD_NL_START_CHAN_5   0x1E058064,0xFF000000
+#define IPU_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5 0x1E058064,0x000F0000
+#define IPU_DC_RL0_CH_5__COD_NF_START_CHAN_5   0x1E058064,0x0000FF00
+#define IPU_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5 0x1E058064,0x0000000F
+
+#define IPU_DC_RL1_CH_5__ADDR                      0x1E058068
+#define IPU_DC_RL1_CH_5__EMPTY                     0x1E058068,0x00000000
+#define IPU_DC_RL1_CH_5__FULL                      0x1E058068,0xffffffff
+#define IPU_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5    0x1E058068,0xFF000000
+#define IPU_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5 0x1E058068,0x000F0000
+#define IPU_DC_RL1_CH_5__COD_EOF_START_CHAN_5      0x1E058068,0x0000FF00
+#define IPU_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5    0x1E058068,0x0000000F
+
+#define IPU_DC_RL2_CH_5__ADDR                       0x1E05806C
+#define IPU_DC_RL2_CH_5__EMPTY                      0x1E05806C,0x00000000
+#define IPU_DC_RL2_CH_5__FULL                       0x1E05806C,0xffffffff
+#define IPU_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5    0x1E05806C,0xFF000000
+#define IPU_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5 0x1E05806C,0x000F0000
+#define IPU_DC_RL2_CH_5__COD_EOL_START_CHAN_5       0x1E05806C,0x0000FF00
+#define IPU_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5     0x1E05806C,0x0000000F
+
+#define IPU_DC_RL3_CH_5__ADDR                        0x1E058070
+#define IPU_DC_RL3_CH_5__EMPTY                       0x1E058070,0x00000000
+#define IPU_DC_RL3_CH_5__FULL                        0x1E058070,0xffffffff
+#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5    0x1E058070,0xFF000000
+#define IPU_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5 0x1E058070,0x000F0000
+#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5    0x1E058070,0x0000FF00
+#define IPU_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5 0x1E058070,0x0000000F
+
+#define IPU_DC_RL4_CH_5__ADDR                        0x1E058074
+#define IPU_DC_RL4_CH_5__EMPTY                       0x1E058074,0x00000000
+#define IPU_DC_RL4_CH_5__FULL                        0x1E058074,0xffffffff
+#define IPU_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5    0x1E058074,0x0000FF00
+#define IPU_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5 0x1E058074,0x0000000F
+
+#define IPU_DC_WR_CH_CONF_6__ADDR               0x1E058078
+#define IPU_DC_WR_CH_CONF_6__EMPTY              0x1E058078,0x00000000
+#define IPU_DC_WR_CH_CONF_6__FULL               0x1E058078,0xffffffff
+#define IPU_DC_WR_CH_CONF_6__PROG_START_TIME_6  0x1E058078,0x07FF0000
+#define IPU_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6 0x1E058078,0x00000100
+#define IPU_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6    0x1E058078,0x000000E0
+#define IPU_DC_WR_CH_CONF_6__PROG_DISP_ID_6     0x1E058078,0x00000018
+#define IPU_DC_WR_CH_CONF_6__PROG_DI_ID_6       0x1E058078,0x00000004
+#define IPU_DC_WR_CH_CONF_6__W_SIZE_6           0x1E058078,0x00000003
+
+#define IPU_DC_WR_CH_ADDR_6__ADDR      0x1E05807C
+#define IPU_DC_WR_CH_ADDR_6__EMPTY     0x1E05807C,0x00000000
+#define IPU_DC_WR_CH_ADDR_6__FULL      0x1E05807C,0xffffffff
+#define IPU_DC_WR_CH_ADDR_6__ST_ADDR_6 0x1E05807C,0x1FFFFFFF
+
+#define IPU_DC_RL0_CH_6__ADDR                  0x1E058080
+#define IPU_DC_RL0_CH_6__EMPTY                 0x1E058080,0x00000000
+#define IPU_DC_RL0_CH_6__FULL                  0x1E058080,0xffffffff
+#define IPU_DC_RL0_CH_6__COD_NL_START_CHAN_6   0x1E058080,0xFF000000
+#define IPU_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6 0x1E058080,0x000F0000
+#define IPU_DC_RL0_CH_6__COD_NF_START_CHAN_6   0x1E058080,0x0000FF00
+#define IPU_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6 0x1E058080,0x0000000F
+
+#define IPU_DC_RL1_CH_6__ADDR                      0x1E058084
+#define IPU_DC_RL1_CH_6__EMPTY                     0x1E058084,0x00000000
+#define IPU_DC_RL1_CH_6__FULL                      0x1E058084,0xffffffff
+#define IPU_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6    0x1E058084,0xFF000000
+#define IPU_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6 0x1E058084,0x000F0000
+#define IPU_DC_RL1_CH_6__COD_EOF_START_CHAN_6      0x1E058084,0x0000FF00
+#define IPU_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6    0x1E058084,0x0000000F
+
+#define IPU_DC_RL2_CH_6__ADDR                       0x1E058088
+#define IPU_DC_RL2_CH_6__EMPTY                      0x1E058088,0x00000000
+#define IPU_DC_RL2_CH_6__FULL                       0x1E058088,0xffffffff
+#define IPU_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6    0x1E058088,0xFF000000
+#define IPU_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6 0x1E058088,0x000F0000
+#define IPU_DC_RL2_CH_6__COD_EOL_START_CHAN_6       0x1E058088,0x0000FF00
+#define IPU_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6     0x1E058088,0x0000000F
+
+#define IPU_DC_RL3_CH_6__ADDR                        0x1E05808C
+#define IPU_DC_RL3_CH_6__EMPTY                       0x1E05808C,0x00000000
+#define IPU_DC_RL3_CH_6__FULL                        0x1E05808C,0xffffffff
+#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6    0x1E05808C,0xFF000000
+#define IPU_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6 0x1E05808C,0x000F0000
+#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6    0x1E05808C,0x0000FF00
+#define IPU_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6 0x1E05808C,0x0000000F
+
+#define IPU_DC_RL4_CH_6__ADDR                        0x1E058090
+#define IPU_DC_RL4_CH_6__EMPTY                       0x1E058090,0x00000000
+#define IPU_DC_RL4_CH_6__FULL                        0x1E058090,0xffffffff
+#define IPU_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6    0x1E058090,0x0000FF00
+#define IPU_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6 0x1E058090,0x0000000F
+
+#define IPU_DC_WR_CH_CONF1_8__ADDR               0x1E058094
+#define IPU_DC_WR_CH_CONF1_8__EMPTY              0x1E058094,0x00000000
+#define IPU_DC_WR_CH_CONF1_8__FULL               0x1E058094,0xffffffff
+#define IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8      0x1E058094,0x00000018
+#define IPU_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8 0x1E058094,0x00000004
+#define IPU_DC_WR_CH_CONF1_8__W_SIZE_8           0x1E058094,0x00000003
+
+#define IPU_DC_WR_CH_CONF2_8__ADDR               0x1E058098
+#define IPU_DC_WR_CH_CONF2_8__EMPTY              0x1E058098,0x00000000
+#define IPU_DC_WR_CH_CONF2_8__FULL               0x1E058098,0xffffffff
+#define IPU_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8 0x1E058098,0x1FFFFFFF
+
+#define IPU_DC_RL1_CH_8__ADDR                         0x1E05809C
+#define IPU_DC_RL1_CH_8__EMPTY                        0x1E05809C,0x00000000
+#define IPU_DC_RL1_CH_8__FULL                         0x1E05809C,0xffffffff
+#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1 0x1E05809C,0xFF000000
+#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0 0x1E05809C,0x0000FF00
+#define IPU_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8  0x1E05809C,0x0000000F
+
+#define IPU_DC_RL2_CH_8__ADDR                         0x1E0580A0
+#define IPU_DC_RL2_CH_8__EMPTY                        0x1E0580A0,0x00000000
+#define IPU_DC_RL2_CH_8__FULL                         0x1E0580A0,0xffffffff
+#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1 0x1E0580A0,0xFF000000
+#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0 0x1E0580A0,0x0000FF00
+#define IPU_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8  0x1E0580A0,0x0000000F
+
+#define IPU_DC_RL3_CH_8__ADDR                         0x1E0580A4
+#define IPU_DC_RL3_CH_8__EMPTY                        0x1E0580A4,0x00000000
+#define IPU_DC_RL3_CH_8__FULL                         0x1E0580A4,0xffffffff
+#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1 0x1E0580A4,0xFF000000
+#define IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0 0x1E0580A4,0x0000FF00
+#define IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8  0x1E0580A4,0x0000000F
+
+#define IPU_DC_RL4_CH_8__ADDR                         0x1E0580A8
+#define IPU_DC_RL4_CH_8__EMPTY                        0x1E0580A8,0x00000000
+#define IPU_DC_RL4_CH_8__FULL                         0x1E0580A8,0xffffffff
+#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1 0x1E0580A8,0xFF000000
+#define IPU_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0 0x1E0580A8,0x0000FF00
+
+#define IPU_DC_RL5_CH_8__ADDR                         0x1E0580AC
+#define IPU_DC_RL5_CH_8__EMPTY                        0x1E0580AC,0x00000000
+#define IPU_DC_RL5_CH_8__FULL                         0x1E0580AC,0xffffffff
+#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1 0x1E0580AC,0xFF000000
+#define IPU_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0 0x1E0580AC,0x0000FF00
+
+#define IPU_DC_RL6_CH_8__ADDR                         0x1E0580B0
+#define IPU_DC_RL6_CH_8__EMPTY                        0x1E0580B0,0x00000000
+#define IPU_DC_RL6_CH_8__FULL                         0x1E0580B0,0xffffffff
+#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1 0x1E0580B0,0xFF000000
+#define IPU_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0 0x1E0580B0,0x0000FF00
+
+#define IPU_DC_WR_CH_CONF1_9__ADDR               0x1E0580B4
+#define IPU_DC_WR_CH_CONF1_9__EMPTY              0x1E0580B4,0x00000000
+#define IPU_DC_WR_CH_CONF1_9__FULL               0x1E0580B4,0xffffffff
+#define IPU_DC_WR_CH_CONF1_9__MCU_DISP_ID_9      0x1E0580B4,0x00000018
+#define IPU_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9 0x1E0580B4,0x00000004
+#define IPU_DC_WR_CH_CONF1_9__W_SIZE_9           0x1E0580B4,0x00000003
+
+#define IPU_DC_WR_CH_CONF2_9__ADDR               0x1E0580B8
+#define IPU_DC_WR_CH_CONF2_9__EMPTY              0x1E0580B8,0x00000000
+#define IPU_DC_WR_CH_CONF2_9__FULL               0x1E0580B8,0xffffffff
+#define IPU_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9 0x1E0580B8,0x1FFFFFFF
+
+#define IPU_DC_RL1_CH_9__ADDR                         0x1E0580BC
+#define IPU_DC_RL1_CH_9__EMPTY                        0x1E0580BC,0x00000000
+#define IPU_DC_RL1_CH_9__FULL                         0x1E0580BC,0xffffffff
+#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1 0x1E0580BC,0xFF000000
+#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0 0x1E0580BC,0x0000FF00
+#define IPU_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9  0x1E0580BC,0x0000000F
+
+#define IPU_DC_RL2_CH_9__ADDR                         0x1E0580C0
+#define IPU_DC_RL2_CH_9__EMPTY                        0x1E0580C0,0x00000000
+#define IPU_DC_RL2_CH_9__FULL                         0x1E0580C0,0xffffffff
+#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1 0x1E0580C0,0xFF000000
+#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0 0x1E0580C0,0x0000FF00
+#define IPU_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9  0x1E0580C0,0x0000000F
+
+#define IPU_DC_RL3_CH_9__ADDR                         0x1E0580C4
+#define IPU_DC_RL3_CH_9__EMPTY                        0x1E0580C4,0x00000000
+#define IPU_DC_RL3_CH_9__FULL                         0x1E0580C4,0xffffffff
+#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1 0x1E0580C4,0xFF000000
+#define IPU_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0 0x1E0580C4,0x0000FF00
+#define IPU_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9  0x1E0580C4,0x0000000F
+
+#define IPU_DC_RL4_CH_9__ADDR                         0x1E0580C8
+#define IPU_DC_RL4_CH_9__EMPTY                        0x1E0580C8,0x00000000
+#define IPU_DC_RL4_CH_9__FULL                         0x1E0580C8,0xffffffff
+#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1 0x1E0580C8,0xFF000000
+#define IPU_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0 0x1E0580C8,0x0000FF00
+
+#define IPU_DC_RL5_CH_9__ADDR                         0x1E0580CC
+#define IPU_DC_RL5_CH_9__EMPTY                        0x1E0580CC,0x00000000
+#define IPU_DC_RL5_CH_9__FULL                         0x1E0580CC,0xffffffff
+#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1 0x1E0580CC,0xFF000000
+#define IPU_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0 0x1E0580CC,0x0000FF00
+
+#define IPU_DC_RL6_CH_9__ADDR                         0x1E0580D0
+#define IPU_DC_RL6_CH_9__EMPTY                        0x1E0580D0,0x00000000
+#define IPU_DC_RL6_CH_9__FULL                         0x1E0580D0,0xffffffff
+#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1 0x1E0580D0,0xFF000000
+#define IPU_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0 0x1E0580D0,0x0000FF00
+
+#define IPU_DC_GEN__ADDR           0x1E0580D4
+#define IPU_DC_GEN__EMPTY          0x1E0580D4,0x00000000
+#define IPU_DC_GEN__FULL           0x1E0580D4,0xffffffff
+#define IPU_DC_GEN__DC_BK_EN       0x1E0580D4,0x01000000
+#define IPU_DC_GEN__DC_BKDIV       0x1E0580D4,0x00FF0000
+#define IPU_DC_GEN__DC_CH5_TYPE            0x1E0580D4,0x00000100
+#define IPU_DC_GEN__SYNC_PRIORITY_1 0x1E0580D4,0x00000080
+#define IPU_DC_GEN__SYNC_PRIORITY_5 0x1E0580D4,0x00000040
+#define IPU_DC_GEN__MASK4CHAN_5            0x1E0580D4,0x00000020
+#define IPU_DC_GEN__MASK_EN        0x1E0580D4,0x00000010
+#define IPU_DC_GEN__SYNC_1_6       0x1E0580D4,0x00000006
+
+#define IPU_DC_DISP_CONF1_0__ADDR               0x1E0580D8
+#define IPU_DC_DISP_CONF1_0__EMPTY              0x1E0580D8,0x00000000
+#define IPU_DC_DISP_CONF1_0__FULL               0x1E0580D8,0xffffffff
+#define IPU_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1E0580D8,0x00000080
+#define IPU_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0  0x1E0580D8,0x00000040
+#define IPU_DC_DISP_CONF1_0__ADDR_BE_L_INC_0    0x1E0580D8,0x00000030
+#define IPU_DC_DISP_CONF1_0__ADDR_INCREMENT_0   0x1E0580D8,0x0000000C
+#define IPU_DC_DISP_CONF1_0__DISP_TYP_0                 0x1E0580D8,0x00000003
+
+#define IPU_DC_DISP_CONF1_1__ADDR               0x1E0580DC
+#define IPU_DC_DISP_CONF1_1__EMPTY              0x1E0580DC,0x00000000
+#define IPU_DC_DISP_CONF1_1__FULL               0x1E0580DC,0xffffffff
+#define IPU_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1E0580DC,0x00000080
+#define IPU_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1  0x1E0580DC,0x00000040
+#define IPU_DC_DISP_CONF1_1__ADDR_BE_L_INC_1    0x1E0580DC,0x00000030
+#define IPU_DC_DISP_CONF1_1__ADDR_INCREMENT_1   0x1E0580DC,0x0000000C
+#define IPU_DC_DISP_CONF1_1__DISP_TYP_1                 0x1E0580DC,0x00000003
+
+#define IPU_DC_DISP_CONF1_2__ADDR               0x1E0580E0
+#define IPU_DC_DISP_CONF1_2__EMPTY              0x1E0580E0,0x00000000
+#define IPU_DC_DISP_CONF1_2__FULL               0x1E0580E0,0xffffffff
+#define IPU_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1E0580E0,0x00000080
+#define IPU_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2  0x1E0580E0,0x00000040
+#define IPU_DC_DISP_CONF1_2__ADDR_BE_L_INC_2    0x1E0580E0,0x00000030
+#define IPU_DC_DISP_CONF1_2__ADDR_INCREMENT_2   0x1E0580E0,0x0000000C
+#define IPU_DC_DISP_CONF1_2__DISP_TYP_2                 0x1E0580E0,0x00000003
+
+#define IPU_DC_DISP_CONF1_3__ADDR               0x1E0580E4
+#define IPU_DC_DISP_CONF1_3__EMPTY              0x1E0580E4,0x00000000
+#define IPU_DC_DISP_CONF1_3__FULL               0x1E0580E4,0xffffffff
+#define IPU_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1E0580E4,0x00000080
+#define IPU_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3  0x1E0580E4,0x00000040
+#define IPU_DC_DISP_CONF1_3__ADDR_BE_L_INC_3    0x1E0580E4,0x00000030
+#define IPU_DC_DISP_CONF1_3__ADDR_INCREMENT_3   0x1E0580E4,0x0000000C
+#define IPU_DC_DISP_CONF1_3__DISP_TYP_3                 0x1E0580E4,0x00000003
+
+#define IPU_DC_DISP_CONF2_0__ADDR  0x1E0580E8
+#define IPU_DC_DISP_CONF2_0__EMPTY 0x1E0580E8,0x00000000
+#define IPU_DC_DISP_CONF2_0__FULL  0x1E0580E8,0xffffffff
+#define IPU_DC_DISP_CONF2_0__SL_0  0x1E0580E8,0x1FFFFFFF
+
+#define IPU_DC_DISP_CONF2_1__ADDR  0x1E0580EC
+#define IPU_DC_DISP_CONF2_1__EMPTY 0x1E0580EC,0x00000000
+#define IPU_DC_DISP_CONF2_1__FULL  0x1E0580EC,0xffffffff
+#define IPU_DC_DISP_CONF2_1__SL_1  0x1E0580EC,0x1FFFFFFF
+
+#define IPU_DC_DISP_CONF2_2__ADDR  0x1E0580F0
+#define IPU_DC_DISP_CONF2_2__EMPTY 0x1E0580F0,0x00000000
+#define IPU_DC_DISP_CONF2_2__FULL  0x1E0580F0,0xffffffff
+#define IPU_DC_DISP_CONF2_2__SL_2  0x1E0580F0,0x1FFFFFFF
+
+#define IPU_DC_DISP_CONF2_3__ADDR  0x1E0580F4
+#define IPU_DC_DISP_CONF2_3__EMPTY 0x1E0580F4,0x00000000
+#define IPU_DC_DISP_CONF2_3__FULL  0x1E0580F4,0xffffffff
+#define IPU_DC_DISP_CONF2_3__SL_3  0x1E0580F4,0x1FFFFFFF
+
+#define IPU_DC_DI0_CONF_1__ADDR                       0x1E0580F8
+#define IPU_DC_DI0_CONF_1__EMPTY              0x1E0580F8,0x00000000
+#define IPU_DC_DI0_CONF_1__FULL                       0x1E0580F8,0xffffffff
+#define IPU_DC_DI0_CONF_1__DI_READ_DATA_MASK_0 0x1E0580F8,0xFFFFFFFF
+
+#define IPU_DC_DI0_CONF_2__ADDR                            0x1E0580FC
+#define IPU_DC_DI0_CONF_2__EMPTY                   0x1E0580FC,0x00000000
+#define IPU_DC_DI0_CONF_2__FULL                            0x1E0580FC,0xffffffff
+#define IPU_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0 0x1E0580FC,0xFFFFFFFF
+
+#define IPU_DC_DI1_CONF_1__ADDR                       0x1E058100
+#define IPU_DC_DI1_CONF_1__EMPTY              0x1E058100,0x00000000
+#define IPU_DC_DI1_CONF_1__FULL                       0x1E058100,0xffffffff
+#define IPU_DC_DI1_CONF_1__DI_READ_DATA_MASK_1 0x1E058100,0xFFFFFFFF
+
+#define IPU_DC_DI1_CONF_2__ADDR                            0x1E058104
+#define IPU_DC_DI1_CONF_2__EMPTY                   0x1E058104,0x00000000
+#define IPU_DC_DI1_CONF_2__FULL                            0x1E058104,0xffffffff
+#define IPU_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1 0x1E058104,0xFFFFFFFF
+
+#define IPU_DC_MAP_CONF_0__ADDR                        0x1E058108
+#define IPU_DC_MAP_CONF_0__EMPTY               0x1E058108,0x00000000
+#define IPU_DC_MAP_CONF_0__FULL                        0x1E058108,0xffffffff
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1 0x1E058108,0x7C000000
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1 0x1E058108,0x03E00000
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1 0x1E058108,0x001F0000
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0 0x1E058108,0x00007C00
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0 0x1E058108,0x000003E0
+#define IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0 0x1E058108,0x0000001F
+
+#define IPU_DC_MAP_CONF_1__ADDR                        0x1E05810C
+#define IPU_DC_MAP_CONF_1__EMPTY               0x1E05810C,0x00000000
+#define IPU_DC_MAP_CONF_1__FULL                        0x1E05810C,0xffffffff
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3 0x1E05810C,0x7C000000
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3 0x1E05810C,0x03E00000
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3 0x1E05810C,0x001F0000
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2 0x1E05810C,0x00007C00
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2 0x1E05810C,0x000003E0
+#define IPU_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2 0x1E05810C,0x0000001F
+
+#define IPU_DC_MAP_CONF_2__ADDR                        0x1E058110
+#define IPU_DC_MAP_CONF_2__EMPTY               0x1E058110,0x00000000
+#define IPU_DC_MAP_CONF_2__FULL                        0x1E058110,0xffffffff
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5 0x1E058110,0x7C000000
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5 0x1E058110,0x03E00000
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5 0x1E058110,0x001F0000
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4 0x1E058110,0x00007C00
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4 0x1E058110,0x000003E0
+#define IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4 0x1E058110,0x0000001F
+
+#define IPU_DC_MAP_CONF_3__ADDR                        0x1E058114
+#define IPU_DC_MAP_CONF_3__EMPTY               0x1E058114,0x00000000
+#define IPU_DC_MAP_CONF_3__FULL                        0x1E058114,0xffffffff
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7 0x1E058114,0x7C000000
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7 0x1E058114,0x03E00000
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7 0x1E058114,0x001F0000
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6 0x1E058114,0x00007C00
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6 0x1E058114,0x000003E0
+#define IPU_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6 0x1E058114,0x0000001F
+
+#define IPU_DC_MAP_CONF_4__ADDR                        0x1E058118
+#define IPU_DC_MAP_CONF_4__EMPTY               0x1E058118,0x00000000
+#define IPU_DC_MAP_CONF_4__FULL                        0x1E058118,0xffffffff
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9 0x1E058118,0x7C000000
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9 0x1E058118,0x03E00000
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9 0x1E058118,0x001F0000
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8 0x1E058118,0x00007C00
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8 0x1E058118,0x000003E0
+#define IPU_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8 0x1E058118,0x0000001F
+
+#define IPU_DC_MAP_CONF_5__ADDR                         0x1E05811C
+#define IPU_DC_MAP_CONF_5__EMPTY                0x1E05811C,0x00000000
+#define IPU_DC_MAP_CONF_5__FULL                         0x1E05811C,0xffffffff
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11 0x1E05811C,0x7C000000
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11 0x1E05811C,0x03E00000
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11 0x1E05811C,0x001F0000
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10 0x1E05811C,0x00007C00
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10 0x1E05811C,0x000003E0
+#define IPU_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10 0x1E05811C,0x0000001F
+
+#define IPU_DC_MAP_CONF_6__ADDR                         0x1E058120
+#define IPU_DC_MAP_CONF_6__EMPTY                0x1E058120,0x00000000
+#define IPU_DC_MAP_CONF_6__FULL                         0x1E058120,0xffffffff
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13 0x1E058120,0x7C000000
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13 0x1E058120,0x03E00000
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13 0x1E058120,0x001F0000
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12 0x1E058120,0x00007C00
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12 0x1E058120,0x000003E0
+#define IPU_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12 0x1E058120,0x0000001F
+
+#define IPU_DC_MAP_CONF_7__ADDR                         0x1E058124
+#define IPU_DC_MAP_CONF_7__EMPTY                0x1E058124,0x00000000
+#define IPU_DC_MAP_CONF_7__FULL                         0x1E058124,0xffffffff
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15 0x1E058124,0x7C000000
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15 0x1E058124,0x03E00000
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15 0x1E058124,0x001F0000
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14 0x1E058124,0x00007C00
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14 0x1E058124,0x000003E0
+#define IPU_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14 0x1E058124,0x0000001F
+
+#define IPU_DC_MAP_CONF_8__ADDR                         0x1E058128
+#define IPU_DC_MAP_CONF_8__EMPTY                0x1E058128,0x00000000
+#define IPU_DC_MAP_CONF_8__FULL                         0x1E058128,0xffffffff
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17 0x1E058128,0x7C000000
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17 0x1E058128,0x03E00000
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17 0x1E058128,0x001F0000
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16 0x1E058128,0x00007C00
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16 0x1E058128,0x000003E0
+#define IPU_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16 0x1E058128,0x0000001F
+
+#define IPU_DC_MAP_CONF_9__ADDR                         0x1E05812C
+#define IPU_DC_MAP_CONF_9__EMPTY                0x1E05812C,0x00000000
+#define IPU_DC_MAP_CONF_9__FULL                         0x1E05812C,0xffffffff
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19 0x1E05812C,0x7C000000
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19 0x1E05812C,0x03E00000
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19 0x1E05812C,0x001F0000
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18 0x1E05812C,0x00007C00
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18 0x1E05812C,0x000003E0
+#define IPU_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18 0x1E05812C,0x0000001F
+
+#define IPU_DC_MAP_CONF_10__ADDR                 0x1E058130
+#define IPU_DC_MAP_CONF_10__EMPTY                0x1E058130,0x00000000
+#define IPU_DC_MAP_CONF_10__FULL                 0x1E058130,0xffffffff
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21 0x1E058130,0x7C000000
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21 0x1E058130,0x03E00000
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21 0x1E058130,0x001F0000
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20 0x1E058130,0x00007C00
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20 0x1E058130,0x000003E0
+#define IPU_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20 0x1E058130,0x0000001F
+
+#define IPU_DC_MAP_CONF_11__ADDR                 0x1E058134
+#define IPU_DC_MAP_CONF_11__EMPTY                0x1E058134,0x00000000
+#define IPU_DC_MAP_CONF_11__FULL                 0x1E058134,0xffffffff
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23 0x1E058134,0x7C000000
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23 0x1E058134,0x03E00000
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23 0x1E058134,0x001F0000
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22 0x1E058134,0x00007C00
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22 0x1E058134,0x000003E0
+#define IPU_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22 0x1E058134,0x0000001F
+
+#define IPU_DC_MAP_CONF_12__ADDR                 0x1E058138
+#define IPU_DC_MAP_CONF_12__EMPTY                0x1E058138,0x00000000
+#define IPU_DC_MAP_CONF_12__FULL                 0x1E058138,0xffffffff
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25 0x1E058138,0x7C000000
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25 0x1E058138,0x03E00000
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25 0x1E058138,0x001F0000
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24 0x1E058138,0x00007C00
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24 0x1E058138,0x000003E0
+#define IPU_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24 0x1E058138,0x0000001F
+
+#define IPU_DC_MAP_CONF_13__ADDR                 0x1E05813C
+#define IPU_DC_MAP_CONF_13__EMPTY                0x1E05813C,0x00000000
+#define IPU_DC_MAP_CONF_13__FULL                 0x1E05813C,0xffffffff
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27 0x1E05813C,0x7C000000
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27 0x1E05813C,0x03E00000
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27 0x1E05813C,0x001F0000
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26 0x1E05813C,0x00007C00
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26 0x1E05813C,0x000003E0
+#define IPU_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26 0x1E05813C,0x0000001F
+
+#define IPU_DC_MAP_CONF_14__ADDR                 0x1E058140
+#define IPU_DC_MAP_CONF_14__EMPTY                0x1E058140,0x00000000
+#define IPU_DC_MAP_CONF_14__FULL                 0x1E058140,0xffffffff
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29 0x1E058140,0x7C000000
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29 0x1E058140,0x03E00000
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29 0x1E058140,0x001F0000
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28 0x1E058140,0x00007C00
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28 0x1E058140,0x000003E0
+#define IPU_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28 0x1E058140,0x0000001F
+
+#define IPU_DC_MAP_CONF_15__ADDR       0x1E058144
+#define IPU_DC_MAP_CONF_15__EMPTY      0x1E058144,0x00000000
+#define IPU_DC_MAP_CONF_15__FULL       0x1E058144,0xffffffff
+#define IPU_DC_MAP_CONF_15__MD_OFFSET_1 0x1E058144,0x1F000000
+#define IPU_DC_MAP_CONF_15__MD_MASK_1  0x1E058144,0x00FF0000
+#define IPU_DC_MAP_CONF_15__MD_OFFSET_0 0x1E058144,0x00001F00
+#define IPU_DC_MAP_CONF_15__MD_MASK_0  0x1E058144,0x000000FF
+
+#define IPU_DC_MAP_CONF_16__ADDR       0x1E058148
+#define IPU_DC_MAP_CONF_16__EMPTY      0x1E058148,0x00000000
+#define IPU_DC_MAP_CONF_16__FULL       0x1E058148,0xffffffff
+#define IPU_DC_MAP_CONF_16__MD_OFFSET_3 0x1E058148,0x1F000000
+#define IPU_DC_MAP_CONF_16__MD_MASK_3  0x1E058148,0x00FF0000
+#define IPU_DC_MAP_CONF_16__MD_OFFSET_2 0x1E058148,0x00001F00
+#define IPU_DC_MAP_CONF_16__MD_MASK_2  0x1E058148,0x000000FF
+
+#define IPU_DC_MAP_CONF_17__ADDR       0x1E05814C
+#define IPU_DC_MAP_CONF_17__EMPTY      0x1E05814C,0x00000000
+#define IPU_DC_MAP_CONF_17__FULL       0x1E05814C,0xffffffff
+#define IPU_DC_MAP_CONF_17__MD_OFFSET_5 0x1E05814C,0x1F000000
+#define IPU_DC_MAP_CONF_17__MD_MASK_5  0x1E05814C,0x00FF0000
+#define IPU_DC_MAP_CONF_17__MD_OFFSET_4 0x1E05814C,0x00001F00
+#define IPU_DC_MAP_CONF_17__MD_MASK_4  0x1E05814C,0x000000FF
+
+#define IPU_DC_MAP_CONF_18__ADDR       0x1E058150
+#define IPU_DC_MAP_CONF_18__EMPTY      0x1E058150,0x00000000
+#define IPU_DC_MAP_CONF_18__FULL       0x1E058150,0xffffffff
+#define IPU_DC_MAP_CONF_18__MD_OFFSET_7 0x1E058150,0x1F000000
+#define IPU_DC_MAP_CONF_18__MD_MASK_7  0x1E058150,0x00FF0000
+#define IPU_DC_MAP_CONF_18__MD_OFFSET_6 0x1E058150,0x00001F00
+#define IPU_DC_MAP_CONF_18__MD_MASK_6  0x1E058150,0x000000FF
+
+#define IPU_DC_MAP_CONF_19__ADDR       0x1E058154
+#define IPU_DC_MAP_CONF_19__EMPTY      0x1E058154,0x00000000
+#define IPU_DC_MAP_CONF_19__FULL       0x1E058154,0xffffffff
+#define IPU_DC_MAP_CONF_19__MD_OFFSET_9 0x1E058154,0x1F000000
+#define IPU_DC_MAP_CONF_19__MD_MASK_9  0x1E058154,0x00FF0000
+#define IPU_DC_MAP_CONF_19__MD_OFFSET_8 0x1E058154,0x00001F00
+#define IPU_DC_MAP_CONF_19__MD_MASK_8  0x1E058154,0x000000FF
+
+#define IPU_DC_MAP_CONF_20__ADDR        0x1E058158
+#define IPU_DC_MAP_CONF_20__EMPTY       0x1E058158,0x00000000
+#define IPU_DC_MAP_CONF_20__FULL        0x1E058158,0xffffffff
+#define IPU_DC_MAP_CONF_20__MD_OFFSET_11 0x1E058158,0x1F000000
+#define IPU_DC_MAP_CONF_20__MD_MASK_11  0x1E058158,0x00FF0000
+#define IPU_DC_MAP_CONF_20__MD_OFFSET_10 0x1E058158,0x00001F00
+#define IPU_DC_MAP_CONF_20__MD_MASK_10  0x1E058158,0x000000FF
+
+#define IPU_DC_MAP_CONF_21__ADDR        0x1E05815C
+#define IPU_DC_MAP_CONF_21__EMPTY       0x1E05815C,0x00000000
+#define IPU_DC_MAP_CONF_21__FULL        0x1E05815C,0xffffffff
+#define IPU_DC_MAP_CONF_21__MD_OFFSET_13 0x1E05815C,0x1F000000
+#define IPU_DC_MAP_CONF_21__MD_MASK_13  0x1E05815C,0x00FF0000
+#define IPU_DC_MAP_CONF_21__MD_OFFSET_12 0x1E05815C,0x00001F00
+#define IPU_DC_MAP_CONF_21__MD_MASK_12  0x1E05815C,0x000000FF
+
+#define IPU_DC_MAP_CONF_22__ADDR        0x1E058160
+#define IPU_DC_MAP_CONF_22__EMPTY       0x1E058160,0x00000000
+#define IPU_DC_MAP_CONF_22__FULL        0x1E058160,0xffffffff
+#define IPU_DC_MAP_CONF_22__MD_OFFSET_15 0x1E058160,0x1F000000
+#define IPU_DC_MAP_CONF_22__MD_MASK_15  0x1E058160,0x00FF0000
+#define IPU_DC_MAP_CONF_22__MD_OFFSET_14 0x1E058160,0x00001F00
+#define IPU_DC_MAP_CONF_22__MD_MASK_14  0x1E058160,0x000000FF
+
+#define IPU_DC_MAP_CONF_23__ADDR        0x1E058164
+#define IPU_DC_MAP_CONF_23__EMPTY       0x1E058164,0x00000000
+#define IPU_DC_MAP_CONF_23__FULL        0x1E058164,0xffffffff
+#define IPU_DC_MAP_CONF_23__MD_OFFSET_17 0x1E058164,0x1F000000
+#define IPU_DC_MAP_CONF_23__MD_MASK_17  0x1E058164,0x00FF0000
+#define IPU_DC_MAP_CONF_23__MD_OFFSET_16 0x1E058164,0x00001F00
+#define IPU_DC_MAP_CONF_23__MD_MASK_16  0x1E058164,0x000000FF
+
+#define IPU_DC_MAP_CONF_24__ADDR        0x1E058168
+#define IPU_DC_MAP_CONF_24__EMPTY       0x1E058168,0x00000000
+#define IPU_DC_MAP_CONF_24__FULL        0x1E058168,0xffffffff
+#define IPU_DC_MAP_CONF_24__MD_OFFSET_19 0x1E058168,0x1F000000
+#define IPU_DC_MAP_CONF_24__MD_MASK_19  0x1E058168,0x00FF0000
+#define IPU_DC_MAP_CONF_24__MD_OFFSET_18 0x1E058168,0x00001F00
+#define IPU_DC_MAP_CONF_24__MD_MASK_18  0x1E058168,0x000000FF
+
+#define IPU_DC_MAP_CONF_25__ADDR        0x1E05816C
+#define IPU_DC_MAP_CONF_25__EMPTY       0x1E05816C,0x00000000
+#define IPU_DC_MAP_CONF_25__FULL        0x1E05816C,0xffffffff
+#define IPU_DC_MAP_CONF_25__MD_OFFSET_21 0x1E05816C,0x1F000000
+#define IPU_DC_MAP_CONF_25__MD_MASK_21  0x1E05816C,0x00FF0000
+#define IPU_DC_MAP_CONF_25__MD_OFFSET_20 0x1E05816C,0x00001F00
+#define IPU_DC_MAP_CONF_25__MD_MASK_20  0x1E05816C,0x000000FF
+
+#define IPU_DC_MAP_CONF_26__ADDR        0x1E058170
+#define IPU_DC_MAP_CONF_26__EMPTY       0x1E058170,0x00000000
+#define IPU_DC_MAP_CONF_26__FULL        0x1E058170,0xffffffff
+#define IPU_DC_MAP_CONF_26__MD_OFFSET_23 0x1E058170,0x1F000000
+#define IPU_DC_MAP_CONF_26__MD_MASK_23  0x1E058170,0x00FF0000
+#define IPU_DC_MAP_CONF_26__MD_OFFSET_22 0x1E058170,0x00001F00
+#define IPU_DC_MAP_CONF_26__MD_MASK_22  0x1E058170,0x000000FF
+
+#define IPU_DC_UGDE0_0__ADDR             0x1E058174
+#define IPU_DC_UGDE0_0__EMPTY            0x1E058174,0x00000000
+#define IPU_DC_UGDE0_0__FULL             0x1E058174,0xffffffff
+#define IPU_DC_UGDE0_0__NF_NL_0                  0x1E058174,0x18000000
+#define IPU_DC_UGDE0_0__AUTORESTART_0    0x1E058174,0x04000000
+#define IPU_DC_UGDE0_0__ODD_EN_0         0x1E058174,0x02000000
+#define IPU_DC_UGDE0_0__COD_ODD_START_0          0x1E058174,0x00FF0000
+#define IPU_DC_UGDE0_0__COD_EV_START_0   0x1E058174,0x0000FF00
+#define IPU_DC_UGDE0_0__COD_EV_PRIORITY_0 0x1E058174,0x00000078
+#define IPU_DC_UGDE0_0__ID_CODED_0       0x1E058174,0x00000007
+
+#define IPU_DC_UGDE0_1__ADDR   0x1E058178
+#define IPU_DC_UGDE0_1__EMPTY  0x1E058178,0x00000000
+#define IPU_DC_UGDE0_1__FULL   0x1E058178,0xffffffff
+#define IPU_DC_UGDE0_1__STEP_0 0x1E058178,0x1FFFFFFF
+
+#define IPU_DC_UGDE0_2__ADDR       0x1E05817C
+#define IPU_DC_UGDE0_2__EMPTY      0x1E05817C,0x00000000
+#define IPU_DC_UGDE0_2__FULL       0x1E05817C,0xffffffff
+#define IPU_DC_UGDE0_2__OFFSET_DT_0 0x1E05817C,0x1FFFFFFF
+
+#define IPU_DC_UGDE0_3__ADDR         0x1E058180
+#define IPU_DC_UGDE0_3__EMPTY        0x1E058180,0x00000000
+#define IPU_DC_UGDE0_3__FULL         0x1E058180,0xffffffff
+#define IPU_DC_UGDE0_3__STEP_REPEAT_0 0x1E058180,0x1FFFFFFF
+
+#define IPU_DC_UGDE1_0__ADDR             0x1E058184
+#define IPU_DC_UGDE1_0__EMPTY            0x1E058184,0x00000000
+#define IPU_DC_UGDE1_0__FULL             0x1E058184,0xffffffff
+#define IPU_DC_UGDE1_0__NF_NL_1                  0x1E058184,0x18000000
+#define IPU_DC_UGDE1_0__AUTORESTART_1    0x1E058184,0x04000000
+#define IPU_DC_UGDE1_0__ODD_EN_1         0x1E058184,0x02000000
+#define IPU_DC_UGDE1_0__COD_ODD_START_1          0x1E058184,0x00FF0000
+#define IPU_DC_UGDE1_0__COD_EV_START_1   0x1E058184,0x00007F80
+#define IPU_DC_UGDE1_0__COD_EV_PRIORITY_1 0x1E058184,0x00000078
+#define IPU_DC_UGDE1_0__ID_CODED_1       0x1E058184,0x00000007
+
+#define IPU_DC_UGDE1_1__ADDR   0x1E058188
+#define IPU_DC_UGDE1_1__EMPTY  0x1E058188,0x00000000
+#define IPU_DC_UGDE1_1__FULL   0x1E058188,0xffffffff
+#define IPU_DC_UGDE1_1__STEP_1 0x1E058188,0x1FFFFFFF
+
+#define IPU_DC_UGDE1_2__ADDR       0x1E05818C
+#define IPU_DC_UGDE1_2__EMPTY      0x1E05818C,0x00000000
+#define IPU_DC_UGDE1_2__FULL       0x1E05818C,0xffffffff
+#define IPU_DC_UGDE1_2__OFFSET_DT_1 0x1E05818C,0x1FFFFFFF
+
+#define IPU_DC_UGDE1_3__ADDR         0x1E058190
+#define IPU_DC_UGDE1_3__EMPTY        0x1E058190,0x00000000
+#define IPU_DC_UGDE1_3__FULL         0x1E058190,0xffffffff
+#define IPU_DC_UGDE1_3__STEP_REPEAT_1 0x1E058190,0x1FFFFFFF
+
+#define IPU_DC_UGDE2_0__ADDR             0x1E058194
+#define IPU_DC_UGDE2_0__EMPTY            0x1E058194,0x00000000
+#define IPU_DC_UGDE2_0__FULL             0x1E058194,0xffffffff
+#define IPU_DC_UGDE2_0__NF_NL_2                  0x1E058194,0x18000000
+#define IPU_DC_UGDE2_0__AUTORESTART_2    0x1E058194,0x04000000
+#define IPU_DC_UGDE2_0__ODD_EN_2         0x1E058194,0x02000000
+#define IPU_DC_UGDE2_0__COD_ODD_START_2          0x1E058194,0x00FF0000
+#define IPU_DC_UGDE2_0__COD_EV_START_2   0x1E058194,0x00007F80
+#define IPU_DC_UGDE2_0__COD_EV_PRIORITY_2 0x1E058194,0x00000078
+#define IPU_DC_UGDE2_0__ID_CODED_2       0x1E058194,0x00000007
+
+#define IPU_DC_UGDE2_1__ADDR   0x1E058198
+#define IPU_DC_UGDE2_1__EMPTY  0x1E058198,0x00000000
+#define IPU_DC_UGDE2_1__FULL   0x1E058198,0xffffffff
+#define IPU_DC_UGDE2_1__STEP_2 0x1E058198,0x1FFFFFFF
+
+#define IPU_DC_UGDE2_2__ADDR       0x1E05819C
+#define IPU_DC_UGDE2_2__EMPTY      0x1E05819C,0x00000000
+#define IPU_DC_UGDE2_2__FULL       0x1E05819C,0xffffffff
+#define IPU_DC_UGDE2_2__OFFSET_DT_2 0x1E05819C,0x1FFFFFFF
+
+#define IPU_DC_UGDE2_3__ADDR         0x1E0581A0
+#define IPU_DC_UGDE2_3__EMPTY        0x1E0581A0,0x00000000
+#define IPU_DC_UGDE2_3__FULL         0x1E0581A0,0xffffffff
+#define IPU_DC_UGDE2_3__STEP_REPEAT_2 0x1E0581A0,0x1FFFFFFF
+
+#define IPU_DC_UGDE3_0__ADDR             0x1E0581A4
+#define IPU_DC_UGDE3_0__EMPTY            0x1E0581A4,0x00000000
+#define IPU_DC_UGDE3_0__FULL             0x1E0581A4,0xffffffff
+#define IPU_DC_UGDE3_0__NF_NL_3                  0x1E0581A4,0x18000000
+#define IPU_DC_UGDE3_0__AUTORESTART_3    0x1E0581A4,0x04000000
+#define IPU_DC_UGDE3_0__ODD_EN_3         0x1E0581A4,0x02000000
+#define IPU_DC_UGDE3_0__COD_ODD_START_3          0x1E0581A4,0x00FF0000
+#define IPU_DC_UGDE3_0__COD_EV_START_3   0x1E0581A4,0x00007F80
+#define IPU_DC_UGDE3_0__COD_EV_PRIORITY_3 0x1E0581A4,0x00000078
+#define IPU_DC_UGDE3_0__ID_CODED_3       0x1E0581A4,0x00000007
+
+#define IPU_DC_UGDE3_1__ADDR   0x1E0581A8
+#define IPU_DC_UGDE3_1__EMPTY  0x1E0581A8,0x00000000
+#define IPU_DC_UGDE3_1__FULL   0x1E0581A8,0xffffffff
+#define IPU_DC_UGDE3_1__STEP_3 0x1E0581A8,0x1FFFFFFF
+
+#define IPU_DC_UGDE3_2__ADDR       0x1E0581AC
+#define IPU_DC_UGDE3_2__EMPTY      0x1E0581AC,0x00000000
+#define IPU_DC_UGDE3_2__FULL       0x1E0581AC,0xffffffff
+#define IPU_DC_UGDE3_2__OFFSET_DT_3 0x1E0581AC,0x1FFFFFFF
+
+#define IPU_DC_UGDE3_3__ADDR         0x1E0581B0
+#define IPU_DC_UGDE3_3__EMPTY        0x1E0581B0,0x00000000
+#define IPU_DC_UGDE3_3__FULL         0x1E0581B0,0xffffffff
+#define IPU_DC_UGDE3_3__STEP_REPEAT_3 0x1E0581B0,0x1FFFFFFF
+
+#define IPU_DC_LLA0__ADDR      0x1E0581B4
+#define IPU_DC_LLA0__EMPTY     0x1E0581B4,0x00000000
+#define IPU_DC_LLA0__FULL      0x1E0581B4,0xffffffff
+#define IPU_DC_LLA0__MCU_RS_3_0 0x1E0581B4,0xFF000000
+#define IPU_DC_LLA0__MCU_RS_2_0 0x1E0581B4,0x00FF0000
+#define IPU_DC_LLA0__MCU_RS_1_0 0x1E0581B4,0x0000FF00
+#define IPU_DC_LLA0__MCU_RS_0_0 0x1E0581B4,0x000000FF
+
+#define IPU_DC_LLA1__ADDR      0x1E0581B8
+#define IPU_DC_LLA1__EMPTY     0x1E0581B8,0x00000000
+#define IPU_DC_LLA1__FULL      0x1E0581B8,0xffffffff
+#define IPU_DC_LLA1__MCU_RS_3_1 0x1E0581B8,0xFF000000
+#define IPU_DC_LLA1__MCU_RS_2_1 0x1E0581B8,0x00FF0000
+#define IPU_DC_LLA1__MCU_RS_1_1 0x1E0581B8,0x0000FF00
+#define IPU_DC_LLA1__MCU_RS_0_1 0x1E0581B8,0x000000FF
+
+#define IPU_DC_R_LLA0__ADDR        0x1E0581BC
+#define IPU_DC_R_LLA0__EMPTY       0x1E0581BC,0x00000000
+#define IPU_DC_R_LLA0__FULL        0x1E0581BC,0xffffffff
+#define IPU_DC_R_LLA0__MCU_RS_R_3_0 0x1E0581BC,0xFF000000
+#define IPU_DC_R_LLA0__MCU_RS_R_2_0 0x1E0581BC,0x00FF0000
+#define IPU_DC_R_LLA0__MCU_RS_R_1_0 0x1E0581BC,0x0000FF00
+#define IPU_DC_R_LLA0__MCU_RS_R_0_0 0x1E0581BC,0x000000FF
+
+#define IPU_DC_R_LLA1__ADDR        0x1E0581C0
+#define IPU_DC_R_LLA1__EMPTY       0x1E0581C0,0x00000000
+#define IPU_DC_R_LLA1__FULL        0x1E0581C0,0xffffffff
+#define IPU_DC_R_LLA1__MCU_RS_R_3_1 0x1E0581C0,0xFF000000
+#define IPU_DC_R_LLA1__MCU_RS_R_2_1 0x1E0581C0,0x00FF0000
+#define IPU_DC_R_LLA1__MCU_RS_R_1_1 0x1E0581C0,0x0000FF00
+#define IPU_DC_R_LLA1__MCU_RS_R_0_1 0x1E0581C0,0x000000FF
+
+#define IPU_DC_WR_CH_ADDR_5_ALT__ADDR         0x1E0581C4
+#define IPU_DC_WR_CH_ADDR_5_ALT__EMPTY        0x1E0581C4,0x00000000
+#define IPU_DC_WR_CH_ADDR_5_ALT__FULL         0x1E0581C4,0xffffffff
+#define IPU_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT 0x1E0581C4,0x1FFFFFFF
+
+#define IPU_DC_STAT__ADDR                      0x1E0581C8
+#define IPU_DC_STAT__EMPTY                     0x1E0581C8,0x00000000
+#define IPU_DC_STAT__FULL                      0x1E0581C8,0xffffffff
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_1 0x1E0581C8,0x00000080
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_1 0x1E0581C8,0x00000040
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_1 0x1E0581C8,0x00000020
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_1  0x1E0581C8,0x00000010
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_EMPTY_0 0x1E0581C8,0x00000008
+#define IPU_DC_STAT__DC_TRIPLE_BUF_DATA_FULL_0 0x1E0581C8,0x00000004
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_EMPTY_0 0x1E0581C8,0x00000002
+#define IPU_DC_STAT__DC_TRIPLE_BUF_CNT_FULL_0  0x1E0581C8,0x00000001
+// ================= End of IPUV3EX DC Registers =====================
+
+// ================= Start of IPUV3EX DMFC Registers =====================
+#define IPU_DMFC_RD_CHAN__ADDR             0x1E060000
+#define IPU_DMFC_RD_CHAN__EMPTY                    0x1E060000,0x00000000
+#define IPU_DMFC_RD_CHAN__FULL             0x1E060000,0xffffffff
+#define IPU_DMFC_RD_CHAN__DMFC_PPW_C       0x1E060000,0x03000000
+#define IPU_DMFC_RD_CHAN__DMFC_WM_CLR_0            0x1E060000,0x00E00000
+#define IPU_DMFC_RD_CHAN__DMFC_WM_SET_0            0x1E060000,0x001C0000
+#define IPU_DMFC_RD_CHAN__DMFC_WM_EN_0     0x1E060000,0x00020000
+#define IPU_DMFC_RD_CHAN__DMFC_BURST_SIZE_0 0x1E060000,0x000000C0
+
+#define IPU_DMFC_WR_CHAN__ADDR              0x1E060004
+#define IPU_DMFC_WR_CHAN__EMPTY                     0x1E060004,0x00000000
+#define IPU_DMFC_WR_CHAN__FULL              0x1E060004,0xffffffff
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C 0x1E060004,0xC0000000
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C  0x1E060004,0x38000000
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2C    0x1E060004,0x07000000
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C 0x1E060004,0x00C00000
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C  0x1E060004,0x00380000
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1C    0x1E060004,0x00070000
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_2  0x1E060004,0x0000C000
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2   0x1E060004,0x00003800
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_2     0x1E060004,0x00000700
+#define IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1  0x1E060004,0x000000C0
+#define IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1   0x1E060004,0x00000038
+#define IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1     0x1E060004,0x00000007
+
+#define IPU_DMFC_WR_CHAN_DEF__ADDR          0x1E060008
+#define IPU_DMFC_WR_CHAN_DEF__EMPTY         0x1E060008,0x00000000
+#define IPU_DMFC_WR_CHAN_DEF__FULL          0x1E060008,0xffffffff
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C 0x1E060008,0xE0000000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C 0x1E060008,0x1C000000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C  0x1E060008,0x02000000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C 0x1E060008,0x00E00000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C 0x1E060008,0x001C0000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C  0x1E060008,0x00020000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2  0x1E060008,0x0000E000
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2  0x1E060008,0x00001C00
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2   0x1E060008,0x00000200
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1  0x1E060008,0x000000E0
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1  0x1E060008,0x0000001C
+#define IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1   0x1E060008,0x00000002
+
+#define IPU_DMFC_DP_CHAN__ADDR              0x1E06000C
+#define IPU_DMFC_DP_CHAN__EMPTY                     0x1E06000C,0x00000000
+#define IPU_DMFC_DP_CHAN__FULL              0x1E06000C,0xffffffff
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F 0x1E06000C,0xC0000000
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F  0x1E06000C,0x38000000
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6F    0x1E06000C,0x07000000
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B 0x1E06000C,0x00C00000
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B  0x1E06000C,0x00380000
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_6B    0x1E06000C,0x00070000
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F 0x1E06000C,0x0000C000
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F  0x1E06000C,0x00003800
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5F    0x1E06000C,0x00000700
+#define IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B 0x1E06000C,0x000000C0
+#define IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B  0x1E06000C,0x00000038
+#define IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5B    0x1E06000C,0x00000007
+
+#define IPU_DMFC_DP_CHAN_DEF__ADDR          0x1E060010
+#define IPU_DMFC_DP_CHAN_DEF__EMPTY         0x1E060010,0x00000000
+#define IPU_DMFC_DP_CHAN_DEF__FULL          0x1E060010,0xffffffff
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F 0x1E060010,0xE0000000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F 0x1E060010,0x1C000000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F  0x1E060010,0x02000000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B 0x1E060010,0x00E00000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B 0x1E060010,0x001C0000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B  0x1E060010,0x00020000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F 0x1E060010,0x0000E000
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F 0x1E060010,0x00001C00
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F  0x1E060010,0x00000200
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B 0x1E060010,0x000000E0
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B 0x1E060010,0x0000001C
+#define IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B  0x1E060010,0x00000002
+
+#define IPU_DMFC_GENERAL1__ADDR                     0x1E060014
+#define IPU_DMFC_GENERAL1__EMPTY            0x1E060014,0x00000000
+#define IPU_DMFC_GENERAL1__FULL                     0x1E060014,0xffffffff
+#define IPU_DMFC_GENERAL1__WAIT4EOT_9       0x1E060014,0x01000000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_6F      0x1E060014,0x00800000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_6B      0x1E060014,0x00400000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_5F      0x1E060014,0x00200000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_5B      0x1E060014,0x00100000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_4       0x1E060014,0x00080000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_3       0x1E060014,0x00040000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_2       0x1E060014,0x00020000
+#define IPU_DMFC_GENERAL1__WAIT4EOT_1       0x1E060014,0x00010000
+#define IPU_DMFC_GENERAL1__DMFC_WM_CLR_9     0x1E060014,0x0000E000
+#define IPU_DMFC_GENERAL1__DMFC_WM_SET_9     0x1E060014,0x00001C00
+#define IPU_DMFC_GENERAL1__DMFC_WM_EN_9             0x1E060014,0x00000200
+#define IPU_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1E060014,0x00000060
+#define IPU_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1E060014,0x00000003
+
+#define IPU_DMFC_GENERAL2__ADDR                        0x1E060018
+#define IPU_DMFC_GENERAL2__EMPTY               0x1E060018,0x00000000
+#define IPU_DMFC_GENERAL2__FULL                        0x1E060018,0xffffffff
+#define IPU_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD 0x1E060018,0x1FFF0000
+#define IPU_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD 0x1E060018,0x00001FFF
+
+#define IPU_DMFC_IC_CTRL__ADDR                   0x1E06001C
+#define IPU_DMFC_IC_CTRL__EMPTY                          0x1E06001C,0x00000000
+#define IPU_DMFC_IC_CTRL__FULL                   0x1E06001C,0xffffffff
+#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD 0x1E06001C,0xFFF80000
+#define IPU_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD  0x1E06001C,0x0007FFC0
+#define IPU_DMFC_IC_CTRL__DMFC_IC_PPW_C                  0x1E06001C,0x00000030
+#define IPU_DMFC_IC_CTRL__DMFC_IC_IN_PORT        0x1E06001C,0x00000007
+
+#define IPU_DMFC_WR_CHAN_ALT__ADDR                 0x1E060020
+#define IPU_DMFC_WR_CHAN_ALT__EMPTY                0x1E060020,0x00000000
+#define IPU_DMFC_WR_CHAN_ALT__FULL                 0x1E060020,0xffffffff
+#define IPU_DMFC_WR_CHAN_ALT__DMFC_BURST_SIZE_2_ALT 0x1E060020,0x0000C000
+#define IPU_DMFC_WR_CHAN_ALT__DMFC_FIFO_SIZE_2_ALT  0x1E060020,0x00003800
+#define IPU_DMFC_WR_CHAN_ALT__DMFC_ST_ADDR_2_ALT    0x1E060020,0x00000700
+
+#define IPU_DMFC_WR_CHAN_DEF_ALT__ADDR             0x1E060024
+#define IPU_DMFC_WR_CHAN_DEF_ALT__EMPTY                    0x1E060024,0x00000000
+#define IPU_DMFC_WR_CHAN_DEF_ALT__FULL             0x1E060024,0xffffffff
+#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_CLR_2_ALT 0x1E060024,0x0000E000
+#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_SET_2_ALT 0x1E060024,0x00001C00
+#define IPU_DMFC_WR_CHAN_DEF_ALT__DMFC_WM_EN_2_ALT  0x1E060024,0x00000200
+
+#define IPU_DMFC_DP_CHAN_ALT__ADDR                  0x1E060028
+#define IPU_DMFC_DP_CHAN_ALT__EMPTY                 0x1E060028,0x00000000
+#define IPU_DMFC_DP_CHAN_ALT__FULL                  0x1E060028,0xffffffff
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_6F_ALT 0x1E060028,0xC0000000
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_6F_ALT  0x1E060028,0x38000000
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_6F_ALT    0x1E060028,0x07000000
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_6B_ALT 0x1E060028,0x00C00000
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_6B_ALT  0x1E060028,0x00380000
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_6B_ALT    0x1E060028,0x00070000
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_BURST_SIZE_5B_ALT 0x1E060028,0x000000C0
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_FIFO_SIZE_5B_ALT  0x1E060028,0x00000038
+#define IPU_DMFC_DP_CHAN_ALT__DMFC_ST_ADDR_5B_ALT    0x1E060028,0x00000007
+
+#define IPU_DMFC_DP_CHAN_DEF_ALT__ADDR              0x1E06002C
+#define IPU_DMFC_DP_CHAN_DEF_ALT__EMPTY                     0x1E06002C,0x00000000
+#define IPU_DMFC_DP_CHAN_DEF_ALT__FULL              0x1E06002C,0xffffffff
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_6F_ALT 0x1E06002C,0xE0000000
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_6F_ALT 0x1E06002C,0x1C000000
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_6F_ALT  0x1E06002C,0x02000000
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_6B_ALT 0x1E06002C,0x00E00000
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_6B_ALT 0x1E06002C,0x001C0000
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_6B_ALT  0x1E06002C,0x00020000
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_CLR_5B_ALT 0x1E06002C,0x000000E0
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_SET_5B_ALT 0x1E06002C,0x0000001C
+#define IPU_DMFC_DP_CHAN_DEF_ALT__DMFC_WM_EN_5B_ALT  0x1E06002C,0x00000002
+
+#define IPU_DMFC_GENERAL1_ALT__ADDR           0x1E060030
+#define IPU_DMFC_GENERAL1_ALT__EMPTY          0x1E060030,0x00000000
+#define IPU_DMFC_GENERAL1_ALT__FULL           0x1E060030,0xffffffff
+#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_6F_ALT 0x1E060030,0x00800000
+#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_6B_ALT 0x1E060030,0x00400000
+#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_5B_ALT 0x1E060030,0x00100000
+#define IPU_DMFC_GENERAL1_ALT__WAIT4EOT_2_ALT  0x1E060030,0x00020000
+
+#define IPU_DMFC_STAT__ADDR                0x1E060034
+#define IPU_DMFC_STAT__EMPTY               0x1E060034,0x00000000
+#define IPU_DMFC_STAT__FULL                0x1E060034,0xffffffff
+#define IPU_DMFC_STAT__DMFC_IC_BUFFER_EMPTY 0x1E060034,0x02000000
+#define IPU_DMFC_STAT__DMFC_IC_BUFFER_FULL  0x1E060034,0x01000000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_11   0x1E060034,0x00800000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_10   0x1E060034,0x00400000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_9    0x1E060034,0x00200000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_8    0x1E060034,0x00100000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_7    0x1E060034,0x00080000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_6    0x1E060034,0x00040000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_5    0x1E060034,0x00020000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_4    0x1E060034,0x00010000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_3    0x1E060034,0x00008000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_2    0x1E060034,0x00004000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_1    0x1E060034,0x00002000
+#define IPU_DMFC_STAT__DMFC_FIFO_EMPTY_0    0x1E060034,0x00001000
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_11    0x1E060034,0x00000800
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_10    0x1E060034,0x00000400
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_9            0x1E060034,0x00000200
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_8            0x1E060034,0x00000100
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_7            0x1E060034,0x00000080
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_6            0x1E060034,0x00000040
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_5            0x1E060034,0x00000020
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_4            0x1E060034,0x00000010
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_3            0x1E060034,0x00000008
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_2            0x1E060034,0x00000004
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_1            0x1E060034,0x00000002
+#define IPU_DMFC_STAT__DMFC_FIFO_FULL_0            0x1E060034,0x00000001
+// ================= End of IPUV3EX DMFC Registers =====================
+
+// ================= Start of IPUV3EX CPMEM Registers =====================
+#define CPMEM_WORD0_DATA0_INT__ADDR  0x1F000000
+#define CPMEM_WORD0_DATA0_INT__EMPTY 0x1F000000,0x00000000
+#define CPMEM_WORD0_DATA0_INT__FULL  0x1F000000,0xffffffff
+#define CPMEM_WORD0_DATA0_INT__XB    0x1F000000,0xFFF80000
+#define CPMEM_WORD0_DATA0_INT__YV    0x1F000000,0x0007FC00
+#define CPMEM_WORD0_DATA0_INT__XV    0x1F000000,0x000003FF
+
+#define CPMEM_WORD0_DATA1_INT__ADDR   0x1F000004
+#define CPMEM_WORD0_DATA1_INT__EMPTY  0x1F000004,0x00000000
+#define CPMEM_WORD0_DATA1_INT__FULL   0x1F000004,0xffffffff
+#define CPMEM_WORD0_DATA1_INT__SY_LOW 0x1F000004,0xFC000000
+#define CPMEM_WORD0_DATA1_INT__SX     0x1F000004,0x03FFC000
+#define CPMEM_WORD0_DATA1_INT__CF     0x1F000004,0x00002000
+#define CPMEM_WORD0_DATA1_INT__NSB_B  0x1F000004,0x00001000
+#define CPMEM_WORD0_DATA1_INT__YB     0x1F000004,0x00000FFF
+
+#define CPMEM_WORD0_DATA2_INT__ADDR    0x1F000008
+#define CPMEM_WORD0_DATA2_INT__EMPTY   0x1F000008,0x00000000
+#define CPMEM_WORD0_DATA2_INT__FULL    0x1F000008,0xffffffff
+#define CPMEM_WORD0_DATA2_INT__SM      0x1F000008,0xFFC00000
+#define CPMEM_WORD0_DATA2_INT__SDX     0x1F000008,0x003F8000
+#define CPMEM_WORD0_DATA2_INT__NS      0x1F000008,0x00007FE0
+#define CPMEM_WORD0_DATA2_INT__SY_HIGH 0x1F000008,0x0000001F
+
+#define CPMEM_WORD0_DATA3_INT__ADDR    0x1F00000C
+#define CPMEM_WORD0_DATA3_INT__EMPTY   0x1F00000C,0x00000000
+#define CPMEM_WORD0_DATA3_INT__FULL    0x1F00000C,0xffffffff
+#define CPMEM_WORD0_DATA3_INT__FW_LOW  0x1F00000C,0xE0000000
+#define CPMEM_WORD0_DATA3_INT__CAE     0x1F00000C,0x10000000
+#define CPMEM_WORD0_DATA3_INT__CAP     0x1F00000C,0x08000000
+#define CPMEM_WORD0_DATA3_INT__THE     0x1F00000C,0x04000000
+#define CPMEM_WORD0_DATA3_INT__VF      0x1F00000C,0x02000000
+#define CPMEM_WORD0_DATA3_INT__HF      0x1F00000C,0x01000000
+#define CPMEM_WORD0_DATA3_INT__ROT     0x1F00000C,0x00800000
+#define CPMEM_WORD0_DATA3_INT__BM      0x1F00000C,0x00600000
+#define CPMEM_WORD0_DATA3_INT__BNDM    0x1F00000C,0x001C0000
+#define CPMEM_WORD0_DATA3_INT__SO      0x1F00000C,0x00020000
+#define CPMEM_WORD0_DATA3_INT__DIM     0x1F00000C,0x00010000
+#define CPMEM_WORD0_DATA3_INT__DEC_SEL 0x1F00000C,0x0000C000
+#define CPMEM_WORD0_DATA3_INT__BPP     0x1F00000C,0x00003800
+#define CPMEM_WORD0_DATA3_INT__SDRY    0x1F00000C,0x00000400
+#define CPMEM_WORD0_DATA3_INT__SDRX    0x1F00000C,0x00000200
+#define CPMEM_WORD0_DATA3_INT__SDY     0x1F00000C,0x000001FC
+#define CPMEM_WORD0_DATA3_INT__SCE     0x1F00000C,0x00000002
+#define CPMEM_WORD0_DATA3_INT__SCC     0x1F00000C,0x00000001
+
+#define CPMEM_WORD0_DATA4_INT__ADDR    0x1F000010
+#define CPMEM_WORD0_DATA4_INT__EMPTY   0x1F000010,0x00000000
+#define CPMEM_WORD0_DATA4_INT__FULL    0x1F000010,0xffffffff
+#define CPMEM_WORD0_DATA4_INT__RESERVED 0x1F000010,0xFFC00000
+#define CPMEM_WORD0_DATA4_INT__FH      0x1F000010,0x003FFC00
+#define CPMEM_WORD0_DATA4_INT__FW_HIGH 0x1F000010,0x000003FF
+
+#define CPMEM_WORD0_DATA0_N_INT__ADDR  0x1F000000
+#define CPMEM_WORD0_DATA0_N_INT__EMPTY 0x1F000000,0x00000000
+#define CPMEM_WORD0_DATA0_N_INT__FULL  0x1F000000,0xffffffff
+#define CPMEM_WORD0_DATA0_N_INT__XB    0x1F000000,0xFFF80000
+#define CPMEM_WORD0_DATA0_N_INT__YV    0x1F000000,0x0007FC00
+#define CPMEM_WORD0_DATA0_N_INT__XV    0x1F000000,0x000003FF
+
+#define CPMEM_WORD0_DATA1_N_INT__ADDR   0x1F000004
+#define CPMEM_WORD0_DATA1_N_INT__EMPTY  0x1F000004,0x00000000
+#define CPMEM_WORD0_DATA1_N_INT__FULL   0x1F000004,0xffffffff
+#define CPMEM_WORD0_DATA1_N_INT__UBO_LOW 0x1F000004,0xFFFFC000
+#define CPMEM_WORD0_DATA1_N_INT__CF     0x1F000004,0x00002000
+#define CPMEM_WORD0_DATA1_N_INT__NSB_B  0x1F000004,0x00001000
+#define CPMEM_WORD0_DATA1_N_INT__YB     0x1F000004,0x00000FFF
+
+#define CPMEM_WORD0_DATA2_N_INT__ADDR    0x1F000008
+#define CPMEM_WORD0_DATA2_N_INT__EMPTY   0x1F000008,0x00000000
+#define CPMEM_WORD0_DATA2_N_INT__FULL    0x1F000008,0xffffffff
+#define CPMEM_WORD0_DATA2_N_INT__RESERVED 0x1F000008,0xFC000000
+#define CPMEM_WORD0_DATA2_N_INT__IOX     0x1F000008,0x3c000000
+#define CPMEM_WORD0_DATA2_N_INT__VBO     0x1F000008,0x03FFFFF0
+#define CPMEM_WORD0_DATA2_N_INT__UBO_HIGH 0x1F000008,0x0000000F
+
+#define CPMEM_WORD0_DATA3_N_INT__ADDR    0x1F00000C
+#define CPMEM_WORD0_DATA3_N_INT__EMPTY   0x1F00000C,0x00000000
+#define CPMEM_WORD0_DATA3_N_INT__FULL    0x1F00000C,0xffffffff
+#define CPMEM_WORD0_DATA3_N_INT__FW_LOW          0x1F00000C,0xE0000000
+#define CPMEM_WORD0_DATA3_N_INT__CAE     0x1F00000C,0x10000000
+#define CPMEM_WORD0_DATA3_N_INT__CAP     0x1F00000C,0x08000000
+#define CPMEM_WORD0_DATA3_N_INT__THE     0x1F00000C,0x04000000
+#define CPMEM_WORD0_DATA3_N_INT__VF      0x1F00000C,0x02000000
+#define CPMEM_WORD0_DATA3_N_INT__HF      0x1F00000C,0x01000000
+#define CPMEM_WORD0_DATA3_N_INT__ROT     0x1F00000C,0x00800000
+#define CPMEM_WORD0_DATA3_N_INT__BM      0x1F00000C,0x00600000
+#define CPMEM_WORD0_DATA3_N_INT__BNDM    0x1F00000C,0x001C0000
+#define CPMEM_WORD0_DATA3_N_INT__SO      0x1F00000C,0x00020000
+#define CPMEM_WORD0_DATA3_N_INT__RESERVED 0x1F00000C,0x0001FFFF
+
+#define CPMEM_WORD0_DATA4_N_INT__ADDR    0x1F000010
+#define CPMEM_WORD0_DATA4_N_INT__EMPTY   0x1F000010,0x00000000
+#define CPMEM_WORD0_DATA4_N_INT__FULL    0x1F000010,0xffffffff
+#define CPMEM_WORD0_DATA4_N_INT__RESERVED 0x1F000010,0xFFC00000
+#define CPMEM_WORD0_DATA4_N_INT__FH      0x1F000010,0x003FFC00
+#define CPMEM_WORD0_DATA4_N_INT__FW_HIGH  0x1F000010,0x000003FF
+
+#define CPMEM_WORD1_DATA0_INT__ADDR    0x1F000020
+#define CPMEM_WORD1_DATA0_INT__EMPTY   0x1F000020,0x00000000
+#define CPMEM_WORD1_DATA0_INT__FULL    0x1F000020,0xffffffff
+#define CPMEM_WORD1_DATA0_INT__EBA1_LOW 0x1F000020,0xE0000000
+#define CPMEM_WORD1_DATA0_INT__EBA0    0x1F000020,0x1FFFFFFF
+
+#define CPMEM_WORD1_DATA1_INT__ADDR     0x1F000024
+#define CPMEM_WORD1_DATA1_INT__EMPTY    0x1F000024,0x00000000
+#define CPMEM_WORD1_DATA1_INT__FULL     0x1F000024,0xffffffff
+#define CPMEM_WORD1_DATA1_INT__ILO_LOW  0x1F000024,0xFC000000
+#define CPMEM_WORD1_DATA1_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF
+
+#define CPMEM_WORD1_DATA2_INT__ADDR    0x1F000028
+#define CPMEM_WORD1_DATA2_INT__EMPTY   0x1F000028,0x00000000
+#define CPMEM_WORD1_DATA2_INT__FULL    0x1F000028,0xffffffff
+#define CPMEM_WORD1_DATA2_INT__TH_LOW  0x1F000028,0x80000000
+#define CPMEM_WORD1_DATA2_INT__ID      0x1F000028,0x60000000
+#define CPMEM_WORD1_DATA2_INT__ALBM    0x1F000028,0x1C000000
+#define CPMEM_WORD1_DATA2_INT__ALU     0x1F000028,0x02000000
+#define CPMEM_WORD1_DATA2_INT__PFS     0x1F000028,0x01E00000
+#define CPMEM_WORD1_DATA2_INT__NPB     0x1F000028,0x001FC000
+#define CPMEM_WORD1_DATA2_INT__ILO_HIGH 0x1F000028,0x00003FFF
+
+#define CPMEM_WORD1_DATA3_INT__ADDR    0x1F00002C
+#define CPMEM_WORD1_DATA3_INT__EMPTY   0x1F00002C,0x00000000
+#define CPMEM_WORD1_DATA3_INT__FULL    0x1F00002C,0xffffffff
+#define CPMEM_WORD1_DATA3_INT__WID3    0x1F00002C,0xE0000000
+#define CPMEM_WORD1_DATA3_INT__WID2    0x1F00002C,0x1C000000
+#define CPMEM_WORD1_DATA3_INT__WID1    0x1F00002C,0x03800000
+#define CPMEM_WORD1_DATA3_INT__WID0    0x1F00002C,0x00700000
+#define CPMEM_WORD1_DATA3_INT__SL      0x1F00002C,0x000FFFC0
+#define CPMEM_WORD1_DATA3_INT__TH_HIGH 0x1F00002C,0x0000003F
+
+#define CPMEM_WORD1_DATA4_INT__ADDR    0x1F000030
+#define CPMEM_WORD1_DATA4_INT__EMPTY   0x1F000030,0x00000000
+#define CPMEM_WORD1_DATA4_INT__FULL    0x1F000030,0xffffffff
+#define CPMEM_WORD1_DATA4_INT__RESERVED 0x1F000030,0xFFF00000
+#define CPMEM_WORD1_DATA4_INT__SXYS    0x1F000030,0x00100000
+#define CPMEM_WORD1_DATA4_INT__OFS3    0x1F000030,0x000F8000
+#define CPMEM_WORD1_DATA4_INT__OFS2    0x1F000030,0x00007C00
+#define CPMEM_WORD1_DATA4_INT__OFS1    0x1F000030,0x000003E0
+#define CPMEM_WORD1_DATA4_INT__OFS0    0x1F000030,0x0000001F
+
+#define CPMEM_WORD1_DATA0_N_INT__ADDR    0x1F000020
+#define CPMEM_WORD1_DATA0_N_INT__EMPTY   0x1F000020,0x00000000
+#define CPMEM_WORD1_DATA0_N_INT__FULL    0x1F000020,0xffffffff
+#define CPMEM_WORD1_DATA0_N_INT__EBA1_LOW 0x1F000020,0xE0000000
+#define CPMEM_WORD1_DATA0_N_INT__EBA0    0x1F000020,0x1FFFFFFF
+
+#define CPMEM_WORD1_DATA1_N_INT__ADDR     0x1F000024
+#define CPMEM_WORD1_DATA1_N_INT__EMPTY    0x1F000024,0x00000000
+#define CPMEM_WORD1_DATA1_N_INT__FULL     0x1F000024,0xffffffff
+#define CPMEM_WORD1_DATA1_N_INT__ILO_LOW   0x1F000024,0xFC000000
+#define CPMEM_WORD1_DATA1_N_INT__EBA1_HIGH 0x1F000024,0x03FFFFFF
+
+#define CPMEM_WORD1_DATA2_N_INT__ADDR    0x1F000028
+#define CPMEM_WORD1_DATA2_N_INT__EMPTY   0x1F000028,0x00000000
+#define CPMEM_WORD1_DATA2_N_INT__FULL    0x1F000028,0xffffffff
+#define CPMEM_WORD1_DATA2_N_INT__TH_LOW          0x1F000028,0x80000000
+#define CPMEM_WORD1_DATA2_N_INT__ID      0x1F000028,0x60000000
+#define CPMEM_WORD1_DATA2_N_INT__ALBM    0x1F000028,0x1C000000
+#define CPMEM_WORD1_DATA2_N_INT__ALU     0x1F000028,0x02000000
+#define CPMEM_WORD1_DATA2_N_INT__PFS     0x1F000028,0x01E00000
+#define CPMEM_WORD1_DATA2_N_INT__NPB     0x1F000028,0x001FC000
+#define CPMEM_WORD1_DATA2_N_INT__ILO_HIGH 0x1F000028,0x00003FFF
+
+#define CPMEM_WORD1_DATA3_N_INT__ADDR    0x1F00002C
+#define CPMEM_WORD1_DATA3_N_INT__EMPTY   0x1F00002C,0x00000000
+#define CPMEM_WORD1_DATA3_N_INT__FULL    0x1F00002C,0xffffffff
+#define CPMEM_WORD1_DATA3_N_INT__SLY     0x1F00002C,0x000FFFC0
+#define CPMEM_WORD1_DATA3_N_INT__WID3    0x1F00002C,0xE0000000
+#define CPMEM_WORD1_DATA3_N_INT__TH_HIGH  0x1F00002C,0x0000003F
+
+#define CPMEM_WORD1_DATA4_N_INT__ADDR     0x1F000030
+#define CPMEM_WORD1_DATA4_N_INT__EMPTY    0x1F000030,0x00000000
+#define CPMEM_WORD1_DATA4_N_INT__FULL     0x1F000030,0xffffffff
+#define CPMEM_WORD1_DATA4_N_INT__RESERVED  0x1F000030,0xFFFFC000
+#define CPMEM_WORD1_DATA4_N_INT__SLUV     0x1F000030,0x00003FFF
+// ================= End of IPUV3EX CPMEM Registers =====================
+
+#define IC_INTERNAL_MEM_FW 0x400
+#define TASK1_TMP_COEF IC_INTERNAL_MEM_FW
+#define TASK1_CSC1_W0   TASK1_TMP_COEF+1
+#define TASK1_CSC1_W1   TASK1_CSC1_W0+1
+#define TASK1_CSC1_W2   TASK1_CSC1_W1+1
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR   0x1F060000 + (TASK1_CSC1_W0 << 3)
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C00    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C11    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_ENC_CSC1_WORD0__C22    IPU_IC_TPMEM_ENC_CSC1_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR     0x1F060000 + (TASK1_CSC1_W0 << 3) + 4
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__FULL     IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__SCALE    IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_ENC_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_ENC_CSC1_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR   0x1F060000 + (TASK1_CSC1_W1 << 3)
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C01    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C10    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_ENC_CSC1_WORD2__C20    IPU_IC_TPMEM_ENC_CSC1_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR    0x1F060000 + (TASK1_CSC1_W1 << 3) + 4
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__FULL    IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR   0x1F060000 + (TASK1_CSC1_W2 << 3)
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__FULL   IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C02    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C12    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_ENC_CSC1_WORD4__C21    IPU_IC_TPMEM_ENC_CSC1_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR    0x1F060000 + (TASK1_CSC1_W2 << 3) + 4
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__FULL    IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_ENC_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_ENC_CSC1_WORD5__ADDR,0x000000FF
+
+#define TASK2_TMP_COEF TASK1_CSC1_W2+IC_INTERNAL_MEM_FW+1
+#define TASK2_CSC1_W0   TASK2_TMP_COEF+1
+#define TASK2_CSC1_W1   TASK2_CSC1_W0+1
+#define TASK2_CSC1_W2   TASK2_CSC1_W1+1
+#define TASK2_CSC2_W0   TASK2_CSC1_W2+1
+#define TASK2_CSC2_W1   TASK2_CSC2_W0+1
+#define TASK2_CSC2_W2   TASK2_CSC2_W1+1
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR   0x1F060000 + (TASK2_CSC1_W0 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C00    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C11    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD0__C22    IPU_IC_TPMEM_VIEW_CSC1_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR     0x1F060000 + (TASK2_CSC1_W0 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__FULL     IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__SCALE    IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_VIEW_CSC1_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR   0x1F060000 + (TASK2_CSC1_W1 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C01    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C10    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD2__C20    IPU_IC_TPMEM_VIEW_CSC1_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR    0x1F060000 + (TASK2_CSC1_W1 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__FULL    IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR   0x1F060000 + (TASK2_CSC1_W2 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__FULL   IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C02    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C12    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD4__C21    IPU_IC_TPMEM_VIEW_CSC1_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR    0x1F060000 + (TASK2_CSC1_W2 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__FULL    IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC1_WORD5__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR   0x1F060000 + (TASK2_CSC2_W0 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C00    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C11    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD0__C22    IPU_IC_TPMEM_VIEW_CSC2_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR     0x1F060000 + (TASK2_CSC2_W0 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__EMPTY    IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__FULL     IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__SCALE    IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD1__A0_HIGH  IPU_IC_TPMEM_VIEW_CSC2_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR   0x1F060000 + (TASK2_CSC2_W1 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C01    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C10    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD2__C20    IPU_IC_TPMEM_VIEW_CSC2_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR    0x1F060000 + (TASK2_CSC2_W1 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__EMPTY   IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__FULL    IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR   0x1F060000 + (TASK2_CSC2_W2 << 3)
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__EMPTY  IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__FULL   IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C02    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C12    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD4__C21    IPU_IC_TPMEM_VIEW_CSC2_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR    0x1F060000 + (TASK2_CSC2_W2 << 3) + 4
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__EMPTY   IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__FULL    IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_VIEW_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_VIEW_CSC2_WORD5__ADDR,0x000000FF
+
+#define TASK3_TMP_COEF TASK2_CSC2_W2+IC_INTERNAL_MEM_FW+1
+#define TASK3_CSC1_W0   TASK3_TMP_COEF+1
+#define TASK3_CSC1_W1   TASK3_CSC1_W0+1
+#define TASK3_CSC1_W2   TASK3_CSC1_W1+1
+#define TASK3_CSC2_W0   TASK3_CSC1_W2+1
+#define TASK3_CSC2_W1   TASK3_CSC2_W0+1
+#define TASK3_CSC2_W2   TASK3_CSC2_W1+1
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR   0x1F060000 + (TASK3_CSC1_W0 << 3)
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__FULL   IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__C00    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__C11    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC1_WORD0__C22    IPU_IC_TPMEM_POST_CSC1_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR     0x1F060000 + (TASK3_CSC1_W0 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__EMPTY    IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__FULL     IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__SCALE    IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_POST_CSC1_WORD1__A0_HIGH  IPU_IC_TPMEM_POST_CSC1_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR   0x1F060000 + (TASK3_CSC1_W1 << 3)
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__FULL   IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__C01    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__C10    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC1_WORD2__C20    IPU_IC_TPMEM_POST_CSC1_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR    0x1F060000 + (TASK3_CSC1_W1 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__EMPTY   IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__FULL    IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC1_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR   0x1F060000 + (TASK3_CSC1_W2 << 3)
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__EMPTY  IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__FULL   IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__C02    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__C12    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC1_WORD4__C21    IPU_IC_TPMEM_POST_CSC1_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR    0x1F060000 + (TASK3_CSC1_W2 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__EMPTY   IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__FULL    IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC1_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC1_WORD5__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR   0x1F060000 + (TASK3_CSC2_W0 << 3)
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__FULL   IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__A0_LOW IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__C00    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__C11    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC2_WORD0__C22    IPU_IC_TPMEM_POST_CSC2_WORD0__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR     0x1F060000 + (TASK3_CSC2_W0 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__EMPTY    IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__FULL     IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__SAT_MODE IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000400
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__SCALE    IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x00000300
+#define IPU_IC_TPMEM_POST_CSC2_WORD1__A0_HIGH  IPU_IC_TPMEM_POST_CSC2_WORD1__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR   0x1F060000 + (TASK3_CSC2_W1 << 3)
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__FULL   IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__A1_LOW IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__C01    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__C10    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC2_WORD2__C20    IPU_IC_TPMEM_POST_CSC2_WORD2__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR    0x1F060000 + (TASK3_CSC2_W1 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__EMPTY   IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__FULL    IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD3__A1_HIGH IPU_IC_TPMEM_POST_CSC2_WORD3__ADDR,0x000000FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR   0x1F060000 + (TASK3_CSC2_W2 << 3)
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__EMPTY  IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__FULL   IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__A2_LOW IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0xF8000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__C02    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x07FC0000
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__C12    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x0003FE00
+#define IPU_IC_TPMEM_POST_CSC2_WORD4__C21    IPU_IC_TPMEM_POST_CSC2_WORD4__ADDR,0x000001FF
+
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR    0x1F060000 + (TASK3_CSC2_W2 << 3) + 4
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__EMPTY   IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x00000000
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__FULL    IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0xffffffff
+#define IPU_IC_TPMEM_POST_CSC2_WORD5__A2_HIGH IPU_IC_TPMEM_POST_CSC2_WORD5__ADDR,0x000000FF
+
+#define SRM_DP_COM_CONF_SYNC__ADDR                    0x1F040000
+#define SRM_DP_COM_CONF_SYNC__EMPTY                   0x1F040000,0x00000000
+#define SRM_DP_COM_CONF_SYNC__FULL                    0x1F040000,0xffffffff
+#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC     0x1F040000,0x00002000
+#define SRM_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC        0x1F040000,0x00001000
+#define SRM_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC 0x1F040000,0x00000800
+#define SRM_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC 0x1F040000,0x00000400
+#define SRM_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC         0x1F040000,0x00000300
+#define SRM_DP_COM_CONF_SYNC__DP_COC_SYNC             0x1F040000,0x00000070
+#define SRM_DP_COM_CONF_SYNC__DP_GWCKE_SYNC           0x1F040000,0x00000008
+#define SRM_DP_COM_CONF_SYNC__DP_GWAM_SYNC            0x1F040000,0x00000004
+#define SRM_DP_COM_CONF_SYNC__DP_GWSEL_SYNC           0x1F040000,0x00000002
+#define SRM_DP_COM_CONF_SYNC__DP_FG_EN_SYNC           0x1F040000,0x00000001
+
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__ADDR         0x1F040004
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__EMPTY        0x1F040004,0x00000000
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__FULL         0x1F040004,0xffffffff
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC  0x1F040004,0xFF000000
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC 0x1F040004,0x00FF0000
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC 0x1F040004,0x0000FF00
+#define SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC 0x1F040004,0x000000FF
+
+#define SRM_DP_FG_POS_SYNC__ADDR        0x1F040008
+#define SRM_DP_FG_POS_SYNC__EMPTY       0x1F040008,0x00000000
+#define SRM_DP_FG_POS_SYNC__FULL        0x1F040008,0xffffffff
+#define SRM_DP_FG_POS_SYNC__DP_FGXP_SYNC 0x1F040008,0x07FF0000
+#define SRM_DP_FG_POS_SYNC__DP_FGYP_SYNC 0x1F040008,0x000007FF
+
+#define SRM_DP_CUR_POS_SYNC__ADDR       0x1F04000C
+#define SRM_DP_CUR_POS_SYNC__EMPTY      0x1F04000C,0x00000000
+#define SRM_DP_CUR_POS_SYNC__FULL       0x1F04000C,0xffffffff
+#define SRM_DP_CUR_POS_SYNC__DP_CXW_SYNC 0x1F04000C,0xF8000000
+#define SRM_DP_CUR_POS_SYNC__DP_CXP_SYNC 0x1F04000C,0x07FF0000
+#define SRM_DP_CUR_POS_SYNC__DP_CYH_SYNC 0x1F04000C,0x0000F800
+#define SRM_DP_CUR_POS_SYNC__DP_CYP_SYNC 0x1F04000C,0x000007FF
+
+#define SRM_DP_CUR_MAP_SYNC__ADDR             0x1F040010
+#define SRM_DP_CUR_MAP_SYNC__EMPTY            0x1F040010,0x00000000
+#define SRM_DP_CUR_MAP_SYNC__FULL             0x1F040010,0xffffffff
+#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_R_SYNC 0x1F040010,0x00FF0000
+#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_G_SYNC 0x1F040010,0x0000FF00
+#define SRM_DP_CUR_MAP_SYNC__DP_CUR_COL_B_SYNC 0x1F040010,0x000000FF
+
+#define SRM_DP_GAMMA_C_SYNC_0__ADDR             0x1F040014
+#define SRM_DP_GAMMA_C_SYNC_0__EMPTY            0x1F040014,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_0__FULL             0x1F040014,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_1 0x1F040014,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_0__DP_GAMMA_C_SYNC_0 0x1F040014,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_1__ADDR             0x1F040018
+#define SRM_DP_GAMMA_C_SYNC_1__EMPTY            0x1F040018,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_1__FULL             0x1F040018,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_3 0x1F040018,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_1__DP_GAMMA_C_SYNC_2 0x1F040018,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_2__ADDR             0x1F04001C
+#define SRM_DP_GAMMA_C_SYNC_2__EMPTY            0x1F04001C,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_2__FULL             0x1F04001C,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_5 0x1F04001C,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_2__DP_GAMMA_C_SYNC_4 0x1F04001C,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_3__ADDR             0x1F040020
+#define SRM_DP_GAMMA_C_SYNC_3__EMPTY            0x1F040020,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_3__FULL             0x1F040020,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_7 0x1F040020,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_3__DP_GAMMA_C_SYNC_6 0x1F040020,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_4__ADDR             0x1F040024
+#define SRM_DP_GAMMA_C_SYNC_4__EMPTY            0x1F040024,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_4__FULL             0x1F040024,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_9 0x1F040024,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_4__DP_GAMMA_C_SYNC_8 0x1F040024,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_5__ADDR              0x1F040028
+#define SRM_DP_GAMMA_C_SYNC_5__EMPTY             0x1F040028,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_5__FULL              0x1F040028,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_11 0x1F040028,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_5__DP_GAMMA_C_SYNC_10 0x1F040028,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_6__ADDR              0x1F04002C
+#define SRM_DP_GAMMA_C_SYNC_6__EMPTY             0x1F04002C,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_6__FULL              0x1F04002C,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_13 0x1F04002C,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_6__DP_GAMMA_C_SYNC_12 0x1F04002C,0x000001FF
+
+#define SRM_DP_GAMMA_C_SYNC_7__ADDR              0x1F040030
+#define SRM_DP_GAMMA_C_SYNC_7__EMPTY             0x1F040030,0x00000000
+#define SRM_DP_GAMMA_C_SYNC_7__FULL              0x1F040030,0xffffffff
+#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_15 0x1F040030,0x01FF0000
+#define SRM_DP_GAMMA_C_SYNC_7__DP_GAMMA_C_SYNC_14 0x1F040030,0x000001FF
+
+#define SRM_DP_GAMMA_S_SYNC_0__ADDR             0x1F040034
+#define SRM_DP_GAMMA_S_SYNC_0__EMPTY            0x1F040034,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_0__FULL             0x1F040034,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_3 0x1F040034,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_2 0x1F040034,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_1 0x1F040034,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_0__DP_GAMMA_S_SYNC_0 0x1F040034,0x000000FF
+
+#define SRM_DP_GAMMA_S_SYNC_1__ADDR             0x1F040038
+#define SRM_DP_GAMMA_S_SYNC_1__EMPTY            0x1F040038,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_1__FULL             0x1F040038,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_7 0x1F040038,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_6 0x1F040038,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_5 0x1F040038,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_1__DP_GAMMA_S_SYNC_4 0x1F040038,0x000000FF
+
+#define SRM_DP_GAMMA_S_SYNC_2__ADDR              0x1F04003C
+#define SRM_DP_GAMMA_S_SYNC_2__EMPTY             0x1F04003C,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_2__FULL              0x1F04003C,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_11 0x1F04003C,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_10 0x1F04003C,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_9  0x1F04003C,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_2__DP_GAMMA_S_SYNC_8  0x1F04003C,0x000000FF
+
+#define SRM_DP_GAMMA_S_SYNC_3__ADDR              0x1F040040
+#define SRM_DP_GAMMA_S_SYNC_3__EMPTY             0x1F040040,0x00000000
+#define SRM_DP_GAMMA_S_SYNC_3__FULL              0x1F040040,0xffffffff
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_15 0x1F040040,0xFF000000
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_14 0x1F040040,0x00FF0000
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_13 0x1F040040,0x0000FF00
+#define SRM_DP_GAMMA_S_SYNC_3__DP_GAMMA_S_SYNC_12 0x1F040040,0x000000FF
+
+#define SRM_DP_CSCA_SYNC_0__ADDR           0x1F040044
+#define SRM_DP_CSCA_SYNC_0__EMPTY          0x1F040044,0x00000000
+#define SRM_DP_CSCA_SYNC_0__FULL           0x1F040044,0xffffffff
+#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_1 0x1F040044,0x03FF0000
+#define SRM_DP_CSCA_SYNC_0__DP_CSC_A_SYNC_0 0x1F040044,0x000003FF
+
+#define SRM_DP_CSCA_SYNC_1__ADDR           0x1F040048
+#define SRM_DP_CSCA_SYNC_1__EMPTY          0x1F040048,0x00000000
+#define SRM_DP_CSCA_SYNC_1__FULL           0x1F040048,0xffffffff
+#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_3 0x1F040048,0x03FF0000
+#define SRM_DP_CSCA_SYNC_1__DP_CSC_A_SYNC_2 0x1F040048,0x000003FF
+
+#define SRM_DP_CSCA_SYNC_2__ADDR           0x1F04004C
+#define SRM_DP_CSCA_SYNC_2__EMPTY          0x1F04004C,0x00000000
+#define SRM_DP_CSCA_SYNC_2__FULL           0x1F04004C,0xffffffff
+#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_5 0x1F04004C,0x03FF0000
+#define SRM_DP_CSCA_SYNC_2__DP_CSC_A_SYNC_4 0x1F04004C,0x000003FF
+
+#define SRM_DP_CSCA_SYNC_3__ADDR           0x1F040050
+#define SRM_DP_CSCA_SYNC_3__EMPTY          0x1F040050,0x00000000
+#define SRM_DP_CSCA_SYNC_3__FULL           0x1F040050,0xffffffff
+#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_7 0x1F040050,0x03FF0000
+#define SRM_DP_CSCA_SYNC_3__DP_CSC_A_SYNC_6 0x1F040050,0x000003FF
+
+#define SRM_DP_CSC_SYNC_0__ADDR                  0x1F040054
+#define SRM_DP_CSC_SYNC_0__EMPTY         0x1F040054,0x00000000
+#define SRM_DP_CSC_SYNC_0__FULL                  0x1F040054,0xffffffff
+#define SRM_DP_CSC_SYNC_0__DP_CSC_S0_SYNC 0x1F040054,0xC0000000
+#define SRM_DP_CSC_SYNC_0__DP_CSC_B0_SYNC 0x1F040054,0x3FFF0000
+#define SRM_DP_CSC_SYNC_0__DP_CSC_A8_SYNC 0x1F040054,0x000003FF
+
+#define SRM_DP_CSC_SYNC_1__ADDR                  0x1F040058
+#define SRM_DP_CSC_SYNC_1__EMPTY         0x1F040058,0x00000000
+#define SRM_DP_CSC_SYNC_1__FULL                  0x1F040058,0xffffffff
+#define SRM_DP_CSC_SYNC_1__DP_CSC_S2_SYNC 0x1F040058,0xC0000000
+#define SRM_DP_CSC_SYNC_1__DP_CSC_B2_SYNC 0x1F040058,0x3FFF0000
+#define SRM_DP_CSC_SYNC_1__DP_CSC_S1_SYNC 0x1F040058,0x0000C000
+#define SRM_DP_CSC_SYNC_1__DP_CSC_B1_SYNC 0x1F040058,0x00003FFF
+
+#define SRM_DP_CUR_POS_ALT__ADDR           0x1F04005C
+#define SRM_DP_CUR_POS_ALT__EMPTY          0x1F04005C,0x00000000
+#define SRM_DP_CUR_POS_ALT__FULL           0x1F04005C,0xffffffff
+#define SRM_DP_CUR_POS_ALT__DP_CXW_SYNC_ALT 0x1F04005C,0xF8000000
+#define SRM_DP_CUR_POS_ALT__DP_CXP_SYNC_ALT 0x1F04005C,0x07FF0000
+#define SRM_DP_CUR_POS_ALT__DP_CYH_SYNC_ALT 0x1F04005C,0x0000F800
+#define SRM_DP_CUR_POS_ALT__DP_CYP_SYNC_ALT 0x1F04005C,0x000007FF
+
+#define SRM_DP_COM_CONF_ASYNC0__ADDR                      0x1F040060
+#define SRM_DP_COM_CONF_ASYNC0__EMPTY                     0x1F040060,0x00000000
+#define SRM_DP_COM_CONF_ASYNC0__FULL                      0x1F040060,0xffffffff
+#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_YUV_EN_ASYNC0    0x1F040060,0x00002000
+#define SRM_DP_COM_CONF_ASYNC0__DP_GAMMA_EN_ASYNC0        0x1F040060,0x00001000
+#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_YUV_SAT_MODE_ASYNC0 0x1F040060,0x00000800
+#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_GAMUT_SAT_EN_ASYNC0 0x1F040060,0x00000400
+#define SRM_DP_COM_CONF_ASYNC0__DP_CSC_DEF_ASYNC0         0x1F040060,0x00000300
+#define SRM_DP_COM_CONF_ASYNC0__DP_COC_ASYNC0             0x1F040060,0x00000070
+#define SRM_DP_COM_CONF_ASYNC0__DP_GWCKE_ASYNC0                   0x1F040060,0x00000008
+#define SRM_DP_COM_CONF_ASYNC0__DP_GWAM_ASYNC0            0x1F040060,0x00000004
+#define SRM_DP_COM_CONF_ASYNC0__DP_GWSEL_ASYNC0                   0x1F040060,0x00000002
+
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__ADDR           0x1F040064
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__EMPTY          0x1F040064,0x00000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__FULL           0x1F040064,0xffffffff
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWAV_ASYNC0  0x1F040064,0xFF000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKR_ASYNC0 0x1F040064,0x00FF0000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKG_ASYNC0 0x1F040064,0x0000FF00
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC0__DP_GWCKB_ASYNC0 0x1F040064,0x000000FF
+
+#define SRM_DP_FG_POS_ASYNC0__ADDR          0x1F040068
+#define SRM_DP_FG_POS_ASYNC0__EMPTY         0x1F040068,0x00000000
+#define SRM_DP_FG_POS_ASYNC0__FULL          0x1F040068,0xffffffff
+#define SRM_DP_FG_POS_ASYNC0__DP_FGXP_ASYNC0 0x1F040068,0x07FF0000
+#define SRM_DP_FG_POS_ASYNC0__DP_FGYP_ASYNC0 0x1F040068,0x000007FF
+
+#define SRM_DP_CUR_POS_ASYNC0__ADDR         0x1F04006C
+#define SRM_DP_CUR_POS_ASYNC0__EMPTY        0x1F04006C,0x00000000
+#define SRM_DP_CUR_POS_ASYNC0__FULL         0x1F04006C,0xffffffff
+#define SRM_DP_CUR_POS_ASYNC0__DP_CXW_ASYNC0 0x1F04006C,0xF8000000
+#define SRM_DP_CUR_POS_ASYNC0__DP_CXP_ASYNC0 0x1F04006C,0x07FF0000
+#define SRM_DP_CUR_POS_ASYNC0__DP_CYH_ASYNC0 0x1F04006C,0x0000F800
+#define SRM_DP_CUR_POS_ASYNC0__DP_CYP_ASYNC0 0x1F04006C,0x000007FF
+
+#define SRM_DP_CUR_MAP_ASYNC0__ADDR            0x1F040070
+#define SRM_DP_CUR_MAP_ASYNC0__EMPTY           0x1F040070,0x00000000
+#define SRM_DP_CUR_MAP_ASYNC0__FULL            0x1F040070,0xffffffff
+#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_R_ASYNC0 0x1F040070,0x00FF0000
+#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_G_ASYNC0 0x1F040070,0x0000FF00
+#define SRM_DP_CUR_MAP_ASYNC0__CUR_COL_B_ASYNC0 0x1F040070,0x000000FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_0__ADDR               0x1F040074
+#define SRM_DP_GAMMA_C_ASYNC0_0__EMPTY              0x1F040074,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_0__FULL               0x1F040074,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_1 0x1F040074,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_0__DP_GAMMA_C_ASYNC0_0 0x1F040074,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_1__ADDR               0x1F040078
+#define SRM_DP_GAMMA_C_ASYNC0_1__EMPTY              0x1F040078,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_1__FULL               0x1F040078,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_3 0x1F040078,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_1__DP_GAMMA_C_ASYNC0_2 0x1F040078,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_2__ADDR               0x1F04007C
+#define SRM_DP_GAMMA_C_ASYNC0_2__EMPTY              0x1F04007C,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_2__FULL               0x1F04007C,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_5 0x1F04007C,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_2__DP_GAMMA_C_ASYNC0_4 0x1F04007C,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_3__ADDR               0x1F040080
+#define SRM_DP_GAMMA_C_ASYNC0_3__EMPTY              0x1F040080,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_3__FULL               0x1F040080,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_7 0x1F040080,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_3__DP_GAMMA_C_ASYNC0_6 0x1F040080,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_4__ADDR               0x1F040084
+#define SRM_DP_GAMMA_C_ASYNC0_4__EMPTY              0x1F040084,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_4__FULL               0x1F040084,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_9 0x1F040084,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_4__DP_GAMMA_C_ASYNC0_8 0x1F040084,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_5__ADDR                0x1F040088
+#define SRM_DP_GAMMA_C_ASYNC0_5__EMPTY               0x1F040088,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_5__FULL                0x1F040088,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_11 0x1F040088,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_5__DP_GAMMA_C_ASYNC0_10 0x1F040088,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_6__ADDR                0x1F04008C
+#define SRM_DP_GAMMA_C_ASYNC0_6__EMPTY               0x1F04008C,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_6__FULL                0x1F04008C,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_13 0x1F04008C,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_6__DP_GAMMA_C_ASYNC0_12 0x1F04008C,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC0_7__ADDR                0x1F040090
+#define SRM_DP_GAMMA_C_ASYNC0_7__EMPTY               0x1F040090,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC0_7__FULL                0x1F040090,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_15 0x1F040090,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC0_7__DP_GAMMA_C_ASYNC0_14 0x1F040090,0x000001FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_0__ADDR               0x1F040094
+#define SRM_DP_GAMMA_S_ASYNC0_0__EMPTY              0x1F040094,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_0__FULL               0x1F040094,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_3 0x1F040094,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_2 0x1F040094,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_1 0x1F040094,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_0__DP_GAMMA_S_ASYNC0_0 0x1F040094,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_1__ADDR               0x1F040098
+#define SRM_DP_GAMMA_S_ASYNC0_1__EMPTY              0x1F040098,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_1__FULL               0x1F040098,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_7 0x1F040098,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_6 0x1F040098,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_5 0x1F040098,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_1__DP_GAMMA_S_ASYNC0_4 0x1F040098,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_2__ADDR                0x1F04009C
+#define SRM_DP_GAMMA_S_ASYNC0_2__EMPTY               0x1F04009C,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_2__FULL                0x1F04009C,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_11 0x1F04009C,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_10 0x1F04009C,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_9  0x1F04009C,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_2__DP_GAMMA_S_ASYNC0_8  0x1F04009C,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC0_3__ADDR                0x1F0400A0
+#define SRM_DP_GAMMA_S_ASYNC0_3__EMPTY               0x1F0400A0,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC0_3__FULL                0x1F0400A0,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_15 0x1F0400A0,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_14 0x1F0400A0,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_13 0x1F0400A0,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC0_3__DP_GAMMA_S_ASYNC0_12 0x1F0400A0,0x000000FF
+
+#define SRM_DP_CSCA_ASYNC0_0__ADDR             0x1F0400A4
+#define SRM_DP_CSCA_ASYNC0_0__EMPTY            0x1F0400A4,0x00000000
+#define SRM_DP_CSCA_ASYNC0_0__FULL             0x1F0400A4,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_1 0x1F0400A4,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_0__DP_CSC_A_ASYNC0_0 0x1F0400A4,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC0_1__ADDR             0x1F0400A8
+#define SRM_DP_CSCA_ASYNC0_1__EMPTY            0x1F0400A8,0x00000000
+#define SRM_DP_CSCA_ASYNC0_1__FULL             0x1F0400A8,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_3 0x1F0400A8,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_1__DP_CSC_A_ASYNC0_2 0x1F0400A8,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC0_2__ADDR             0x1F0400AC
+#define SRM_DP_CSCA_ASYNC0_2__EMPTY            0x1F0400AC,0x00000000
+#define SRM_DP_CSCA_ASYNC0_2__FULL             0x1F0400AC,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_5 0x1F0400AC,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_2__DP_CSC_A_ASYNC0_4 0x1F0400AC,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC0_3__ADDR             0x1F0400B0
+#define SRM_DP_CSCA_ASYNC0_3__EMPTY            0x1F0400B0,0x00000000
+#define SRM_DP_CSCA_ASYNC0_3__FULL             0x1F0400B0,0xffffffff
+#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_7 0x1F0400B0,0x03FF0000
+#define SRM_DP_CSCA_ASYNC0_3__DP_CSC_A_ASYNC0_6 0x1F0400B0,0x000003FF
+
+#define SRM_DP_CSC_ASYNC0_0__ADDR            0x1F0400B4
+#define SRM_DP_CSC_ASYNC0_0__EMPTY           0x1F0400B4,0x00000000
+#define SRM_DP_CSC_ASYNC0_0__FULL            0x1F0400B4,0xffffffff
+#define SRM_DP_CSC_ASYNC0_0__DP_CSC_S0_ASYNC0 0x1F0400B4,0xC0000000
+#define SRM_DP_CSC_ASYNC0_0__DP_CSC_B0_ASYNC0 0x1F0400B4,0x3FFF0000
+#define SRM_DP_CSC_ASYNC0_0__DP_CSC_A8_ASYNC0 0x1F0400B4,0x000003FF
+
+#define SRM_DP_CSC_ASYNC0_1__ADDR            0x1F0400B8
+#define SRM_DP_CSC_ASYNC0_1__EMPTY           0x1F0400B8,0x00000000
+#define SRM_DP_CSC_ASYNC0_1__FULL            0x1F0400B8,0xffffffff
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S2_ASYNC0 0x1F0400B8,0xC0000000
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B2_ASYNC0 0x1F0400B8,0x3FFF0000
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_S1_ASYNC0 0x1F0400B8,0x0000C000
+#define SRM_DP_CSC_ASYNC0_1__DP_CSC_B1_ASYNC0 0x1F0400B8,0x00003FFF
+
+#define SRM_DP_COM_CONF_ASYNC1__ADDR                      0x1F0400BC
+#define SRM_DP_COM_CONF_ASYNC1__EMPTY                     0x1F0400BC,0x00000000
+#define SRM_DP_COM_CONF_ASYNC1__FULL                      0x1F0400BC,0xffffffff
+#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_YUV_EN_ASYNC1    0x1F0400BC,0x00002000
+#define SRM_DP_COM_CONF_ASYNC1__DP_GAMMA_EN_ASYNC1        0x1F0400BC,0x00001000
+#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_YUV_SAT_MODE_ASYNC1 0x1F0400BC,0x00000800
+#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_GAMUT_SAT_EN_ASYNC1 0x1F0400BC,0x00000400
+#define SRM_DP_COM_CONF_ASYNC1__DP_CSC_DEF_ASYNC1         0x1F0400BC,0x00000300
+#define SRM_DP_COM_CONF_ASYNC1__DP_COC_ASYNC1             0x1F0400BC,0x00000070
+#define SRM_DP_COM_CONF_ASYNC1__DP_GWCKE_ASYNC1                   0x1F0400BC,0x00000008
+#define SRM_DP_COM_CONF_ASYNC1__DP_GWAM_ASYNC1            0x1F0400BC,0x00000004
+#define SRM_DP_COM_CONF_ASYNC1__DP_GWSEL_ASYNC1                   0x1F0400BC,0x00000002
+
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__ADDR           0x1F0400C0
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__EMPTY          0x1F0400C0,0x00000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__FULL           0x1F0400C0,0xffffffff
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWAV_ASYNC1  0x1F0400C0,0xFF000000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKR_ASYNC1 0x1F0400C0,0x00FF0000
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKG_ASYNC1 0x1F0400C0,0x0000FF00
+#define SRM_DP_GRAPH_WIND_CTRL_ASYNC1__DP_GWCKB_ASYNC1 0x1F0400C0,0x000000FF
+
+#define SRM_DP_FG_POS_ASYNC1__ADDR          0x1F0400C4
+#define SRM_DP_FG_POS_ASYNC1__EMPTY         0x1F0400C4,0x00000000
+#define SRM_DP_FG_POS_ASYNC1__FULL          0x1F0400C4,0xffffffff
+#define SRM_DP_FG_POS_ASYNC1__DP_FGXP_ASYNC1 0x1F0400C4,0x07FF0000
+#define SRM_DP_FG_POS_ASYNC1__DP_FGYP_ASYNC1 0x1F0400C4,0x000007FF
+
+#define SRM_DP_CUR_POS_ASYNC1__ADDR         0x1F0400C8
+#define SRM_DP_CUR_POS_ASYNC1__EMPTY        0x1F0400C8,0x00000000
+#define SRM_DP_CUR_POS_ASYNC1__FULL         0x1F0400C8,0xffffffff
+#define SRM_DP_CUR_POS_ASYNC1__DP_CXW_ASYNC1 0x1F0400C8,0xF8000000
+#define SRM_DP_CUR_POS_ASYNC1__DP_CXP_ASYNC1 0x1F0400C8,0x07FF0000
+#define SRM_DP_CUR_POS_ASYNC1__DP_CYH_ASYNC1 0x1F0400C8,0x0000F800
+#define SRM_DP_CUR_POS_ASYNC1__DP_CYP_ASYNC1 0x1F0400C8,0x000007FF
+
+#define SRM_DP_CUR_MAP_ASYNC1__ADDR            0x1F0400CC
+#define SRM_DP_CUR_MAP_ASYNC1__EMPTY           0x1F0400CC,0x00000000
+#define SRM_DP_CUR_MAP_ASYNC1__FULL            0x1F0400CC,0xffffffff
+#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_R_ASYNC1 0x1F0400CC,0x00FF0000
+#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_G_ASYNC1 0x1F0400CC,0x0000FF00
+#define SRM_DP_CUR_MAP_ASYNC1__CUR_COL_B_ASYNC1 0x1F0400CC,0x000000FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_0__ADDR               0x1F0400D0
+#define SRM_DP_GAMMA_C_ASYNC1_0__EMPTY              0x1F0400D0,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_0__FULL               0x1F0400D0,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_1 0x1F0400D0,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_0__DP_GAMMA_C_ASYNC1_0 0x1F0400D0,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_1__ADDR               0x1F0400D4
+#define SRM_DP_GAMMA_C_ASYNC1_1__EMPTY              0x1F0400D4,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_1__FULL               0x1F0400D4,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_3 0x1F0400D4,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_1__DP_GAMMA_C_ASYNC1_2 0x1F0400D4,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_2__ADDR               0x1F0400D8
+#define SRM_DP_GAMMA_C_ASYNC1_2__EMPTY              0x1F0400D8,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_2__FULL               0x1F0400D8,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_5 0x1F0400D8,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_2__DP_GAMMA_C_ASYNC1_4 0x1F0400D8,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_3__ADDR               0x1F0400DC
+#define SRM_DP_GAMMA_C_ASYNC1_3__EMPTY              0x1F0400DC,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_3__FULL               0x1F0400DC,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_7 0x1F0400DC,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_3__DP_GAMMA_C_ASYNC1_6 0x1F0400DC,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_4__ADDR               0x1F0400E0
+#define SRM_DP_GAMMA_C_ASYNC1_4__EMPTY              0x1F0400E0,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_4__FULL               0x1F0400E0,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_9 0x1F0400E0,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_4__DP_GAMMA_C_ASYNC1_8 0x1F0400E0,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_5__ADDR                0x1F0400E4
+#define SRM_DP_GAMMA_C_ASYNC1_5__EMPTY               0x1F0400E4,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_5__FULL                0x1F0400E4,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_11 0x1F0400E4,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_5__DP_GAMMA_C_ASYNC1_10 0x1F0400E4,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_6__ADDR                0x1F0400E8
+#define SRM_DP_GAMMA_C_ASYNC1_6__EMPTY               0x1F0400E8,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_6__FULL                0x1F0400E8,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_13 0x1F0400E8,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_6__DP_GAMMA_C_ASYNC1_12 0x1F0400E8,0x000001FF
+
+#define SRM_DP_GAMMA_C_ASYNC1_7__ADDR                0x1F0400EC
+#define SRM_DP_GAMMA_C_ASYNC1_7__EMPTY               0x1F0400EC,0x00000000
+#define SRM_DP_GAMMA_C_ASYNC1_7__FULL                0x1F0400EC,0xffffffff
+#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_15 0x1F0400EC,0x01FF0000
+#define SRM_DP_GAMMA_C_ASYNC1_7__DP_GAMMA_C_ASYNC1_14 0x1F0400EC,0x000001FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_0__ADDR               0x1F0400F0
+#define SRM_DP_GAMMA_S_ASYNC1_0__EMPTY              0x1F0400F0,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_0__FULL               0x1F0400F0,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_3 0x1F0400F0,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_2 0x1F0400F0,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_1 0x1F0400F0,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_0__DP_GAMMA_S_ASYNC1_0 0x1F0400F0,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_1__ADDR               0x1F0400F4
+#define SRM_DP_GAMMA_S_ASYNC1_1__EMPTY              0x1F0400F4,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_1__FULL               0x1F0400F4,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_7 0x1F0400F4,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_6 0x1F0400F4,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_5 0x1F0400F4,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_1__DP_GAMMA_S_ASYNC1_4 0x1F0400F4,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_2__ADDR                0x1F0400F8
+#define SRM_DP_GAMMA_S_ASYNC1_2__EMPTY               0x1F0400F8,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_2__FULL                0x1F0400F8,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_11 0x1F0400F8,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_10 0x1F0400F8,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_9  0x1F0400F8,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_2__DP_GAMMA_S_ASYNC1_8  0x1F0400F8,0x000000FF
+
+#define SRM_DP_GAMMA_S_ASYNC1_3__ADDR                0x1F0400FC
+#define SRM_DP_GAMMA_S_ASYNC1_3__EMPTY               0x1F0400FC,0x00000000
+#define SRM_DP_GAMMA_S_ASYNC1_3__FULL                0x1F0400FC,0xffffffff
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_15 0x1F0400FC,0xFF000000
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_14 0x1F0400FC,0x00FF0000
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_13 0x1F0400FC,0x0000FF00
+#define SRM_DP_GAMMA_S_ASYNC1_3__DP_GAMMA_S_ASYNC1_12 0x1F0400FC,0x000000FF
+
+#define SRM_DP_CSCA_ASYNC1_0__ADDR             0x1F040100
+#define SRM_DP_CSCA_ASYNC1_0__EMPTY            0x1F040100,0x00000000
+#define SRM_DP_CSCA_ASYNC1_0__FULL             0x1F040100,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_1 0x1F040100,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_0__DP_CSC_A_ASYNC1_0 0x1F040100,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC1_1__ADDR             0x1F040104
+#define SRM_DP_CSCA_ASYNC1_1__EMPTY            0x1F040104,0x00000000
+#define SRM_DP_CSCA_ASYNC1_1__FULL             0x1F040104,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_3 0x1F040104,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_1__DP_CSC_A_ASYNC1_2 0x1F040104,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC1_2__ADDR             0x1F040108
+#define SRM_DP_CSCA_ASYNC1_2__EMPTY            0x1F040108,0x00000000
+#define SRM_DP_CSCA_ASYNC1_2__FULL             0x1F040108,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_5 0x1F040108,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_2__DP_CSC_A_ASYNC1_4 0x1F040108,0x000003FF
+
+#define SRM_DP_CSCA_ASYNC1_3__ADDR             0x1F04010C
+#define SRM_DP_CSCA_ASYNC1_3__EMPTY            0x1F04010C,0x00000000
+#define SRM_DP_CSCA_ASYNC1_3__FULL             0x1F04010C,0xffffffff
+#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_7 0x1F04010C,0x03FF0000
+#define SRM_DP_CSCA_ASYNC1_3__DP_CSC_A_ASYNC1_6 0x1F04010C,0x000003FF
+
+#define SRM_DP_CSC_ASYNC1_0__ADDR            0x1F040110
+#define SRM_DP_CSC_ASYNC1_0__EMPTY           0x1F040110,0x00000000
+#define SRM_DP_CSC_ASYNC1_0__FULL            0x1F040110,0xffffffff
+#define SRM_DP_CSC_ASYNC1_0__DP_CSC_S0_ASYNC1 0x1F040110,0xC0000000
+#define SRM_DP_CSC_ASYNC1_0__DP_CSC_B0_ASYNC1 0x1F040110,0x3FFF0000
+#define SRM_DP_CSC_ASYNC1_0__DP_CSC_A8_ASYNC1 0x1F040110,0x000003FF
+
+#define SRM_DP_CSC_ASYNC1_1__ADDR            0x1F040114
+#define SRM_DP_CSC_ASYNC1_1__EMPTY           0x1F040114,0x00000000
+#define SRM_DP_CSC_ASYNC1_1__FULL            0x1F040114,0xffffffff
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S2_ASYNC1 0x1F040114,0xC0000000
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B2_ASYNC1 0x1F040114,0x3FFF0000
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_S1_ASYNC1 0x1F040114,0x0000C000
+#define SRM_DP_CSC_ASYNC1_1__DP_CSC_B1_ASYNC1 0x1F040114,0x00003FFF
+
+#define SRM_ISP_C0__ADDR                  0x1F040118
+#define SRM_ISP_C0__EMPTY      0x1F040118,0x00000000
+#define SRM_ISP_C0__FULL       0x1F040118,0xffffffff
+#define SRM_ISP_C0__ISP_BURST_SIZE      0x1F040118,0x001C0000
+#define SRM_ISP_C0__ISP_RED_ROW_BEGIN      0x1F040118,0x00020000
+#define SRM_ISP_C0__ISP_GREEN_P_BEGIN      0x1F040118,0x00010000
+#define SRM_ISP_C0__LINEARCCM_ON       0x1F040118,0x00004000
+#define SRM_ISP_C0__LLF_G_EN      0x1F040118,0x00002000
+#define SRM_ISP_C0__LLF_RB_EN      0x1F040118,0x00001000
+#define SRM_ISP_C0__AD_EN      0x1F040118,0x00000800
+#define SRM_ISP_C0__STS_EN      0x1F040118,0x00000400
+#define SRM_ISP_C0__CL_EN      0x1F040118,0x00000200
+#define SRM_ISP_C0__CS_EN      0x1F040118,0x00000100
+#define SRM_ISP_C0__CCA_EN      0x1F040118,0x00000080
+#define SRM_ISP_C0__HFE_EN      0x1F040118,0x00000040
+#define SRM_ISP_C0__CNS_EN      0x1F040118,0x00000020
+#define SRM_ISP_C0__MTF_ROC_EN      0x1F040118,0x00000010
+#define SRM_ISP_C0__GAMMA_EN      0x1F040118,0x00000008
+#define SRM_ISP_C0__CROC_EN      0x1F040118,0x00000004
+#define SRM_ISP_C0__TBPR_EN      0x1F040118,0x00000002
+#define SRM_ISP_C0__BPR_EN      0x1F040118,0x00000001
+
+#define SRM_ISP_C1__ADDR                  0x1F04011C
+#define SRM_ISP_C1__EMPTY      0x1F04011C,0x00000000
+#define SRM_ISP_C1__FULL       0x1F04011C,0xffffffff
+#define SRM_ISP_C1__YUV_EN      0x1F04011C,0x20000000
+#define SRM_ISP_C1__CSC_SAT_MODE       0x1F04011C,0x10000000
+#define SRM_ISP_C1__BOTTOM_CROP              0x1F04011C,0x0E000000
+#define SRM_ISP_C1__TOP_CROP      0x1F04011C,0x01C00000
+#define SRM_ISP_C1__RIGHT_CROP      0x1F04011C,0x00380000
+#define SRM_ISP_C1__LEFT_CROP      0x1F04011C,0x00070000
+#define SRM_ISP_C1__MTF_ROC_SH_M       0x1F04011C,0x00006000
+#define SRM_ISP_C1__MTF_ROC_SH_N       0x1F04011C,0x00001800
+#define SRM_ISP_C1__MTF_ROC_SH_QA      0x1F04011C,0x00000700
+#define SRM_ISP_C1__MTF_ROC_SH_SHARP      0x1F04011C,0x000000E0
+#define SRM_ISP_C1__WIDEASPECT      0x1F04011C,0x00000010
+#define SRM_ISP_C1__APP_SEL      0x1F04011C,0x0000000C
+#define SRM_ISP_C1__INT_MODE      0x1F04011C,0x00000003
+
+#define SRM_ISP_FS__ADDR                  0x1F040120
+#define SRM_ISP_FS__EMPTY      0x1F040120,0x00000000
+#define SRM_ISP_FS__FULL       0x1F040120,0xffffffff
+#define SRM_ISP_FS__FWIDTH      0x1F040120,0x0FFF0000
+#define SRM_ISP_FS__FHEIGHT      0x1F040120,0x00000FFF
+
+#define SRM_ISP_BI__ADDR                  0x1F040124
+#define SRM_ISP_BI__EMPTY      0x1F040124,0x00000000
+#define SRM_ISP_BI__FULL       0x1F040124,0xffffffff
+#define SRM_ISP_BI__HBLANK      0x1F040124,0x0FFF0000
+#define SRM_ISP_BI__VBLANK      0x1F040124,0x00000FFF
+
+#define SRM_ISP_OCO__ADDR                  0x1F040128
+#define SRM_ISP_OCO__EMPTY      0x1F040128,0x00000000
+#define SRM_ISP_OCO__FULL      0x1F040128,0xffffffff
+#define SRM_ISP_OCO__HOFFSET      0x1F040128,0x1FFF0000
+#define SRM_ISP_OCO__VOFFSET      0x1F040128,0x00001FFF
+
+#define SRM_ISP_BPR1__ADDR                  0x1F04012C
+#define SRM_ISP_BPR1__EMPTY      0x1F04012C,0x00000000
+#define SRM_ISP_BPR1__FULL      0x1F04012C,0xffffffff
+#define SRM_ISP_BPR1__TB       0x1F04012C,0xFF000000
+#define SRM_ISP_BPR1__TDR      0x1F04012C,0x00FF0000
+#define SRM_ISP_BPR1__TR       0x1F04012C,0x0000FF00
+#define SRM_ISP_BPR1__DKR      0x1F04012C,0x000000FF
+
+#define SRM_ISP_BPR2__ADDR                  0x1F040130
+#define SRM_ISP_BPR2__EMPTY      0x1F040130,0x00000000
+#define SRM_ISP_BPR2__FULL      0x1F040130,0xffffffff
+#define SRM_ISP_BPR2__BRB      0x1F040130,0xFF000000
+#define SRM_ISP_BPR2__TT       0x1F040130,0x00FF0000
+#define SRM_ISP_BPR2__TVDB      0x1F040130,0x0000FF00
+#define SRM_ISP_BPR2__TDB      0x1F040130,0x000000FF
+
+#define SRM_ISP_BPR3__ADDR                  0x1F040134
+#define SRM_ISP_BPR3__EMPTY      0x1F040134,0x00000000
+#define SRM_ISP_BPR3__FULL      0x1F040134,0xffffffff
+#define SRM_ISP_BPR3__TG       0x1F040134,0xFF000000
+#define SRM_ISP_BPR3__TGF      0x1F040134,0x00FF0000
+#define SRM_ISP_BPR3__DKB      0x1F040134,0x0000FF00
+#define SRM_ISP_BPR3__TG2      0x1F040134,0x000000FF
+
+#define SRM_ISP_BPR4__ADDR                  0x1F040138
+#define SRM_ISP_BPR4__EMPTY      0x1F040138,0x00000000
+#define SRM_ISP_BPR4__FULL      0x1F040138,0xffffffff
+#define SRM_ISP_BPR4__DKRCL      0x1F040138,0xFF000000
+#define SRM_ISP_BPR4__TGFCL      0x1F040138,0x00FF0000
+#define SRM_ISP_BPR4__TCL2      0x1F040138,0x0000FF00
+#define SRM_ISP_BPR4__TCL      0x1F040138,0x000000FF
+
+#define SRM_ISP_BPR5__ADDR                  0x1F04013C
+#define SRM_ISP_BPR5__EMPTY      0x1F04013C,0x00000000
+#define SRM_ISP_BPR5__FULL      0x1F04013C,0xffffffff
+#define SRM_ISP_BPR5__TGL2  0x1E010024,0x0000FF00
+#define SRM_ISP_BPR5__TBC      0x1F04013C,0x000000FF
+
+#define SRM_ISP_CCMLIN0__ADDR                  0x1F040140
+#define SRM_ISP_CCMLIN0__EMPTY      0x1F040140,0x00000000
+#define SRM_ISP_CCMLIN0__FULL      0x1F040140,0xffffffff
+#define SRM_ISP_CCMLIN0__CCMLIN12      0x1F040140,0x7C000000
+#define SRM_ISP_CCMLIN0__CCMLIN11      0x1F040140,0x03E00000
+#define SRM_ISP_CCMLIN0__CCMLIN10      0x1F040140,0x001F0000
+#define SRM_ISP_CCMLIN0__CCMLIN02      0x1F040140,0x00007C00
+#define SRM_ISP_CCMLIN0__CCMLIN01      0x1F040140,0x000003E0
+#define SRM_ISP_CCMLIN0__CCMLIN00      0x1F040140,0x0000001F
+
+#define SRM_ISP_CCMLIN1__ADDR                  0x1F040144
+#define SRM_ISP_CCMLIN1__EMPTY      0x1F040144,0x00000000
+#define SRM_ISP_CCMLIN1__FULL      0x1F040144,0xffffffff
+#define SRM_ISP_CCMLIN1__CCMLIN22      0x1F040144,0x00007C00
+#define SRM_ISP_CCMLIN1__CCMLIN21      0x1F040144,0x000003E0
+#define SRM_ISP_CCMLIN1__CCMLIN20      0x1F040144,0x0000001F
+
+#define SRM_ISP_CG_0__ADDR                  0x1F040148
+#define SRM_ISP_CG_0__EMPTY      0x1F040148,0x00000000
+#define SRM_ISP_CG_0__FULL      0x1F040148,0xffffffff
+#define SRM_ISP_CG_0__BGAIN      0x1F040148,0xFF000000
+#define SRM_ISP_CG_0__GBGAIN      0x1F040148,0x00FF0000
+#define SRM_ISP_CG_0__GRGAIN      0x1F040148,0x0000FF00
+#define SRM_ISP_CG_0__RGAIN      0x1F040148,0x000000FF
+
+#define SRM_ISP_CG_1__ADDR                  0x1F04014C
+#define SRM_ISP_CG_1__EMPTY      0x1F04014C,0x00000000
+#define SRM_ISP_CG_1__FULL      0x1F04014C,0xffffffff
+#define SRM_ISP_CG_1__BSHIFT      0x1F04014C,0x00000030
+#define SRM_ISP_CG_1__GSHIFT      0x1F04014C,0x0000000C
+#define SRM_ISP_CG_1__RSHIFT      0x1F04014C,0x00000003
+
+#define SRM_ISP_ROC_0__ADDR                  0x1F040150
+#define SRM_ISP_ROC_0__EMPTY      0x1F040150,0x00000000
+#define SRM_ISP_ROC_0__FULL      0x1F040150,0xffffffff
+#define SRM_ISP_ROC_0__CROC_Q_BLIN      0x1F040150,0x01C00000
+#define SRM_ISP_ROC_0__CROC_Q_GLIN      0x1F040150,0x00380000
+#define SRM_ISP_ROC_0__CROC_Q_RLIN      0x1F040150,0x00070000
+#define SRM_ISP_ROC_0__CROC_SH_QR      0x1F040150,0x00007000
+#define SRM_ISP_ROC_0__CROC_SH_QRGB      0x1F040150,0x00000E00
+#define SRM_ISP_ROC_0__CROC_SH_QB      0x1F040150,0x000001C0
+#define SRM_ISP_ROC_0__CROC_R_APP      0x1F040150,0x00000030
+#define SRM_ISP_ROC_0__CROC_G_APP      0x1F040150,0x0000000C
+#define SRM_ISP_ROC_0__CROC_B_APP      0x1F040150,0x00000003
+
+#define SRM_ISP_ROC_1__ADDR                  0x1F040154
+#define SRM_ISP_ROC_1__EMPTY      0x1F040154,0x00000000
+#define SRM_ISP_ROC_1__FULL      0x1F040154,0xffffffff
+#define SRM_ISP_ROC_1__CROC_MYB              0x1F040154,0xFF000000
+#define SRM_ISP_ROC_1__CROC_MXB              0x1F040154,0x00FF0000
+#define SRM_ISP_ROC_1__CROC_MYG              0x1F040154,0x0000FF00
+#define SRM_ISP_ROC_1__CROC_MXG              0x1F040154,0x000000FF
+
+#define SRM_ISP_ROC_2__ADDR                  0x1F040158
+#define SRM_ISP_ROC_2__EMPTY      0x1F040158,0x00000000
+#define SRM_ISP_ROC_2__FULL      0x1F040158,0xffffffff
+#define SRM_ISP_ROC_2__CROC_MYR              0x1F040158,0x0000FF00
+#define SRM_ISP_ROC_2__CROC_MXR              0x1F040158,0x000000FF
+
+#define SRM_ISP_RROC_0__ADDR                  0x1F04015C
+#define SRM_ISP_RROC_0__EMPTY      0x1F04015C,0x00000000
+#define SRM_ISP_RROC_0__FULL      0x1F04015C,0xffffffff
+#define SRM_ISP_RROC_0__CROC_RC1       0x1F04015C,0x07FF0000
+#define SRM_ISP_RROC_0__CROC_RC0       0x1F04015C,0x000007FF
+
+#define SRM_ISP_RROC_1__ADDR                  0x1F040160
+#define SRM_ISP_RROC_1__EMPTY      0x1F040160,0x00000000
+#define SRM_ISP_RROC_1__FULL      0x1F040160,0xffffffff
+#define SRM_ISP_RROC_1__CROC_RC3       0x1F040160,0x07FF0000
+#define SRM_ISP_RROC_1__CROC_RC2       0x1F040160,0x000007FF
+
+#define SRM_ISP_RROC_2__ADDR                  0x1F040164
+#define SRM_ISP_RROC_2__EMPTY      0x1F040164,0x00000000
+#define SRM_ISP_RROC_2__FULL      0x1F040164,0xffffffff
+#define SRM_ISP_RROC_2__CROC_RC5       0x1F040164,0x07FF0000
+#define SRM_ISP_RROC_2__CROC_RC4       0x1F040164,0x000007FF
+
+#define SRM_ISP_RROC_3__ADDR                  0x1F040168
+#define SRM_ISP_RROC_3__EMPTY      0x1F040168,0x00000000
+#define SRM_ISP_RROC_3__FULL      0x1F040168,0xffffffff
+#define SRM_ISP_RROC_3__CROC_RC7       0x1F040168,0x07FF0000
+#define SRM_ISP_RROC_3__CROC_RC6       0x1F040168,0x000007FF
+
+#define SRM_ISP_RROC_4__ADDR                  0x1F04016C
+#define SRM_ISP_RROC_4__EMPTY      0x1F04016C,0x00000000
+#define SRM_ISP_RROC_4__FULL      0x1F04016C,0xffffffff
+#define SRM_ISP_RROC_4__CROC_RC9       0x1F04016C,0x07FF0000
+#define SRM_ISP_RROC_4__CROC_RC8       0x1F04016C,0x000007FF
+
+#define SRM_ISP_RROC_5__ADDR                  0x1F040170
+#define SRM_ISP_RROC_5__EMPTY      0x1F040170,0x00000000
+#define SRM_ISP_RROC_5__FULL      0x1F040170,0xffffffff
+#define SRM_ISP_RROC_5__CROC_RC11      0x1F040170,0x07FF0000
+#define SRM_ISP_RROC_5__CROC_RC10      0x1F040170,0x000007FF
+
+#define SRM_ISP_RROC_6__ADDR                  0x1F040174
+#define SRM_ISP_RROC_6__EMPTY      0x1F040174,0x00000000
+#define SRM_ISP_RROC_6__FULL      0x1F040174,0xffffffff
+#define SRM_ISP_RROC_6__CROC_RC13      0x1F040174,0x07FF0000
+#define SRM_ISP_RROC_6__CROC_RC12      0x1F040174,0x000007FF
+
+#define SRM_ISP_RROC_7__ADDR                  0x1F040178
+#define SRM_ISP_RROC_7__EMPTY      0x1F040178,0x00000000
+#define SRM_ISP_RROC_7__FULL      0x1F040178,0xffffffff
+#define SRM_ISP_RROC_7__CROC_RC15      0x1F040178,0x07FF0000
+#define SRM_ISP_RROC_7__CROC_RC14      0x1F040178,0x000007FF
+
+#define SRM_ISP_RROS_0__ADDR                  0x1F04017C
+#define SRM_ISP_RROS_0__EMPTY      0x1F04017C,0x00000000
+#define SRM_ISP_RROS_0__FULL      0x1F04017C,0xffffffff
+#define SRM_ISP_RROS_0__CROC_RS3       0x1F04017C,0x7F000000
+#define SRM_ISP_RROS_0__CROC_RS2       0x1F04017C,0x007F0000
+#define SRM_ISP_RROS_0__CROC_RS1       0x1F04017C,0x00007F00
+#define SRM_ISP_RROS_0__CROC_RS0       0x1F04017C,0x0000007F
+
+#define SRM_ISP_RROS_1__ADDR                  0x1F040180
+#define SRM_ISP_RROS_1__EMPTY      0x1F040180,0x00000000
+#define SRM_ISP_RROS_1__FULL      0x1F040180,0xffffffff
+#define SRM_ISP_RROS_1__CROC_RS7       0x1F040180,0x7F000000
+#define SRM_ISP_RROS_1__CROC_RS6       0x1F040180,0x007F0000
+#define SRM_ISP_RROS_1__CROC_RS5       0x1F040180,0x00007F00
+#define SRM_ISP_RROS_1__CROC_RS4       0x1F040180,0x0000007F
+
+#define SRM_ISP_RROS_2__ADDR                  0x1F040184
+#define SRM_ISP_RROS_2__EMPTY      0x1F040184,0x00000000
+#define SRM_ISP_RROS_2__FULL      0x1F040184,0xffffffff
+#define SRM_ISP_RROS_2__CROC_RS11      0x1F040184,0x7F000000
+#define SRM_ISP_RROS_2__CROC_RS10      0x1F040184,0x007F0000
+#define SRM_ISP_RROS_2__CROC_RS9       0x1F040184,0x00007F00
+#define SRM_ISP_RROS_2__CROC_RS8       0x1F040184,0x0000007F
+
+#define SRM_ISP_RROS_3__ADDR                  0x1F040188
+#define SRM_ISP_RROS_3__EMPTY      0x1F040188,0x00000000
+#define SRM_ISP_RROS_3__FULL      0x1F040188,0xffffffff
+#define SRM_ISP_RROS_3__CROC_RS15      0x1F040188,0x7F000000
+#define SRM_ISP_RROS_3__CROC_RS14      0x1F040188,0x007F0000
+#define SRM_ISP_RROS_3__CROC_RS13      0x1F040188,0x00007F00
+#define SRM_ISP_RROS_3__CROC_RS12      0x1F040188,0x0000007F
+
+#define SRM_ISP_GROC_0__ADDR                  0x1F04018C
+#define SRM_ISP_GROC_0__EMPTY      0x1F04018C,0x00000000
+#define SRM_ISP_GROC_0__FULL      0x1F04018C,0xffffffff
+#define SRM_ISP_GROC_0__CROC_GC1       0x1F04018C,0x07FF0000
+#define SRM_ISP_GROC_0__CROC_GC0       0x1F04018C,0x000007FF
+
+#define SRM_ISP_GROC_1__ADDR                  0x1F040190
+#define SRM_ISP_GROC_1__EMPTY      0x1F040190,0x00000000
+#define SRM_ISP_GROC_1__FULL      0x1F040190,0xffffffff
+#define SRM_ISP_GROC_1__CROC_GC3       0x1F040190,0x07FF0000
+#define SRM_ISP_GROC_1__CROC_GC2       0x1F040190,0x000007FF
+
+#define SRM_ISP_GROC_2__ADDR                  0x1F040194
+#define SRM_ISP_GROC_2__EMPTY      0x1F040194,0x00000000
+#define SRM_ISP_GROC_2__FULL      0x1F040194,0xffffffff
+#define SRM_ISP_GROC_2__CROC_GC5       0x1F040194,0x07FF0000
+#define SRM_ISP_GROC_2__CROC_GC4       0x1F040194,0x000007FF
+
+#define SRM_ISP_GROC_3__ADDR                  0x1F040198
+#define SRM_ISP_GROC_3__EMPTY      0x1F040198,0x00000000
+#define SRM_ISP_GROC_3__FULL      0x1F040198,0xffffffff
+#define SRM_ISP_GROC_3__CROC_GC7       0x1F040198,0x07FF0000
+#define SRM_ISP_GROC_3__CROC_GC6       0x1F040198,0x000007FF
+
+#define SRM_ISP_GROC_4__ADDR                  0x1F04019C
+#define SRM_ISP_GROC_4__EMPTY      0x1F04019C,0x00000000
+#define SRM_ISP_GROC_4__FULL      0x1F04019C,0xffffffff
+#define SRM_ISP_GROC_4__CROC_GC9       0x1F04019C,0x07FF0000
+#define SRM_ISP_GROC_4__CROC_GC8       0x1F04019C,0x000007FF
+
+#define SRM_ISP_GROC_5__ADDR                  0x1F0401A0
+#define SRM_ISP_GROC_5__EMPTY      0x1F0401A0,0x00000000
+#define SRM_ISP_GROC_5__FULL      0x1F0401A0,0xffffffff
+#define SRM_ISP_GROC_5__CROC_GC11      0x1F0401A0,0x07FF0000
+#define SRM_ISP_GROC_5__CROC_GC10      0x1F0401A0,0x000007FF
+
+#define SRM_ISP_GROC_6__ADDR                  0x1F0401A4
+#define SRM_ISP_GROC_6__EMPTY      0x1F0401A4,0x00000000
+#define SRM_ISP_GROC_6__FULL      0x1F0401A4,0xffffffff
+#define SRM_ISP_GROC_6__CROC_GC13      0x1F0401A4,0x07FF0000
+#define SRM_ISP_GROC_6__CROC_GC12      0x1F0401A4,0x000007FF
+
+#define SRM_ISP_GROC_7__ADDR                  0x1F0401A8
+#define SRM_ISP_GROC_7__EMPTY      0x1F0401A8,0x00000000
+#define SRM_ISP_GROC_7__FULL      0x1F0401A8,0xffffffff
+#define SRM_ISP_GROC_7__CROC_GC15      0x1F0401A8,0x07FF0000
+#define SRM_ISP_GROC_7__CROC_GC14      0x1F0401A8,0x000007FF
+
+#define SRM_ISP_GROS_0__ADDR                  0x1F0401AC
+#define SRM_ISP_GROS_0__EMPTY      0x1F0401AC,0x00000000
+#define SRM_ISP_GROS_0__FULL      0x1F0401AC,0xffffffff
+#define SRM_ISP_GROS_0__CROC_GS3       0x1F0401AC,0x7F000000
+#define SRM_ISP_GROS_0__CROC_GS2       0x1F0401AC,0x007F0000
+#define SRM_ISP_GROS_0__CROC_GS1       0x1F0401AC,0x00007F00
+#define SRM_ISP_GROS_0__CROC_GS0       0x1F0401AC,0x0000007F
+
+#define SRM_ISP_GROS_1__ADDR                  0x1F0401B0
+#define SRM_ISP_GROS_1__EMPTY      0x1F0401B0,0x00000000
+#define SRM_ISP_GROS_1__FULL      0x1F0401B0,0xffffffff
+#define SRM_ISP_GROS_1__CROC_GS7       0x1F0401B0,0x7F000000
+#define SRM_ISP_GROS_1__CROC_GS6       0x1F0401B0,0x007F0000
+#define SRM_ISP_GROS_1__CROC_GS5       0x1F0401B0,0x00007F00
+#define SRM_ISP_GROS_1__CROC_GS4       0x1F0401B0,0x0000007F
+
+#define SRM_ISP_GROS_2__ADDR                  0x1F0401B4
+#define SRM_ISP_GROS_2__EMPTY      0x1F0401B4,0x00000000
+#define SRM_ISP_GROS_2__FULL      0x1F0401B4,0xffffffff
+#define SRM_ISP_GROS_2__CROC_GS11      0x1F0401B4,0x7F000000
+#define SRM_ISP_GROS_2__CROC_GS10      0x1F0401B4,0x007F0000
+#define SRM_ISP_GROS_2__CROC_GS9       0x1F0401B4,0x00007F00
+#define SRM_ISP_GROS_2__CROC_GS8       0x1F0401B4,0x0000007F
+
+#define SRM_ISP_GROS_3__ADDR                  0x1F0401B8
+#define SRM_ISP_GROS_3__EMPTY      0x1F0401B8,0x00000000
+#define SRM_ISP_GROS_3__FULL      0x1F0401B8,0xffffffff
+#define SRM_ISP_GROS_3__CROC_GS15      0x1F0401B8,0x7F000000
+#define SRM_ISP_GROS_3__CROC_GS14      0x1F0401B8,0x007F0000
+#define SRM_ISP_GROS_3__CROC_GS13      0x1F0401B8,0x00007F00
+#define SRM_ISP_GROS_3__CROC_GS12      0x1F0401B8,0x0000007F
+
+#define SRM_ISP_BROC_0__ADDR                  0x1F0401BC
+#define SRM_ISP_BROC_0__EMPTY      0x1F0401BC,0x00000000
+#define SRM_ISP_BROC_0__FULL      0x1F0401BC,0xffffffff
+#define SRM_ISP_BROC_0__CROC_BC1       0x1F0401BC,0x07FF0000
+#define SRM_ISP_BROC_0__CROC_BC0       0x1F0401BC,0x000007FF
+
+#define SRM_ISP_BROC_1__ADDR                  0x1F0401C0
+#define SRM_ISP_BROC_1__EMPTY      0x1F0401C0,0x00000000
+#define SRM_ISP_BROC_1__FULL      0x1F0401C0,0xffffffff
+#define SRM_ISP_BROC_1__CROC_BC3       0x1F0401C0,0x07FF0000
+#define SRM_ISP_BROC_1__CROC_BC2       0x1F0401C0,0x000007FF
+
+#define SRM_ISP_BROC_2__ADDR                  0x1F0401C4
+#define SRM_ISP_BROC_2__EMPTY      0x1F0401C4,0x00000000
+#define SRM_ISP_BROC_2__FULL      0x1F0401C4,0xffffffff
+#define SRM_ISP_BROC_2__CROC_BC5       0x1F0401C4,0x07FF0000
+#define SRM_ISP_BROC_2__CROC_BC4       0x1F0401C4,0x000007FF
+
+#define SRM_ISP_BROC_3__ADDR                  0x1F0401C8
+#define SRM_ISP_BROC_3__EMPTY      0x1F0401C8,0x00000000
+#define SRM_ISP_BROC_3__FULL      0x1F0401C8,0xffffffff
+#define SRM_ISP_BROC_3__CROC_BC7       0x1F0401C8,0x07FF0000
+#define SRM_ISP_BROC_3__CROC_BC6       0x1F0401C8,0x000007FF
+
+#define SRM_ISP_BROC_4__ADDR                  0x1F0401CC
+#define SRM_ISP_BROC_4__EMPTY      0x1F0401CC,0x00000000
+#define SRM_ISP_BROC_4__FULL      0x1F0401CC,0xffffffff
+#define SRM_ISP_BROC_4__CROC_BC9       0x1F0401CC,0x07FF0000
+#define SRM_ISP_BROC_4__CROC_BC8       0x1F0401CC,0x000007FF
+
+#define SRM_ISP_BROC_5__ADDR                  0x1F0401D0
+#define SRM_ISP_BROC_5__EMPTY      0x1F0401D0,0x00000000
+#define SRM_ISP_BROC_5__FULL      0x1F0401D0,0xffffffff
+#define SRM_ISP_BROC_5__CROC_BC11      0x1F0401D0,0x07FF0000
+#define SRM_ISP_BROC_5__CROC_BC10      0x1F0401D0,0x000007FF
+
+#define SRM_ISP_BROC_6__ADDR                  0x1F0401D4
+#define SRM_ISP_BROC_6__EMPTY      0x1F0401D4,0x00000000
+#define SRM_ISP_BROC_6__FULL      0x1F0401D4,0xffffffff
+#define SRM_ISP_BROC_6__CROC_BC13      0x1F0401D4,0x07FF0000
+#define SRM_ISP_BROC_6__CROC_BC12      0x1F0401D4,0x000007FF
+
+#define SRM_ISP_BROC_7__ADDR                  0x1F0401D8
+#define SRM_ISP_BROC_7__EMPTY      0x1F0401D8,0x00000000
+#define SRM_ISP_BROC_7__FULL      0x1F0401D8,0xffffffff
+#define SRM_ISP_BROC_7__CROC_BC15      0x1F0401D8,0x07FF0000
+#define SRM_ISP_BROC_7__CROC_BC14      0x1F0401D8,0x000007FF
+
+#define SRM_ISP_BROS_0__ADDR                  0x1F0401DC
+#define SRM_ISP_BROS_0__EMPTY      0x1F0401DC,0x00000000
+#define SRM_ISP_BROS_0__FULL      0x1F0401DC,0xffffffff
+#define SRM_ISP_BROS_0__CROC_BS3       0x1F0401DC,0x7F000000
+#define SRM_ISP_BROS_0__CROC_BS2       0x1F0401DC,0x007F0000
+#define SRM_ISP_BROS_0__CROC_BS1       0x1F0401DC,0x00007F00
+#define SRM_ISP_BROS_0__CROC_BS0       0x1F0401DC,0x0000007F
+
+#define SRM_ISP_BROS_1__ADDR                  0x1F0401E0
+#define SRM_ISP_BROS_1__EMPTY      0x1F0401E0,0x00000000
+#define SRM_ISP_BROS_1__FULL      0x1F0401E0,0xffffffff
+#define SRM_ISP_BROS_1__CROC_BS7       0x1F0401E0,0x7F000000
+#define SRM_ISP_BROS_1__CROC_BS6       0x1F0401E0,0x007F0000
+#define SRM_ISP_BROS_1__CROC_BS5       0x1F0401E0,0x00007F00
+#define SRM_ISP_BROS_1__CROC_BS4       0x1F0401E0,0x0000007F
+
+#define SRM_ISP_BROS_2__ADDR                  0x1F0401E4
+#define SRM_ISP_BROS_2__EMPTY      0x1F0401E4,0x00000000
+#define SRM_ISP_BROS_2__FULL      0x1F0401E4,0xffffffff
+#define SRM_ISP_BROS_2__CROC_BS11      0x1F0401E4,0x7F000000
+#define SRM_ISP_BROS_2__CROC_BS10      0x1F0401E4,0x007F0000
+#define SRM_ISP_BROS_2__CROC_BS9       0x1F0401E4,0x00007F00
+#define SRM_ISP_BROS_2__CROC_BS8       0x1F0401E4,0x0000007F
+
+#define SRM_ISP_BROS_3__ADDR                  0x1F0401E8
+#define SRM_ISP_BROS_3__EMPTY      0x1F0401E8,0x00000000
+#define SRM_ISP_BROS_3__FULL      0x1F0401E8,0xffffffff
+#define SRM_ISP_BROS_3__CROC_BS15      0x1F0401E8,0x7F000000
+#define SRM_ISP_BROS_3__CROC_BS14      0x1F0401E8,0x007F0000
+#define SRM_ISP_BROS_3__CROC_BS13      0x1F0401E8,0x00007F00
+#define SRM_ISP_BROS_3__CROC_BS12      0x1F0401E8,0x0000007F
+
+#define SRM_ISP_GAMMA_C_0__ADDR                          0x1F0401EC
+#define SRM_ISP_GAMMA_C_0__EMPTY       0x1F0401EC,0x00000000
+#define SRM_ISP_GAMMA_C_0__FULL              0x1F0401EC,0xffffffff
+#define SRM_ISP_GAMMA_C_0__GAMMA_C1      0x1F0401EC,0x01FF0000
+#define SRM_ISP_GAMMA_C_0__GAMMA_C0      0x1F0401EC,0x000001FF
+
+#define SRM_ISP_GAMMA_C_1__ADDR                          0x1F0401F0
+#define SRM_ISP_GAMMA_C_1__EMPTY       0x1F0401F0,0x00000000
+#define SRM_ISP_GAMMA_C_1__FULL              0x1F0401F0,0xffffffff
+#define SRM_ISP_GAMMA_C_1__GAMMA_C3      0x1F0401F0,0x01FF0000
+#define SRM_ISP_GAMMA_C_1__GAMMA_C2      0x1F0401F0,0x000001FF
+
+#define SRM_ISP_GAMMA_C_2__ADDR                          0x1F0401F4
+#define SRM_ISP_GAMMA_C_2__EMPTY       0x1F0401F4,0x00000000
+#define SRM_ISP_GAMMA_C_2__FULL              0x1F0401F4,0xffffffff
+#define SRM_ISP_GAMMA_C_2__GAMMA_C5      0x1F0401F4,0x01FF0000
+#define SRM_ISP_GAMMA_C_2__GAMMA_C4      0x1F0401F4,0x000001FF
+
+#define SRM_ISP_GAMMA_C_3__ADDR                          0x1F0401F8
+#define SRM_ISP_GAMMA_C_3__EMPTY       0x1F0401F8,0x00000000
+#define SRM_ISP_GAMMA_C_3__FULL              0x1F0401F8,0xffffffff
+#define SRM_ISP_GAMMA_C_3__GAMMA_C7      0x1F0401F8,0x01FF0000
+#define SRM_ISP_GAMMA_C_3__GAMMA_C6      0x1F0401F8,0x000001FF
+
+#define SRM_ISP_GAMMA_C_4__ADDR                          0x1F0401FC
+#define SRM_ISP_GAMMA_C_4__EMPTY       0x1F0401FC,0x00000000
+#define SRM_ISP_GAMMA_C_4__FULL              0x1F0401FC,0xffffffff
+#define SRM_ISP_GAMMA_C_4__GAMMA_C9      0x1F0401FC,0x01FF0000
+#define SRM_ISP_GAMMA_C_4__GAMMA_C8      0x1F0401FC,0x000001FF
+
+#define SRM_ISP_GAMMA_C_5__ADDR                          0x1F040200
+#define SRM_ISP_GAMMA_C_5__EMPTY       0x1F040200,0x00000000
+#define SRM_ISP_GAMMA_C_5__FULL              0x1F040200,0xffffffff
+#define SRM_ISP_GAMMA_C_5__GAMMA_C11      0x1F040200,0x01FF0000
+#define SRM_ISP_GAMMA_C_5__GAMMA_C10      0x1F040200,0x000001FF
+
+#define SRM_ISP_GAMMA_C_6__ADDR                          0x1F040204
+#define SRM_ISP_GAMMA_C_6__EMPTY       0x1F040204,0x00000000
+#define SRM_ISP_GAMMA_C_6__FULL              0x1F040204,0xffffffff
+#define SRM_ISP_GAMMA_C_6__GAMMA_C13      0x1F040204,0x01FF0000
+#define SRM_ISP_GAMMA_C_6__GAMMA_C12      0x1F040204,0x000001FF
+
+#define SRM_ISP_GAMMA_C_7__ADDR                          0x1F040208
+#define SRM_ISP_GAMMA_C_7__EMPTY       0x1F040208,0x00000000
+#define SRM_ISP_GAMMA_C_7__FULL              0x1F040208,0xffffffff
+#define SRM_ISP_GAMMA_C_7__GAMMA_C15      0x1F040208,0x01FF0000
+#define SRM_ISP_GAMMA_C_7__GAMMA_C14      0x1F040208,0x000001FF
+
+#define SRM_ISP_GAMMA_S_0__ADDR                          0x1F04020C
+#define SRM_ISP_GAMMA_S_0__EMPTY       0x1F04020C,0x00000000
+#define SRM_ISP_GAMMA_S_0__FULL              0x1F04020C,0xffffffff
+#define SRM_ISP_GAMMA_S_0__GAMMA_S3      0x1F04020C,0xFF000000
+#define SRM_ISP_GAMMA_S_0__GAMMA_S2      0x1F04020C,0x00FF0000
+#define SRM_ISP_GAMMA_S_0__GAMMA_S1      0x1F04020C,0x0000FF00
+#define SRM_ISP_GAMMA_S_0__GAMMA_S0      0x1F04020C,0x000000FF
+
+#define SRM_ISP_GAMMA_S_1__ADDR                          0x1F040210
+#define SRM_ISP_GAMMA_S_1__EMPTY       0x1F040210,0x00000000
+#define SRM_ISP_GAMMA_S_1__FULL              0x1F040210,0xffffffff
+#define SRM_ISP_GAMMA_S_1__GAMMA_S7      0x1F040210,0xFF000000
+#define SRM_ISP_GAMMA_S_1__GAMMA_S6      0x1F040210,0x00FF0000
+#define SRM_ISP_GAMMA_S_1__GAMMA_S5      0x1F040210,0x0000FF00
+#define SRM_ISP_GAMMA_S_1__GAMMA_S4      0x1F040210,0x000000FF
+
+#define SRM_ISP_GAMMA_S_2__ADDR                          0x1F040214
+#define SRM_ISP_GAMMA_S_2__EMPTY       0x1F040214,0x00000000
+#define SRM_ISP_GAMMA_S_2__FULL              0x1F040214,0xffffffff
+#define SRM_ISP_GAMMA_S_2__GAMMA_S11      0x1F040214,0xFF000000
+#define SRM_ISP_GAMMA_S_2__GAMMA_S10      0x1F040214,0x00FF0000
+#define SRM_ISP_GAMMA_S_2__GAMMA_S9      0x1F040214,0x0000FF00
+#define SRM_ISP_GAMMA_S_2__GAMMA_S8      0x1F040214,0x000000FF
+
+#define SRM_ISP_GAMMA_S_3__ADDR                          0x1F040218
+#define SRM_ISP_GAMMA_S_3__EMPTY       0x1F040218,0x00000000
+#define SRM_ISP_GAMMA_S_3__FULL              0x1F040218,0xffffffff
+#define SRM_ISP_GAMMA_S_3__GAMMA_S15      0x1F040218,0xFF000000
+#define SRM_ISP_GAMMA_S_3__GAMMA_S14      0x1F040218,0x00FF0000
+#define SRM_ISP_GAMMA_S_3__GAMMA_S13      0x1F040218,0x0000FF00
+#define SRM_ISP_GAMMA_S_3__GAMMA_S12      0x1F040218,0x000000FF
+
+#define SRM_ISP_CSCA_0__ADDR                  0x1F04021C
+#define SRM_ISP_CSCA_0__EMPTY      0x1F04021C,0x00000000
+#define SRM_ISP_CSCA_0__FULL      0x1F04021C,0xffffffff
+#define SRM_ISP_CSCA_0__CSC_A1      0x1F04021C,0x03FF0000
+#define SRM_ISP_CSCA_0__CSC_A0      0x1F04021C,0x000003FF
+
+#define SRM_ISP_CSCA_1__ADDR                  0x1F040220
+#define SRM_ISP_CSCA_1__EMPTY      0x1F040220,0x00000000
+#define SRM_ISP_CSCA_1__FULL      0x1F040220,0xffffffff
+#define SRM_ISP_CSCA_1__CSC_A3      0x1F040220,0x03FF0000
+#define SRM_ISP_CSCA_1__CSC_A2      0x1F040220,0x000003FF
+
+#define SRM_ISP_CSCA_2__ADDR                  0x1F040224
+#define SRM_ISP_CSCA_2__EMPTY      0x1F040224,0x00000000
+#define SRM_ISP_CSCA_2__FULL      0x1F040224,0xffffffff
+#define SRM_ISP_CSCA_2__CSC_A5      0x1F040224,0x03FF0000
+#define SRM_ISP_CSCA_2__CSC_A4      0x1F040224,0x000003FF
+
+#define SRM_ISP_CSCA_3__ADDR                  0x1F040228
+#define SRM_ISP_CSCA_3__EMPTY      0x1F040228,0x00000000
+#define SRM_ISP_CSCA_3__FULL      0x1F040228,0xffffffff
+#define SRM_ISP_CSCA_3__CSC_A7      0x1F040228,0x03FF0000
+#define SRM_ISP_CSCA_3__CSC_A6      0x1F040228,0x000003FF
+
+#define SRM_ISP_CSC_0__ADDR                  0x1F04022C
+#define SRM_ISP_CSC_0__EMPTY      0x1F04022C,0x00000000
+#define SRM_ISP_CSC_0__FULL      0x1F04022C,0xffffffff
+#define SRM_ISP_CSC_0__CSC_S0      0x1F04022C,0xC0000000
+#define SRM_ISP_CSC_0__CSC_B0      0x1F04022C,0x3FFF0000
+#define SRM_ISP_CSC_0__CSC_A8      0x1F04022C,0x000003FF
+
+#define SRM_ISP_CSC_1__ADDR                  0x1F040230
+#define SRM_ISP_CSC_1__EMPTY      0x1F040230,0x00000000
+#define SRM_ISP_CSC_1__FULL      0x1F040230,0xffffffff
+#define SRM_ISP_CSC_1__CSC_S2      0x1F040230,0xC0000000
+#define SRM_ISP_CSC_1__CSC_B2      0x1F040230,0x3FFF0000
+#define SRM_ISP_CSC_1__CSC_S1      0x1F040230,0x0000C000
+#define SRM_ISP_CSC_1__CSC_B1      0x1F040230,0x00003FFF
+
+#define SRM_ISP_CNS_C_0__ADDR                  0x1F040234
+#define SRM_ISP_CNS_C_0__EMPTY      0x1F040234,0x00000000
+#define SRM_ISP_CNS_C_0__FULL      0x1F040234,0xffffffff
+#define SRM_ISP_CNS_C_0__CNS_C1              0x1F040234,0x01FF0000
+#define SRM_ISP_CNS_C_0__CNS_C0              0x1F040234,0x000001FF
+
+#define SRM_ISP_CNS_C_1__ADDR                  0x1F040238
+#define SRM_ISP_CNS_C_1__EMPTY      0x1F040238,0x00000000
+#define SRM_ISP_CNS_C_1__FULL      0x1F040238,0xffffffff
+#define SRM_ISP_CNS_C_1__CNS_C3              0x1F040238,0x01FF0000
+#define SRM_ISP_CNS_C_1__CNS_C2              0x1F040238,0x000001FF
+
+#define SRM_ISP_CNS_C_2__ADDR                  0x1F04023C
+#define SRM_ISP_CNS_C_2__EMPTY      0x1F04023C,0x00000000
+#define SRM_ISP_CNS_C_2__FULL      0x1F04023C,0xffffffff
+#define SRM_ISP_CNS_C_2__CNS_C5              0x1F04023C,0x01FF0000
+#define SRM_ISP_CNS_C_2__CNS_C4              0x1F04023C,0x000001FF
+
+#define SRM_ISP_CNS_C_3__ADDR                  0x1F040240
+#define SRM_ISP_CNS_C_3__EMPTY      0x1F040240,0x00000000
+#define SRM_ISP_CNS_C_3__FULL      0x1F040240,0xffffffff
+#define SRM_ISP_CNS_C_3__CNS_C7              0x1F040240,0x01FF0000
+#define SRM_ISP_CNS_C_3__CNS_C6              0x1F040240,0x000001FF
+
+#define SRM_ISP_CNS_C_4__ADDR                  0x1F040244
+#define SRM_ISP_CNS_C_4__EMPTY      0x1F040244,0x00000000
+#define SRM_ISP_CNS_C_4__FULL      0x1F040244,0xffffffff
+#define SRM_ISP_CNS_C_4__CNS_C9              0x1F040244,0x01FF0000
+#define SRM_ISP_CNS_C_4__CNS_C8              0x1F040244,0x000001FF
+
+#define SRM_ISP_CNS_C_5__ADDR                  0x1F040248
+#define SRM_ISP_CNS_C_5__EMPTY      0x1F040248,0x00000000
+#define SRM_ISP_CNS_C_5__FULL      0x1F040248,0xffffffff
+#define SRM_ISP_CNS_C_5__CNS_C11       0x1F040248,0x01FF0000
+#define SRM_ISP_CNS_C_5__CNS_C10       0x1F040248,0x000001FF
+
+#define SRM_ISP_CNS_C_6__ADDR                  0x1F04024C
+#define SRM_ISP_CNS_C_6__EMPTY      0x1F04024C,0x00000000
+#define SRM_ISP_CNS_C_6__FULL      0x1F04024C,0xffffffff
+#define SRM_ISP_CNS_C_6__CNS_C13       0x1F04024C,0x01FF0000
+#define SRM_ISP_CNS_C_6__CNS_C12       0x1F04024C,0x000001FF
+
+#define SRM_ISP_CNS_C_7__ADDR                  0x1F040250
+#define SRM_ISP_CNS_C_7__EMPTY      0x1F040250,0x00000000
+#define SRM_ISP_CNS_C_7__FULL      0x1F040250,0xffffffff
+#define SRM_ISP_CNS_C_7__CNS_C15       0x1F040250,0x01FF0000
+#define SRM_ISP_CNS_C_7__CNS_C14       0x1F040250,0x000001FF
+
+#define SRM_ISP_CNS_S_0__ADDR                  0x1F040254
+#define SRM_ISP_CNS_S_0__EMPTY      0x1F040254,0x00000000
+#define SRM_ISP_CNS_S_0__FULL      0x1F040254,0xffffffff
+#define SRM_ISP_CNS_S_0__CNS_S3              0x1F040254,0xFF000000
+#define SRM_ISP_CNS_S_0__CNS_S2              0x1F040254,0x00FF0000
+#define SRM_ISP_CNS_S_0__CNS_S1              0x1F040254,0x0000FF00
+#define SRM_ISP_CNS_S_0__CNS_S0              0x1F040254,0x000000FF
+
+#define SRM_ISP_CNS_S_1__ADDR                  0x1F040258
+#define SRM_ISP_CNS_S_1__EMPTY      0x1F040258,0x00000000
+#define SRM_ISP_CNS_S_1__FULL      0x1F040258,0xffffffff
+#define SRM_ISP_CNS_S_1__CNS_S7              0x1F040258,0xFF000000
+#define SRM_ISP_CNS_S_1__CNS_S6              0x1F040258,0x00FF0000
+#define SRM_ISP_CNS_S_1__CNS_S5              0x1F040258,0x0000FF00
+#define SRM_ISP_CNS_S_1__CNS_S4              0x1F040258,0x000000FF
+
+#define SRM_ISP_CNS_S_2__ADDR                  0x1F04025C
+#define SRM_ISP_CNS_S_2__EMPTY      0x1F04025C,0x00000000
+#define SRM_ISP_CNS_S_2__FULL      0x1F04025C,0xffffffff
+#define SRM_ISP_CNS_S_2__CNS_S11       0x1F04025C,0xFF000000
+#define SRM_ISP_CNS_S_2__CNS_S10       0x1F04025C,0x00FF0000
+#define SRM_ISP_CNS_S_2__CNS_S9              0x1F04025C,0x0000FF00
+#define SRM_ISP_CNS_S_2__CNS_S8              0x1F04025C,0x000000FF
+
+#define SRM_ISP_CNS_S_3__ADDR                  0x1F040260
+#define SRM_ISP_CNS_S_3__EMPTY      0x1F040260,0x00000000
+#define SRM_ISP_CNS_S_3__FULL      0x1F040260,0xffffffff
+#define SRM_ISP_CNS_S_3__CNS_S15       0x1F040260,0xFF000000
+#define SRM_ISP_CNS_S_3__CNS_S14       0x1F040260,0x00FF0000
+#define SRM_ISP_CNS_S_3__CNS_S13       0x1F040260,0x0000FF00
+#define SRM_ISP_CNS_S_3__CNS_S12       0x1F040260,0x000000FF
+
+#define SRM_ISP_MTF_ROC_C_0__ADDR                  0x1F040264
+#define SRM_ISP_MTF_ROC_C_0__EMPTY      0x1F040264,0x00000000
+#define SRM_ISP_MTF_ROC_C_0__FULL      0x1F040264,0xffffffff
+#define SRM_ISP_MTF_ROC_C_0__MTF_ROC_C1              0x1F040264,0x01FF0000
+#define SRM_ISP_MTF_ROC_C_0__MTF_ROC_C0              0x1F040264,0x000001FF
+
+#define SRM_ISP_MTF_ROC_C_1__ADDR                  0x1F040268
+#define SRM_ISP_MTF_ROC_C_1__EMPTY      0x1F040268,0x00000000
+#define SRM_ISP_MTF_ROC_C_1__FULL      0x1F040268,0xffffffff
+#define SRM_ISP_MTF_ROC_C_1__MTF_ROC_C3              0x1F040268,0x01FF0000
+#define SRM_ISP_MTF_ROC_C_1__MTF_ROC_C2              0x1F040268,0x000001FF
+
+#define SRM_ISP_MTF_ROC_C_2__ADDR                  0x1F04026C
+#define SRM_ISP_MTF_ROC_C_2__EMPTY      0x1F04026C,0x00000000
+#define SRM_ISP_MTF_ROC_C_2__FULL      0x1F04026C,0xffffffff
+#define SRM_ISP_MTF_ROC_C_2__MTF_ROC_C5              0x1F04026C,0x01FF0000
+#define SRM_ISP_MTF_ROC_C_2__MTF_ROC_C4              0x1F04026C,0x000001FF
+
+#define SRM_ISP_MTF_ROC_C_3__ADDR                  0x1F040270
+#define SRM_ISP_MTF_ROC_C_3__EMPTY      0x1F040270,0x00000000
+#define SRM_ISP_MTF_ROC_C_3__FULL      0x1F040270,0xffffffff
+#define SRM_ISP_MTF_ROC_C_3__MTF_ROC_C7              0x1F040270,0x01FF0000
+#define SRM_ISP_MTF_ROC_C_3__MTF_ROC_C6              0x1F040270,0x000001FF
+
+#define SRM_ISP_MTF_ROC_S_0__ADDR                  0x1F040274
+#define SRM_ISP_MTF_ROC_S_0__EMPTY      0x1F040274,0x00000000
+#define SRM_ISP_MTF_ROC_S_0__FULL      0x1F040274,0xffffffff
+#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S3              0x1F040274,0xFF000000
+#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S2              0x1F040274,0x00FF0000
+#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S1              0x1F040274,0x0000FF00
+#define SRM_ISP_MTF_ROC_S_0__MTF_ROC_S0              0x1F040274,0x000000FF
+
+#define SRM_ISP_MTF_ROC_S_1__ADDR                  0x1F040278
+#define SRM_ISP_MTF_ROC_S_1__EMPTY      0x1F040278,0x00000000
+#define SRM_ISP_MTF_ROC_S_1__FULL      0x1F040278,0xffffffff
+#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S7              0x1F040278,0xFF000000
+#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S6              0x1F040278,0x00FF0000
+#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S5              0x1F040278,0x0000FF00
+#define SRM_ISP_MTF_ROC_S_1__MTF_ROC_S4              0x1F040278,0x000000FF
+
+#define SRM_ISP_HFE_0__ADDR                  0x1F04027C
+#define SRM_ISP_HFE_0__EMPTY      0x1F04027C,0x00000000
+#define SRM_ISP_HFE_0__FULL      0x1F04027C,0xffffffff
+#define SRM_ISP_HFE_0__HFE_LUT5              0x1F04027C,0x7C000000
+#define SRM_ISP_HFE_0__HFE_LUT4              0x1F04027C,0x03E00000
+#define SRM_ISP_HFE_0__HFE_LUT3              0x1F04027C,0x001F0000
+#define SRM_ISP_HFE_0__HFE_LUT2              0x1F04027C,0x00007C00
+#define SRM_ISP_HFE_0__HFE_LUT1              0x1F04027C,0x000003E0
+#define SRM_ISP_HFE_0__HFE_LUT0              0x1F04027C,0x0000001F
+
+#define SRM_ISP_HFE_1__ADDR                  0x1F040280
+#define SRM_ISP_HFE_1__EMPTY      0x1F040280,0x00000000
+#define SRM_ISP_HFE_1__FULL      0x1F040280,0xffffffff
+#define SRM_ISP_HFE_1__HFE_LUT11       0x1F040280,0x7C000000
+#define SRM_ISP_HFE_1__HFE_LUT10       0x1F040280,0x03E00000
+#define SRM_ISP_HFE_1__HFE_LUT9              0x1F040280,0x001F0000
+#define SRM_ISP_HFE_1__HFE_LUT8              0x1F040280,0x00007C00
+#define SRM_ISP_HFE_1__HFE_LUT7              0x1F040280,0x000003E0
+#define SRM_ISP_HFE_1__HFE_LUT6              0x1F040280,0x0000001F
+
+#define SRM_ISP_HFE_2__ADDR                  0x1F040284
+#define SRM_ISP_HFE_2__EMPTY      0x1F040284,0x00000000
+#define SRM_ISP_HFE_2__FULL      0x1F040284,0xffffffff
+#define SRM_ISP_HFE_2__HFE_LUT15       0x1F040284,0x001F0000
+#define SRM_ISP_HFE_2__HFE_LUT14       0x1F040284,0x00007C00
+#define SRM_ISP_HFE_2__HFE_LUT13       0x1F040284,0x000003E0
+#define SRM_ISP_HFE_2__HFE_LUT12       0x1F040284,0x0000001F
+
+#define SRM_ISP_HFE_S_0__ADDR                  0x1F040288
+#define SRM_ISP_HFE_S_0__EMPTY      0x1F040288,0x00000000
+#define SRM_ISP_HFE_S_0__FULL      0x1F040288,0xffffffff
+#define SRM_ISP_HFE_S_0__HFE_S1              0x1F040288,0x01FF0000
+#define SRM_ISP_HFE_S_0__HFE_S0              0x1F040288,0x000001FF
+
+#define SRM_ISP_HFE_S_1__ADDR                  0x1F04028C
+#define SRM_ISP_HFE_S_1__EMPTY      0x1F04028C,0x00000000
+#define SRM_ISP_HFE_S_1__FULL      0x1F04028C,0xffffffff
+#define SRM_ISP_HFE_S_1__HFE_S3              0x1F04028C,0x01FF0000
+#define SRM_ISP_HFE_S_1__HFE_S2              0x1F04028C,0x000001FF
+
+#define SRM_ISP_HFE_S_2__ADDR                  0x1F040290
+#define SRM_ISP_HFE_S_2__EMPTY      0x1F040290,0x00000000
+#define SRM_ISP_HFE_S_2__FULL      0x1F040290,0xffffffff
+#define SRM_ISP_HFE_S_2__HFE_S5              0x1F040290,0x01FF0000
+#define SRM_ISP_HFE_S_2__HFE_S4              0x1F040290,0x000001FF
+
+#define SRM_ISP_HFE_S_3__ADDR                  0x1F040294
+#define SRM_ISP_HFE_S_3__EMPTY      0x1F040294,0x00000000
+#define SRM_ISP_HFE_S_3__FULL      0x1F040294,0xffffffff
+#define SRM_ISP_HFE_S_3__HFE_S7              0x1F040294,0x01FF0000
+#define SRM_ISP_HFE_S_3__HFE_S6              0x1F040294,0x000001FF
+
+#define SRM_ISP_HFE_C_0__ADDR                  0x1F040298
+#define SRM_ISP_HFE_C_0__EMPTY      0x1F040298,0x00000000
+#define SRM_ISP_HFE_C_0__FULL      0x1F040298,0xffffffff
+#define SRM_ISP_HFE_C_0__HFE_C1              0x1F040298,0x01FF0000
+#define SRM_ISP_HFE_C_0__HFE_C0              0x1F040298,0x000001FF
+
+#define SRM_ISP_HFE_C_1__ADDR                  0x1F04029C
+#define SRM_ISP_HFE_C_1__EMPTY      0x1F04029C,0x00000000
+#define SRM_ISP_HFE_C_1__FULL      0x1F04029C,0xffffffff
+#define SRM_ISP_HFE_C_1__HFE_C3              0x1F04029C,0x01FF0000
+#define SRM_ISP_HFE_C_1__HFE_C2              0x1F04029C,0x000001FF
+
+#define SRM_ISP_HFE_C_2__ADDR                  0x1F0402A0
+#define SRM_ISP_HFE_C_2__EMPTY      0x1F0402A0,0x00000000
+#define SRM_ISP_HFE_C_2__FULL      0x1F0402A0,0xffffffff
+#define SRM_ISP_HFE_C_2__HFE_C5              0x1F0402A0,0x01FF0000
+#define SRM_ISP_HFE_C_2__HFE_C4              0x1F0402A0,0x000001FF
+
+#define SRM_ISP_HFE_C_3__ADDR                  0x1F0402A4
+#define SRM_ISP_HFE_C_3__EMPTY      0x1F0402A4,0x00000000
+#define SRM_ISP_HFE_C_3__FULL      0x1F0402A4,0xffffffff
+#define SRM_ISP_HFE_C_3__HFE_C7              0x1F0402A4,0x01FF0000
+#define SRM_ISP_HFE_C_3__HFE_C6              0x1F0402A4,0x000001FF
+
+#define SRM_ISP_STC_0__ADDR                  0x1F0402A8
+#define SRM_ISP_STC_0__EMPTY      0x1F0402A8,0x00000000
+#define SRM_ISP_STC_0__FULL      0x1F0402A8,0xffffffff
+#define SRM_ISP_STC_0__VNMBR_BLKS      0x1F0402A8,0x03E00000
+#define SRM_ISP_STC_0__HNMBR_BLKS      0x1F0402A8,0x001F0000
+#define SRM_ISP_STC_0__PIX_SKIP              0x1F0402A8,0x00006000
+#define SRM_ISP_STC_0__VBLK_EXP              0x1F0402A8,0x00001C00
+#define SRM_ISP_STC_0__VBLK_MNTS       0x1F0402A8,0x00000300
+#define SRM_ISP_STC_0__HBLK_EXP              0x1F0402A8,0x000000E0
+#define SRM_ISP_STC_0__HBLK_MNTS       0x1F0402A8,0x00000018
+#define SRM_ISP_STC_0__Y_HT_EN      0x1F0402A8,0x00000004
+#define SRM_ISP_STC_0__RAW_HT_EN       0x1F0402A8,0x00000002
+#define SRM_ISP_STC_0__ST_EN      0x1F0402A8,0x00000001
+
+#define SRM_ISP_STC_1__ADDR                  0x1F0402AC
+#define SRM_ISP_STC_1__EMPTY      0x1F0402AC,0x00000000
+#define SRM_ISP_STC_1__FULL      0x1F0402AC,0xffffffff
+#define SRM_ISP_STC_1__TOP_SKIP              0x1F0402AC,0x07FF0000
+#define SRM_ISP_STC_1__LEFT_SKIP       0x1F0402AC,0x000007FF
+
+#define SRM_ISP_FC_0__ADDR                  0x1F0402B0
+#define SRM_ISP_FC_0__EMPTY      0x1F0402B0,0x00000000
+#define SRM_ISP_FC_0__FULL      0x1F0402B0,0xffffffff
+#define SRM_ISP_FC_0__FL_LAST_PHASE      0x1F0402B0,0x00007FE0
+#define SRM_ISP_FC_0__FL_SHIFT      0x1F0402B0,0x0000001F
+
+#define SRM_ISP_FC_1__ADDR                  0x1F0402B4
+#define SRM_ISP_FC_1__EMPTY      0x1F0402B4,0x00000000
+#define SRM_ISP_FC_1__FULL      0x1F0402B4,0xffffffff
+#define SRM_ISP_FC_1__FL_PHASE      0x1F0402B4,0x000FFFFF
+
+#define SRM_ISP_DC1__ADDR                  0x1F0402B8
+#define SRM_ISP_DC1__EMPTY      0x1F0402B8,0x00000000
+#define SRM_ISP_DC1__FULL      0x1F0402B8,0xffffffff
+#define SRM_ISP_DC1__SMOOTH      0x1F0402B8,0x7C000000
+#define SRM_ISP_DC1__NOSTEP      0x1F0402B8,0x03E00000
+#define SRM_ISP_DC1__NOLINE      0x1F0402B8,0x001F0000
+#define SRM_ISP_DC1__BOTHSTEP      0x1F0402B8,0x00003800
+#define SRM_ISP_DC1__LNSHIFTN      0x1F0402B8,0x00000600
+#define SRM_ISP_DC1__LNSHIFTM      0x1F0402B8,0x00000180
+#define SRM_ISP_DC1__NOLINEINSTEP      0x1F0402B8,0x0000007C
+#define SRM_ISP_DC1__ALIASSHIFT              0x1F0402B8,0x00000003
+
+#define SRM_ISP_DC2__ADDR                  0x1F0402BC
+#define SRM_ISP_DC2__EMPTY      0x1F0402BC,0x00000000
+#define SRM_ISP_DC2__FULL      0x1F0402BC,0xffffffff
+#define SRM_ISP_DC2__NOSTEPNOISE       0x1F0402BC,0x03E00000
+#define SRM_ISP_DC2__NOLINENOISE       0x1F0402BC,0x001F0000
+#define SRM_ISP_DC2__ACT       0x1F0402BC,0x00007C00
+#define SRM_ISP_DC2__MSMOOTH      0x1F0402BC,0x00000180
+#define SRM_ISP_DC2__MBRIGHT      0x1F0402BC,0x00000060
+#define SRM_ISP_DC2__BRIGHT      0x1F0402BC,0x0000001F
+
+#define SRM_ISP_DC3__ADDR                  0x1F0402C0
+#define SRM_ISP_DC3__EMPTY      0x1F0402C0,0x00000000
+#define SRM_ISP_DC3__FULL      0x1F0402C0,0xffffffff
+#define SRM_ISP_DC3__NORIMNOISE              0x1F0402C0,0x000003FF
+
+#define SRM_CSI0_CPD_CTRL__ADDR                          0x1F0402C4
+#define SRM_CSI0_CPD_CTRL__EMPTY       0x1F0402C4,0x00000000
+#define SRM_CSI0_CPD_CTRL__FULL              0x1F0402C4,0xffffffff
+#define SRM_CSI0_CPD_CTRL__CSI0_CPD      0x1F0402C4,0x0000001C
+#define SRM_CSI0_CPD_CTRL__CSI0_RED_ROW_BEGIN      0x1F0402C4,0x00000002
+#define SRM_CSI0_CPD_CTRL__CSI0_GREEN_P_BEGIN      0x1F0402C4,0x00000001
+
+#define SRM_CSI0_CPD_RC_0__ADDR                          0x1F0402C8
+#define SRM_CSI0_CPD_RC_0__EMPTY       0x1F0402C8,0x00000000
+#define SRM_CSI0_CPD_RC_0__FULL              0x1F0402C8,0xffffffff
+#define SRM_CSI0_CPD_RC_0__CSI0_CPD_RC_1       0x1F0402C8,0x01FF0000
+#define SRM_CSI0_CPD_RC_0__CSI0_CPD_RC_0       0x1F0402C8,0x000001FF
+
+#define SRM_CSI0_CPD_RC_1__ADDR                          0x1F0402CC
+#define SRM_CSI0_CPD_RC_1__EMPTY       0x1F0402CC,0x00000000
+#define SRM_CSI0_CPD_RC_1__FULL              0x1F0402CC,0xffffffff
+#define SRM_CSI0_CPD_RC_1__CSI0_CPD_RC_3       0x1F0402CC,0x01FF0000
+#define SRM_CSI0_CPD_RC_1__CSI0_CPD_RC_2       0x1F0402CC,0x000001FF
+
+#define SRM_CSI0_CPD_RC_2__ADDR                          0x1F0402D0
+#define SRM_CSI0_CPD_RC_2__EMPTY       0x1F0402D0,0x00000000
+#define SRM_CSI0_CPD_RC_2__FULL              0x1F0402D0,0xffffffff
+#define SRM_CSI0_CPD_RC_2__CSI0_CPD_RC_5       0x1F0402D0,0x01FF0000
+#define SRM_CSI0_CPD_RC_2__CSI0_CPD_RC_4       0x1F0402D0,0x000001FF
+
+#define SRM_CSI0_CPD_RC_3__ADDR                          0x1F0402D4
+#define SRM_CSI0_CPD_RC_3__EMPTY       0x1F0402D4,0x00000000
+#define SRM_CSI0_CPD_RC_3__FULL              0x1F0402D4,0xffffffff
+#define SRM_CSI0_CPD_RC_3__CSI0_CPD_RC_7       0x1F0402D4,0x01FF0000
+#define SRM_CSI0_CPD_RC_3__CSI0_CPD_RC_6       0x1F0402D4,0x000001FF
+
+#define SRM_CSI0_CPD_RC_4__ADDR                          0x1F0402D8
+#define SRM_CSI0_CPD_RC_4__EMPTY       0x1F0402D8,0x00000000
+#define SRM_CSI0_CPD_RC_4__FULL              0x1F0402D8,0xffffffff
+#define SRM_CSI0_CPD_RC_4__CSI0_CPD_RC_9       0x1F0402D8,0x01FF0000
+#define SRM_CSI0_CPD_RC_4__CSI0_CPD_RC_8       0x1F0402D8,0x000001FF
+
+#define SRM_CSI0_CPD_RC_5__ADDR                          0x1F0402DC
+#define SRM_CSI0_CPD_RC_5__EMPTY       0x1F0402DC,0x00000000
+#define SRM_CSI0_CPD_RC_5__FULL              0x1F0402DC,0xffffffff
+#define SRM_CSI0_CPD_RC_5__CSI0_CPD_RC_11      0x1F0402DC,0x01FF0000
+#define SRM_CSI0_CPD_RC_5__CSI0_CPD_RC_10      0x1F0402DC,0x000001FF
+
+#define SRM_CSI0_CPD_RC_6__ADDR                          0x1F0402E0
+#define SRM_CSI0_CPD_RC_6__EMPTY       0x1F0402E0,0x00000000
+#define SRM_CSI0_CPD_RC_6__FULL              0x1F0402E0,0xffffffff
+#define SRM_CSI0_CPD_RC_6__CSI0_CPD_RC_13      0x1F0402E0,0x01FF0000
+#define SRM_CSI0_CPD_RC_6__CSI0_CPD_RC_12      0x1F0402E0,0x000001FF
+
+#define SRM_CSI0_CPD_RC_7__ADDR                          0x1F0402E4
+#define SRM_CSI0_CPD_RC_7__EMPTY       0x1F0402E4,0x00000000
+#define SRM_CSI0_CPD_RC_7__FULL              0x1F0402E4,0xffffffff
+#define SRM_CSI0_CPD_RC_7__CSI0_CPD_RC_15      0x1F0402E4,0x01FF0000
+#define SRM_CSI0_CPD_RC_7__CSI0_CPD_RC_14      0x1F0402E4,0x000001FF
+
+#define SRM_CSI0_CPD_RS_0__ADDR                          0x1F0402E8
+#define SRM_CSI0_CPD_RS_0__EMPTY       0x1F0402E8,0x00000000
+#define SRM_CSI0_CPD_RS_0__FULL              0x1F0402E8,0xffffffff
+#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS3              0x1F0402E8,0xFF000000
+#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS2              0x1F0402E8,0x00FF0000
+#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS1              0x1F0402E8,0x0000FF00
+#define SRM_CSI0_CPD_RS_0__CSI0_CPD_RS0              0x1F0402E8,0x000000FF
+
+#define SRM_CSI0_CPD_RS_1__ADDR                          0x1F0402EC
+#define SRM_CSI0_CPD_RS_1__EMPTY       0x1F0402EC,0x00000000
+#define SRM_CSI0_CPD_RS_1__FULL              0x1F0402EC,0xffffffff
+#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS7              0x1F0402EC,0xFF000000
+#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS6              0x1F0402EC,0x00FF0000
+#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS5              0x1F0402EC,0x0000FF00
+#define SRM_CSI0_CPD_RS_1__CSI0_CPD_RS4              0x1F0402EC,0x000000FF
+
+#define SRM_CSI0_CPD_RS_2__ADDR                          0x1F0402F0
+#define SRM_CSI0_CPD_RS_2__EMPTY       0x1F0402F0,0x00000000
+#define SRM_CSI0_CPD_RS_2__FULL              0x1F0402F0,0xffffffff
+#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS11       0x1F0402F0,0xFF000000
+#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS10       0x1F0402F0,0x00FF0000
+#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS9              0x1F0402F0,0x0000FF00
+#define SRM_CSI0_CPD_RS_2__CSI0_CPD_RS8              0x1F0402F0,0x000000FF
+
+#define SRM_CSI0_CPD_RS_3__ADDR                          0x1F0402F4
+#define SRM_CSI0_CPD_RS_3__EMPTY       0x1F0402F4,0x00000000
+#define SRM_CSI0_CPD_RS_3__FULL              0x1F0402F4,0xffffffff
+#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS15       0x1F0402F4,0xFF000000
+#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS14       0x1F0402F4,0x00FF0000
+#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS13       0x1F0402F4,0x0000FF00
+#define SRM_CSI0_CPD_RS_3__CSI0_CPD_RS12       0x1F0402F4,0x000000FF
+
+#define SRM_CSI0_CPD_GRC_0__ADDR                  0x1F0402F8
+#define SRM_CSI0_CPD_GRC_0__EMPTY      0x1F0402F8,0x00000000
+#define SRM_CSI0_CPD_GRC_0__FULL       0x1F0402F8,0xffffffff
+#define SRM_CSI0_CPD_GRC_0__CSI0_CPD_GRC1      0x1F0402F8,0x01FF0000
+#define SRM_CSI0_CPD_GRC_0__CSI0_CPD_GRC0      0x1F0402F8,0x000001FF
+
+#define SRM_CSI0_CPD_GRC_1__ADDR                  0x1F0402FC
+#define SRM_CSI0_CPD_GRC_1__EMPTY      0x1F0402FC,0x00000000
+#define SRM_CSI0_CPD_GRC_1__FULL       0x1F0402FC,0xffffffff
+#define SRM_CSI0_CPD_GRC_1__CSI0_CPD_GRC3      0x1F0402FC,0x01FF0000
+#define SRM_CSI0_CPD_GRC_1__CSI0_CPD_GRC2      0x1F0402FC,0x000001FF
+
+#define SRM_CSI0_CPD_GRC_2__ADDR                  0x1F040300
+#define SRM_CSI0_CPD_GRC_2__EMPTY      0x1F040300,0x00000000
+#define SRM_CSI0_CPD_GRC_2__FULL       0x1F040300,0xffffffff
+#define SRM_CSI0_CPD_GRC_2__CSI0_CPD_GRC5      0x1F040300,0x01FF0000
+#define SRM_CSI0_CPD_GRC_2__CSI0_CPD_GRC4      0x1F040300,0x000001FF
+
+#define SRM_CSI0_CPD_GRC_3__ADDR                  0x1F040304
+#define SRM_CSI0_CPD_GRC_3__EMPTY      0x1F040304,0x00000000
+#define SRM_CSI0_CPD_GRC_3__FULL       0x1F040304,0xffffffff
+#define SRM_CSI0_CPD_GRC_3__CSI0_CPD_GRC7      0x1F040304,0x01FF0000
+#define SRM_CSI0_CPD_GRC_3__CSI0_CPD_GRC6      0x1F040304,0x000001FF
+
+#define SRM_CSI0_CPD_GRC_4__ADDR                  0x1F040308
+#define SRM_CSI0_CPD_GRC_4__EMPTY      0x1F040308,0x00000000
+#define SRM_CSI0_CPD_GRC_4__FULL       0x1F040308,0xffffffff
+#define SRM_CSI0_CPD_GRC_4__CSI0_CPD_GRC9      0x1F040308,0x01FF0000
+#define SRM_CSI0_CPD_GRC_4__CSI0_CPD_GRC8      0x1F040308,0x000001FF
+
+#define SRM_CSI0_CPD_GRC_5__ADDR                  0x1F04030C
+#define SRM_CSI0_CPD_GRC_5__EMPTY      0x1F04030C,0x00000000
+#define SRM_CSI0_CPD_GRC_5__FULL       0x1F04030C,0xffffffff
+#define SRM_CSI0_CPD_GRC_5__CSI0_CPD_GRC11      0x1F04030C,0x01FF0000
+#define SRM_CSI0_CPD_GRC_5__CSI0_CPD_GRC10      0x1F04030C,0x000001FF
+
+#define SRM_CSI0_CPD_GRC_6__ADDR                  0x1F040310
+#define SRM_CSI0_CPD_GRC_6__EMPTY      0x1F040310,0x00000000
+#define SRM_CSI0_CPD_GRC_6__FULL       0x1F040310,0xffffffff
+#define SRM_CSI0_CPD_GRC_6__CSI0_CPD_GRC13      0x1F040310,0x01FF0000
+#define SRM_CSI0_CPD_GRC_6__CSI0_CPD_GRC12      0x1F040310,0x000001FF
+
+#define SRM_CSI0_CPD_GRC_7__ADDR                  0x1F040314
+#define SRM_CSI0_CPD_GRC_7__EMPTY      0x1F040314,0x00000000
+#define SRM_CSI0_CPD_GRC_7__FULL       0x1F040314,0xffffffff
+#define SRM_CSI0_CPD_GRC_7__CSI0_CPD_GRC15      0x1F040314,0x01FF0000
+#define SRM_CSI0_CPD_GRC_7__CSI0_CPD_GRC14      0x1F040314,0x000001FF
+
+#define SRM_CSI0_CPD_GRS_0__ADDR                  0x1F040318
+#define SRM_CSI0_CPD_GRS_0__EMPTY      0x1F040318,0x00000000
+#define SRM_CSI0_CPD_GRS_0__FULL       0x1F040318,0xffffffff
+#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS3      0x1F040318,0xFF000000
+#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS2      0x1F040318,0x00FF0000
+#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS1      0x1F040318,0x0000FF00
+#define SRM_CSI0_CPD_GRS_0__CSI0_CPD_GRS0      0x1F040318,0x000000FF
+
+#define SRM_CSI0_CPD_GRS_1__ADDR                  0x1F04031C
+#define SRM_CSI0_CPD_GRS_1__EMPTY      0x1F04031C,0x00000000
+#define SRM_CSI0_CPD_GRS_1__FULL       0x1F04031C,0xffffffff
+#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS7      0x1F04031C,0xFF000000
+#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS6      0x1F04031C,0x00FF0000
+#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS5      0x1F04031C,0x0000FF00
+#define SRM_CSI0_CPD_GRS_1__CSI0_CPD_GRS4      0x1F04031C,0x000000FF
+
+#define SRM_CSI0_CPD_GRS_2__ADDR                  0x1F040320
+#define SRM_CSI0_CPD_GRS_2__EMPTY      0x1F040320,0x00000000
+#define SRM_CSI0_CPD_GRS_2__FULL       0x1F040320,0xffffffff
+#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS11      0x1F040320,0xFF000000
+#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS10      0x1F040320,0x00FF0000
+#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS9      0x1F040320,0x0000FF00
+#define SRM_CSI0_CPD_GRS_2__CSI0_CPD_GRS8      0x1F040320,0x000000FF
+
+#define SRM_CSI0_CPD_GRS_3__ADDR                  0x1F040324
+#define SRM_CSI0_CPD_GRS_3__EMPTY      0x1F040324,0x00000000
+#define SRM_CSI0_CPD_GRS_3__FULL       0x1F040324,0xffffffff
+#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS15      0x1F040324,0xFF000000
+#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS14      0x1F040324,0x00FF0000
+#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS13      0x1F040324,0x0000FF00
+#define SRM_CSI0_CPD_GRS_3__CSI0_CPD_GRS12      0x1F040324,0x000000FF
+
+#define SRM_CSI0_CPD_GBC_0__ADDR                  0x1F040328
+#define SRM_CSI0_CPD_GBC_0__EMPTY      0x1F040328,0x00000000
+#define SRM_CSI0_CPD_GBC_0__FULL       0x1F040328,0xffffffff
+#define SRM_CSI0_CPD_GBC_0__CSI0_CPD_GBC1      0x1F040328,0x01FF0000
+#define SRM_CSI0_CPD_GBC_0__CSI0_CPD_GBC0      0x1F040328,0x000001FF
+
+#define SRM_CSI0_CPD_GBC_1__ADDR                  0x1F04032C
+#define SRM_CSI0_CPD_GBC_1__EMPTY      0x1F04032C,0x00000000
+#define SRM_CSI0_CPD_GBC_1__FULL       0x1F04032C,0xffffffff
+#define SRM_CSI0_CPD_GBC_1__CSI0_CPD_GBC3      0x1F04032C,0x01FF0000
+#define SRM_CSI0_CPD_GBC_1__CSI0_CPD_GBC2      0x1F04032C,0x000001FF
+
+#define SRM_CSI0_CPD_GBC_2__ADDR                  0x1F040330
+#define SRM_CSI0_CPD_GBC_2__EMPTY      0x1F040330,0x00000000
+#define SRM_CSI0_CPD_GBC_2__FULL       0x1F040330,0xffffffff
+#define SRM_CSI0_CPD_GBC_2__CSI0_CPD_GBC5      0x1F040330,0x01FF0000
+#define SRM_CSI0_CPD_GBC_2__CSI0_CPD_GBC4      0x1F040330,0x000001FF
+
+#define SRM_CSI0_CPD_GBC_3__ADDR                  0x1F040334
+#define SRM_CSI0_CPD_GBC_3__EMPTY      0x1F040334,0x00000000
+#define SRM_CSI0_CPD_GBC_3__FULL       0x1F040334,0xffffffff
+#define SRM_CSI0_CPD_GBC_3__CSI0_CPD_GBC7      0x1F040334,0x01FF0000
+#define SRM_CSI0_CPD_GBC_3__CSI0_CPD_GBC6      0x1F040334,0x000001FF
+
+#define SRM_CSI0_CPD_GBC_4__ADDR                  0x1F040338
+#define SRM_CSI0_CPD_GBC_4__EMPTY      0x1F040338,0x00000000
+#define SRM_CSI0_CPD_GBC_4__FULL       0x1F040338,0xffffffff
+#define SRM_CSI0_CPD_GBC_4__CSI0_CPD_GBC9      0x1F040338,0x01FF0000
+#define SRM_CSI0_CPD_GBC_4__CSI0_CPD_GBC8      0x1F040338,0x000001FF
+
+#define SRM_CSI0_CPD_GBC_5__ADDR                  0x1F04033C
+#define SRM_CSI0_CPD_GBC_5__EMPTY      0x1F04033C,0x00000000
+#define SRM_CSI0_CPD_GBC_5__FULL       0x1F04033C,0xffffffff
+#define SRM_CSI0_CPD_GBC_5__CSI0_CPD_GBC11      0x1F04033C,0x01FF0000
+#define SRM_CSI0_CPD_GBC_5__CSI0_CPD_GBC10      0x1F04033C,0x000001FF
+
+#define SRM_CSI0_CPD_GBC_6__ADDR                  0x1F040340
+#define SRM_CSI0_CPD_GBC_6__EMPTY      0x1F040340,0x00000000
+#define SRM_CSI0_CPD_GBC_6__FULL       0x1F040340,0xffffffff
+#define SRM_CSI0_CPD_GBC_6__CSI0_CPD_GBC13      0x1F040340,0x01FF0000
+#define SRM_CSI0_CPD_GBC_6__CSI0_CPD_GBC12      0x1F040340,0x000001FF
+
+#define SRM_CSI0_CPD_GBC_7__ADDR                  0x1F040344
+#define SRM_CSI0_CPD_GBC_7__EMPTY      0x1F040344,0x00000000
+#define SRM_CSI0_CPD_GBC_7__FULL       0x1F040344,0xffffffff
+#define SRM_CSI0_CPD_GBC_7__CSI0_CPD_GBC15      0x1F040344,0x01FF0000
+#define SRM_CSI0_CPD_GBC_7__CSI0_CPD_GBC14      0x1F040344,0x000001FF
+
+#define SRM_CSI0_CPD_GBS_0__ADDR                  0x1F040348
+#define SRM_CSI0_CPD_GBS_0__EMPTY      0x1F040348,0x00000000
+#define SRM_CSI0_CPD_GBS_0__FULL       0x1F040348,0xffffffff
+#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS3      0x1F040348,0xFF000000
+#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS2      0x1F040348,0x00FF0000
+#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS1      0x1F040348,0x0000FF00
+#define SRM_CSI0_CPD_GBS_0__CSI0_CPD_GBS0      0x1F040348,0x000000FF
+
+#define SRM_CSI0_CPD_GBS_1__ADDR                  0x1F04034C
+#define SRM_CSI0_CPD_GBS_1__EMPTY      0x1F04034C,0x00000000
+#define SRM_CSI0_CPD_GBS_1__FULL       0x1F04034C,0xffffffff
+#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS7      0x1F04034C,0xFF000000
+#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS6      0x1F04034C,0x00FF0000
+#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS5      0x1F04034C,0x0000FF00
+#define SRM_CSI0_CPD_GBS_1__CSI0_CPD_GBS4      0x1F04034C,0x000000FF
+
+#define SRM_CSI0_CPD_GBS_2__ADDR                  0x1F040350
+#define SRM_CSI0_CPD_GBS_2__EMPTY      0x1F040350,0x00000000
+#define SRM_CSI0_CPD_GBS_2__FULL       0x1F040350,0xffffffff
+#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS11      0x1F040350,0xFF000000
+#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS10      0x1F040350,0x00FF0000
+#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS9      0x1F040350,0x0000FF00
+#define SRM_CSI0_CPD_GBS_2__CSI0_CPD_GBS8      0x1F040350,0x000000FF
+
+#define SRM_CSI0_CPD_GBS_3__ADDR                  0x1F040354
+#define SRM_CSI0_CPD_GBS_3__EMPTY      0x1F040354,0x00000000
+#define SRM_CSI0_CPD_GBS_3__FULL       0x1F040354,0xffffffff
+#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS15      0x1F040354,0xFF000000
+#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS14      0x1F040354,0x00FF0000
+#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS13      0x1F040354,0x0000FF00
+#define SRM_CSI0_CPD_GBS_3__CSI0_CPD_GBS12      0x1F040354,0x000000FF
+
+#define SRM_CSI0_CPD_BC_0__ADDR                          0x1F040358
+#define SRM_CSI0_CPD_BC_0__EMPTY       0x1F040358,0x00000000
+#define SRM_CSI0_CPD_BC_0__FULL              0x1F040358,0xffffffff
+#define SRM_CSI0_CPD_BC_0__CSI0_CPD_BC1              0x1F040358,0x01FF0000
+#define SRM_CSI0_CPD_BC_0__CSI0_CPD_BC0              0x1F040358,0x000001FF
+
+#define SRM_CSI0_CPD_BC_1__ADDR                          0x1F04035C
+#define SRM_CSI0_CPD_BC_1__EMPTY       0x1F04035C,0x00000000
+#define SRM_CSI0_CPD_BC_1__FULL              0x1F04035C,0xffffffff
+#define SRM_CSI0_CPD_BC_1__CSI0_CPD_BC3              0x1F04035C,0x01FF0000
+#define SRM_CSI0_CPD_BC_1__CSI0_CPD_BC2              0x1F04035C,0x000001FF
+
+#define SRM_CSI0_CPD_BC_2__ADDR                          0x1F040360
+#define SRM_CSI0_CPD_BC_2__EMPTY       0x1F040360,0x00000000
+#define SRM_CSI0_CPD_BC_2__FULL              0x1F040360,0xffffffff
+#define SRM_CSI0_CPD_BC_2__CSI0_CPD_BC5              0x1F040360,0x01FF0000
+#define SRM_CSI0_CPD_BC_2__CSI0_CPD_BC4              0x1F040360,0x000001FF
+
+#define SRM_CSI0_CPD_BC_3__ADDR                          0x1F040364
+#define SRM_CSI0_CPD_BC_3__EMPTY       0x1F040364,0x00000000
+#define SRM_CSI0_CPD_BC_3__FULL              0x1F040364,0xffffffff
+#define SRM_CSI0_CPD_BC_3__CSI0_CPD_BC7              0x1F040364,0x01FF0000
+#define SRM_CSI0_CPD_BC_3__CSI0_CPD_BC6              0x1F040364,0x000001FF
+
+#define SRM_CSI0_CPD_BC_4__ADDR                          0x1F040368
+#define SRM_CSI0_CPD_BC_4__EMPTY       0x1F040368,0x00000000
+#define SRM_CSI0_CPD_BC_4__FULL              0x1F040368,0xffffffff
+#define SRM_CSI0_CPD_BC_4__CSI0_CPD_BC9              0x1F040368,0x01FF0000
+#define SRM_CSI0_CPD_BC_4__CSI0_CPD_BC8              0x1F040368,0x000001FF
+
+#define SRM_CSI0_CPD_BC_5__ADDR                          0x1F04036C
+#define SRM_CSI0_CPD_BC_5__EMPTY       0x1F04036C,0x00000000
+#define SRM_CSI0_CPD_BC_5__FULL              0x1F04036C,0xffffffff
+#define SRM_CSI0_CPD_BC_5__CSI0_CPD_BC11       0x1F04036C,0x01FF0000
+#define SRM_CSI0_CPD_BC_5__CSI0_CPD_BC10       0x1F04036C,0x000001FF
+
+#define SRM_CSI0_CPD_BC_6__ADDR                          0x1F040370
+#define SRM_CSI0_CPD_BC_6__EMPTY       0x1F040370,0x00000000
+#define SRM_CSI0_CPD_BC_6__FULL              0x1F040370,0xffffffff
+#define SRM_CSI0_CPD_BC_6__CSI0_CPD_BC13       0x1F040370,0x01FF0000
+#define SRM_CSI0_CPD_BC_6__CSI0_CPD_BC12       0x1F040370,0x000001FF
+
+#define SRM_CSI0_CPD_BC_7__ADDR                          0x1F040374
+#define SRM_CSI0_CPD_BC_7__EMPTY       0x1F040374,0x00000000
+#define SRM_CSI0_CPD_BC_7__FULL              0x1F040374,0xffffffff
+#define SRM_CSI0_CPD_BC_7__CSI0_CPD_BC15       0x1F040374,0x01FF0000
+#define SRM_CSI0_CPD_BC_7__CSI0_CPD_BC14       0x1F040374,0x000001FF
+
+#define SRM_CSI0_CPD_BS_0__ADDR                          0x1F040378
+#define SRM_CSI0_CPD_BS_0__EMPTY       0x1F040378,0x00000000
+#define SRM_CSI0_CPD_BS_0__FULL              0x1F040378,0xffffffff
+#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS3              0x1F040378,0xFF000000
+#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS2              0x1F040378,0x00FF0000
+#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS1              0x1F040378,0x0000FF00
+#define SRM_CSI0_CPD_BS_0__CSI0_CPD_BS0              0x1F040378,0x000000FF
+
+#define SRM_CSI0_CPD_BS_1__ADDR                          0x1F04037C
+#define SRM_CSI0_CPD_BS_1__EMPTY       0x1F04037C,0x00000000
+#define SRM_CSI0_CPD_BS_1__FULL              0x1F04037C,0xffffffff
+#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS7              0x1F04037C,0xFF000000
+#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS6              0x1F04037C,0x00FF0000
+#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS5              0x1F04037C,0x0000FF00
+#define SRM_CSI0_CPD_BS_1__CSI0_CPD_BS4              0x1F04037C,0x000000FF
+
+#define SRM_CSI0_CPD_BS_2__ADDR                          0x1F040380
+#define SRM_CSI0_CPD_BS_2__EMPTY       0x1F040380,0x00000000
+#define SRM_CSI0_CPD_BS_2__FULL              0x1F040380,0xffffffff
+#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS11       0x1F040380,0xFF000000
+#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS10       0x1F040380,0x00FF0000
+#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS9              0x1F040380,0x0000FF00
+#define SRM_CSI0_CPD_BS_2__CSI0_CPD_BS8              0x1F040380,0x000000FF
+
+#define SRM_CSI0_CPD_BS_3__ADDR                          0x1F040384
+#define SRM_CSI0_CPD_BS_3__EMPTY       0x1F040384,0x00000000
+#define SRM_CSI0_CPD_BS_3__FULL              0x1F040384,0xffffffff
+#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS15       0x1F040384,0xFF000000
+#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS14       0x1F040384,0x00FF0000
+#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS13       0x1F040384,0x0000FF00
+#define SRM_CSI0_CPD_BS_3__CSI0_CPD_BS12       0x1F040384,0x000000FF
+
+#define SRM_CSI0_CPD_OFFSET1__ADDR                  0x1F040388
+#define SRM_CSI0_CPD_OFFSET1__EMPTY      0x1F040388,0x00000000
+#define SRM_CSI0_CPD_OFFSET1__FULL      0x1F040388,0xffffffff
+#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_B_OFFSET              0x1F040388,0x3FF00000
+#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_GB_OFFSET       0x1F040388,0x000FFC00
+#define SRM_CSI0_CPD_OFFSET1__CSI0_CPD_GR_OFFSET       0x1F040388,0x000003FF
+
+#define SRM_CSI0_CPD_OFFSET2__ADDR                  0x1F04038C
+#define SRM_CSI0_CPD_OFFSET2__EMPTY      0x1F04038C,0x00000000
+#define SRM_CSI0_CPD_OFFSET2__FULL      0x1F04038C,0xffffffff
+#define SRM_CSI0_CPD_OFFSET2__CSI0_CPD_R_OFFSET              0x1F04038C,0x000003FF
+
+#define SRM_CSI1_CPD_CTRL__ADDR                          0x1F040390
+#define SRM_CSI1_CPD_CTRL__EMPTY       0x1F040390,0x00000000
+#define SRM_CSI1_CPD_CTRL__FULL              0x1F040390,0xffffffff
+#define SRM_CSI1_CPD_CTRL__CSI1_CPD      0x1F040390,0x0000001C
+#define SRM_CSI1_CPD_CTRL__CSI1_RED_ROW_BEGIN      0x1F040390,0x00000002
+#define SRM_CSI1_CPD_CTRL__CSI1_GREEN_P_BEGIN      0x1F040390,0x00000001
+
+#define SRM_CSI1_CPD_RC_0__ADDR                          0x1F040394
+#define SRM_CSI1_CPD_RC_0__EMPTY       0x1F040394,0x00000000
+#define SRM_CSI1_CPD_RC_0__FULL              0x1F040394,0xffffffff
+#define SRM_CSI1_CPD_RC_0__CSI1_CPD_RC_1       0x1F040394,0x01FF0000
+#define SRM_CSI1_CPD_RC_0__CSI1_CPD_RC_0       0x1F040394,0x000001FF
+
+#define SRM_CSI1_CPD_RC_1__ADDR                          0x1F040398
+#define SRM_CSI1_CPD_RC_1__EMPTY       0x1F040398,0x00000000
+#define SRM_CSI1_CPD_RC_1__FULL              0x1F040398,0xffffffff
+#define SRM_CSI1_CPD_RC_1__CSI1_CPD_RC_3       0x1F040398,0x01FF0000
+#define SRM_CSI1_CPD_RC_1__CSI1_CPD_RC_2       0x1F040398,0x000001FF
+
+#define SRM_CSI1_CPD_RC_2__ADDR                          0x1F04039C
+#define SRM_CSI1_CPD_RC_2__EMPTY       0x1F04039C,0x00000000
+#define SRM_CSI1_CPD_RC_2__FULL              0x1F04039C,0xffffffff
+#define SRM_CSI1_CPD_RC_2__CSI1_CPD_RC_5       0x1F04039C,0x01FF0000
+#define SRM_CSI1_CPD_RC_2__CSI1_CPD_RC_4       0x1F04039C,0x000001FF
+
+#define SRM_CSI1_CPD_RC_3__ADDR                          0x1F0403A0
+#define SRM_CSI1_CPD_RC_3__EMPTY       0x1F0403A0,0x00000000
+#define SRM_CSI1_CPD_RC_3__FULL              0x1F0403A0,0xffffffff
+#define SRM_CSI1_CPD_RC_3__CSI1_CPD_RC_7       0x1F0403A0,0x01FF0000
+#define SRM_CSI1_CPD_RC_3__CSI1_CPD_RC_6       0x1F0403A0,0x000001FF
+
+#define SRM_CSI1_CPD_RC_4__ADDR                          0x1F0403A4
+#define SRM_CSI1_CPD_RC_4__EMPTY       0x1F0403A4,0x00000000
+#define SRM_CSI1_CPD_RC_4__FULL              0x1F0403A4,0xffffffff
+#define SRM_CSI1_CPD_RC_4__CSI1_CPD_RC_9       0x1F0403A4,0x01FF0000
+#define SRM_CSI1_CPD_RC_4__CSI1_CPD_RC_8       0x1F0403A4,0x000001FF
+
+#define SRM_CSI1_CPD_RC_5__ADDR                          0x1F0403A8
+#define SRM_CSI1_CPD_RC_5__EMPTY       0x1F0403A8,0x00000000
+#define SRM_CSI1_CPD_RC_5__FULL              0x1F0403A8,0xffffffff
+#define SRM_CSI1_CPD_RC_5__CSI1_CPD_RC_11      0x1F0403A8,0x01FF0000
+#define SRM_CSI1_CPD_RC_5__CSI1_CPD_RC_10      0x1F0403A8,0x000001FF
+
+#define SRM_CSI1_CPD_RC_6__ADDR                          0x1F0403AC
+#define SRM_CSI1_CPD_RC_6__EMPTY       0x1F0403AC,0x00000000
+#define SRM_CSI1_CPD_RC_6__FULL              0x1F0403AC,0xffffffff
+#define SRM_CSI1_CPD_RC_6__CSI1_CPD_RC_13      0x1F0403AC,0x01FF0000
+#define SRM_CSI1_CPD_RC_6__CSI1_CPD_RC_12      0x1F0403AC,0x000001FF
+
+#define SRM_CSI1_CPD_RC_7__ADDR                          0x1F0403B0
+#define SRM_CSI1_CPD_RC_7__EMPTY       0x1F0403B0,0x00000000
+#define SRM_CSI1_CPD_RC_7__FULL              0x1F0403B0,0xffffffff
+#define SRM_CSI1_CPD_RC_7__CSI1_CPD_RC_15      0x1F0403B0,0x01FF0000
+#define SRM_CSI1_CPD_RC_7__CSI1_CPD_RC_14      0x1F0403B0,0x000001FF
+
+#define SRM_CSI1_CPD_RS_0__ADDR                          0x1F0403B4
+#define SRM_CSI1_CPD_RS_0__EMPTY       0x1F0403B4,0x00000000
+#define SRM_CSI1_CPD_RS_0__FULL              0x1F0403B4,0xffffffff
+#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS3              0x1F0403B4,0xFF000000
+#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS2              0x1F0403B4,0x00FF0000
+#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS1              0x1F0403B4,0x0000FF00
+#define SRM_CSI1_CPD_RS_0__CSI1_CPD_RS0              0x1F0403B4,0x000000FF
+
+#define SRM_CSI1_CPD_RS_1__ADDR                          0x1F0403B8
+#define SRM_CSI1_CPD_RS_1__EMPTY       0x1F0403B8,0x00000000
+#define SRM_CSI1_CPD_RS_1__FULL              0x1F0403B8,0xffffffff
+#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS7              0x1F0403B8,0xFF000000
+#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS6              0x1F0403B8,0x00FF0000
+#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS5              0x1F0403B8,0x0000FF00
+#define SRM_CSI1_CPD_RS_1__CSI1_CPD_RS4              0x1F0403B8,0x000000FF
+
+#define SRM_CSI1_CPD_RS_2__ADDR                          0x1F0403BC
+#define SRM_CSI1_CPD_RS_2__EMPTY       0x1F0403BC,0x00000000
+#define SRM_CSI1_CPD_RS_2__FULL              0x1F0403BC,0xffffffff
+#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS11       0x1F0403BC,0xFF000000
+#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS10       0x1F0403BC,0x00FF0000
+#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS9              0x1F0403BC,0x0000FF00
+#define SRM_CSI1_CPD_RS_2__CSI1_CPD_RS8              0x1F0403BC,0x000000FF
+
+#define SRM_CSI1_CPD_RS_3__ADDR                          0x1F0403C0
+#define SRM_CSI1_CPD_RS_3__EMPTY       0x1F0403C0,0x00000000
+#define SRM_CSI1_CPD_RS_3__FULL              0x1F0403C0,0xffffffff
+#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS15       0x1F0403C0,0xFF000000
+#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS14       0x1F0403C0,0x00FF0000
+#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS13       0x1F0403C0,0x0000FF00
+#define SRM_CSI1_CPD_RS_3__CSI1_CPD_RS12       0x1F0403C0,0x000000FF
+
+#define SRM_CSI1_CPD_GRC_0__ADDR                  0x1F0403C4
+#define SRM_CSI1_CPD_GRC_0__EMPTY      0x1F0403C4,0x00000000
+#define SRM_CSI1_CPD_GRC_0__FULL       0x1F0403C4,0xffffffff
+#define SRM_CSI1_CPD_GRC_0__CSI1_CPD_GRC1      0x1F0403C4,0x01FF0000
+#define SRM_CSI1_CPD_GRC_0__CSI1_CPD_GRC0      0x1F0403C4,0x000001FF
+
+#define SRM_CSI1_CPD_GRC_1__ADDR                  0x1F0403C8
+#define SRM_CSI1_CPD_GRC_1__EMPTY      0x1F0403C8,0x00000000
+#define SRM_CSI1_CPD_GRC_1__FULL       0x1F0403C8,0xffffffff
+#define SRM_CSI1_CPD_GRC_1__CSI1_CPD_GRC3      0x1F0403C8,0x01FF0000
+#define SRM_CSI1_CPD_GRC_1__CSI1_CPD_GRC2      0x1F0403C8,0x000001FF
+
+#define SRM_CSI1_CPD_GRC_2__ADDR                  0x1F0403CC
+#define SRM_CSI1_CPD_GRC_2__EMPTY      0x1F0403CC,0x00000000
+#define SRM_CSI1_CPD_GRC_2__FULL       0x1F0403CC,0xffffffff
+#define SRM_CSI1_CPD_GRC_2__CSI1_CPD_GRC5      0x1F0403CC,0x01FF0000
+#define SRM_CSI1_CPD_GRC_2__CSI1_CPD_GRC4      0x1F0403CC,0x000001FF
+
+#define SRM_CSI1_CPD_GRC_3__ADDR                  0x1F0403D0
+#define SRM_CSI1_CPD_GRC_3__EMPTY      0x1F0403D0,0x00000000
+#define SRM_CSI1_CPD_GRC_3__FULL       0x1F0403D0,0xffffffff
+#define SRM_CSI1_CPD_GRC_3__CSI1_CPD_GRC7      0x1F0403D0,0x01FF0000
+#define SRM_CSI1_CPD_GRC_3__CSI1_CPD_GRC6      0x1F0403D0,0x000001FF
+
+#define SRM_CSI1_CPD_GRC_4__ADDR                  0x1F0403D4
+#define SRM_CSI1_CPD_GRC_4__EMPTY      0x1F0403D4,0x00000000
+#define SRM_CSI1_CPD_GRC_4__FULL       0x1F0403D4,0xffffffff
+#define SRM_CSI1_CPD_GRC_4__CSI1_CPD_GRC9      0x1F0403D4,0x01FF0000
+#define SRM_CSI1_CPD_GRC_4__CSI1_CPD_GRC8      0x1F0403D4,0x000001FF
+
+#define SRM_CSI1_CPD_GRC_5__ADDR                  0x1F0403D8
+#define SRM_CSI1_CPD_GRC_5__EMPTY      0x1F0403D8,0x00000000
+#define SRM_CSI1_CPD_GRC_5__FULL       0x1F0403D8,0xffffffff
+#define SRM_CSI1_CPD_GRC_5__CSI1_CPD_GRC11      0x1F0403D8,0x01FF0000
+#define SRM_CSI1_CPD_GRC_5__CSI1_CPD_GRC10      0x1F0403D8,0x000001FF
+
+#define SRM_CSI1_CPD_GRC_6__ADDR                  0x1F0403DC
+#define SRM_CSI1_CPD_GRC_6__EMPTY      0x1F0403DC,0x00000000
+#define SRM_CSI1_CPD_GRC_6__FULL       0x1F0403DC,0xffffffff
+#define SRM_CSI1_CPD_GRC_6__CSI1_CPD_GRC13      0x1F0403DC,0x01FF0000
+#define SRM_CSI1_CPD_GRC_6__CSI1_CPD_GRC12      0x1F0403DC,0x000001FF
+
+#define SRM_CSI1_CPD_GRC_7__ADDR                  0x1F0403E0
+#define SRM_CSI1_CPD_GRC_7__EMPTY      0x1F0403E0,0x00000000
+#define SRM_CSI1_CPD_GRC_7__FULL       0x1F0403E0,0xffffffff
+#define SRM_CSI1_CPD_GRC_7__CSI1_CPD_GRC15      0x1F0403E0,0x01FF0000
+#define SRM_CSI1_CPD_GRC_7__CSI1_CPD_GRC14      0x1F0403E0,0x000001FF
+
+#define SRM_CSI1_CPD_GRS_0__ADDR                  0x1F0403E4
+#define SRM_CSI1_CPD_GRS_0__EMPTY      0x1F0403E4,0x00000000
+#define SRM_CSI1_CPD_GRS_0__FULL       0x1F0403E4,0xffffffff
+#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS3      0x1F0403E4,0xFF000000
+#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS2      0x1F0403E4,0x00FF0000
+#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS1      0x1F0403E4,0x0000FF00
+#define SRM_CSI1_CPD_GRS_0__CSI1_CPD_GRS0      0x1F0403E4,0x000000FF
+
+#define SRM_CSI1_CPD_GRS_1__ADDR                  0x1F0403E8
+#define SRM_CSI1_CPD_GRS_1__EMPTY      0x1F0403E8,0x00000000
+#define SRM_CSI1_CPD_GRS_1__FULL       0x1F0403E8,0xffffffff
+#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS7      0x1F0403E8,0xFF000000
+#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS6      0x1F0403E8,0x00FF0000
+#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS5      0x1F0403E8,0x0000FF00
+#define SRM_CSI1_CPD_GRS_1__CSI1_CPD_GRS4      0x1F0403E8,0x000000FF
+
+#define SRM_CSI1_CPD_GRS_2__ADDR                  0x1F0403EC
+#define SRM_CSI1_CPD_GRS_2__EMPTY      0x1F0403EC,0x00000000
+#define SRM_CSI1_CPD_GRS_2__FULL       0x1F0403EC,0xffffffff
+#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS11      0x1F0403EC,0xFF000000
+#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS10      0x1F0403EC,0x00FF0000
+#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS9      0x1F0403EC,0x0000FF00
+#define SRM_CSI1_CPD_GRS_2__CSI1_CPD_GRS8      0x1F0403EC,0x000000FF
+
+#define SRM_CSI1_CPD_GRS_3__ADDR                  0x1F0403F0
+#define SRM_CSI1_CPD_GRS_3__EMPTY      0x1F0403F0,0x00000000
+#define SRM_CSI1_CPD_GRS_3__FULL       0x1F0403F0,0xffffffff
+#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS15      0x1F0403F0,0xFF000000
+#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS14      0x1F0403F0,0x00FF0000
+#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS13      0x1F0403F0,0x0000FF00
+#define SRM_CSI1_CPD_GRS_3__CSI1_CPD_GRS12      0x1F0403F0,0x000000FF
+
+#define SRM_CSI1_CPD_GBC_0__ADDR                  0x1F0403F4
+#define SRM_CSI1_CPD_GBC_0__EMPTY      0x1F0403F4,0x00000000
+#define SRM_CSI1_CPD_GBC_0__FULL       0x1F0403F4,0xffffffff
+#define SRM_CSI1_CPD_GBC_0__CSI1_CPD_GBC1      0x1F0403F4,0x01FF0000
+#define SRM_CSI1_CPD_GBC_0__CSI1_CPD_GBC0      0x1F0403F4,0x000001FF
+
+#define SRM_CSI1_CPD_GBC_1__ADDR                  0x1F0403F8
+#define SRM_CSI1_CPD_GBC_1__EMPTY      0x1F0403F8,0x00000000
+#define SRM_CSI1_CPD_GBC_1__FULL       0x1F0403F8,0xffffffff
+#define SRM_CSI1_CPD_GBC_1__CSI1_CPD_GBC3      0x1F0403F8,0x01FF0000
+#define SRM_CSI1_CPD_GBC_1__CSI1_CPD_GBC2      0x1F0403F8,0x000001FF
+
+#define SRM_CSI1_CPD_GBC_2__ADDR                  0x1F0403FC
+#define SRM_CSI1_CPD_GBC_2__EMPTY      0x1F0403FC,0x00000000
+#define SRM_CSI1_CPD_GBC_2__FULL       0x1F0403FC,0xffffffff
+#define SRM_CSI1_CPD_GBC_2__CSI1_CPD_GBC5      0x1F0403FC,0x01FF0000
+#define SRM_CSI1_CPD_GBC_2__CSI1_CPD_GBC4      0x1F0403FC,0x000001FF
+
+#define SRM_CSI1_CPD_GBC_3__ADDR                  0x1F040400
+#define SRM_CSI1_CPD_GBC_3__EMPTY      0x1F040400,0x00000000
+#define SRM_CSI1_CPD_GBC_3__FULL       0x1F040400,0xffffffff
+#define SRM_CSI1_CPD_GBC_3__CSI1_CPD_GBC7      0x1F040400,0x01FF0000
+#define SRM_CSI1_CPD_GBC_3__CSI1_CPD_GBC6      0x1F040400,0x000001FF
+
+#define SRM_CSI1_CPD_GBC_4__ADDR                  0x1F040404
+#define SRM_CSI1_CPD_GBC_4__EMPTY      0x1F040404,0x00000000
+#define SRM_CSI1_CPD_GBC_4__FULL       0x1F040404,0xffffffff
+#define SRM_CSI1_CPD_GBC_4__CSI1_CPD_GBC9      0x1F040404,0x01FF0000
+#define SRM_CSI1_CPD_GBC_4__CSI1_CPD_GBC8      0x1F040404,0x000001FF
+
+#define SRM_CSI1_CPD_GBC_5__ADDR                  0x1F040408
+#define SRM_CSI1_CPD_GBC_5__EMPTY      0x1F040408,0x00000000
+#define SRM_CSI1_CPD_GBC_5__FULL       0x1F040408,0xffffffff
+#define SRM_CSI1_CPD_GBC_5__CSI1_CPD_GBC11      0x1F040408,0x01FF0000
+#define SRM_CSI1_CPD_GBC_5__CSI1_CPD_GBC10      0x1F040408,0x000001FF
+
+#define SRM_CSI1_CPD_GBC_6__ADDR                  0x1F04040C
+#define SRM_CSI1_CPD_GBC_6__EMPTY      0x1F04040C,0x00000000
+#define SRM_CSI1_CPD_GBC_6__FULL       0x1F04040C,0xffffffff
+#define SRM_CSI1_CPD_GBC_6__CSI1_CPD_GBC13      0x1F04040C,0x01FF0000
+#define SRM_CSI1_CPD_GBC_6__CSI1_CPD_GBC12      0x1F04040C,0x000001FF
+
+#define SRM_CSI1_CPD_GBC_7__ADDR                  0x1F040410
+#define SRM_CSI1_CPD_GBC_7__EMPTY      0x1F040410,0x00000000
+#define SRM_CSI1_CPD_GBC_7__FULL       0x1F040410,0xffffffff
+#define SRM_CSI1_CPD_GBC_7__CSI1_CPD_GBC15      0x1F040410,0x01FF0000
+#define SRM_CSI1_CPD_GBC_7__CSI1_CPD_GBC14      0x1F040410,0x000001FF
+
+#define SRM_CSI1_CPD_GBS_0__ADDR                  0x1F040414
+#define SRM_CSI1_CPD_GBS_0__EMPTY      0x1F040414,0x00000000
+#define SRM_CSI1_CPD_GBS_0__FULL       0x1F040414,0xffffffff
+#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS3      0x1F040414,0xFF000000
+#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS2      0x1F040414,0x00FF0000
+#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS1      0x1F040414,0x0000FF00
+#define SRM_CSI1_CPD_GBS_0__CSI1_CPD_GBS0      0x1F040414,0x000000FF
+
+#define SRM_CSI1_CPD_GBS_1__ADDR                  0x1F040418
+#define SRM_CSI1_CPD_GBS_1__EMPTY      0x1F040418,0x00000000
+#define SRM_CSI1_CPD_GBS_1__FULL       0x1F040418,0xffffffff
+#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS7      0x1F040418,0xFF000000
+#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS6      0x1F040418,0x00FF0000
+#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS5      0x1F040418,0x0000FF00
+#define SRM_CSI1_CPD_GBS_1__CSI1_CPD_GBS4      0x1F040418,0x000000FF
+
+#define SRM_CSI1_CPD_GBS_2__ADDR                  0x1F04041C
+#define SRM_CSI1_CPD_GBS_2__EMPTY      0x1F04041C,0x00000000
+#define SRM_CSI1_CPD_GBS_2__FULL       0x1F04041C,0xffffffff
+#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS11      0x1F04041C,0xFF000000
+#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS10      0x1F04041C,0x00FF0000
+#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS9      0x1F04041C,0x0000FF00
+#define SRM_CSI1_CPD_GBS_2__CSI1_CPD_GBS8      0x1F04041C,0x000000FF
+
+#define SRM_CSI1_CPD_GBS_3__ADDR                  0x1F040420
+#define SRM_CSI1_CPD_GBS_3__EMPTY      0x1F040420,0x00000000
+#define SRM_CSI1_CPD_GBS_3__FULL       0x1F040420,0xffffffff
+#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS15      0x1F040420,0xFF000000
+#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS14      0x1F040420,0x00FF0000
+#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS13      0x1F040420,0x0000FF00
+#define SRM_CSI1_CPD_GBS_3__CSI1_CPD_GBS12      0x1F040420,0x000000FF
+
+#define SRM_CSI1_CPD_BC_0__ADDR                          0x1F040424
+#define SRM_CSI1_CPD_BC_0__EMPTY       0x1F040424,0x00000000
+#define SRM_CSI1_CPD_BC_0__FULL              0x1F040424,0xffffffff
+#define SRM_CSI1_CPD_BC_0__CSI1_CPD_BC1              0x1F040424,0x01FF0000
+#define SRM_CSI1_CPD_BC_0__CSI1_CPD_BC0              0x1F040424,0x000001FF
+
+#define SRM_CSI1_CPD_BC_1__ADDR                          0x1F040428
+#define SRM_CSI1_CPD_BC_1__EMPTY       0x1F040428,0x00000000
+#define SRM_CSI1_CPD_BC_1__FULL              0x1F040428,0xffffffff
+#define SRM_CSI1_CPD_BC_1__CSI1_CPD_BC3              0x1F040428,0x01FF0000
+#define SRM_CSI1_CPD_BC_1__CSI1_CPD_BC2              0x1F040428,0x000001FF
+
+#define SRM_CSI1_CPD_BC_2__ADDR                          0x1F04042C
+#define SRM_CSI1_CPD_BC_2__EMPTY       0x1F04042C,0x00000000
+#define SRM_CSI1_CPD_BC_2__FULL              0x1F04042C,0xffffffff
+#define SRM_CSI1_CPD_BC_2__CSI1_CPD_BC5              0x1F04042C,0x01FF0000
+#define SRM_CSI1_CPD_BC_2__CSI1_CPD_BC4              0x1F04042C,0x000001FF
+
+#define SRM_CSI1_CPD_BC_3__ADDR                          0x1F040430
+#define SRM_CSI1_CPD_BC_3__EMPTY       0x1F040430,0x00000000
+#define SRM_CSI1_CPD_BC_3__FULL              0x1F040430,0xffffffff
+#define SRM_CSI1_CPD_BC_3__CSI1_CPD_BC7              0x1F040430,0x01FF0000
+#define SRM_CSI1_CPD_BC_3__CSI1_CPD_BC6              0x1F040430,0x000001FF
+
+#define SRM_CSI1_CPD_BC_4__ADDR                          0x1F040434
+#define SRM_CSI1_CPD_BC_4__EMPTY       0x1F040434,0x00000000
+#define SRM_CSI1_CPD_BC_4__FULL              0x1F040434,0xffffffff
+#define SRM_CSI1_CPD_BC_4__CSI1_CPD_BC9              0x1F040434,0x01FF0000
+#define SRM_CSI1_CPD_BC_4__CSI1_CPD_BC8              0x1F040434,0x000001FF
+
+#define SRM_CSI1_CPD_BC_5__ADDR                          0x1F040438
+#define SRM_CSI1_CPD_BC_5__EMPTY       0x1F040438,0x00000000
+#define SRM_CSI1_CPD_BC_5__FULL              0x1F040438,0xffffffff
+#define SRM_CSI1_CPD_BC_5__CSI1_CPD_BC11       0x1F040438,0x01FF0000
+#define SRM_CSI1_CPD_BC_5__CSI1_CPD_BC10       0x1F040438,0x000001FF
+
+#define SRM_CSI1_CPD_BC_6__ADDR                          0x1F04043C
+#define SRM_CSI1_CPD_BC_6__EMPTY       0x1F04043C,0x00000000
+#define SRM_CSI1_CPD_BC_6__FULL              0x1F04043C,0xffffffff
+#define SRM_CSI1_CPD_BC_6__CSI1_CPD_BC13       0x1F04043C,0x01FF0000
+#define SRM_CSI1_CPD_BC_6__CSI1_CPD_BC12       0x1F04043C,0x000001FF
+
+#define SRM_CSI1_CPD_BC_7__ADDR                          0x1F040440
+#define SRM_CSI1_CPD_BC_7__EMPTY       0x1F040440,0x00000000
+#define SRM_CSI1_CPD_BC_7__FULL              0x1F040440,0xffffffff
+#define SRM_CSI1_CPD_BC_7__CSI1_CPD_BC15       0x1F040440,0x01FF0000
+#define SRM_CSI1_CPD_BC_7__CSI1_CPD_BC14       0x1F040440,0x000001FF
+
+#define SRM_CSI1_CPD_BS_0__ADDR                          0x1F040444
+#define SRM_CSI1_CPD_BS_0__EMPTY       0x1F040444,0x00000000
+#define SRM_CSI1_CPD_BS_0__FULL              0x1F040444,0xffffffff
+#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS3              0x1F040444,0xFF000000
+#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS2              0x1F040444,0x00FF0000
+#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS1              0x1F040444,0x0000FF00
+#define SRM_CSI1_CPD_BS_0__CSI1_CPD_BS0              0x1F040444,0x000000FF
+
+#define SRM_CSI1_CPD_BS_1__ADDR                          0x1F040448
+#define SRM_CSI1_CPD_BS_1__EMPTY       0x1F040448,0x00000000
+#define SRM_CSI1_CPD_BS_1__FULL              0x1F040448,0xffffffff
+#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS7              0x1F040448,0xFF000000
+#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS6              0x1F040448,0x00FF0000
+#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS5              0x1F040448,0x0000FF00
+#define SRM_CSI1_CPD_BS_1__CSI1_CPD_BS4              0x1F040448,0x000000FF
+
+#define SRM_CSI1_CPD_BS_2__ADDR                          0x1F04044C
+#define SRM_CSI1_CPD_BS_2__EMPTY       0x1F04044C,0x00000000
+#define SRM_CSI1_CPD_BS_2__FULL              0x1F04044C,0xffffffff
+#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS11       0x1F04044C,0xFF000000
+#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS10       0x1F04044C,0x00FF0000
+#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS9              0x1F04044C,0x0000FF00
+#define SRM_CSI1_CPD_BS_2__CSI1_CPD_BS8              0x1F04044C,0x000000FF
+
+#define SRM_CSI1_CPD_BS_3__ADDR                          0x1F040450
+#define SRM_CSI1_CPD_BS_3__EMPTY       0x1F040450,0x00000000
+#define SRM_CSI1_CPD_BS_3__FULL              0x1F040450,0xffffffff
+#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS15       0x1F040450,0xFF000000
+#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS14       0x1F040450,0x00FF0000
+#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS13       0x1F040450,0x0000FF00
+#define SRM_CSI1_CPD_BS_3__CSI1_CPD_BS12       0x1F040450,0x000000FF
+
+#define SRM_CSI1_CPD_OFFSET1__ADDR                  0x1F040454
+#define SRM_CSI1_CPD_OFFSET1__EMPTY      0x1F040454,0x00000000
+#define SRM_CSI1_CPD_OFFSET1__FULL      0x1F040454,0xffffffff
+#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_B_OFFSET              0x1F040454,0x3FF00000
+#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_GB_OFFSET       0x1F040454,0x000FFC00
+#define SRM_CSI1_CPD_OFFSET1__CSI1_CPD_GR_OFFSET       0x1F040454,0x000003FF
+
+#define SRM_CSI1_CPD_OFFSET2__ADDR                  0x1F040458
+#define SRM_CSI1_CPD_OFFSET2__EMPTY      0x1F040458,0x00000000
+#define SRM_CSI1_CPD_OFFSET2__FULL      0x1F040458,0xffffffff
+#define SRM_CSI1_CPD_OFFSET2__CSI1_CPD_R_OFFSET              0x1F040458,0x000003FF
+
+#define SRM_DI0_GENERAL__ADDR                  0x1F040494
+#define SRM_DI0_GENERAL__EMPTY      0x1F040494,0x00000000
+#define SRM_DI0_GENERAL__FULL      0x1F040494,0xffffffff
+#define SRM_DI0_GENERAL__DI0_DISP_Y_SEL              0x1F040494,0x70000000
+#define SRM_DI0_GENERAL__DI0_CLOCK_STOP_MODE      0x1F040494,0x0F000000
+#define SRM_DI0_GENERAL__DI0_DISP_CLOCK_INIT   0x1F040494,0x00800000
+#define SRM_DI0_GENERAL__DI0_MASK_SEL      0x1F040494,0x00400000
+#define SRM_DI0_GENERAL__DI0_VSYNC_EXT      0x1F040494,0x00200000
+#define SRM_DI0_GENERAL__DI0_CLK_EXT      0x1F040494,0x00100000
+#define SRM_DI0_GENERAL__DI0_WATCHDOG_MODE     0x1F040494,0x000C0000
+#define SRM_DI0_GENERAL__DI0_POLARITY_DISP_CLK      0x1F040494,0x00020000
+#define SRM_DI0_GENERAL__DI0_SYNC_COUNT_SEL      0x1F040494,0x0000F000
+#define SRM_DI0_GENERAL__DI0_ERR_TREATMENT      0x1F040494,0x00000800
+#define SRM_DI0_GENERAL__DI0_ERM_VSYNC_SEL     0x1F040494,0x00000400
+#define SRM_DI0_GENERAL__DI0_POLARITY_CS1      0x1F040494,0x00000200
+#define SRM_DI0_GENERAL__DI0_POLARITY_CS0      0x1F040494,0x00000100
+#define SRM_DI0_GENERAL__DI0_POLARITY_8              0x1F040494,0x00000080
+#define SRM_DI0_GENERAL__DI0_POLARITY_7              0x1F040494,0x00000040
+#define SRM_DI0_GENERAL__DI0_POLARITY_6              0x1F040494,0x00000020
+#define SRM_DI0_GENERAL__DI0_POLARITY_5              0x1F040494,0x00000010
+#define SRM_DI0_GENERAL__DI0_POLARITY_4              0x1F040494,0x00000008
+#define SRM_DI0_GENERAL__DI0_POLARITY_3              0x1F040494,0x00000004
+#define SRM_DI0_GENERAL__DI0_POLARITY_2              0x1F040494,0x00000002
+#define SRM_DI0_GENERAL__DI0_POLARITY_1              0x1F040494,0x00000001
+
+#define SRM_DI0_BS_CLKGEN0__ADDR                  0x1F040498
+#define SRM_DI0_BS_CLKGEN0__EMPTY      0x1F040498,0x00000000
+#define SRM_DI0_BS_CLKGEN0__FULL       0x1F040498,0xffffffff
+#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET              0x1F040498,0x01FF0000
+#define SRM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD              0x1F040498,0x00000FFF
+
+#define SRM_DI0_BS_CLKGEN1__ADDR                  0x1F04049C
+#define SRM_DI0_BS_CLKGEN1__EMPTY      0x1F04049C,0x00000000
+#define SRM_DI0_BS_CLKGEN1__FULL       0x1F04049C,0xffffffff
+#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN      0x1F04049C,0x01FF0000
+#define SRM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP      0x1F04049C,0x000001FF
+
+#define SRM_DI0_SW_GEN0_1__ADDR                          0x1F0404A0
+#define SRM_DI0_SW_GEN0_1__EMPTY       0x1F0404A0,0x00000000
+#define SRM_DI0_SW_GEN0_1__FULL              0x1F0404A0,0xffffffff
+#define SRM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1      0x1F0404A0,0x7FF80000
+#define SRM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1              0x1F0404A0,0x00070000
+#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1      0x1F0404A0,0x00007FF8
+#define SRM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1      0x1F0404A0,0x00000007
+
+#define SRM_DI0_SW_GEN0_2__ADDR                          0x1F0404A4
+#define SRM_DI0_SW_GEN0_2__EMPTY       0x1F0404A4,0x00000000
+#define SRM_DI0_SW_GEN0_2__FULL              0x1F0404A4,0xffffffff
+#define SRM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2      0x1F0404A4,0x7FF80000
+#define SRM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2              0x1F0404A4,0x00070000
+#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2      0x1F0404A4,0x00007FF8
+#define SRM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2      0x1F0404A4,0x00000007
+
+#define SRM_DI0_SW_GEN0_3__ADDR                          0x1F0404A8
+#define SRM_DI0_SW_GEN0_3__EMPTY       0x1F0404A8,0x00000000
+#define SRM_DI0_SW_GEN0_3__FULL              0x1F0404A8,0xffffffff
+#define SRM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3      0x1F0404A8,0x7FF80000
+#define SRM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3              0x1F0404A8,0x00070000
+#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3      0x1F0404A8,0x00007FF8
+#define SRM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3      0x1F0404A8,0x00000007
+
+#define SRM_DI0_SW_GEN0_4__ADDR                          0x1F0404AC
+#define SRM_DI0_SW_GEN0_4__EMPTY       0x1F0404AC,0x00000000
+#define SRM_DI0_SW_GEN0_4__FULL              0x1F0404AC,0xffffffff
+#define SRM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4      0x1F0404AC,0x7FF80000
+#define SRM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4              0x1F0404AC,0x00070000
+#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4      0x1F0404AC,0x00007FF8
+#define SRM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4      0x1F0404AC,0x00000007
+
+#define SRM_DI0_SW_GEN0_5__ADDR                          0x1F0404B0
+#define SRM_DI0_SW_GEN0_5__EMPTY       0x1F0404B0,0x00000000
+#define SRM_DI0_SW_GEN0_5__FULL              0x1F0404B0,0xffffffff
+#define SRM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5      0x1F0404B0,0x7FF80000
+#define SRM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5              0x1F0404B0,0x00070000
+#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5      0x1F0404B0,0x00007FF8
+#define SRM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5      0x1F0404B0,0x00000007
+
+#define SRM_DI0_SW_GEN0_6__ADDR                          0x1F0404B4
+#define SRM_DI0_SW_GEN0_6__EMPTY       0x1F0404B4,0x00000000
+#define SRM_DI0_SW_GEN0_6__FULL              0x1F0404B4,0xffffffff
+#define SRM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6      0x1F0404B4,0x7FF80000
+#define SRM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6              0x1F0404B4,0x00070000
+#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6      0x1F0404B4,0x00007FF8
+#define SRM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6      0x1F0404B4,0x00000007
+
+#define SRM_DI0_SW_GEN0_7__ADDR                          0x1F0404B8
+#define SRM_DI0_SW_GEN0_7__EMPTY       0x1F0404B8,0x00000000
+#define SRM_DI0_SW_GEN0_7__FULL              0x1F0404B8,0xffffffff
+#define SRM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7      0x1F0404B8,0x7FF80000
+#define SRM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7              0x1F0404B8,0x00070000
+#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7      0x1F0404B8,0x00007FF8
+#define SRM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7      0x1F0404B8,0x00000007
+
+#define SRM_DI0_SW_GEN0_8__ADDR                          0x1F0404BC
+#define SRM_DI0_SW_GEN0_8__EMPTY       0x1F0404BC,0x00000000
+#define SRM_DI0_SW_GEN0_8__FULL              0x1F0404BC,0xffffffff
+#define SRM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8      0x1F0404BC,0x7FF80000
+#define SRM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8              0x1F0404BC,0x00070000
+#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8      0x1F0404BC,0x00007FF8
+#define SRM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8      0x1F0404BC,0x00000007
+
+#define SRM_DI0_SW_GEN0_9__ADDR                          0x1F0404C0
+#define SRM_DI0_SW_GEN0_9__EMPTY       0x1F0404C0,0x00000000
+#define SRM_DI0_SW_GEN0_9__FULL              0x1F0404C0,0xffffffff
+#define SRM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9      0x1F0404C0,0x7FF80000
+#define SRM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9              0x1F0404C0,0x00070000
+#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9      0x1F0404C0,0x00007FF8
+#define SRM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9      0x1F0404C0,0x00000007
+
+#define SRM_DI0_SW_GEN1_1__ADDR                          0x1F0404C4
+#define SRM_DI0_SW_GEN1_1__EMPTY       0x1F0404C4,0x00000000
+#define SRM_DI0_SW_GEN1_1__FULL              0x1F0404C4,0xffffffff
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1      0x1F0404C4,0x60000000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1       0x1F0404C4,0x10000000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1      0x1F0404C4,0x0E000000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1      0x1F0404C4,0x01FF0000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1      0x1F0404C4,0x00007000
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1      0x1F0404C4,0x00000E00
+#define SRM_DI0_SW_GEN1_1__DI0_CNT_UP_1              0x1F0404C4,0x000001FF
+
+#define SRM_DI0_SW_GEN1_2__ADDR                          0x1F0404C8
+#define SRM_DI0_SW_GEN1_2__EMPTY       0x1F0404C8,0x00000000
+#define SRM_DI0_SW_GEN1_2__FULL              0x1F0404C8,0xffffffff
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2      0x1F0404C8,0x60000000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2       0x1F0404C8,0x10000000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2      0x1F0404C8,0x0E000000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2      0x1F0404C8,0x01FF0000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2      0x1F0404C8,0x00007000
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2      0x1F0404C8,0x00000E00
+#define SRM_DI0_SW_GEN1_2__DI0_CNT_UP_2              0x1F0404C8,0x000001FF
+
+#define SRM_DI0_SW_GEN1_3__ADDR                          0x1F0404CC
+#define SRM_DI0_SW_GEN1_3__EMPTY       0x1F0404CC,0x00000000
+#define SRM_DI0_SW_GEN1_3__FULL              0x1F0404CC,0xffffffff
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3      0x1F0404CC,0x60000000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3       0x1F0404CC,0x10000000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3      0x1F0404CC,0x0E000000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3      0x1F0404CC,0x01FF0000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3      0x1F0404CC,0x00007000
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3      0x1F0404CC,0x00000E00
+#define SRM_DI0_SW_GEN1_3__DI0_CNT_UP_3              0x1F0404CC,0x000001FF
+
+#define SRM_DI0_SW_GEN1_4__ADDR                          0x1F0404D0
+#define SRM_DI0_SW_GEN1_4__EMPTY       0x1F0404D0,0x00000000
+#define SRM_DI0_SW_GEN1_4__FULL              0x1F0404D0,0xffffffff
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4      0x1F0404D0,0x60000000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4       0x1F0404D0,0x10000000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4      0x1F0404D0,0x0E000000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4      0x1F0404D0,0x01FF0000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4      0x1F0404D0,0x00007000
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4      0x1F0404D0,0x00000E00
+#define SRM_DI0_SW_GEN1_4__DI0_CNT_UP_4              0x1F0404D0,0x000001FF
+
+#define SRM_DI0_SW_GEN1_5__ADDR                          0x1F0404D4
+#define SRM_DI0_SW_GEN1_5__EMPTY       0x1F0404D4,0x00000000
+#define SRM_DI0_SW_GEN1_5__FULL              0x1F0404D4,0xffffffff
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5      0x1F0404D4,0x60000000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5       0x1F0404D4,0x10000000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5      0x1F0404D4,0x0E000000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5      0x1F0404D4,0x01FF0000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5      0x1F0404D4,0x00007000
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5      0x1F0404D4,0x00000E00
+#define SRM_DI0_SW_GEN1_5__DI0_CNT_UP_5              0x1F0404D4,0x000001FF
+
+#define SRM_DI0_SW_GEN1_6__ADDR                          0x1F0404D8
+#define SRM_DI0_SW_GEN1_6__EMPTY       0x1F0404D8,0x00000000
+#define SRM_DI0_SW_GEN1_6__FULL              0x1F0404D8,0xffffffff
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6      0x1F0404D8,0x60000000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6       0x1F0404D8,0x10000000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6      0x1F0404D8,0x0E000000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6      0x1F0404D8,0x01FF0000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6      0x1F0404D8,0x00007000
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6      0x1F0404D8,0x00000E00
+#define SRM_DI0_SW_GEN1_6__DI0_CNT_UP_6              0x1F0404D8,0x000001FF
+
+#define SRM_DI0_SW_GEN1_7__ADDR                          0x1F0404DC
+#define SRM_DI0_SW_GEN1_7__EMPTY       0x1F0404DC,0x00000000
+#define SRM_DI0_SW_GEN1_7__FULL              0x1F0404DC,0xffffffff
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7      0x1F0404DC,0x60000000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7       0x1F0404DC,0x10000000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7      0x1F0404DC,0x0E000000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7      0x1F0404DC,0x01FF0000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7      0x1F0404DC,0x00007000
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7      0x1F0404DC,0x00000E00
+#define SRM_DI0_SW_GEN1_7__DI0_CNT_UP_7              0x1F0404DC,0x000001FF
+
+#define SRM_DI0_SW_GEN1_8__ADDR                          0x1F0404E0
+#define SRM_DI0_SW_GEN1_8__EMPTY       0x1F0404E0,0x00000000
+#define SRM_DI0_SW_GEN1_8__FULL              0x1F0404E0,0xffffffff
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8      0x1F0404E0,0x60000000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8       0x1F0404E0,0x10000000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8      0x1F0404E0,0x0E000000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8      0x1F0404E0,0x01FF0000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8      0x1F0404E0,0x00007000
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8      0x1F0404E0,0x00000E00
+#define SRM_DI0_SW_GEN1_8__DI0_CNT_UP_8              0x1F0404E0,0x000001FF
+
+#define SRM_DI0_SW_GEN1_9__ADDR                          0x1F0404E4
+#define SRM_DI0_SW_GEN1_9__EMPTY       0x1F0404E4,0x00000000
+#define SRM_DI0_SW_GEN1_9__FULL              0x1F0404E4,0xffffffff
+#define SRM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9      0x1F0404E4,0xE0000000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9       0x1F0404E4,0x10000000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9      0x1F0404E4,0x0E000000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9      0x1F0404E4,0x01FF0000
+#define SRM_DI0_SW_GEN1_9__DI0_TAG_SEL_9       0x1F0404E4,0x00008000
+#define SRM_DI0_SW_GEN1_9__DI0_CNT_UP_9              0x1F0404E4,0x000001FF
+
+#define SRM_DI0_SYNC_AS_GEN__ADDR                  0x1F0404E8
+#define SRM_DI0_SYNC_AS_GEN__EMPTY      0x1F0404E8,0x00000000
+#define SRM_DI0_SYNC_AS_GEN__FULL      0x1F0404E8,0xffffffff
+#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN      0x1F0404E8,0x10000000
+#define SRM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL      0x1F0404E8,0x0000E000
+#define SRM_DI0_SYNC_AS_GEN__DI0_SYNC_START      0x1F0404E8,0x00000FFF
+
+#define SRM_DI0_DW_GEN_0__ADDR                 0x1F0404EC
+#define SRM_DI0_DW_GEN_0__EMPTY                        0x1F0404EC,0x00000000
+#define SRM_DI0_DW_GEN_0__FULL                 0x1F0404EC,0xffffffff
+#define SRM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0    0x1F0404EC,0xFF000000
+#define SRM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0 0x1F0404EC,0x00FF0000
+#define SRM_DI0_DW_GEN_0__DI0_CST_0            0x1F0404EC,0x0000C000
+#define SRM_DI0_DW_GEN_0__DI0_PT_6_0           0x1F0404EC,0x00003000
+#define SRM_DI0_DW_GEN_0__DI0_PT_5_0           0x1F0404EC,0x00000C00
+#define SRM_DI0_DW_GEN_0__DI0_PT_4_0           0x1F0404EC,0x00000300
+#define SRM_DI0_DW_GEN_0__DI0_PT_3_0           0x1F0404EC,0x000000C0
+#define SRM_DI0_DW_GEN_0__DI0_PT_2_0           0x1F0404EC,0x00000030
+#define SRM_DI0_DW_GEN_0__DI0_PT_1_0           0x1F0404EC,0x0000000C
+#define SRM_DI0_DW_GEN_0__DI0_PT_0_0           0x1F0404EC,0x00000003
+
+#define SRM_DI0_DW_GEN_0__ADDR                   0x1F0404EC
+#define SRM_DI0_DW_GEN_0__EMPTY                          0x1F0404EC,0x00000000
+#define SRM_DI0_DW_GEN_0__FULL                   0x1F0404EC,0xffffffff
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0    0x1F0404EC,0xFF000000
+#define SRM_DI0_DW_GEN_0__DI0_START_PERIOD_0     0x1F0404EC,0x00FF0000
+#define SRM_DI0_DW_GEN_0__DI0_CST_0              0x1F0404EC,0x0000C000
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0 0x1F0404EC,0x000001F0
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_RS_0        0x1F0404EC,0x0000000C
+#define SRM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0       0x1F0404EC,0x00000003
+
+#define SRM_DI0_DW_GEN_1__ADDR                 0x1F0404F0
+#define SRM_DI0_DW_GEN_1__EMPTY                        0x1F0404F0,0x00000000
+#define SRM_DI0_DW_GEN_1__FULL                 0x1F0404F0,0xffffffff
+#define SRM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1    0x1F0404F0,0xFF000000
+#define SRM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1 0x1F0404F0,0x00FF0000
+#define SRM_DI0_DW_GEN_1__DI0_CST_1            0x1F0404F0,0x0000C000
+#define SRM_DI0_DW_GEN_1__DI0_PT_6_1           0x1F0404F0,0x00003000
+#define SRM_DI0_DW_GEN_1__DI0_PT_5_1           0x1F0404F0,0x00000C00
+#define SRM_DI0_DW_GEN_1__DI0_PT_4_1           0x1F0404F0,0x00000300
+#define SRM_DI0_DW_GEN_1__DI0_PT_3_1           0x1F0404F0,0x000000C0
+#define SRM_DI0_DW_GEN_1__DI0_PT_2_1           0x1F0404F0,0x00000030
+#define SRM_DI0_DW_GEN_1__DI0_PT_1_1           0x1F0404F0,0x0000000C
+#define SRM_DI0_DW_GEN_1__DI0_PT_0_1           0x1F0404F0,0x00000003
+
+#define SRM_DI0_DW_GEN_1__ADDR                   0x1F0404F0
+#define SRM_DI0_DW_GEN_1__EMPTY                          0x1F0404F0,0x00000000
+#define SRM_DI0_DW_GEN_1__FULL                   0x1F0404F0,0xffffffff
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1    0x1F0404F0,0xFF000000
+#define SRM_DI0_DW_GEN_1__DI0_START_PERIOD_1     0x1F0404F0,0x00FF0000
+#define SRM_DI0_DW_GEN_1__DI0_CST_1              0x1F0404F0,0x0000C000
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1 0x1F0404F0,0x000001F0
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_RS_1        0x1F0404F0,0x0000000C
+#define SRM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1       0x1F0404F0,0x00000003
+
+#define SRM_DI0_DW_GEN_2__ADDR                 0x1F0404F4
+#define SRM_DI0_DW_GEN_2__EMPTY                        0x1F0404F4,0x00000000
+#define SRM_DI0_DW_GEN_2__FULL                 0x1F0404F4,0xffffffff
+#define SRM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2    0x1F0404F4,0xFF000000
+#define SRM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2 0x1F0404F4,0x00FF0000
+#define SRM_DI0_DW_GEN_2__DI0_CST_2            0x1F0404F4,0x0000C000
+#define SRM_DI0_DW_GEN_2__DI0_PT_6_2           0x1F0404F4,0x00003000
+#define SRM_DI0_DW_GEN_2__DI0_PT_5_2           0x1F0404F4,0x00000C00
+#define SRM_DI0_DW_GEN_2__DI0_PT_4_2           0x1F0404F4,0x00000300
+#define SRM_DI0_DW_GEN_2__DI0_PT_3_2           0x1F0404F4,0x000000C0
+#define SRM_DI0_DW_GEN_2__DI0_PT_2_2           0x1F0404F4,0x00000030
+#define SRM_DI0_DW_GEN_2__DI0_PT_1_2           0x1F0404F4,0x0000000C
+#define SRM_DI0_DW_GEN_2__DI0_PT_0_2           0x1F0404F4,0x00000003
+
+#define SRM_DI0_DW_GEN_2__ADDR                   0x1F0404F4
+#define SRM_DI0_DW_GEN_2__EMPTY                          0x1F0404F4,0x00000000
+#define SRM_DI0_DW_GEN_2__FULL                   0x1F0404F4,0xffffffff
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2    0x1F0404F4,0xFF000000
+#define SRM_DI0_DW_GEN_2__DI0_START_PERIOD_2     0x1F0404F4,0x00FF0000
+#define SRM_DI0_DW_GEN_2__DI0_CST_2              0x1F0404F4,0x0000C000
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2 0x1F0404F4,0x000001F0
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_RS_2        0x1F0404F4,0x0000000C
+#define SRM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2       0x1F0404F4,0x00000003
+
+#define SRM_DI0_DW_GEN_3__ADDR                 0x1F0404F8
+#define SRM_DI0_DW_GEN_3__EMPTY                        0x1F0404F8,0x00000000
+#define SRM_DI0_DW_GEN_3__FULL                 0x1F0404F8,0xffffffff
+#define SRM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3    0x1F0404F8,0xFF000000
+#define SRM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3 0x1F0404F8,0x00FF0000
+#define SRM_DI0_DW_GEN_3__DI0_CST_3            0x1F0404F8,0x0000C000
+#define SRM_DI0_DW_GEN_3__DI0_PT_6_3           0x1F0404F8,0x00003000
+#define SRM_DI0_DW_GEN_3__DI0_PT_5_3           0x1F0404F8,0x00000C00
+#define SRM_DI0_DW_GEN_3__DI0_PT_4_3           0x1F0404F8,0x00000300
+#define SRM_DI0_DW_GEN_3__DI0_PT_3_3           0x1F0404F8,0x000000C0
+#define SRM_DI0_DW_GEN_3__DI0_PT_2_3           0x1F0404F8,0x00000030
+#define SRM_DI0_DW_GEN_3__DI0_PT_1_3           0x1F0404F8,0x0000000C
+#define SRM_DI0_DW_GEN_3__DI0_PT_0_3           0x1F0404F8,0x00000003
+
+#define SRM_DI0_DW_GEN_3__ADDR                   0x1F0404F8
+#define SRM_DI0_DW_GEN_3__EMPTY                          0x1F0404F8,0x00000000
+#define SRM_DI0_DW_GEN_3__FULL                   0x1F0404F8,0xffffffff
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3    0x1F0404F8,0xFF000000
+#define SRM_DI0_DW_GEN_3__DI0_START_PERIOD_3     0x1F0404F8,0x00FF0000
+#define SRM_DI0_DW_GEN_3__DI0_CST_3              0x1F0404F8,0x0000C000
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3 0x1F0404F8,0x000001F0
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_RS_3        0x1F0404F8,0x0000000C
+#define SRM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3       0x1F0404F8,0x00000003
+
+#define SRM_DI0_DW_GEN_4__ADDR                 0x1F0404FC
+#define SRM_DI0_DW_GEN_4__EMPTY                        0x1F0404FC,0x00000000
+#define SRM_DI0_DW_GEN_4__FULL                 0x1F0404FC,0xffffffff
+#define SRM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4    0x1F0404FC,0xFF000000
+#define SRM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4 0x1F0404FC,0x00FF0000
+#define SRM_DI0_DW_GEN_4__DI0_CST_4            0x1F0404FC,0x0000C000
+#define SRM_DI0_DW_GEN_4__DI0_PT_6_4           0x1F0404FC,0x00003000
+#define SRM_DI0_DW_GEN_4__DI0_PT_5_4           0x1F0404FC,0x00000C00
+#define SRM_DI0_DW_GEN_4__DI0_PT_4_4           0x1F0404FC,0x00000300
+#define SRM_DI0_DW_GEN_4__DI0_PT_3_4           0x1F0404FC,0x000000C0
+#define SRM_DI0_DW_GEN_4__DI0_PT_2_4           0x1F0404FC,0x00000030
+#define SRM_DI0_DW_GEN_4__DI0_PT_1_4           0x1F0404FC,0x0000000C
+#define SRM_DI0_DW_GEN_4__DI0_PT_0_4           0x1F0404FC,0x00000003
+
+#define SRM_DI0_DW_GEN_4__ADDR                   0x1F0404FC
+#define SRM_DI0_DW_GEN_4__EMPTY                          0x1F0404FC,0x00000000
+#define SRM_DI0_DW_GEN_4__FULL                   0x1F0404FC,0xffffffff
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4    0x1F0404FC,0xFF000000
+#define SRM_DI0_DW_GEN_4__DI0_START_PERIOD_4     0x1F0404FC,0x00FF0000
+#define SRM_DI0_DW_GEN_4__DI0_CST_4              0x1F0404FC,0x0000C000
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4 0x1F0404FC,0x000001F0
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_RS_4        0x1F0404FC,0x0000000C
+#define SRM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4       0x1F0404FC,0x00000003
+
+#define SRM_DI0_DW_GEN_5__ADDR                 0x1F040500
+#define SRM_DI0_DW_GEN_5__EMPTY                        0x1F040500,0x00000000
+#define SRM_DI0_DW_GEN_5__FULL                 0x1F040500,0xffffffff
+#define SRM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5    0x1F040500,0xFF000000
+#define SRM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5 0x1F040500,0x00FF0000
+#define SRM_DI0_DW_GEN_5__DI0_CST_5            0x1F040500,0x0000C000
+#define SRM_DI0_DW_GEN_5__DI0_PT_6_5           0x1F040500,0x00003000
+#define SRM_DI0_DW_GEN_5__DI0_PT_5_5           0x1F040500,0x00000C00
+#define SRM_DI0_DW_GEN_5__DI0_PT_4_5           0x1F040500,0x00000300
+#define SRM_DI0_DW_GEN_5__DI0_PT_3_5           0x1F040500,0x000000C0
+#define SRM_DI0_DW_GEN_5__DI0_PT_2_5           0x1F040500,0x00000030
+#define SRM_DI0_DW_GEN_5__DI0_PT_1_5           0x1F040500,0x0000000C
+#define SRM_DI0_DW_GEN_5__DI0_PT_0_5           0x1F040500,0x00000003
+
+#define SRM_DI0_DW_GEN_5__ADDR                   0x1F040500
+#define SRM_DI0_DW_GEN_5__EMPTY                          0x1F040500,0x00000000
+#define SRM_DI0_DW_GEN_5__FULL                   0x1F040500,0xffffffff
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5    0x1F040500,0xFF000000
+#define SRM_DI0_DW_GEN_5__DI0_START_PERIOD_5     0x1F040500,0x00FF0000
+#define SRM_DI0_DW_GEN_5__DI0_CST_5              0x1F040500,0x0000C000
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5 0x1F040500,0x000001F0
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_RS_5        0x1F040500,0x0000000C
+#define SRM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5       0x1F040500,0x00000003
+
+#define SRM_DI0_DW_GEN_6__ADDR                 0x1F040504
+#define SRM_DI0_DW_GEN_6__EMPTY                        0x1F040504,0x00000000
+#define SRM_DI0_DW_GEN_6__FULL                 0x1F040504,0xffffffff
+#define SRM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6    0x1F040504,0xFF000000
+#define SRM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6 0x1F040504,0x00FF0000
+#define SRM_DI0_DW_GEN_6__DI0_CST_6            0x1F040504,0x0000C000
+#define SRM_DI0_DW_GEN_6__DI0_PT_6_6           0x1F040504,0x00003000
+#define SRM_DI0_DW_GEN_6__DI0_PT_5_6           0x1F040504,0x00000C00
+#define SRM_DI0_DW_GEN_6__DI0_PT_4_6           0x1F040504,0x00000300
+#define SRM_DI0_DW_GEN_6__DI0_PT_3_6           0x1F040504,0x000000C0
+#define SRM_DI0_DW_GEN_6__DI0_PT_2_6           0x1F040504,0x00000030
+#define SRM_DI0_DW_GEN_6__DI0_PT_1_6           0x1F040504,0x0000000C
+#define SRM_DI0_DW_GEN_6__DI0_PT_0_6           0x1F040504,0x00000003
+
+#define SRM_DI0_DW_GEN_6__ADDR                   0x1F040504
+#define SRM_DI0_DW_GEN_6__EMPTY                          0x1F040504,0x00000000
+#define SRM_DI0_DW_GEN_6__FULL                   0x1F040504,0xffffffff
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6    0x1F040504,0xFF000000
+#define SRM_DI0_DW_GEN_6__DI0_START_PERIOD_6     0x1F040504,0x00FF0000
+#define SRM_DI0_DW_GEN_6__DI0_CST_6              0x1F040504,0x0000C000
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6 0x1F040504,0x000001F0
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_RS_6        0x1F040504,0x0000000C
+#define SRM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6       0x1F040504,0x00000003
+
+#define SRM_DI0_DW_GEN_7__ADDR                 0x1F040508
+#define SRM_DI0_DW_GEN_7__EMPTY                        0x1F040508,0x00000000
+#define SRM_DI0_DW_GEN_7__FULL                 0x1F040508,0xffffffff
+#define SRM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7    0x1F040508,0xFF000000
+#define SRM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7 0x1F040508,0x00FF0000
+#define SRM_DI0_DW_GEN_7__DI0_CST_7            0x1F040508,0x0000C000
+#define SRM_DI0_DW_GEN_7__DI0_PT_6_7           0x1F040508,0x00003000
+#define SRM_DI0_DW_GEN_7__DI0_PT_5_7           0x1F040508,0x00000C00
+#define SRM_DI0_DW_GEN_7__DI0_PT_4_7           0x1F040508,0x00000300
+#define SRM_DI0_DW_GEN_7__DI0_PT_3_7           0x1F040508,0x000000C0
+#define SRM_DI0_DW_GEN_7__DI0_PT_2_7           0x1F040508,0x00000030
+#define SRM_DI0_DW_GEN_7__DI0_PT_1_7           0x1F040508,0x0000000C
+#define SRM_DI0_DW_GEN_7__DI0_PT_0_7           0x1F040508,0x00000003
+
+#define SRM_DI0_DW_GEN_7__ADDR                   0x1F040508
+#define SRM_DI0_DW_GEN_7__EMPTY                          0x1F040508,0x00000000
+#define SRM_DI0_DW_GEN_7__FULL                   0x1F040508,0xffffffff
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7    0x1F040508,0xFF000000
+#define SRM_DI0_DW_GEN_7__DI0_START_PERIOD_7     0x1F040508,0x00FF0000
+#define SRM_DI0_DW_GEN_7__DI0_CST_7              0x1F040508,0x0000C000
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7 0x1F040508,0x000001F0
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_RS_7        0x1F040508,0x0000000C
+#define SRM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7       0x1F040508,0x00000003
+
+#define SRM_DI0_DW_GEN_8__ADDR                 0x1F04050C
+#define SRM_DI0_DW_GEN_8__EMPTY                        0x1F04050C,0x00000000
+#define SRM_DI0_DW_GEN_8__FULL                 0x1F04050C,0xffffffff
+#define SRM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8    0x1F04050C,0xFF000000
+#define SRM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8 0x1F04050C,0x00FF0000
+#define SRM_DI0_DW_GEN_8__DI0_CST_8            0x1F04050C,0x0000C000
+#define SRM_DI0_DW_GEN_8__DI0_PT_6_8           0x1F04050C,0x00003000
+#define SRM_DI0_DW_GEN_8__DI0_PT_5_8           0x1F04050C,0x00000C00
+#define SRM_DI0_DW_GEN_8__DI0_PT_4_8           0x1F04050C,0x00000300
+#define SRM_DI0_DW_GEN_8__DI0_PT_3_8           0x1F04050C,0x000000C0
+#define SRM_DI0_DW_GEN_8__DI0_PT_2_8           0x1F04050C,0x00000030
+#define SRM_DI0_DW_GEN_8__DI0_PT_1_8           0x1F04050C,0x0000000C
+#define SRM_DI0_DW_GEN_8__DI0_PT_0_8           0x1F04050C,0x00000003
+
+#define SRM_DI0_DW_GEN_8__ADDR                   0x1F04050C
+#define SRM_DI0_DW_GEN_8__EMPTY                          0x1F04050C,0x00000000
+#define SRM_DI0_DW_GEN_8__FULL                   0x1F04050C,0xffffffff
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8    0x1F04050C,0xFF000000
+#define SRM_DI0_DW_GEN_8__DI0_START_PERIOD_8     0x1F04050C,0x00FF0000
+#define SRM_DI0_DW_GEN_8__DI0_CST_8              0x1F04050C,0x0000C000
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8 0x1F04050C,0x000001F0
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_RS_8        0x1F04050C,0x0000000C
+#define SRM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8       0x1F04050C,0x00000003
+
+#define SRM_DI0_DW_GEN_9__ADDR                 0x1F040510
+#define SRM_DI0_DW_GEN_9__EMPTY                        0x1F040510,0x00000000
+#define SRM_DI0_DW_GEN_9__FULL                 0x1F040510,0xffffffff
+#define SRM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9    0x1F040510,0xFF000000
+#define SRM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9 0x1F040510,0x00FF0000
+#define SRM_DI0_DW_GEN_9__DI0_CST_9            0x1F040510,0x0000C000
+#define SRM_DI0_DW_GEN_9__DI0_PT_6_9           0x1F040510,0x00003000
+#define SRM_DI0_DW_GEN_9__DI0_PT_5_9           0x1F040510,0x00000C00
+#define SRM_DI0_DW_GEN_9__DI0_PT_4_9           0x1F040510,0x00000300
+#define SRM_DI0_DW_GEN_9__DI0_PT_3_9           0x1F040510,0x000000C0
+#define SRM_DI0_DW_GEN_9__DI0_PT_2_9           0x1F040510,0x00000030
+#define SRM_DI0_DW_GEN_9__DI0_PT_1_9           0x1F040510,0x0000000C
+#define SRM_DI0_DW_GEN_9__DI0_PT_0_9           0x1F040510,0x00000003
+
+#define SRM_DI0_DW_GEN_9__ADDR                   0x1F040510
+#define SRM_DI0_DW_GEN_9__EMPTY                          0x1F040510,0x00000000
+#define SRM_DI0_DW_GEN_9__FULL                   0x1F040510,0xffffffff
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9    0x1F040510,0xFF000000
+#define SRM_DI0_DW_GEN_9__DI0_START_PERIOD_9     0x1F040510,0x00FF0000
+#define SRM_DI0_DW_GEN_9__DI0_CST_9              0x1F040510,0x0000C000
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9 0x1F040510,0x000001F0
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_RS_9        0x1F040510,0x0000000C
+#define SRM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9       0x1F040510,0x00000003
+
+#define SRM_DI0_DW_GEN_10__ADDR                          0x1F040514
+#define SRM_DI0_DW_GEN_10__EMPTY                 0x1F040514,0x00000000
+#define SRM_DI0_DW_GEN_10__FULL                          0x1F040514,0xffffffff
+#define SRM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10    0x1F040514,0xFF000000
+#define SRM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10 0x1F040514,0x00FF0000
+#define SRM_DI0_DW_GEN_10__DI0_CST_10            0x1F040514,0x0000C000
+#define SRM_DI0_DW_GEN_10__DI0_PT_6_10           0x1F040514,0x00003000
+#define SRM_DI0_DW_GEN_10__DI0_PT_5_10           0x1F040514,0x00000C00
+#define SRM_DI0_DW_GEN_10__DI0_PT_4_10           0x1F040514,0x00000300
+#define SRM_DI0_DW_GEN_10__DI0_PT_3_10           0x1F040514,0x000000C0
+#define SRM_DI0_DW_GEN_10__DI0_PT_2_10           0x1F040514,0x00000030
+#define SRM_DI0_DW_GEN_10__DI0_PT_1_10           0x1F040514,0x0000000C
+#define SRM_DI0_DW_GEN_10__DI0_PT_0_10           0x1F040514,0x00000003
+
+#define SRM_DI0_DW_GEN_10__ADDR                            0x1F040514
+#define SRM_DI0_DW_GEN_10__EMPTY                   0x1F040514,0x00000000
+#define SRM_DI0_DW_GEN_10__FULL                            0x1F040514,0xffffffff
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10            0x1F040514,0xFF000000
+#define SRM_DI0_DW_GEN_10__DI0_START_PERIOD_10     0x1F040514,0x00FF0000
+#define SRM_DI0_DW_GEN_10__DI0_CST_10              0x1F040514,0x0000C000
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040514,0x000001F0
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_RS_10        0x1F040514,0x0000000C
+#define SRM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10       0x1F040514,0x00000003
+
+#define SRM_DI0_DW_GEN_11__ADDR                          0x1F040518
+#define SRM_DI0_DW_GEN_11__EMPTY                 0x1F040518,0x00000000
+#define SRM_DI0_DW_GEN_11__FULL                          0x1F040518,0xffffffff
+#define SRM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11    0x1F040518,0xFF000000
+#define SRM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11 0x1F040518,0x00FF0000
+#define SRM_DI0_DW_GEN_11__DI0_CST_11            0x1F040518,0x0000C000
+#define SRM_DI0_DW_GEN_11__DI0_PT_6_11           0x1F040518,0x00003000
+#define SRM_DI0_DW_GEN_11__DI0_PT_5_11           0x1F040518,0x00000C00
+#define SRM_DI0_DW_GEN_11__DI0_PT_4_11           0x1F040518,0x00000300
+#define SRM_DI0_DW_GEN_11__DI0_PT_3_11           0x1F040518,0x000000C0
+#define SRM_DI0_DW_GEN_11__DI0_PT_2_11           0x1F040518,0x00000030
+#define SRM_DI0_DW_GEN_11__DI0_PT_1_11           0x1F040518,0x0000000C
+#define SRM_DI0_DW_GEN_11__DI0_PT_0_11           0x1F040518,0x00000003
+
+#define SRM_DI0_DW_GEN_11__ADDR                            0x1F040518
+#define SRM_DI0_DW_GEN_11__EMPTY                   0x1F040518,0x00000000
+#define SRM_DI0_DW_GEN_11__FULL                            0x1F040518,0xffffffff
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11            0x1F040518,0xFF000000
+#define SRM_DI0_DW_GEN_11__DI0_START_PERIOD_11     0x1F040518,0x00FF0000
+#define SRM_DI0_DW_GEN_11__DI0_CST_11              0x1F040518,0x0000C000
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F040518,0x000001F0
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_RS_11        0x1F040518,0x0000000C
+#define SRM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11       0x1F040518,0x00000003
+
+#define SRM_DI0_DW_SET0_0__ADDR                          0x1F04051C
+#define SRM_DI0_DW_SET0_0__EMPTY       0x1F04051C,0x00000000
+#define SRM_DI0_DW_SET0_0__FULL              0x1F04051C,0xffffffff
+#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0              0x1F04051C,0x01FF0000
+#define SRM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0      0x1F04051C,0x000001FF
+
+#define SRM_DI0_DW_SET0_1__ADDR                          0x1F040520
+#define SRM_DI0_DW_SET0_1__EMPTY       0x1F040520,0x00000000
+#define SRM_DI0_DW_SET0_1__FULL              0x1F040520,0xffffffff
+#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1              0x1F040520,0x01FF0000
+#define SRM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1      0x1F040520,0x000001FF
+
+#define SRM_DI0_DW_SET0_2__ADDR                          0x1F040524
+#define SRM_DI0_DW_SET0_2__EMPTY       0x1F040524,0x00000000
+#define SRM_DI0_DW_SET0_2__FULL              0x1F040524,0xffffffff
+#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2              0x1F040524,0x01FF0000
+#define SRM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2      0x1F040524,0x000001FF
+
+#define SRM_DI0_DW_SET0_3__ADDR                          0x1F040528
+#define SRM_DI0_DW_SET0_3__EMPTY       0x1F040528,0x00000000
+#define SRM_DI0_DW_SET0_3__FULL              0x1F040528,0xffffffff
+#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3              0x1F040528,0x01FF0000
+#define SRM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3      0x1F040528,0x000001FF
+
+#define SRM_DI0_DW_SET0_4__ADDR                          0x1F04052C
+#define SRM_DI0_DW_SET0_4__EMPTY       0x1F04052C,0x00000000
+#define SRM_DI0_DW_SET0_4__FULL              0x1F04052C,0xffffffff
+#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4              0x1F04052C,0x01FF0000
+#define SRM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4      0x1F04052C,0x000001FF
+
+#define SRM_DI0_DW_SET0_5__ADDR                          0x1F040530
+#define SRM_DI0_DW_SET0_5__EMPTY       0x1F040530,0x00000000
+#define SRM_DI0_DW_SET0_5__FULL              0x1F040530,0xffffffff
+#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5              0x1F040530,0x01FF0000
+#define SRM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5      0x1F040530,0x000001FF
+
+#define SRM_DI0_DW_SET0_6__ADDR                          0x1F040534
+#define SRM_DI0_DW_SET0_6__EMPTY       0x1F040534,0x00000000
+#define SRM_DI0_DW_SET0_6__FULL              0x1F040534,0xffffffff
+#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6              0x1F040534,0x01FF0000
+#define SRM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6      0x1F040534,0x000001FF
+
+#define SRM_DI0_DW_SET0_7__ADDR                          0x1F040538
+#define SRM_DI0_DW_SET0_7__EMPTY       0x1F040538,0x00000000
+#define SRM_DI0_DW_SET0_7__FULL              0x1F040538,0xffffffff
+#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7              0x1F040538,0x01FF0000
+#define SRM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7      0x1F040538,0x000001FF
+
+#define SRM_DI0_DW_SET0_8__ADDR                          0x1F04053C
+#define SRM_DI0_DW_SET0_8__EMPTY       0x1F04053C,0x00000000
+#define SRM_DI0_DW_SET0_8__FULL              0x1F04053C,0xffffffff
+#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8              0x1F04053C,0x01FF0000
+#define SRM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8      0x1F04053C,0x000001FF
+
+#define SRM_DI0_DW_SET0_9__ADDR                          0x1F040540
+#define SRM_DI0_DW_SET0_9__EMPTY       0x1F040540,0x00000000
+#define SRM_DI0_DW_SET0_9__FULL              0x1F040540,0xffffffff
+#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9              0x1F040540,0x01FF0000
+#define SRM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9      0x1F040540,0x000001FF
+
+#define SRM_DI0_DW_SET0_10__ADDR                  0x1F040544
+#define SRM_DI0_DW_SET0_10__EMPTY      0x1F040544,0x00000000
+#define SRM_DI0_DW_SET0_10__FULL       0x1F040544,0xffffffff
+#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10      0x1F040544,0x01FF0000
+#define SRM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10              0x1F040544,0x000001FF
+
+#define SRM_DI0_DW_SET0_11__ADDR                  0x1F040548
+#define SRM_DI0_DW_SET0_11__EMPTY      0x1F040548,0x00000000
+#define SRM_DI0_DW_SET0_11__FULL       0x1F040548,0xffffffff
+#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11      0x1F040548,0x01FF0000
+#define SRM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11              0x1F040548,0x000001FF
+
+#define SRM_DI0_DW_SET1_0__ADDR                          0x1F04054C
+#define SRM_DI0_DW_SET1_0__EMPTY       0x1F04054C,0x00000000
+#define SRM_DI0_DW_SET1_0__FULL              0x1F04054C,0xffffffff
+#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0              0x1F04054C,0x01FF0000
+#define SRM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0      0x1F04054C,0x000001FF
+
+#define SRM_DI0_DW_SET1_1__ADDR                          0x1F040550
+#define SRM_DI0_DW_SET1_1__EMPTY       0x1F040550,0x00000000
+#define SRM_DI0_DW_SET1_1__FULL              0x1F040550,0xffffffff
+#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1              0x1F040550,0x01FF0000
+#define SRM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1      0x1F040550,0x000001FF
+
+#define SRM_DI0_DW_SET1_2__ADDR                          0x1F040554
+#define SRM_DI0_DW_SET1_2__EMPTY       0x1F040554,0x00000000
+#define SRM_DI0_DW_SET1_2__FULL              0x1F040554,0xffffffff
+#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2              0x1F040554,0x01FF0000
+#define SRM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2      0x1F040554,0x000001FF
+
+#define SRM_DI0_DW_SET1_3__ADDR                          0x1F040558
+#define SRM_DI0_DW_SET1_3__EMPTY       0x1F040558,0x00000000
+#define SRM_DI0_DW_SET1_3__FULL              0x1F040558,0xffffffff
+#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3              0x1F040558,0x01FF0000
+#define SRM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3      0x1F040558,0x000001FF
+
+#define SRM_DI0_DW_SET1_4__ADDR                          0x1F04055C
+#define SRM_DI0_DW_SET1_4__EMPTY       0x1F04055C,0x00000000
+#define SRM_DI0_DW_SET1_4__FULL              0x1F04055C,0xffffffff
+#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4              0x1F04055C,0x01FF0000
+#define SRM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4      0x1F04055C,0x000001FF
+
+#define SRM_DI0_DW_SET1_5__ADDR                          0x1F040560
+#define SRM_DI0_DW_SET1_5__EMPTY       0x1F040560,0x00000000
+#define SRM_DI0_DW_SET1_5__FULL              0x1F040560,0xffffffff
+#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5              0x1F040560,0x01FF0000
+#define SRM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5      0x1F040560,0x000001FF
+
+#define SRM_DI0_DW_SET1_6__ADDR                          0x1F040564
+#define SRM_DI0_DW_SET1_6__EMPTY       0x1F040564,0x00000000
+#define SRM_DI0_DW_SET1_6__FULL              0x1F040564,0xffffffff
+#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6              0x1F040564,0x01FF0000
+#define SRM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6      0x1F040564,0x000001FF
+
+#define SRM_DI0_DW_SET1_7__ADDR                          0x1F040568
+#define SRM_DI0_DW_SET1_7__EMPTY       0x1F040568,0x00000000
+#define SRM_DI0_DW_SET1_7__FULL              0x1F040568,0xffffffff
+#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7              0x1F040568,0x01FF0000
+#define SRM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7      0x1F040568,0x000001FF
+
+#define SRM_DI0_DW_SET1_8__ADDR                          0x1F04056C
+#define SRM_DI0_DW_SET1_8__EMPTY       0x1F04056C,0x00000000
+#define SRM_DI0_DW_SET1_8__FULL              0x1F04056C,0xffffffff
+#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8              0x1F04056C,0x01FF0000
+#define SRM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8      0x1F04056C,0x000001FF
+
+#define SRM_DI0_DW_SET1_9__ADDR                          0x1F040570
+#define SRM_DI0_DW_SET1_9__EMPTY       0x1F040570,0x00000000
+#define SRM_DI0_DW_SET1_9__FULL              0x1F040570,0xffffffff
+#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9              0x1F040570,0x01FF0000
+#define SRM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9      0x1F040570,0x000001FF
+
+#define SRM_DI0_DW_SET1_10__ADDR                  0x1F040574
+#define SRM_DI0_DW_SET1_10__EMPTY      0x1F040574,0x00000000
+#define SRM_DI0_DW_SET1_10__FULL       0x1F040574,0xffffffff
+#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10      0x1F040574,0x01FF0000
+#define SRM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10              0x1F040574,0x000001FF
+
+#define SRM_DI0_DW_SET1_11__ADDR                  0x1F040578
+#define SRM_DI0_DW_SET1_11__EMPTY      0x1F040578,0x00000000
+#define SRM_DI0_DW_SET1_11__FULL       0x1F040578,0xffffffff
+#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11      0x1F040578,0x01FF0000
+#define SRM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11              0x1F040578,0x000001FF
+
+#define SRM_DI0_DW_SET2_0__ADDR                          0x1F04057C
+#define SRM_DI0_DW_SET2_0__EMPTY       0x1F04057C,0x00000000
+#define SRM_DI0_DW_SET2_0__FULL              0x1F04057C,0xffffffff
+#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0              0x1F04057C,0x01FF0000
+#define SRM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0      0x1F04057C,0x000001FF
+
+#define SRM_DI0_DW_SET2_1__ADDR                          0x1F040580
+#define SRM_DI0_DW_SET2_1__EMPTY       0x1F040580,0x00000000
+#define SRM_DI0_DW_SET2_1__FULL              0x1F040580,0xffffffff
+#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1              0x1F040580,0x01FF0000
+#define SRM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1      0x1F040580,0x000001FF
+
+#define SRM_DI0_DW_SET2_2__ADDR                          0x1F040584
+#define SRM_DI0_DW_SET2_2__EMPTY       0x1F040584,0x00000000
+#define SRM_DI0_DW_SET2_2__FULL              0x1F040584,0xffffffff
+#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2              0x1F040584,0x01FF0000
+#define SRM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2      0x1F040584,0x000001FF
+
+#define SRM_DI0_DW_SET2_3__ADDR                          0x1F040588
+#define SRM_DI0_DW_SET2_3__EMPTY       0x1F040588,0x00000000
+#define SRM_DI0_DW_SET2_3__FULL              0x1F040588,0xffffffff
+#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3              0x1F040588,0x01FF0000
+#define SRM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3      0x1F040588,0x000001FF
+
+#define SRM_DI0_DW_SET2_4__ADDR                          0x1F04058C
+#define SRM_DI0_DW_SET2_4__EMPTY       0x1F04058C,0x00000000
+#define SRM_DI0_DW_SET2_4__FULL              0x1F04058C,0xffffffff
+#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4              0x1F04058C,0x01FF0000
+#define SRM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4      0x1F04058C,0x000001FF
+
+#define SRM_DI0_DW_SET2_5__ADDR                          0x1F040590
+#define SRM_DI0_DW_SET2_5__EMPTY       0x1F040590,0x00000000
+#define SRM_DI0_DW_SET2_5__FULL              0x1F040590,0xffffffff
+#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5              0x1F040590,0x01FF0000
+#define SRM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5      0x1F040590,0x000001FF
+
+#define SRM_DI0_DW_SET2_6__ADDR                          0x1F040594
+#define SRM_DI0_DW_SET2_6__EMPTY       0x1F040594,0x00000000
+#define SRM_DI0_DW_SET2_6__FULL              0x1F040594,0xffffffff
+#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6              0x1F040594,0x01FF0000
+#define SRM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6      0x1F040594,0x000001FF
+
+#define SRM_DI0_DW_SET2_7__ADDR                          0x1F040598
+#define SRM_DI0_DW_SET2_7__EMPTY       0x1F040598,0x00000000
+#define SRM_DI0_DW_SET2_7__FULL              0x1F040598,0xffffffff
+#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7              0x1F040598,0x01FF0000
+#define SRM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7      0x1F040598,0x000001FF
+
+#define SRM_DI0_DW_SET2_8__ADDR                          0x1F04059C
+#define SRM_DI0_DW_SET2_8__EMPTY       0x1F04059C,0x00000000
+#define SRM_DI0_DW_SET2_8__FULL              0x1F04059C,0xffffffff
+#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8              0x1F04059C,0x01FF0000
+#define SRM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8      0x1F04059C,0x000001FF
+
+#define SRM_DI0_DW_SET2_9__ADDR                          0x1F0405A0
+#define SRM_DI0_DW_SET2_9__EMPTY       0x1F0405A0,0x00000000
+#define SRM_DI0_DW_SET2_9__FULL              0x1F0405A0,0xffffffff
+#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9              0x1F0405A0,0x01FF0000
+#define SRM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9      0x1F0405A0,0x000001FF
+
+#define SRM_DI0_DW_SET2_10__ADDR                  0x1F0405A4
+#define SRM_DI0_DW_SET2_10__EMPTY      0x1F0405A4,0x00000000
+#define SRM_DI0_DW_SET2_10__FULL       0x1F0405A4,0xffffffff
+#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10      0x1F0405A4,0x01FF0000
+#define SRM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10              0x1F0405A4,0x000001FF
+
+#define SRM_DI0_DW_SET2_11__ADDR                  0x1F0405A8
+#define SRM_DI0_DW_SET2_11__EMPTY      0x1F0405A8,0x00000000
+#define SRM_DI0_DW_SET2_11__FULL       0x1F0405A8,0xffffffff
+#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11      0x1F0405A8,0x01FF0000
+#define SRM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11              0x1F0405A8,0x000001FF
+
+#define SRM_DI0_DW_SET3_0__ADDR                          0x1F0405AC
+#define SRM_DI0_DW_SET3_0__EMPTY       0x1F0405AC,0x00000000
+#define SRM_DI0_DW_SET3_0__FULL              0x1F0405AC,0xffffffff
+#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0              0x1F0405AC,0x01FF0000
+#define SRM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0      0x1F0405AC,0x000001FF
+
+#define SRM_DI0_DW_SET3_1__ADDR                          0x1F0405B0
+#define SRM_DI0_DW_SET3_1__EMPTY       0x1F0405B0,0x00000000
+#define SRM_DI0_DW_SET3_1__FULL              0x1F0405B0,0xffffffff
+#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1              0x1F0405B0,0x01FF0000
+#define SRM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1      0x1F0405B0,0x000001FF
+
+#define SRM_DI0_DW_SET3_2__ADDR                          0x1F0405B4
+#define SRM_DI0_DW_SET3_2__EMPTY       0x1F0405B4,0x00000000
+#define SRM_DI0_DW_SET3_2__FULL              0x1F0405B4,0xffffffff
+#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2              0x1F0405B4,0x01FF0000
+#define SRM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2      0x1F0405B4,0x000001FF
+
+#define SRM_DI0_DW_SET3_3__ADDR                          0x1F0405B8
+#define SRM_DI0_DW_SET3_3__EMPTY       0x1F0405B8,0x00000000
+#define SRM_DI0_DW_SET3_3__FULL              0x1F0405B8,0xffffffff
+#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3              0x1F0405B8,0x01FF0000
+#define SRM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3      0x1F0405B8,0x000001FF
+
+#define SRM_DI0_DW_SET3_4__ADDR                          0x1F0405BC
+#define SRM_DI0_DW_SET3_4__EMPTY       0x1F0405BC,0x00000000
+#define SRM_DI0_DW_SET3_4__FULL              0x1F0405BC,0xffffffff
+#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4              0x1F0405BC,0x01FF0000
+#define SRM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4      0x1F0405BC,0x000001FF
+
+#define SRM_DI0_DW_SET3_5__ADDR                          0x1F0405C0
+#define SRM_DI0_DW_SET3_5__EMPTY       0x1F0405C0,0x00000000
+#define SRM_DI0_DW_SET3_5__FULL              0x1F0405C0,0xffffffff
+#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5              0x1F0405C0,0x01FF0000
+#define SRM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5      0x1F0405C0,0x000001FF
+
+#define SRM_DI0_DW_SET3_6__ADDR                          0x1F0405C4
+#define SRM_DI0_DW_SET3_6__EMPTY       0x1F0405C4,0x00000000
+#define SRM_DI0_DW_SET3_6__FULL              0x1F0405C4,0xffffffff
+#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6              0x1F0405C4,0x01FF0000
+#define SRM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6      0x1F0405C4,0x000001FF
+
+#define SRM_DI0_DW_SET3_7__ADDR                          0x1F0405C8
+#define SRM_DI0_DW_SET3_7__EMPTY       0x1F0405C8,0x00000000
+#define SRM_DI0_DW_SET3_7__FULL              0x1F0405C8,0xffffffff
+#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7              0x1F0405C8,0x01FF0000
+#define SRM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7      0x1F0405C8,0x000001FF
+
+#define SRM_DI0_DW_SET3_8__ADDR                          0x1F0405CC
+#define SRM_DI0_DW_SET3_8__EMPTY       0x1F0405CC,0x00000000
+#define SRM_DI0_DW_SET3_8__FULL              0x1F0405CC,0xffffffff
+#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8              0x1F0405CC,0x01FF0000
+#define SRM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8      0x1F0405CC,0x000001FF
+
+#define SRM_DI0_DW_SET3_9__ADDR                          0x1F0405D0
+#define SRM_DI0_DW_SET3_9__EMPTY       0x1F0405D0,0x00000000
+#define SRM_DI0_DW_SET3_9__FULL              0x1F0405D0,0xffffffff
+#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9              0x1F0405D0,0x01FF0000
+#define SRM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9      0x1F0405D0,0x000001FF
+
+#define SRM_DI0_DW_SET3_10__ADDR                  0x1F0405D4
+#define SRM_DI0_DW_SET3_10__EMPTY      0x1F0405D4,0x00000000
+#define SRM_DI0_DW_SET3_10__FULL       0x1F0405D4,0xffffffff
+#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10      0x1F0405D4,0x01FF0000
+#define SRM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10              0x1F0405D4,0x000001FF
+
+#define SRM_DI0_DW_SET3_11__ADDR                  0x1F0405D8
+#define SRM_DI0_DW_SET3_11__EMPTY      0x1F0405D8,0x00000000
+#define SRM_DI0_DW_SET3_11__FULL       0x1F0405D8,0xffffffff
+#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11      0x1F0405D8,0x01FF0000
+#define SRM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11              0x1F0405D8,0x000001FF
+
+#define SRM_DI0_STP_REP_1__ADDR                          0x1F0405DC
+#define SRM_DI0_STP_REP_1__EMPTY       0x1F0405DC,0x00000000
+#define SRM_DI0_STP_REP_1__FULL              0x1F0405DC,0xffffffff
+#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_2      0x1F0405DC,0x0FFF0000
+#define SRM_DI0_STP_REP_1__DI0_STEP_REPEAT_1      0x1F0405DC,0x00000FFF
+
+#define SRM_DI0_STP_REP_2__ADDR                          0x1F0405E0
+#define SRM_DI0_STP_REP_2__EMPTY       0x1F0405E0,0x00000000
+#define SRM_DI0_STP_REP_2__FULL              0x1F0405E0,0xffffffff
+#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_4      0x1F0405E0,0x0FFF0000
+#define SRM_DI0_STP_REP_2__DI0_STEP_REPEAT_3      0x1F0405E0,0x00000FFF
+
+#define SRM_DI0_STP_REP_3__ADDR                          0x1F0405E4
+#define SRM_DI0_STP_REP_3__EMPTY       0x1F0405E4,0x00000000
+#define SRM_DI0_STP_REP_3__FULL              0x1F0405E4,0xffffffff
+#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_6      0x1F0405E4,0x0FFF0000
+#define SRM_DI0_STP_REP_3__DI0_STEP_REPEAT_5      0x1F0405E4,0x00000FFF
+
+#define SRM_DI0_STP_REP_4__ADDR                          0x1F0405E8
+#define SRM_DI0_STP_REP_4__EMPTY       0x1F0405E8,0x00000000
+#define SRM_DI0_STP_REP_4__FULL              0x1F0405E8,0xffffffff
+#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_8      0x1F0405E8,0x0FFF0000
+#define SRM_DI0_STP_REP_4__DI0_STEP_REPEAT_7      0x1F0405E8,0x00000FFF
+
+#define SRM_DI0_STP_REP_9__ADDR                          0x1F0405EC
+#define SRM_DI0_STP_REP_9__EMPTY       0x1F0405EC,0x00000000
+#define SRM_DI0_STP_REP_9__FULL              0x1F0405EC,0xffffffff
+#define SRM_DI0_STP_REP_9__DI0_STEP_REPEAT_9      0x1F0405EC,0x00000FFF
+
+#define SRM_DI0_SER_CONF__ADDR                  0x1F0405F0
+#define SRM_DI0_SER_CONF__EMPTY              0x1F0405F0,0x00000000
+#define SRM_DI0_SER_CONF__FULL      0x1F0405F0,0xffffffff
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1      0x1F0405F0,0xF0000000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0      0x1F0405F0,0x0F000000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1      0x1F0405F0,0x00F00000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0      0x1F0405F0,0x000F0000
+#define SRM_DI0_SER_CONF__DI0_SERIAL_LATCH      0x1F0405F0,0x0000FF00
+#define SRM_DI0_SER_CONF__DI0_LLA_SER_ACCESS      0x1F0405F0,0x00000020
+#define SRM_DI0_SER_CONF__DI0_SER_CLK_POLARITY      0x1F0405F0,0x00000010
+#define SRM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY      0x1F0405F0,0x00000008
+#define SRM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY       0x1F0405F0,0x00000004
+#define SRM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY       0x1F0405F0,0x00000002
+#define SRM_DI0_SER_CONF__DI0_WAIT4SERIAL      0x1F0405F0,0x00000001
+
+#define SRM_DI0_SSC__ADDR                  0x1F0405F4
+#define SRM_DI0_SSC__EMPTY      0x1F0405F4,0x00000000
+#define SRM_DI0_SSC__FULL      0x1F0405F4,0xffffffff
+#define SRM_DI0_SSC__DI0_PIN17_ERM     0x1F0405F4,0x00800000
+#define SRM_DI0_SSC__DI0_PIN16_ERM     0x1F0405F4,0x00400000
+#define SRM_DI0_SSC__DI0_PIN15_ERM     0x1F0405F4,0x00200000
+#define SRM_DI0_SSC__DI0_PIN14_ERM     0x1F0405F4,0x00100000
+#define SRM_DI0_SSC__DI0_PIN13_ERM     0x1F0405F4,0x00080000
+#define SRM_DI0_SSC__DI0_PIN12_ERM     0x1F0405F4,0x00040000
+#define SRM_DI0_SSC__DI0_PIN11_ERM     0x1F0405F4,0x00020000
+#define SRM_DI0_SSC__DI0_CS_ERM               0x1F0405F4,0x00010000
+#define SRM_DI0_SSC__DI0_WAIT_ON       0x1F0405F4,0x00000020
+#define SRM_DI0_SSC__DI0_BYTE_EN_RD_IN      0x1F0405F4,0x00000008
+#define SRM_DI0_SSC__DI0_BYTE_EN_PNTR      0x1F0405F4,0x00000007
+
+#define SRM_DI0_POL__ADDR                  0x1F0405F8
+#define SRM_DI0_POL__EMPTY      0x1F0405F8,0x00000000
+#define SRM_DI0_POL__FULL      0x1F0405F8,0xffffffff
+#define SRM_DI0_POL__DI0_WAIT_POLARITY      0x1F0405F8,0x04000000
+#define SRM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY      0x1F0405F8,0x02000000
+#define SRM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY      0x1F0405F8,0x01000000
+#define SRM_DI0_POL__DI0_CS1_DATA_POLARITY      0x1F0405F8,0x00800000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_17       0x1F0405F8,0x00400000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_16       0x1F0405F8,0x00200000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_15       0x1F0405F8,0x00100000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_14       0x1F0405F8,0x00080000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_13       0x1F0405F8,0x00040000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_12       0x1F0405F8,0x00020000
+#define SRM_DI0_POL__DI0_CS1_POLARITY_11       0x1F0405F8,0x00010000
+#define SRM_DI0_POL__DI0_CS0_DATA_POLARITY      0x1F0405F8,0x00008000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_17       0x1F0405F8,0x00004000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_16       0x1F0405F8,0x00002000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_15       0x1F0405F8,0x00001000
+#define SRM_DI0_POL__DI0_CS0_POLARITY_14       0x1F0405F8,0x00000800
+#define SRM_DI0_POL__DI0_CS0_POLARITY_13       0x1F0405F8,0x00000400
+#define SRM_DI0_POL__DI0_CS0_POLARITY_12       0x1F0405F8,0x00000200
+#define SRM_DI0_POL__DI0_CS0_POLARITY_11       0x1F0405F8,0x00000100
+#define SRM_DI0_POL__DI0_DRDY_DATA_POLARITY      0x1F0405F8,0x00000080
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_17      0x1F0405F8,0x00000040
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_16      0x1F0405F8,0x00000020
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_15      0x1F0405F8,0x00000010
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_14      0x1F0405F8,0x00000008
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_13      0x1F0405F8,0x00000004
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_12      0x1F0405F8,0x00000002
+#define SRM_DI0_POL__DI0_DRDY_POLARITY_11      0x1F0405F8,0x00000001
+
+#define SRM_DI0_AW0__ADDR                  0x1F0405FC
+#define SRM_DI0_AW0__EMPTY      0x1F0405FC,0x00000000
+#define SRM_DI0_AW0__FULL      0x1F0405FC,0xffffffff
+#define SRM_DI0_AW0__DI0_AW_TRIG_SEL      0x1F0405FC,0xF0000000
+#define SRM_DI0_AW0__DI0_AW_HEND       0x1F0405FC,0x0FFF0000
+#define SRM_DI0_AW0__DI0_AW_HCOUNT_SEL      0x1F0405FC,0x0000F000
+#define SRM_DI0_AW0__DI0_AW_HSTART      0x1F0405FC,0x00000FFF
+
+#define SRM_DI0_AW1__ADDR                  0x1F040600
+#define SRM_DI0_AW1__EMPTY      0x1F040600,0x00000000
+#define SRM_DI0_AW1__FULL      0x1F040600,0xffffffff
+#define SRM_DI0_AW1__DI0_AW_VEND       0x1F040600,0x0FFF0000
+#define SRM_DI0_AW1__DI0_AW_VCOUNT_SEL      0x1F040600,0x0000F000
+#define SRM_DI0_AW1__DI0_AW_VSTART      0x1F040600,0x00000FFF
+
+#define SRM_DI0_SCR_CONF__ADDR                  0x1F040604
+#define SRM_DI0_SCR_CONF__EMPTY              0x1F040604,0x00000000
+#define SRM_DI0_SCR_CONF__FULL      0x1F040604,0xffffffff
+#define SRM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT      0x1F040604,0x00000FFF
+
+#define SRM_DI1_GENERAL__ADDR                  0x1F040608
+#define SRM_DI1_GENERAL__EMPTY      0x1F040608,0x00000000
+#define SRM_DI1_GENERAL__FULL      0x1F040608,0xffffffff
+#define SRM_DI1_GENERAL__DI1_DISP_Y_SEL              0x1F040608,0x70000000
+#define SRM_DI1_GENERAL__DI1_CLOCK_STOP_MODE      0x1F040608,0x0F000000
+#define SRM_DI1_GENERAL__DI1_DISP_CLOCK_INIT   0x1F040608,0x00800000
+#define SRM_DI1_GENERAL__DI1_MASK_SEL      0x1F040608,0x00400000
+#define SRM_DI1_GENERAL__DI1_VSYNC_EXT      0x1F040608,0x00200000
+#define SRM_DI1_GENERAL__DI1_CLK_EXT      0x1F040608,0x00100000
+#define SRN_DI1_GENERAL__DI1_WATCHDOG_MODE     0x1F040608,0x000C0000
+#define SRM_DI1_GENERAL__DI1_POLARITY_DISP_CLK      0x1F040608,0x00020000
+#define SRM_DI1_GENERAL__DI1_SYNC_COUNT_SEL      0x1F040608,0x0000F000
+#define SRM_DI1_GENERAL__DI1_ERR_TREATMENT      0x1F040608,0x00000800
+#define SRM_DI1_GENERAL__DI1_ERM_VSYNC_SEL     0x1F040608,0x00000400
+#define SRM_DI1_GENERAL__DI1_POLARITY_CS1      0x1F040608,0x00000200
+#define SRM_DI1_GENERAL__DI1_POLARITY_CS0      0x1F040608,0x00000100
+#define SRM_DI1_GENERAL__DI1_POLARITY_8              0x1F040608,0x00000080
+#define SRM_DI1_GENERAL__DI1_POLARITY_7              0x1F040608,0x00000040
+#define SRM_DI1_GENERAL__DI1_POLARITY_6              0x1F040608,0x00000020
+#define SRM_DI1_GENERAL__DI1_POLARITY_5              0x1F040608,0x00000010
+#define SRM_DI1_GENERAL__DI1_POLARITY_4              0x1F040608,0x00000008
+#define SRM_DI1_GENERAL__DI1_POLARITY_3              0x1F040608,0x00000004
+#define SRM_DI1_GENERAL__DI1_POLARITY_2              0x1F040608,0x00000002
+#define SRM_DI1_GENERAL__DI1_POLARITY_1              0x1F040608,0x00000001
+
+#define SRM_DI1_BS_CLKGEN0__ADDR                  0x1F04060C
+#define SRM_DI1_BS_CLKGEN0__EMPTY      0x1F04060C,0x00000000
+#define SRM_DI1_BS_CLKGEN0__FULL       0x1F04060C,0xffffffff
+#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET              0x1F04060C,0x01FF0000
+#define SRM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD              0x1F04060C,0x00000FFF
+
+#define SRM_DI1_BS_CLKGEN1__ADDR                  0x1F040610
+#define SRM_DI1_BS_CLKGEN1__EMPTY      0x1F040610,0x00000000
+#define SRM_DI1_BS_CLKGEN1__FULL       0x1F040610,0xffffffff
+#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN      0x1F040610,0x01FF0000
+#define SRM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP      0x1F040610,0x000001FF
+
+#define SRM_DI1_SW_GEN0_1__ADDR                          0x1F040614
+#define SRM_DI1_SW_GEN0_1__EMPTY       0x1F040614,0x00000000
+#define SRM_DI1_SW_GEN0_1__FULL              0x1F040614,0xffffffff
+#define SRM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1      0x1F040614,0x7FF80000
+#define SRM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1              0x1F040614,0x00070000
+#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1      0x1F040614,0x00007FF8
+#define SRM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1      0x1F040614,0x00000007
+
+#define SRM_DI1_SW_GEN0_2__ADDR                          0x1F040618
+#define SRM_DI1_SW_GEN0_2__EMPTY       0x1F040618,0x00000000
+#define SRM_DI1_SW_GEN0_2__FULL              0x1F040618,0xffffffff
+#define SRM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2      0x1F040618,0x7FF80000
+#define SRM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2              0x1F040618,0x00070000
+#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2      0x1F040618,0x00007FF8
+#define SRM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2      0x1F040618,0x00000007
+
+#define SRM_DI1_SW_GEN0_3__ADDR                          0x1F04061C
+#define SRM_DI1_SW_GEN0_3__EMPTY       0x1F04061C,0x00000000
+#define SRM_DI1_SW_GEN0_3__FULL              0x1F04061C,0xffffffff
+#define SRM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3      0x1F04061C,0x7FF80000
+#define SRM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3              0x1F04061C,0x00070000
+#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3      0x1F04061C,0x00007FF8
+#define SRM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3      0x1F04061C,0x00000007
+
+#define SRM_DI1_SW_GEN0_4__ADDR                          0x1F040620
+#define SRM_DI1_SW_GEN0_4__EMPTY       0x1F040620,0x00000000
+#define SRM_DI1_SW_GEN0_4__FULL              0x1F040620,0xffffffff
+#define SRM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4      0x1F040620,0x7FF80000
+#define SRM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4              0x1F040620,0x00070000
+#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4      0x1F040620,0x00007FF8
+#define SRM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4      0x1F040620,0x00000007
+
+#define SRM_DI1_SW_GEN0_5__ADDR                          0x1F040624
+#define SRM_DI1_SW_GEN0_5__EMPTY       0x1F040624,0x00000000
+#define SRM_DI1_SW_GEN0_5__FULL              0x1F040624,0xffffffff
+#define SRM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5      0x1F040624,0x7FF80000
+#define SRM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5              0x1F040624,0x00070000
+#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5      0x1F040624,0x00007FF8
+#define SRM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5      0x1F040624,0x00000007
+
+#define SRM_DI1_SW_GEN0_6__ADDR                          0x1F040628
+#define SRM_DI1_SW_GEN0_6__EMPTY       0x1F040628,0x00000000
+#define SRM_DI1_SW_GEN0_6__FULL              0x1F040628,0xffffffff
+#define SRM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6      0x1F040628,0x7FF80000
+#define SRM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6              0x1F040628,0x00070000
+#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6      0x1F040628,0x00007FF8
+#define SRM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6      0x1F040628,0x00000007
+
+#define SRM_DI1_SW_GEN0_7__ADDR                          0x1F04062C
+#define SRM_DI1_SW_GEN0_7__EMPTY       0x1F04062C,0x00000000
+#define SRM_DI1_SW_GEN0_7__FULL              0x1F04062C,0xffffffff
+#define SRM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7      0x1F04062C,0x7FF80000
+#define SRM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7              0x1F04062C,0x00070000
+#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7      0x1F04062C,0x00007FF8
+#define SRM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7      0x1F04062C,0x00000007
+
+#define SRM_DI1_SW_GEN0_8__ADDR                          0x1F040630
+#define SRM_DI1_SW_GEN0_8__EMPTY       0x1F040630,0x00000000
+#define SRM_DI1_SW_GEN0_8__FULL              0x1F040630,0xffffffff
+#define SRM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8      0x1F040630,0x7FF80000
+#define SRM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8              0x1F040630,0x00070000
+#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8      0x1F040630,0x00007FF8
+#define SRM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8      0x1F040630,0x00000007
+
+#define SRM_DI1_SW_GEN0_9__ADDR                          0x1F040634
+#define SRM_DI1_SW_GEN0_9__EMPTY       0x1F040634,0x00000000
+#define SRM_DI1_SW_GEN0_9__FULL              0x1F040634,0xffffffff
+#define SRM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9      0x1F040634,0x7FF80000
+#define SRM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9              0x1F040634,0x00070000
+#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9      0x1F040634,0x00007FF8
+#define SRM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9      0x1F040634,0x00000007
+
+#define SRM_DI1_SW_GEN1_1__ADDR                          0x1F040638
+#define SRM_DI1_SW_GEN1_1__EMPTY       0x1F040638,0x00000000
+#define SRM_DI1_SW_GEN1_1__FULL              0x1F040638,0xffffffff
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1      0x1F040638,0x60000000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1       0x1F040638,0x10000000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1      0x1F040638,0x0E000000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1      0x1F040638,0x01FF0000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1      0x1F040638,0x00007000
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1      0x1F040638,0x00000E00
+#define SRM_DI1_SW_GEN1_1__DI1_CNT_UP_1              0x1F040638,0x000001FF
+
+#define SRM_DI1_SW_GEN1_2__ADDR                          0x1F04063C
+#define SRM_DI1_SW_GEN1_2__EMPTY       0x1F04063C,0x00000000
+#define SRM_DI1_SW_GEN1_2__FULL              0x1F04063C,0xffffffff
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2      0x1F04063C,0x60000000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2       0x1F04063C,0x10000000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2      0x1F04063C,0x0E000000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2      0x1F04063C,0x01FF0000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2      0x1F04063C,0x00007000
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2      0x1F04063C,0x00000E00
+#define SRM_DI1_SW_GEN1_2__DI1_CNT_UP_2              0x1F04063C,0x000001FF
+
+#define SRM_DI1_SW_GEN1_3__ADDR                          0x1F040640
+#define SRM_DI1_SW_GEN1_3__EMPTY       0x1F040640,0x00000000
+#define SRM_DI1_SW_GEN1_3__FULL              0x1F040640,0xffffffff
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3      0x1F040640,0x60000000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3       0x1F040640,0x10000000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3      0x1F040640,0x0E000000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3      0x1F040640,0x01FF0000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3      0x1F040640,0x00007000
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3      0x1F040640,0x00000E00
+#define SRM_DI1_SW_GEN1_3__DI1_CNT_UP_3              0x1F040640,0x000001FF
+
+#define SRM_DI1_SW_GEN1_4__ADDR                          0x1F040644
+#define SRM_DI1_SW_GEN1_4__EMPTY       0x1F040644,0x00000000
+#define SRM_DI1_SW_GEN1_4__FULL              0x1F040644,0xffffffff
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4      0x1F040644,0x60000000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4       0x1F040644,0x10000000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4      0x1F040644,0x0E000000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4      0x1F040644,0x01FF0000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4      0x1F040644,0x00007000
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4      0x1F040644,0x00000E00
+#define SRM_DI1_SW_GEN1_4__DI1_CNT_UP_4              0x1F040644,0x000001FF
+
+#define SRM_DI1_SW_GEN1_5__ADDR                          0x1F040648
+#define SRM_DI1_SW_GEN1_5__EMPTY       0x1F040648,0x00000000
+#define SRM_DI1_SW_GEN1_5__FULL              0x1F040648,0xffffffff
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5      0x1F040648,0x60000000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5       0x1F040648,0x10000000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5      0x1F040648,0x0E000000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5      0x1F040648,0x01FF0000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5      0x1F040648,0x00007000
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5      0x1F040648,0x00000E00
+#define SRM_DI1_SW_GEN1_5__DI1_CNT_UP_5              0x1F040648,0x000001FF
+
+#define SRM_DI1_SW_GEN1_6__ADDR                          0x1F04064C
+#define SRM_DI1_SW_GEN1_6__EMPTY       0x1F04064C,0x00000000
+#define SRM_DI1_SW_GEN1_6__FULL              0x1F04064C,0xffffffff
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6      0x1F04064C,0x60000000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6       0x1F04064C,0x10000000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6      0x1F04064C,0x0E000000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6      0x1F04064C,0x01FF0000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6      0x1F04064C,0x00007000
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6      0x1F04064C,0x00000E00
+#define SRM_DI1_SW_GEN1_6__DI1_CNT_UP_6              0x1F04064C,0x000001FF
+
+#define SRM_DI1_SW_GEN1_7__ADDR                          0x1F040650
+#define SRM_DI1_SW_GEN1_7__EMPTY       0x1F040650,0x00000000
+#define SRM_DI1_SW_GEN1_7__FULL              0x1F040650,0xffffffff
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7      0x1F040650,0x60000000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7       0x1F040650,0x10000000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7      0x1F040650,0x0E000000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7      0x1F040650,0x01FF0000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7      0x1F040650,0x00007000
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7      0x1F040650,0x00000E00
+#define SRM_DI1_SW_GEN1_7__DI1_CNT_UP_7              0x1F040650,0x000001FF
+
+#define SRM_DI1_SW_GEN1_8__ADDR                          0x1F040654
+#define SRM_DI1_SW_GEN1_8__EMPTY       0x1F040654,0x00000000
+#define SRM_DI1_SW_GEN1_8__FULL              0x1F040654,0xffffffff
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8      0x1F040654,0x60000000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8       0x1F040654,0x10000000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8      0x1F040654,0x0E000000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8      0x1F040654,0x01FF0000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8      0x1F040654,0x00007000
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8      0x1F040654,0x00000E00
+#define SRM_DI1_SW_GEN1_8__DI1_CNT_UP_8              0x1F040654,0x000001FF
+
+#define SRM_DI1_SW_GEN1_9__ADDR                          0x1F040658
+#define SRM_DI1_SW_GEN1_9__EMPTY       0x1F040658,0x00000000
+#define SRM_DI1_SW_GEN1_9__FULL              0x1F040658,0xffffffff
+#define SRM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9      0x1F040658,0xE0000000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9       0x1F040658,0x10000000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9      0x1F040658,0x0E000000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9      0x1F040658,0x01FF0000
+#define SRM_DI1_SW_GEN1_9__DI1_TAG_SEL_9       0x1F040658,0x00008000
+#define SRM_DI1_SW_GEN1_9__DI1_CNT_UP_9              0x1F040658,0x000001FF
+
+#define SRM_DI1_SYNC_AS_GEN__ADDR                  0x1F04065C
+#define SRM_DI1_SYNC_AS_GEN__EMPTY      0x1F04065C,0x00000000
+#define SRM_DI1_SYNC_AS_GEN__FULL      0x1F04065C,0xffffffff
+#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN      0x1F04065C,0x10000000
+#define SRM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL      0x1F04065C,0x0000E000
+#define SRM_DI1_SYNC_AS_GEN__DI1_SYNC_START      0x1F04065C,0x00000FFF
+
+#define SRM_DI1_DW_GEN_0__ADDR                 0x1F040660
+#define SRM_DI1_DW_GEN_0__EMPTY                        0x1F040660,0x00000000
+#define SRM_DI1_DW_GEN_0__FULL                 0x1F040660,0xffffffff
+#define SRM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0    0x1F040660,0xFF000000
+#define SRM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0 0x1F040660,0x00FF0000
+#define SRM_DI1_DW_GEN_0__DI1_CST_0            0x1F040660,0x0000C000
+#define SRM_DI1_DW_GEN_0__DI1_PT_6_0           0x1F040660,0x00003000
+#define SRM_DI1_DW_GEN_0__DI1_PT_5_0           0x1F040660,0x00000C00
+#define SRM_DI1_DW_GEN_0__DI1_PT_4_0           0x1F040660,0x00000300
+#define SRM_DI1_DW_GEN_0__DI1_PT_3_0           0x1F040660,0x000000C0
+#define SRM_DI1_DW_GEN_0__DI1_PT_2_0           0x1F040660,0x00000030
+#define SRM_DI1_DW_GEN_0__DI1_PT_1_0           0x1F040660,0x0000000C
+#define SRM_DI1_DW_GEN_0__DI1_PT_0_0           0x1F040660,0x00000003
+
+#define SRM_DI1_DW_GEN_0__ADDR                   0x1F040660
+#define SRM_DI1_DW_GEN_0__EMPTY                          0x1F040660,0x00000000
+#define SRM_DI1_DW_GEN_0__FULL                   0x1F040660,0xffffffff
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0    0x1F040660,0xFF000000
+#define SRM_DI1_DW_GEN_0__DI1_START_PERIOD_0     0x1F040660,0x00FF0000
+#define SRM_DI1_DW_GEN_0__DI1_CST_0              0x1F040660,0x0000C000
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0 0x1F040660,0x000001F0
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_RS_0        0x1F040660,0x0000000C
+#define SRM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0       0x1F040660,0x00000003
+
+#define SRM_DI1_DW_GEN_1__ADDR                 0x1F040664
+#define SRM_DI1_DW_GEN_1__EMPTY                        0x1F040664,0x00000000
+#define SRM_DI1_DW_GEN_1__FULL                 0x1F040664,0xffffffff
+#define SRM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1    0x1F040664,0xFF000000
+#define SRM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1 0x1F040664,0x00FF0000
+#define SRM_DI1_DW_GEN_1__DI1_CST_1            0x1F040664,0x0000C000
+#define SRM_DI1_DW_GEN_1__DI1_PT_6_1           0x1F040664,0x00003000
+#define SRM_DI1_DW_GEN_1__DI1_PT_5_1           0x1F040664,0x00000C00
+#define SRM_DI1_DW_GEN_1__DI1_PT_4_1           0x1F040664,0x00000300
+#define SRM_DI1_DW_GEN_1__DI1_PT_3_1           0x1F040664,0x000000C0
+#define SRM_DI1_DW_GEN_1__DI1_PT_2_1           0x1F040664,0x00000030
+#define SRM_DI1_DW_GEN_1__DI1_PT_1_1           0x1F040664,0x0000000C
+#define SRM_DI1_DW_GEN_1__DI1_PT_0_1           0x1F040664,0x00000003
+
+#define SRM_DI1_DW_GEN_1__ADDR                   0x1F040664
+#define SRM_DI1_DW_GEN_1__EMPTY                          0x1F040664,0x00000000
+#define SRM_DI1_DW_GEN_1__FULL                   0x1F040664,0xffffffff
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1    0x1F040664,0xFF000000
+#define SRM_DI1_DW_GEN_1__DI1_START_PERIOD_1     0x1F040664,0x00FF0000
+#define SRM_DI1_DW_GEN_1__DI1_CST_1              0x1F040664,0x0000C000
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1 0x1F040664,0x000001F0
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_RS_1        0x1F040664,0x0000000C
+#define SRM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1       0x1F040664,0x00000003
+
+#define SRM_DI1_DW_GEN_2__ADDR                 0x1F040668
+#define SRM_DI1_DW_GEN_2__EMPTY                        0x1F040668,0x00000000
+#define SRM_DI1_DW_GEN_2__FULL                 0x1F040668,0xffffffff
+#define SRM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2    0x1F040668,0xFF000000
+#define SRM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2 0x1F040668,0x00FF0000
+#define SRM_DI1_DW_GEN_2__DI1_CST_2            0x1F040668,0x0000C000
+#define SRM_DI1_DW_GEN_2__DI1_PT_6_2           0x1F040668,0x00003000
+#define SRM_DI1_DW_GEN_2__DI1_PT_5_2           0x1F040668,0x00000C00
+#define SRM_DI1_DW_GEN_2__DI1_PT_4_2           0x1F040668,0x00000300
+#define SRM_DI1_DW_GEN_2__DI1_PT_3_2           0x1F040668,0x000000C0
+#define SRM_DI1_DW_GEN_2__DI1_PT_2_2           0x1F040668,0x00000030
+#define SRM_DI1_DW_GEN_2__DI1_PT_1_2           0x1F040668,0x0000000C
+#define SRM_DI1_DW_GEN_2__DI1_PT_0_2           0x1F040668,0x00000003
+
+#define SRM_DI1_DW_GEN_2__ADDR                   0x1F040668
+#define SRM_DI1_DW_GEN_2__EMPTY                          0x1F040668,0x00000000
+#define SRM_DI1_DW_GEN_2__FULL                   0x1F040668,0xffffffff
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2    0x1F040668,0xFF000000
+#define SRM_DI1_DW_GEN_2__DI1_START_PERIOD_2     0x1F040668,0x00FF0000
+#define SRM_DI1_DW_GEN_2__DI1_CST_2              0x1F040668,0x0000C000
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2 0x1F040668,0x000001F0
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_RS_2        0x1F040668,0x0000000C
+#define SRM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2       0x1F040668,0x00000003
+
+#define SRM_DI1_DW_GEN_3__ADDR                 0x1F04066C
+#define SRM_DI1_DW_GEN_3__EMPTY                        0x1F04066C,0x00000000
+#define SRM_DI1_DW_GEN_3__FULL                 0x1F04066C,0xffffffff
+#define SRM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3    0x1F04066C,0xFF000000
+#define SRM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3 0x1F04066C,0x00FF0000
+#define SRM_DI1_DW_GEN_3__DI1_CST_3            0x1F04066C,0x0000C000
+#define SRM_DI1_DW_GEN_3__DI1_PT_6_3           0x1F04066C,0x00003000
+#define SRM_DI1_DW_GEN_3__DI1_PT_5_3           0x1F04066C,0x00000C00
+#define SRM_DI1_DW_GEN_3__DI1_PT_4_3           0x1F04066C,0x00000300
+#define SRM_DI1_DW_GEN_3__DI1_PT_3_3           0x1F04066C,0x000000C0
+#define SRM_DI1_DW_GEN_3__DI1_PT_2_3           0x1F04066C,0x00000030
+#define SRM_DI1_DW_GEN_3__DI1_PT_1_3           0x1F04066C,0x0000000C
+#define SRM_DI1_DW_GEN_3__DI1_PT_0_3           0x1F04066C,0x00000003
+
+#define SRM_DI1_DW_GEN_3__ADDR                   0x1F04066C
+#define SRM_DI1_DW_GEN_3__EMPTY                          0x1F04066C,0x00000000
+#define SRM_DI1_DW_GEN_3__FULL                   0x1F04066C,0xffffffff
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3    0x1F04066C,0xFF000000
+#define SRM_DI1_DW_GEN_3__DI1_START_PERIOD_3     0x1F04066C,0x00FF0000
+#define SRM_DI1_DW_GEN_3__DI1_CST_3              0x1F04066C,0x0000C000
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3 0x1F04066C,0x000001F0
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_RS_3        0x1F04066C,0x0000000C
+#define SRM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3       0x1F04066C,0x00000003
+
+#define SRM_DI1_DW_GEN_4__ADDR                 0x1F040670
+#define SRM_DI1_DW_GEN_4__EMPTY                        0x1F040670,0x00000000
+#define SRM_DI1_DW_GEN_4__FULL                 0x1F040670,0xffffffff
+#define SRM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4    0x1F040670,0xFF000000
+#define SRM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4 0x1F040670,0x00FF0000
+#define SRM_DI1_DW_GEN_4__DI1_CST_4            0x1F040670,0x0000C000
+#define SRM_DI1_DW_GEN_4__DI1_PT_6_4           0x1F040670,0x00003000
+#define SRM_DI1_DW_GEN_4__DI1_PT_5_4           0x1F040670,0x00000C00
+#define SRM_DI1_DW_GEN_4__DI1_PT_4_4           0x1F040670,0x00000300
+#define SRM_DI1_DW_GEN_4__DI1_PT_3_4           0x1F040670,0x000000C0
+#define SRM_DI1_DW_GEN_4__DI1_PT_2_4           0x1F040670,0x00000030
+#define SRM_DI1_DW_GEN_4__DI1_PT_1_4           0x1F040670,0x0000000C
+#define SRM_DI1_DW_GEN_4__DI1_PT_0_4           0x1F040670,0x00000003
+
+#define SRM_DI1_DW_GEN_4__ADDR                   0x1F040670
+#define SRM_DI1_DW_GEN_4__EMPTY                          0x1F040670,0x00000000
+#define SRM_DI1_DW_GEN_4__FULL                   0x1F040670,0xffffffff
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4    0x1F040670,0xFF000000
+#define SRM_DI1_DW_GEN_4__DI1_START_PERIOD_4     0x1F040670,0x00FF0000
+#define SRM_DI1_DW_GEN_4__DI1_CST_4              0x1F040670,0x0000C000
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4 0x1F040670,0x000001F0
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_RS_4        0x1F040670,0x0000000C
+#define SRM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4       0x1F040670,0x00000003
+
+#define SRM_DI1_DW_GEN_5__ADDR                 0x1F040674
+#define SRM_DI1_DW_GEN_5__EMPTY                        0x1F040674,0x00000000
+#define SRM_DI1_DW_GEN_5__FULL                 0x1F040674,0xffffffff
+#define SRM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5    0x1F040674,0xFF000000
+#define SRM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5 0x1F040674,0x00FF0000
+#define SRM_DI1_DW_GEN_5__DI1_CST_5            0x1F040674,0x0000C000
+#define SRM_DI1_DW_GEN_5__DI1_PT_6_5           0x1F040674,0x00003000
+#define SRM_DI1_DW_GEN_5__DI1_PT_5_5           0x1F040674,0x00000C00
+#define SRM_DI1_DW_GEN_5__DI1_PT_4_5           0x1F040674,0x00000300
+#define SRM_DI1_DW_GEN_5__DI1_PT_3_5           0x1F040674,0x000000C0
+#define SRM_DI1_DW_GEN_5__DI1_PT_2_5           0x1F040674,0x00000030
+#define SRM_DI1_DW_GEN_5__DI1_PT_1_5           0x1F040674,0x0000000C
+#define SRM_DI1_DW_GEN_5__DI1_PT_0_5           0x1F040674,0x00000003
+
+#define SRM_DI1_DW_GEN_5__ADDR                   0x1F040674
+#define SRM_DI1_DW_GEN_5__EMPTY                          0x1F040674,0x00000000
+#define SRM_DI1_DW_GEN_5__FULL                   0x1F040674,0xffffffff
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5    0x1F040674,0xFF000000
+#define SRM_DI1_DW_GEN_5__DI1_START_PERIOD_5     0x1F040674,0x00FF0000
+#define SRM_DI1_DW_GEN_5__DI1_CST_5              0x1F040674,0x0000C000
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5 0x1F040674,0x000001F0
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_RS_5        0x1F040674,0x0000000C
+#define SRM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5       0x1F040674,0x00000003
+
+#define SRM_DI1_DW_GEN_6__ADDR                 0x1F040678
+#define SRM_DI1_DW_GEN_6__EMPTY                        0x1F040678,0x00000000
+#define SRM_DI1_DW_GEN_6__FULL                 0x1F040678,0xffffffff
+#define SRM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6    0x1F040678,0xFF000000
+#define SRM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6 0x1F040678,0x00FF0000
+#define SRM_DI1_DW_GEN_6__DI1_CST_6            0x1F040678,0x0000C000
+#define SRM_DI1_DW_GEN_6__DI1_PT_6_6           0x1F040678,0x00003000
+#define SRM_DI1_DW_GEN_6__DI1_PT_5_6           0x1F040678,0x00000C00
+#define SRM_DI1_DW_GEN_6__DI1_PT_4_6           0x1F040678,0x00000300
+#define SRM_DI1_DW_GEN_6__DI1_PT_3_6           0x1F040678,0x000000C0
+#define SRM_DI1_DW_GEN_6__DI1_PT_2_6           0x1F040678,0x00000030
+#define SRM_DI1_DW_GEN_6__DI1_PT_1_6           0x1F040678,0x0000000C
+#define SRM_DI1_DW_GEN_6__DI1_PT_0_6           0x1F040678,0x00000003
+
+#define SRM_DI1_DW_GEN_6__ADDR                   0x1F040678
+#define SRM_DI1_DW_GEN_6__EMPTY                          0x1F040678,0x00000000
+#define SRM_DI1_DW_GEN_6__FULL                   0x1F040678,0xffffffff
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6    0x1F040678,0xFF000000
+#define SRM_DI1_DW_GEN_6__DI1_START_PERIOD_6     0x1F040678,0x00FF0000
+#define SRM_DI1_DW_GEN_6__DI1_CST_6              0x1F040678,0x0000C000
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6 0x1F040678,0x000001F0
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_RS_6        0x1F040678,0x0000000C
+#define SRM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6       0x1F040678,0x00000003
+
+#define SRM_DI1_DW_GEN_7__ADDR                 0x1F04067C
+#define SRM_DI1_DW_GEN_7__EMPTY                        0x1F04067C,0x00000000
+#define SRM_DI1_DW_GEN_7__FULL                 0x1F04067C,0xffffffff
+#define SRM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7    0x1F04067C,0xFF000000
+#define SRM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7 0x1F04067C,0x00FF0000
+#define SRM_DI1_DW_GEN_7__DI1_CST_7            0x1F04067C,0x0000C000
+#define SRM_DI1_DW_GEN_7__DI1_PT_6_7           0x1F04067C,0x00003000
+#define SRM_DI1_DW_GEN_7__DI1_PT_5_7           0x1F04067C,0x00000C00
+#define SRM_DI1_DW_GEN_7__DI1_PT_4_7           0x1F04067C,0x00000300
+#define SRM_DI1_DW_GEN_7__DI1_PT_3_7           0x1F04067C,0x000000C0
+#define SRM_DI1_DW_GEN_7__DI1_PT_2_7           0x1F04067C,0x00000030
+#define SRM_DI1_DW_GEN_7__DI1_PT_1_7           0x1F04067C,0x0000000C
+#define SRM_DI1_DW_GEN_7__DI1_PT_0_7           0x1F04067C,0x00000003
+
+#define SRM_DI1_DW_GEN_7__ADDR                   0x1F04067C
+#define SRM_DI1_DW_GEN_7__EMPTY                          0x1F04067C,0x00000000
+#define SRM_DI1_DW_GEN_7__FULL                   0x1F04067C,0xffffffff
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7    0x1F04067C,0xFF000000
+#define SRM_DI1_DW_GEN_7__DI1_START_PERIOD_7     0x1F04067C,0x00FF0000
+#define SRM_DI1_DW_GEN_7__DI1_CST_7              0x1F04067C,0x0000C000
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7 0x1F04067C,0x000001F0
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_RS_7        0x1F04067C,0x0000000C
+#define SRM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7       0x1F04067C,0x00000003
+
+#define SRM_DI1_DW_GEN_8__ADDR                 0x1F040680
+#define SRM_DI1_DW_GEN_8__EMPTY                        0x1F040680,0x00000000
+#define SRM_DI1_DW_GEN_8__FULL                 0x1F040680,0xffffffff
+#define SRM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8    0x1F040680,0xFF000000
+#define SRM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8 0x1F040680,0x00FF0000
+#define SRM_DI1_DW_GEN_8__DI1_CST_8            0x1F040680,0x0000C000
+#define SRM_DI1_DW_GEN_8__DI1_PT_6_8           0x1F040680,0x00003000
+#define SRM_DI1_DW_GEN_8__DI1_PT_5_8           0x1F040680,0x00000C00
+#define SRM_DI1_DW_GEN_8__DI1_PT_4_8           0x1F040680,0x00000300
+#define SRM_DI1_DW_GEN_8__DI1_PT_3_8           0x1F040680,0x000000C0
+#define SRM_DI1_DW_GEN_8__DI1_PT_2_8           0x1F040680,0x00000030
+#define SRM_DI1_DW_GEN_8__DI1_PT_1_8           0x1F040680,0x0000000C
+#define SRM_DI1_DW_GEN_8__DI1_PT_0_8           0x1F040680,0x00000003
+
+#define SRM_DI1_DW_GEN_8__ADDR                   0x1F040680
+#define SRM_DI1_DW_GEN_8__EMPTY                          0x1F040680,0x00000000
+#define SRM_DI1_DW_GEN_8__FULL                   0x1F040680,0xffffffff
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8    0x1F040680,0xFF000000
+#define SRM_DI1_DW_GEN_8__DI1_START_PERIOD_8     0x1F040680,0x00FF0000
+#define SRM_DI1_DW_GEN_8__DI1_CST_8              0x1F040680,0x0000C000
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8 0x1F040680,0x000001F0
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_RS_8        0x1F040680,0x0000000C
+#define SRM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8       0x1F040680,0x00000003
+
+#define SRM_DI1_DW_GEN_9__ADDR                 0x1F040684
+#define SRM_DI1_DW_GEN_9__EMPTY                        0x1F040684,0x00000000
+#define SRM_DI1_DW_GEN_9__FULL                 0x1F040684,0xffffffff
+#define SRM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9    0x1F040684,0xFF000000
+#define SRM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9 0x1F040684,0x00FF0000
+#define SRM_DI1_DW_GEN_9__DI1_CST_9            0x1F040684,0x0000C000
+#define SRM_DI1_DW_GEN_9__DI1_PT_6_9           0x1F040684,0x00003000
+#define SRM_DI1_DW_GEN_9__DI1_PT_5_9           0x1F040684,0x00000C00
+#define SRM_DI1_DW_GEN_9__DI1_PT_4_9           0x1F040684,0x00000300
+#define SRM_DI1_DW_GEN_9__DI1_PT_3_9           0x1F040684,0x000000C0
+#define SRM_DI1_DW_GEN_9__DI1_PT_2_9           0x1F040684,0x00000030
+#define SRM_DI1_DW_GEN_9__DI1_PT_1_9           0x1F040684,0x0000000C
+#define SRM_DI1_DW_GEN_9__DI1_PT_0_9           0x1F040684,0x00000003
+
+#define SRM_DI1_DW_GEN_9__ADDR                   0x1F040684
+#define SRM_DI1_DW_GEN_9__EMPTY                          0x1F040684,0x00000000
+#define SRM_DI1_DW_GEN_9__FULL                   0x1F040684,0xffffffff
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9    0x1F040684,0xFF000000
+#define SRM_DI1_DW_GEN_9__DI1_START_PERIOD_9     0x1F040684,0x00FF0000
+#define SRM_DI1_DW_GEN_9__DI1_CST_9              0x1F040684,0x0000C000
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9 0x1F040684,0x000001F0
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_RS_9        0x1F040684,0x0000000C
+#define SRM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9       0x1F040684,0x00000003
+
+#define SRM_DI1_DW_GEN_10__ADDR                          0x1F040688
+#define SRM_DI1_DW_GEN_10__EMPTY                 0x1F040688,0x00000000
+#define SRM_DI1_DW_GEN_10__FULL                          0x1F040688,0xffffffff
+#define SRM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10    0x1F040688,0xFF000000
+#define SRM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10 0x1F040688,0x00FF0000
+#define SRM_DI1_DW_GEN_10__DI1_CST_10            0x1F040688,0x0000C000
+#define SRM_DI1_DW_GEN_10__DI1_PT_6_10           0x1F040688,0x00003000
+#define SRM_DI1_DW_GEN_10__DI1_PT_5_10           0x1F040688,0x00000C00
+#define SRM_DI1_DW_GEN_10__DI1_PT_4_10           0x1F040688,0x00000300
+#define SRM_DI1_DW_GEN_10__DI1_PT_3_10           0x1F040688,0x000000C0
+#define SRM_DI1_DW_GEN_10__DI1_PT_2_10           0x1F040688,0x00000030
+#define SRM_DI1_DW_GEN_10__DI1_PT_1_10           0x1F040688,0x0000000C
+#define SRM_DI1_DW_GEN_10__DI1_PT_0_10           0x1F040688,0x00000003
+
+#define SRM_DI1_DW_GEN_10__ADDR                            0x1F040688
+#define SRM_DI1_DW_GEN_10__EMPTY                   0x1F040688,0x00000000
+#define SRM_DI1_DW_GEN_10__FULL                            0x1F040688,0xffffffff
+#define SRM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10            0x1F040688,0xFF000000
+#define SRM_DI1_DW_GEN_10__DI1_START_PERIOD_10     0x1F040688,0x00FF0000
+#define SRM_DI1_DW_GEN_10__DI1_CST_10              0x1F040688,0x0000C000
+#define SRM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10 0x1F040688,0x000001F0
+#define SRM_DI1_DW_GEN_10__DI1_SERIAL_RS_10        0x1F040688,0x0000000C
+#define SRM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10       0x1F040688,0x00000003
+
+#define SRM_DI1_DW_GEN_11__ADDR                          0x1F04068C
+#define SRM_DI1_DW_GEN_11__EMPTY                 0x1F04068C,0x00000000
+#define SRM_DI1_DW_GEN_11__FULL                          0x1F04068C,0xffffffff
+#define SRM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11    0x1F04068C,0xFF000000
+#define SRM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11 0x1F04068C,0x00FF0000
+#define SRM_DI1_DW_GEN_11__DI1_CST_11            0x1F04068C,0x0000C000
+#define SRM_DI1_DW_GEN_11__DI1_PT_6_11           0x1F04068C,0x00003000
+#define SRM_DI1_DW_GEN_11__DI1_PT_5_11           0x1F04068C,0x00000C00
+#define SRM_DI1_DW_GEN_11__DI1_PT_4_11           0x1F04068C,0x00000300
+#define SRM_DI1_DW_GEN_11__DI1_PT_3_11           0x1F04068C,0x000000C0
+#define SRM_DI1_DW_GEN_11__DI1_PT_2_11           0x1F04068C,0x00000030
+#define SRM_DI1_DW_GEN_11__DI1_PT_1_11           0x1F04068C,0x0000000C
+#define SRM_DI1_DW_GEN_11__DI1_PT_0_11           0x1F04068C,0x00000003
+
+#define SRM_DI1_DW_GEN_11__ADDR                            0x1F04068C
+#define SRM_DI1_DW_GEN_11__EMPTY                   0x1F04068C,0x00000000
+#define SRM_DI1_DW_GEN_11__FULL                            0x1F04068C,0xffffffff
+#define SRM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11            0x1F04068C,0xFF000000
+#define SRM_DI1_DW_GEN_11__DI1_START_PERIOD_11     0x1F04068C,0x00FF0000
+#define SRM_DI1_DW_GEN_11__DI1_CST_11              0x1F04068C,0x0000C000
+#define SRM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11 0x1F04068C,0x000001F0
+#define SRM_DI1_DW_GEN_11__DI1_SERIAL_RS_11        0x1F04068C,0x0000000C
+#define SRM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11       0x1F04068C,0x00000003
+
+#define SRM_DI1_DW_SET0_0__ADDR                          0x1F040690
+#define SRM_DI1_DW_SET0_0__EMPTY       0x1F040690,0x00000000
+#define SRM_DI1_DW_SET0_0__FULL              0x1F040690,0xffffffff
+#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0              0x1F040690,0x01FF0000
+#define SRM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0      0x1F040690,0x000001FF
+
+#define SRM_DI1_DW_SET0_1__ADDR                          0x1F040694
+#define SRM_DI1_DW_SET0_1__EMPTY       0x1F040694,0x00000000
+#define SRM_DI1_DW_SET0_1__FULL              0x1F040694,0xffffffff
+#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1              0x1F040694,0x01FF0000
+#define SRM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1      0x1F040694,0x000001FF
+
+#define SRM_DI1_DW_SET0_2__ADDR                          0x1F040698
+#define SRM_DI1_DW_SET0_2__EMPTY       0x1F040698,0x00000000
+#define SRM_DI1_DW_SET0_2__FULL              0x1F040698,0xffffffff
+#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2              0x1F040698,0x01FF0000
+#define SRM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2      0x1F040698,0x000001FF
+
+#define SRM_DI1_DW_SET0_3__ADDR                          0x1F04069C
+#define SRM_DI1_DW_SET0_3__EMPTY       0x1F04069C,0x00000000
+#define SRM_DI1_DW_SET0_3__FULL              0x1F04069C,0xffffffff
+#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3              0x1F04069C,0x01FF0000
+#define SRM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3      0x1F04069C,0x000001FF
+
+#define SRM_DI1_DW_SET0_4__ADDR                          0x1F0406A0
+#define SRM_DI1_DW_SET0_4__EMPTY       0x1F0406A0,0x00000000
+#define SRM_DI1_DW_SET0_4__FULL              0x1F0406A0,0xffffffff
+#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4              0x1F0406A0,0x01FF0000
+#define SRM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4      0x1F0406A0,0x000001FF
+
+#define SRM_DI1_DW_SET0_5__ADDR                          0x1F0406A4
+#define SRM_DI1_DW_SET0_5__EMPTY       0x1F0406A4,0x00000000
+#define SRM_DI1_DW_SET0_5__FULL              0x1F0406A4,0xffffffff
+#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5              0x1F0406A4,0x01FF0000
+#define SRM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5      0x1F0406A4,0x000001FF
+
+#define SRM_DI1_DW_SET0_6__ADDR                          0x1F0406A8
+#define SRM_DI1_DW_SET0_6__EMPTY       0x1F0406A8,0x00000000
+#define SRM_DI1_DW_SET0_6__FULL              0x1F0406A8,0xffffffff
+#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6              0x1F0406A8,0x01FF0000
+#define SRM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6      0x1F0406A8,0x000001FF
+
+#define SRM_DI1_DW_SET0_7__ADDR                          0x1F0406AC
+#define SRM_DI1_DW_SET0_7__EMPTY       0x1F0406AC,0x00000000
+#define SRM_DI1_DW_SET0_7__FULL              0x1F0406AC,0xffffffff
+#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7              0x1F0406AC,0x01FF0000
+#define SRM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7      0x1F0406AC,0x000001FF
+
+#define SRM_DI1_DW_SET0_8__ADDR                          0x1F0406B0
+#define SRM_DI1_DW_SET0_8__EMPTY       0x1F0406B0,0x00000000
+#define SRM_DI1_DW_SET0_8__FULL              0x1F0406B0,0xffffffff
+#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8              0x1F0406B0,0x01FF0000
+#define SRM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8      0x1F0406B0,0x000001FF
+
+#define SRM_DI1_DW_SET0_9__ADDR                          0x1F0406B4
+#define SRM_DI1_DW_SET0_9__EMPTY       0x1F0406B4,0x00000000
+#define SRM_DI1_DW_SET0_9__FULL              0x1F0406B4,0xffffffff
+#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9              0x1F0406B4,0x01FF0000
+#define SRM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9      0x1F0406B4,0x000001FF
+
+#define SRM_DI1_DW_SET0_10__ADDR                  0x1F0406B8
+#define SRM_DI1_DW_SET0_10__EMPTY      0x1F0406B8,0x00000000
+#define SRM_DI1_DW_SET0_10__FULL       0x1F0406B8,0xffffffff
+#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10      0x1F0406B8,0x01FF0000
+#define SRM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10              0x1F0406B8,0x000001FF
+
+#define SRM_DI1_DW_SET0_11__ADDR                  0x1F0406BC
+#define SRM_DI1_DW_SET0_11__EMPTY      0x1F0406BC,0x00000000
+#define SRM_DI1_DW_SET0_11__FULL       0x1F0406BC,0xffffffff
+#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11      0x1F0406BC,0x01FF0000
+#define SRM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11              0x1F0406BC,0x000001FF
+
+#define SRM_DI1_DW_SET1_0__ADDR                          0x1F0406C0
+#define SRM_DI1_DW_SET1_0__EMPTY       0x1F0406C0,0x00000000
+#define SRM_DI1_DW_SET1_0__FULL              0x1F0406C0,0xffffffff
+#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0              0x1F0406C0,0x01FF0000
+#define SRM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0      0x1F0406C0,0x000001FF
+
+#define SRM_DI1_DW_SET1_1__ADDR                          0x1F0406C4
+#define SRM_DI1_DW_SET1_1__EMPTY       0x1F0406C4,0x00000000
+#define SRM_DI1_DW_SET1_1__FULL              0x1F0406C4,0xffffffff
+#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1              0x1F0406C4,0x01FF0000
+#define SRM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1      0x1F0406C4,0x000001FF
+
+#define SRM_DI1_DW_SET1_2__ADDR                          0x1F0406C8
+#define SRM_DI1_DW_SET1_2__EMPTY       0x1F0406C8,0x00000000
+#define SRM_DI1_DW_SET1_2__FULL              0x1F0406C8,0xffffffff
+#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2              0x1F0406C8,0x01FF0000
+#define SRM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2      0x1F0406C8,0x000001FF
+
+#define SRM_DI1_DW_SET1_3__ADDR                          0x1F0406CC
+#define SRM_DI1_DW_SET1_3__EMPTY       0x1F0406CC,0x00000000
+#define SRM_DI1_DW_SET1_3__FULL              0x1F0406CC,0xffffffff
+#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3              0x1F0406CC,0x01FF0000
+#define SRM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3      0x1F0406CC,0x000001FF
+
+#define SRM_DI1_DW_SET1_4__ADDR                          0x1F0406D0
+#define SRM_DI1_DW_SET1_4__EMPTY       0x1F0406D0,0x00000000
+#define SRM_DI1_DW_SET1_4__FULL              0x1F0406D0,0xffffffff
+#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4              0x1F0406D0,0x01FF0000
+#define SRM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4      0x1F0406D0,0x000001FF
+
+#define SRM_DI1_DW_SET1_5__ADDR                          0x1F0406D4
+#define SRM_DI1_DW_SET1_5__EMPTY       0x1F0406D4,0x00000000
+#define SRM_DI1_DW_SET1_5__FULL              0x1F0406D4,0xffffffff
+#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5              0x1F0406D4,0x01FF0000
+#define SRM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5      0x1F0406D4,0x000001FF
+
+#define SRM_DI1_DW_SET1_6__ADDR                          0x1F0406D8
+#define SRM_DI1_DW_SET1_6__EMPTY       0x1F0406D8,0x00000000
+#define SRM_DI1_DW_SET1_6__FULL              0x1F0406D8,0xffffffff
+#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6              0x1F0406D8,0x01FF0000
+#define SRM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6      0x1F0406D8,0x000001FF
+
+#define SRM_DI1_DW_SET1_7__ADDR                          0x1F0406DC
+#define SRM_DI1_DW_SET1_7__EMPTY       0x1F0406DC,0x00000000
+#define SRM_DI1_DW_SET1_7__FULL              0x1F0406DC,0xffffffff
+#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7              0x1F0406DC,0x01FF0000
+#define SRM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7      0x1F0406DC,0x000001FF
+
+#define SRM_DI1_DW_SET1_8__ADDR                          0x1F0406E0
+#define SRM_DI1_DW_SET1_8__EMPTY       0x1F0406E0,0x00000000
+#define SRM_DI1_DW_SET1_8__FULL              0x1F0406E0,0xffffffff
+#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8              0x1F0406E0,0x01FF0000
+#define SRM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8      0x1F0406E0,0x000001FF
+
+#define SRM_DI1_DW_SET1_9__ADDR                          0x1F0406E4
+#define SRM_DI1_DW_SET1_9__EMPTY       0x1F0406E4,0x00000000
+#define SRM_DI1_DW_SET1_9__FULL              0x1F0406E4,0xffffffff
+#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9              0x1F0406E4,0x01FF0000
+#define SRM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9      0x1F0406E4,0x000001FF
+
+#define SRM_DI1_DW_SET1_10__ADDR                  0x1F0406E8
+#define SRM_DI1_DW_SET1_10__EMPTY      0x1F0406E8,0x00000000
+#define SRM_DI1_DW_SET1_10__FULL       0x1F0406E8,0xffffffff
+#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10      0x1F0406E8,0x01FF0000
+#define SRM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10              0x1F0406E8,0x000001FF
+
+#define SRM_DI1_DW_SET1_11__ADDR                  0x1F0406EC
+#define SRM_DI1_DW_SET1_11__EMPTY      0x1F0406EC,0x00000000
+#define SRM_DI1_DW_SET1_11__FULL       0x1F0406EC,0xffffffff
+#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11      0x1F0406EC,0x01FF0000
+#define SRM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11              0x1F0406EC,0x000001FF
+
+#define SRM_DI1_DW_SET2_0__ADDR                          0x1F0406F0
+#define SRM_DI1_DW_SET2_0__EMPTY       0x1F0406F0,0x00000000
+#define SRM_DI1_DW_SET2_0__FULL              0x1F0406F0,0xffffffff
+#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0              0x1F0406F0,0x01FF0000
+#define SRM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0      0x1F0406F0,0x000001FF
+
+#define SRM_DI1_DW_SET2_1__ADDR                          0x1F0406F4
+#define SRM_DI1_DW_SET2_1__EMPTY       0x1F0406F4,0x00000000
+#define SRM_DI1_DW_SET2_1__FULL              0x1F0406F4,0xffffffff
+#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1              0x1F0406F4,0x01FF0000
+#define SRM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1      0x1F0406F4,0x000001FF
+
+#define SRM_DI1_DW_SET2_2__ADDR                          0x1F0406F8
+#define SRM_DI1_DW_SET2_2__EMPTY       0x1F0406F8,0x00000000
+#define SRM_DI1_DW_SET2_2__FULL              0x1F0406F8,0xffffffff
+#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2              0x1F0406F8,0x01FF0000
+#define SRM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2      0x1F0406F8,0x000001FF
+
+#define SRM_DI1_DW_SET2_3__ADDR                          0x1F0406FC
+#define SRM_DI1_DW_SET2_3__EMPTY       0x1F0406FC,0x00000000
+#define SRM_DI1_DW_SET2_3__FULL              0x1F0406FC,0xffffffff
+#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3              0x1F0406FC,0x01FF0000
+#define SRM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3      0x1F0406FC,0x000001FF
+
+#define SRM_DI1_DW_SET2_4__ADDR                          0x1F040700
+#define SRM_DI1_DW_SET2_4__EMPTY       0x1F040700,0x00000000
+#define SRM_DI1_DW_SET2_4__FULL              0x1F040700,0xffffffff
+#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4              0x1F040700,0x01FF0000
+#define SRM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4      0x1F040700,0x000001FF
+
+#define SRM_DI1_DW_SET2_5__ADDR                          0x1F040704
+#define SRM_DI1_DW_SET2_5__EMPTY       0x1F040704,0x00000000
+#define SRM_DI1_DW_SET2_5__FULL              0x1F040704,0xffffffff
+#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5              0x1F040704,0x01FF0000
+#define SRM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5      0x1F040704,0x000001FF
+
+#define SRM_DI1_DW_SET2_6__ADDR                          0x1F040708
+#define SRM_DI1_DW_SET2_6__EMPTY       0x1F040708,0x00000000
+#define SRM_DI1_DW_SET2_6__FULL              0x1F040708,0xffffffff
+#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6              0x1F040708,0x01FF0000
+#define SRM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6      0x1F040708,0x000001FF
+
+#define SRM_DI1_DW_SET2_7__ADDR                          0x1F04070C
+#define SRM_DI1_DW_SET2_7__EMPTY       0x1F04070C,0x00000000
+#define SRM_DI1_DW_SET2_7__FULL              0x1F04070C,0xffffffff
+#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7              0x1F04070C,0x01FF0000
+#define SRM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7      0x1F04070C,0x000001FF
+
+#define SRM_DI1_DW_SET2_8__ADDR                          0x1F040710
+#define SRM_DI1_DW_SET2_8__EMPTY       0x1F040710,0x00000000
+#define SRM_DI1_DW_SET2_8__FULL              0x1F040710,0xffffffff
+#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8              0x1F040710,0x01FF0000
+#define SRM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8      0x1F040710,0x000001FF
+
+#define SRM_DI1_DW_SET2_9__ADDR                          0x1F040714
+#define SRM_DI1_DW_SET2_9__EMPTY       0x1F040714,0x00000000
+#define SRM_DI1_DW_SET2_9__FULL              0x1F040714,0xffffffff
+#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9              0x1F040714,0x01FF0000
+#define SRM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9      0x1F040714,0x000001FF
+
+#define SRM_DI1_DW_SET2_10__ADDR                  0x1F040718
+#define SRM_DI1_DW_SET2_10__EMPTY      0x1F040718,0x00000000
+#define SRM_DI1_DW_SET2_10__FULL       0x1F040718,0xffffffff
+#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10      0x1F040718,0x01FF0000
+#define SRM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10              0x1F040718,0x000001FF
+
+#define SRM_DI1_DW_SET2_11__ADDR                  0x1F04071C
+#define SRM_DI1_DW_SET2_11__EMPTY      0x1F04071C,0x00000000
+#define SRM_DI1_DW_SET2_11__FULL       0x1F04071C,0xffffffff
+#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11      0x1F04071C,0x01FF0000
+#define SRM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11              0x1F04071C,0x000001FF
+
+#define SRM_DI1_DW_SET3_0__ADDR                          0x1F040720
+#define SRM_DI1_DW_SET3_0__EMPTY       0x1F040720,0x00000000
+#define SRM_DI1_DW_SET3_0__FULL              0x1F040720,0xffffffff
+#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0              0x1F040720,0x01FF0000
+#define SRM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0      0x1F040720,0x000001FF
+
+#define SRM_DI1_DW_SET3_1__ADDR                          0x1F040724
+#define SRM_DI1_DW_SET3_1__EMPTY       0x1F040724,0x00000000
+#define SRM_DI1_DW_SET3_1__FULL              0x1F040724,0xffffffff
+#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1              0x1F040724,0x01FF0000
+#define SRM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1      0x1F040724,0x000001FF
+
+#define SRM_DI1_DW_SET3_2__ADDR                          0x1F040728
+#define SRM_DI1_DW_SET3_2__EMPTY       0x1F040728,0x00000000
+#define SRM_DI1_DW_SET3_2__FULL              0x1F040728,0xffffffff
+#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2              0x1F040728,0x01FF0000
+#define SRM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2      0x1F040728,0x000001FF
+
+#define SRM_DI1_DW_SET3_3__ADDR                          0x1F04072C
+#define SRM_DI1_DW_SET3_3__EMPTY       0x1F04072C,0x00000000
+#define SRM_DI1_DW_SET3_3__FULL              0x1F04072C,0xffffffff
+#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3              0x1F04072C,0x01FF0000
+#define SRM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3      0x1F04072C,0x000001FF
+
+#define SRM_DI1_DW_SET3_4__ADDR                          0x1F040730
+#define SRM_DI1_DW_SET3_4__EMPTY       0x1F040730,0x00000000
+#define SRM_DI1_DW_SET3_4__FULL              0x1F040730,0xffffffff
+#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4              0x1F040730,0x01FF0000
+#define SRM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4      0x1F040730,0x000001FF
+
+#define SRM_DI1_DW_SET3_5__ADDR                          0x1F040734
+#define SRM_DI1_DW_SET3_5__EMPTY       0x1F040734,0x00000000
+#define SRM_DI1_DW_SET3_5__FULL              0x1F040734,0xffffffff
+#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5              0x1F040734,0x01FF0000
+#define SRM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5      0x1F040734,0x000001FF
+
+#define SRM_DI1_DW_SET3_6__ADDR                          0x1F040738
+#define SRM_DI1_DW_SET3_6__EMPTY       0x1F040738,0x00000000
+#define SRM_DI1_DW_SET3_6__FULL              0x1F040738,0xffffffff
+#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6              0x1F040738,0x01FF0000
+#define SRM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6      0x1F040738,0x000001FF
+
+#define SRM_DI1_DW_SET3_7__ADDR                          0x1F04073C
+#define SRM_DI1_DW_SET3_7__EMPTY       0x1F04073C,0x00000000
+#define SRM_DI1_DW_SET3_7__FULL              0x1F04073C,0xffffffff
+#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7              0x1F04073C,0x01FF0000
+#define SRM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7      0x1F04073C,0x000001FF
+
+#define SRM_DI1_DW_SET3_8__ADDR                          0x1F040740
+#define SRM_DI1_DW_SET3_8__EMPTY       0x1F040740,0x00000000
+#define SRM_DI1_DW_SET3_8__FULL              0x1F040740,0xffffffff
+#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8              0x1F040740,0x01FF0000
+#define SRM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8      0x1F040740,0x000001FF
+
+#define SRM_DI1_DW_SET3_9__ADDR                          0x1F040744
+#define SRM_DI1_DW_SET3_9__EMPTY       0x1F040744,0x00000000
+#define SRM_DI1_DW_SET3_9__FULL              0x1F040744,0xffffffff
+#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9              0x1F040744,0x01FF0000
+#define SRM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9      0x1F040744,0x000001FF
+
+#define SRM_DI1_DW_SET3_10__ADDR                  0x1F040748
+#define SRM_DI1_DW_SET3_10__EMPTY      0x1F040748,0x00000000
+#define SRM_DI1_DW_SET3_10__FULL       0x1F040748,0xffffffff
+#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10      0x1F040748,0x01FF0000
+#define SRM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10              0x1F040748,0x000001FF
+
+#define SRM_DI1_DW_SET3_11__ADDR                  0x1F04074C
+#define SRM_DI1_DW_SET3_11__EMPTY      0x1F04074C,0x00000000
+#define SRM_DI1_DW_SET3_11__FULL       0x1F04074C,0xffffffff
+#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11      0x1F04074C,0x01FF0000
+#define SRM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11              0x1F04074C,0x000001FF
+
+#define SRM_DI1_STP_REP_1__ADDR                          0x1F040750
+#define SRM_DI1_STP_REP_1__EMPTY       0x1F040750,0x00000000
+#define SRM_DI1_STP_REP_1__FULL              0x1F040750,0xffffffff
+#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_2      0x1F040750,0x0FFF0000
+#define SRM_DI1_STP_REP_1__DI1_STEP_REPEAT_1      0x1F040750,0x00000FFF
+
+#define SRM_DI1_STP_REP_2__ADDR                          0x1F040754
+#define SRM_DI1_STP_REP_2__EMPTY       0x1F040754,0x00000000
+#define SRM_DI1_STP_REP_2__FULL              0x1F040754,0xffffffff
+#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_4      0x1F040754,0x0FFF0000
+#define SRM_DI1_STP_REP_2__DI1_STEP_REPEAT_3      0x1F040754,0x00000FFF
+
+#define SRM_DI1_STP_REP_3__ADDR                          0x1F040758
+#define SRM_DI1_STP_REP_3__EMPTY       0x1F040758,0x00000000
+#define SRM_DI1_STP_REP_3__FULL              0x1F040758,0xffffffff
+#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_6      0x1F040758,0x0FFF0000
+#define SRM_DI1_STP_REP_3__DI1_STEP_REPEAT_5      0x1F040758,0x00000FFF
+
+#define SRM_DI1_STP_REP_4__ADDR                          0x1F04075C
+#define SRM_DI1_STP_REP_4__EMPTY       0x1F04075C,0x00000000
+#define SRM_DI1_STP_REP_4__FULL              0x1F04075C,0xffffffff
+#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_8      0x1F04075C,0x0FFF0000
+#define SRM_DI1_STP_REP_4__DI1_STEP_REPEAT_7      0x1F04075C,0x00000FFF
+
+#define SRM_DI1_STP_REP_9__ADDR                          0x1F040760
+#define SRM_DI1_STP_REP_9__EMPTY       0x1F040760,0x00000000
+#define SRM_DI1_STP_REP_9__FULL              0x1F040760,0xffffffff
+#define SRM_DI1_STP_REP_9__DI1_STEP_REPEAT_9      0x1F040760,0x00000FFF
+
+#define SRM_DI1_SER_CONF__ADDR                  0x1F040764
+#define SRM_DI1_SER_CONF__EMPTY              0x1F040764,0x00000000
+#define SRM_DI1_SER_CONF__FULL      0x1F040764,0xffffffff
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1      0x1F040764,0xF0000000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0      0x1F040764,0x0F000000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1      0x1F040764,0x00F00000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0      0x1F040764,0x000F0000
+#define SRM_DI1_SER_CONF__DI1_SERIAL_LATCH      0x1F040764,0x0000FF00
+#define SRM_DI1_SER_CONF__DI1_LLA_SER_ACCESS      0x1F040764,0x00000020
+#define SRM_DI1_SER_CONF__DI1_SER_CLK_POLARITY      0x1F040764,0x00000010
+#define SRM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY      0x1F040764,0x00000008
+#define SRM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY       0x1F040764,0x00000004
+#define SRM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY       0x1F040764,0x00000002
+#define SRM_DI1_SER_CONF__DI1_WAIT4SERIAL      0x1F040764,0x00000001
+
+#define SRM_DI1_SSC__ADDR                  0x1F040768
+#define SRM_DI1_SSC__EMPTY      0x1F040768,0x00000000
+#define SRM_DI1_SSC__FULL      0x1F040768,0xffffffff
+#define SRM_DI1_SSC__DI1_PIN17_ERM     0x1F040768,0x00800000
+#define SRM_DI1_SSC__DI1_PIN16_ERM     0x1F040768,0x00400000
+#define SRM_DI1_SSC__DI1_PIN15_ERM     0x1F040768,0x00200000
+#define SRM_DI1_SSC__DI1_PIN14_ERM     0x1F040768,0x00100000
+#define SRM_DI1_SSC__DI1_PIN13_ERM     0x1F040768,0x00080000
+#define SRM_DI1_SSC__DI1_PIN12_ERM     0x1F040768,0x00040000
+#define SRM_DI1_SSC__DI1_PIN11_ERM     0x1F040768,0x00020000
+#define SRM_DI1_SSC__DI1_CS_ERM               0x1F040768,0x00010000
+#define SRM_DI1_SSC__DI1_WAIT_ON       0x1F040768,0x00000020
+#define SRM_DI1_SSC__DI1_BYTE_EN_RD_IN      0x1F040768,0x00000008
+#define SRM_DI1_SSC__DI1_BYTE_EN_PNTR      0x1F040768,0x00000007
+
+#define SRM_DI1_POL__ADDR                  0x1F04076C
+#define SRM_DI1_POL__EMPTY      0x1F04076C,0x00000000
+#define SRM_DI1_POL__FULL      0x1F04076C,0xffffffff
+#define SRM_DI1_POL__DI1_WAIT_POLARITY      0x1F04076C,0x04000000
+#define SRM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY      0x1F04076C,0x02000000
+#define SRM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY      0x1F04076C,0x01000000
+#define SRM_DI1_POL__DI1_CS1_DATA_POLARITY      0x1F04076C,0x00800000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_17       0x1F04076C,0x00400000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_16       0x1F04076C,0x00200000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_15       0x1F04076C,0x00100000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_14       0x1F04076C,0x00080000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_13       0x1F04076C,0x00040000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_12       0x1F04076C,0x00020000
+#define SRM_DI1_POL__DI1_CS1_POLARITY_11       0x1F04076C,0x00010000
+#define SRM_DI1_POL__DI1_CS0_DATA_POLARITY      0x1F04076C,0x00008000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_17       0x1F04076C,0x00004000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_16       0x1F04076C,0x00002000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_15       0x1F04076C,0x00001000
+#define SRM_DI1_POL__DI1_CS0_POLARITY_14       0x1F04076C,0x00000800
+#define SRM_DI1_POL__DI1_CS0_POLARITY_13       0x1F04076C,0x00000400
+#define SRM_DI1_POL__DI1_CS0_POLARITY_12       0x1F04076C,0x00000200
+#define SRM_DI1_POL__DI1_CS0_POLARITY_11       0x1F04076C,0x00000100
+#define SRM_DI1_POL__DI1_DRDY_DATA_POLARITY      0x1F04076C,0x00000080
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_17      0x1F04076C,0x00000040
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_16      0x1F04076C,0x00000020
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_15      0x1F04076C,0x00000010
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_14      0x1F04076C,0x00000008
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_13      0x1F04076C,0x00000004
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_12      0x1F04076C,0x00000002
+#define SRM_DI1_POL__DI1_DRDY_POLARITY_11      0x1F04076C,0x00000001
+
+#define SRM_DI1_AW0__ADDR                  0x1F040770
+#define SRM_DI1_AW0__EMPTY      0x1F040770,0x00000000
+#define SRM_DI1_AW0__FULL      0x1F040770,0xffffffff
+#define SRM_DI1_AW0__DI1_AW_TRIG_SEL      0x1F040770,0xF0000000
+#define SRM_DI1_AW0__DI1_AW_HEND       0x1F040770,0x0FFF0000
+#define SRM_DI1_AW0__DI1_AW_HCOUNT_SEL      0x1F040770,0x0000F000
+#define SRM_DI1_AW0__DI1_AW_HSTART      0x1F040770,0x00000FFF
+
+#define SRM_DI1_AW1__ADDR                  0x1F040774
+#define SRM_DI1_AW1__EMPTY      0x1F040774,0x00000000
+#define SRM_DI1_AW1__FULL      0x1F040774,0xffffffff
+#define SRM_DI1_AW1__DI1_AW_VEND       0x1F040774,0x0FFF0000
+#define SRM_DI1_AW1__DI1_AW_VCOUNT_SEL      0x1F040774,0x0000F000
+#define SRM_DI1_AW1__DI1_AW_VSTART      0x1F040774,0x00000FFF
+
+#define SRM_DI1_SCR_CONF__ADDR                  0x1F040778
+#define SRM_DI1_SCR_CONF__EMPTY              0x1F040778,0x00000000
+#define SRM_DI1_SCR_CONF__FULL      0x1F040778,0xffffffff
+#define SRM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT      0x1F040778,0x00000FFF
+
+#define SRM_DC_WR_CH_CONF_2__ADDR                  0x1F04045C
+#define SRM_DC_WR_CH_CONF_2__EMPTY      0x1F04045C,0x00000000
+#define SRM_DC_WR_CH_CONF_2__FULL      0x1F04045C,0xffffffff
+#define SRM_DC_WR_CH_CONF_2__PROG_START_TIME_2      0x1F04045C,0x07FF0000
+#define SRM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2       0x1F04045C,0x00000100
+#define SRM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2      0x1F04045C,0x000000E0
+#define SRM_DC_WR_CH_CONF_2__PROG_DISP_ID_2      0x1F04045C,0x00000018
+#define SRM_DC_WR_CH_CONF_2__PROG_DI_ID_2      0x1F04045C,0x00000004
+#define SRM_DC_WR_CH_CONF_2__W_SIZE_2      0x1F04045C,0x00000003
+
+#define SRM_DC_WR_CH_ADDR_2__ADDR                  0x1F040460
+#define SRM_DC_WR_CH_ADDR_2__EMPTY      0x1F040460,0x00000000
+#define SRM_DC_WR_CH_ADDR_2__FULL      0x1F040460,0xffffffff
+#define SRM_DC_WR_CH_ADDR_2__ST_ADDR_2      0x1F040460,0x1FFFFFFF
+
+#define SRM_DC_RL0_CH_2__ADDR                  0x1F040464
+#define SRM_DC_RL0_CH_2__EMPTY      0x1F040464,0x00000000
+#define SRM_DC_RL0_CH_2__FULL      0x1F040464,0xffffffff
+#define SRM_DC_RL0_CH_2__COD_NL_START_CHAN_2      0x1F040464,0xFF000000
+#define SRM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2              0x1F040464,0x000F0000
+#define SRM_DC_RL0_CH_2__COD_NF_START_CHAN_2      0x1F040464,0x0000FF00
+#define SRM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2              0x1F040464,0x0000000F
+
+#define SRM_DC_RL1_CH_2__ADDR                  0x1F040468
+#define SRM_DC_RL1_CH_2__EMPTY      0x1F040468,0x00000000
+#define SRM_DC_RL1_CH_2__FULL      0x1F040468,0xffffffff
+#define SRM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2       0x1F040468,0xFF000000
+#define SRM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2      0x1F040468,0x000F0000
+#define SRM_DC_RL1_CH_2__COD_EOF_START_CHAN_2      0x1F040468,0x0000FF00
+#define SRM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2       0x1F040468,0x0000000F
+
+#define SRM_DC_RL2_CH_2__ADDR                  0x1F04046C
+#define SRM_DC_RL2_CH_2__EMPTY      0x1F04046C,0x00000000
+#define SRM_DC_RL2_CH_2__FULL      0x1F04046C,0xffffffff
+#define SRM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2      0x1F04046C,0xFF000000
+#define SRM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2      0x1F04046C,0x000F0000
+#define SRM_DC_RL2_CH_2__COD_EOL_START_CHAN_2      0x1F04046C,0x0000FF00
+#define SRM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2       0x1F04046C,0x0000000F
+
+#define SRM_DC_RL3_CH_2__ADDR                  0x1F040470
+#define SRM_DC_RL3_CH_2__EMPTY      0x1F040470,0x00000000
+#define SRM_DC_RL3_CH_2__FULL      0x1F040470,0xffffffff
+#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2      0x1F040470,0xFF000000
+#define SRM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2      0x1F040470,0x000F0000
+#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2      0x1F040470,0x0000FF00
+#define SRM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2      0x1F040470,0x0000000F
+
+#define SRM_DC_RL4_CH_2__ADDR                  0x1F040474
+#define SRM_DC_RL4_CH_2__EMPTY      0x1F040474,0x00000000
+#define SRM_DC_RL4_CH_2__FULL      0x1F040474,0xffffffff
+#define SRM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2      0x1F040474,0x0000FF00
+#define SRM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2      0x1F040474,0x0000000F
+
+#define SRM_DC_WR_CH_CONF_6__ADDR                  0x1F040478
+#define SRM_DC_WR_CH_CONF_6__EMPTY      0x1F040478,0x00000000
+#define SRM_DC_WR_CH_CONF_6__FULL      0x1F040478,0xffffffff
+#define SRM_DC_WR_CH_CONF_6__PROG_START_TIME_6      0x1F040478,0x07FF0000
+#define SRM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6       0x1F040478,0x00000100
+#define SRM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6      0x1F040478,0x000000E0
+#define SRM_DC_WR_CH_CONF_6__PROG_DISP_ID_6      0x1F040478,0x00000018
+#define SRM_DC_WR_CH_CONF_6__PROG_DI_ID_6      0x1F040478,0x00000004
+#define SRM_DC_WR_CH_CONF_6__W_SIZE_6      0x1F040478,0x00000003
+
+#define SRM_DC_WR_CH_ADDR_6__ADDR                  0x1F04047C
+#define SRM_DC_WR_CH_ADDR_6__EMPTY      0x1F04047C,0x00000000
+#define SRM_DC_WR_CH_ADDR_6__FULL      0x1F04047C,0xffffffff
+#define SRM_DC_WR_CH_ADDR_6__ST_ADDR_6      0x1F04047C,0x1FFFFFFF
+
+#define SRM_DC_RL0_CH_6__ADDR                  0x1F040480
+#define SRM_DC_RL0_CH_6__EMPTY      0x1F040480,0x00000000
+#define SRM_DC_RL0_CH_6__FULL      0x1F040480,0xffffffff
+#define SRM_DC_RL0_CH_6__COD_NL_START_CHAN_6      0x1F040480,0xFF000000
+#define SRM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6              0x1F040480,0x000F0000
+#define SRM_DC_RL0_CH_6__COD_NF_START_CHAN_6      0x1F040480,0x0000FF00
+#define SRM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6              0x1F040480,0x0000000F
+
+#define SRM_DC_RL1_CH_6__ADDR                  0x1F040484
+#define SRM_DC_RL1_CH_6__EMPTY      0x1F040484,0x00000000
+#define SRM_DC_RL1_CH_6__FULL      0x1F040484,0xffffffff
+#define SRM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6       0x1F040484,0xFF000000
+#define SRM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6      0x1F040484,0x000F0000
+#define SRM_DC_RL1_CH_6__COD_EOF_START_CHAN_6      0x1F040484,0x0000FF00
+#define SRM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6       0x1F040484,0x0000000F
+
+#define SRM_DC_RL2_CH_6__ADDR                  0x1F040488
+#define SRM_DC_RL2_CH_6__EMPTY      0x1F040488,0x00000000
+#define SRM_DC_RL2_CH_6__FULL      0x1F040488,0xffffffff
+#define SRM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6      0x1F040488,0xFF000000
+#define SRM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6      0x1F040488,0x000F0000
+#define SRM_DC_RL2_CH_6__COD_EOL_START_CHAN_6      0x1F040488,0x0000FF00
+#define SRM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6       0x1F040488,0x0000000F
+
+#define SRM_DC_RL3_CH_6__ADDR                  0x1F04048C
+#define SRM_DC_RL3_CH_6__EMPTY      0x1F04048C,0x00000000
+#define SRM_DC_RL3_CH_6__FULL      0x1F04048C,0xffffffff
+#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6      0x1F04048C,0xFF000000
+#define SRM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6      0x1F04048C,0x000F0000
+#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6      0x1F04048C,0x0000FF00
+#define SRM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6      0x1F04048C,0x0000000F
+
+#define SRM_DC_RL4_CH_6__ADDR                  0x1F040490
+#define SRM_DC_RL4_CH_6__EMPTY      0x1F040490,0x00000000
+#define SRM_DC_RL4_CH_6__FULL      0x1F040490,0xffffffff
+#define SRM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6      0x1F040490,0x0000FF00
+#define SRM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6      0x1F040490,0x0000000F
+
+#define IPU_MEM_DC_MICROCODE_BASE_ADDR 0x1F080000
+
+#define IPU_ISP_TBPR_0__ADDR                  0x1F0C0000
+#define IPU_ISP_TBPR_0__EMPTY      0x1F0C0000,0x00000000
+#define IPU_ISP_TBPR_0__FULL       0x1F0C0000,0xffffffff
+#define IPU_ISP_TBPR_0__HCB_0      0x1F0C0000,0x0FFF0000
+#define IPU_ISP_TBPR_0__VCB_0      0x1F0C0000,0x00000FFF
+
+#define IPU_ISP_TBPR_1__ADDR                  0x1F0C0004
+#define IPU_ISP_TBPR_1__EMPTY      0x1F0C0004,0x00000000
+#define IPU_ISP_TBPR_1__FULL       0x1F0C0004,0xffffffff
+#define IPU_ISP_TBPR_1__HCB_1      0x1F0C0004,0x0FFF0000
+#define IPU_ISP_TBPR_1__VCB_1      0x1F0C0004,0x00000FFF
+
+#define IPU_ISP_TBPR_2__ADDR                  0x1F0C0008
+#define IPU_ISP_TBPR_2__EMPTY      0x1F0C0008,0x00000000
+#define IPU_ISP_TBPR_2__FULL       0x1F0C0008,0xffffffff
+#define IPU_ISP_TBPR_2__HCB_2      0x1F0C0008,0x0FFF0000
+#define IPU_ISP_TBPR_2__VCB_2      0x1F0C0008,0x00000FFF
+
+#define IPU_ISP_TBPR_3__ADDR                  0x1F0C000C
+#define IPU_ISP_TBPR_3__EMPTY      0x1F0C000C,0x00000000
+#define IPU_ISP_TBPR_3__FULL       0x1F0C000C,0xffffffff
+#define IPU_ISP_TBPR_3__HCB_3      0x1F0C000C,0x0FFF0000
+#define IPU_ISP_TBPR_3__VCB_3      0x1F0C000C,0x00000FFF
+
+#define IPU_ISP_TBPR_4__ADDR                  0x1F0C0010
+#define IPU_ISP_TBPR_4__EMPTY      0x1F0C0010,0x00000000
+#define IPU_ISP_TBPR_4__FULL       0x1F0C0010,0xffffffff
+#define IPU_ISP_TBPR_4__HCB_4      0x1F0C0010,0x0FFF0000
+#define IPU_ISP_TBPR_4__VCB_4      0x1F0C0010,0x00000FFF
+
+#define IPU_ISP_TBPR_5__ADDR                  0x1F0C0014
+#define IPU_ISP_TBPR_5__EMPTY      0x1F0C0014,0x00000000
+#define IPU_ISP_TBPR_5__FULL       0x1F0C0014,0xffffffff
+#define IPU_ISP_TBPR_5__HCB_5      0x1F0C0014,0x0FFF0000
+#define IPU_ISP_TBPR_5__VCB_5      0x1F0C0014,0x00000FFF
+
+#define IPU_ISP_TBPR_6__ADDR                  0x1F0C0018
+#define IPU_ISP_TBPR_6__EMPTY      0x1F0C0018,0x00000000
+#define IPU_ISP_TBPR_6__FULL       0x1F0C0018,0xffffffff
+#define IPU_ISP_TBPR_6__HCB_6      0x1F0C0018,0x0FFF0000
+#define IPU_ISP_TBPR_6__VCB_6      0x1F0C0018,0x00000FFF
+
+#define IPU_ISP_TBPR_7__ADDR                  0x1F0C001C
+#define IPU_ISP_TBPR_7__EMPTY      0x1F0C001C,0x00000000
+#define IPU_ISP_TBPR_7__FULL       0x1F0C001C,0xffffffff
+#define IPU_ISP_TBPR_7__HCB_7      0x1F0C001C,0x0FFF0000
+#define IPU_ISP_TBPR_7__VCB_7      0x1F0C001C,0x00000FFF
+
+#define IPU_ISP_TBPR_8__ADDR                  0x1F0C0020
+#define IPU_ISP_TBPR_8__EMPTY      0x1F0C0020,0x00000000
+#define IPU_ISP_TBPR_8__FULL       0x1F0C0020,0xffffffff
+#define IPU_ISP_TBPR_8__HCB_8      0x1F0C0020,0x0FFF0000
+#define IPU_ISP_TBPR_8__VCB_8      0x1F0C0020,0x00000FFF
+
+#define IPU_ISP_TBPR_9__ADDR                  0x1F0C0024
+#define IPU_ISP_TBPR_9__EMPTY      0x1F0C0024,0x00000000
+#define IPU_ISP_TBPR_9__FULL       0x1F0C0024,0xffffffff
+#define IPU_ISP_TBPR_9__HCB_9      0x1F0C0024,0x0FFF0000
+#define IPU_ISP_TBPR_9__VCB_9      0x1F0C0024,0x00000FFF
+
+#define IPU_ISP_TBPR_10__ADDR                  0x1F0C0028
+#define IPU_ISP_TBPR_10__EMPTY      0x1F0C0028,0x00000000
+#define IPU_ISP_TBPR_10__FULL       0x1F0C0028,0xffffffff
+#define IPU_ISP_TBPR_10__HCB_10              0x1F0C0028,0x0FFF0000
+#define IPU_ISP_TBPR_10__VCB_10              0x1F0C0028,0x00000FFF
+
+#define IPU_ISP_TBPR_11__ADDR                  0x1F0C002C
+#define IPU_ISP_TBPR_11__EMPTY      0x1F0C002C,0x00000000
+#define IPU_ISP_TBPR_11__FULL       0x1F0C002C,0xffffffff
+#define IPU_ISP_TBPR_11__HCB_11              0x1F0C002C,0x0FFF0000
+#define IPU_ISP_TBPR_11__VCB_11              0x1F0C002C,0x00000FFF
+
+#define IPU_ISP_TBPR_12__ADDR                  0x1F0C0030
+#define IPU_ISP_TBPR_12__EMPTY      0x1F0C0030,0x00000000
+#define IPU_ISP_TBPR_12__FULL       0x1F0C0030,0xffffffff
+#define IPU_ISP_TBPR_12__HCB_12              0x1F0C0030,0x0FFF0000
+#define IPU_ISP_TBPR_12__VCB_12              0x1F0C0030,0x00000FFF
+
+#define IPU_ISP_TBPR_13__ADDR                  0x1F0C0034
+#define IPU_ISP_TBPR_13__EMPTY      0x1F0C0034,0x00000000
+#define IPU_ISP_TBPR_13__FULL       0x1F0C0034,0xffffffff
+#define IPU_ISP_TBPR_13__HCB_13              0x1F0C0034,0x0FFF0000
+#define IPU_ISP_TBPR_13__VCB_13              0x1F0C0034,0x00000FFF
+
+#define IPU_ISP_TBPR_14__ADDR                  0x1F0C0038
+#define IPU_ISP_TBPR_14__EMPTY      0x1F0C0038,0x00000000
+#define IPU_ISP_TBPR_14__FULL       0x1F0C0038,0xffffffff
+#define IPU_ISP_TBPR_14__HCB_14              0x1F0C0038,0x0FFF0000
+#define IPU_ISP_TBPR_14__VCB_14              0x1F0C0038,0x00000FFF
+
+#define IPU_ISP_TBPR_15__ADDR                  0x1F0C003C
+#define IPU_ISP_TBPR_15__EMPTY      0x1F0C003C,0x00000000
+#define IPU_ISP_TBPR_15__FULL       0x1F0C003C,0xffffffff
+#define IPU_ISP_TBPR_15__HCB_15              0x1F0C003C,0x0FFF0000
+#define IPU_ISP_TBPR_15__VCB_15              0x1F0C003C,0x00000FFF
+
+#define IPU_ISP_TBPR_16__ADDR                  0x1F0C0040
+#define IPU_ISP_TBPR_16__EMPTY      0x1F0C0040,0x00000000
+#define IPU_ISP_TBPR_16__FULL       0x1F0C0040,0xffffffff
+#define IPU_ISP_TBPR_16__HCB_16              0x1F0C0040,0x0FFF0000
+#define IPU_ISP_TBPR_16__VCB_16              0x1F0C0040,0x00000FFF
+
+#define IPU_ISP_TBPR_17__ADDR                  0x1F0C0044
+#define IPU_ISP_TBPR_17__EMPTY      0x1F0C0044,0x00000000
+#define IPU_ISP_TBPR_17__FULL       0x1F0C0044,0xffffffff
+#define IPU_ISP_TBPR_17__HCB_17              0x1F0C0044,0x0FFF0000
+#define IPU_ISP_TBPR_17__VCB_17              0x1F0C0044,0x00000FFF
+
+#define IPU_ISP_TBPR_18__ADDR                  0x1F0C0048
+#define IPU_ISP_TBPR_18__EMPTY      0x1F0C0048,0x00000000
+#define IPU_ISP_TBPR_18__FULL       0x1F0C0048,0xffffffff
+#define IPU_ISP_TBPR_18__HCB_18              0x1F0C0048,0x0FFF0000
+#define IPU_ISP_TBPR_18__VCB_18              0x1F0C0048,0x00000FFF
+
+#define IPU_ISP_TBPR_19__ADDR                  0x1F0C004C
+#define IPU_ISP_TBPR_19__EMPTY      0x1F0C004C,0x00000000
+#define IPU_ISP_TBPR_19__FULL       0x1F0C004C,0xffffffff
+#define IPU_ISP_TBPR_19__HCB_19              0x1F0C004C,0x0FFF0000
+#define IPU_ISP_TBPR_19__VCB_19              0x1F0C004C,0x00000FFF
+
+#define IPU_ISP_TBPR_20__ADDR                  0x1F0C0050
+#define IPU_ISP_TBPR_20__EMPTY      0x1F0C0050,0x00000000
+#define IPU_ISP_TBPR_20__FULL       0x1F0C0050,0xffffffff
+#define IPU_ISP_TBPR_20__HCB_20              0x1F0C0050,0x0FFF0000
+#define IPU_ISP_TBPR_20__VCB_20              0x1F0C0050,0x00000FFF
+
+#define IPU_ISP_TBPR_21__ADDR                  0x1F0C0054
+#define IPU_ISP_TBPR_21__EMPTY      0x1F0C0054,0x00000000
+#define IPU_ISP_TBPR_21__FULL       0x1F0C0054,0xffffffff
+#define IPU_ISP_TBPR_21__HCB_21              0x1F0C0054,0x0FFF0000
+#define IPU_ISP_TBPR_21__VCB_21              0x1F0C0054,0x00000FFF
+
+#define IPU_ISP_TBPR_22__ADDR                  0x1F0C0058
+#define IPU_ISP_TBPR_22__EMPTY      0x1F0C0058,0x00000000
+#define IPU_ISP_TBPR_22__FULL       0x1F0C0058,0xffffffff
+#define IPU_ISP_TBPR_22__HCB_22              0x1F0C0058,0x0FFF0000
+#define IPU_ISP_TBPR_22__VCB_22              0x1F0C0058,0x00000FFF
+
+#define IPU_ISP_TBPR_23__ADDR                  0x1F0C005C
+#define IPU_ISP_TBPR_23__EMPTY      0x1F0C005C,0x00000000
+#define IPU_ISP_TBPR_23__FULL       0x1F0C005C,0xffffffff
+#define IPU_ISP_TBPR_23__HCB_23              0x1F0C005C,0x0FFF0000
+#define IPU_ISP_TBPR_23__VCB_23              0x1F0C005C,0x00000FFF
+
+#define IPU_ISP_TBPR_24__ADDR                  0x1F0C0060
+#define IPU_ISP_TBPR_24__EMPTY      0x1F0C0060,0x00000000
+#define IPU_ISP_TBPR_24__FULL       0x1F0C0060,0xffffffff
+#define IPU_ISP_TBPR_24__HCB_24              0x1F0C0060,0x0FFF0000
+#define IPU_ISP_TBPR_24__VCB_24              0x1F0C0060,0x00000FFF
+
+#define IPU_ISP_TBPR_25__ADDR                  0x1F0C0064
+#define IPU_ISP_TBPR_25__EMPTY      0x1F0C0064,0x00000000
+#define IPU_ISP_TBPR_25__FULL       0x1F0C0064,0xffffffff
+#define IPU_ISP_TBPR_25__HCB_25              0x1F0C0064,0x0FFF0000
+#define IPU_ISP_TBPR_25__VCB_25              0x1F0C0064,0x00000FFF
+
+#define IPU_ISP_TBPR_26__ADDR                  0x1F0C0068
+#define IPU_ISP_TBPR_26__EMPTY      0x1F0C0068,0x00000000
+#define IPU_ISP_TBPR_26__FULL       0x1F0C0068,0xffffffff
+#define IPU_ISP_TBPR_26__HCB_26              0x1F0C0068,0x0FFF0000
+#define IPU_ISP_TBPR_26__VCB_26              0x1F0C0068,0x00000FFF
+
+#define IPU_ISP_TBPR_27__ADDR                  0x1F0C006C
+#define IPU_ISP_TBPR_27__EMPTY      0x1F0C006C,0x00000000
+#define IPU_ISP_TBPR_27__FULL       0x1F0C006C,0xffffffff
+#define IPU_ISP_TBPR_27__HCB_27              0x1F0C006C,0x0FFF0000
+#define IPU_ISP_TBPR_27__VCB_27              0x1F0C006C,0x00000FFF
+
+#define IPU_ISP_TBPR_28__ADDR                  0x1F0C0070
+#define IPU_ISP_TBPR_28__EMPTY      0x1F0C0070,0x00000000
+#define IPU_ISP_TBPR_28__FULL       0x1F0C0070,0xffffffff
+#define IPU_ISP_TBPR_28__HCB_28              0x1F0C0070,0x0FFF0000
+#define IPU_ISP_TBPR_28__VCB_28              0x1F0C0070,0x00000FFF
+
+#define IPU_ISP_TBPR_29__ADDR                  0x1F0C0074
+#define IPU_ISP_TBPR_29__EMPTY      0x1F0C0074,0x00000000
+#define IPU_ISP_TBPR_29__FULL       0x1F0C0074,0xffffffff
+#define IPU_ISP_TBPR_29__HCB_29              0x1F0C0074,0x0FFF0000
+#define IPU_ISP_TBPR_29__VCB_29              0x1F0C0074,0x00000FFF
+
+#define IPU_ISP_TBPR_30__ADDR                  0x1F0C0078
+#define IPU_ISP_TBPR_30__EMPTY      0x1F0C0078,0x00000000
+#define IPU_ISP_TBPR_30__FULL       0x1F0C0078,0xffffffff
+#define IPU_ISP_TBPR_30__HCB_30              0x1F0C0078,0x0FFF0000
+#define IPU_ISP_TBPR_30__VCB_30              0x1F0C0078,0x00000FFF
+
+#define IPU_ISP_TBPR_31__ADDR                  0x1F0C007C
+#define IPU_ISP_TBPR_31__EMPTY      0x1F0C007C,0x00000000
+#define IPU_ISP_TBPR_31__FULL       0x1F0C007C,0xffffffff
+#define IPU_ISP_TBPR_31__HCB_31              0x1F0C007C,0x0FFF0000
+#define IPU_ISP_TBPR_31__VCB_31              0x1F0C007C,0x00000FFF
+
+#define IPU_ISP_TBPR_32__ADDR                  0x1F0C0080
+#define IPU_ISP_TBPR_32__EMPTY      0x1F0C0080,0x00000000
+#define IPU_ISP_TBPR_32__FULL       0x1F0C0080,0xffffffff
+#define IPU_ISP_TBPR_32__HCB_32              0x1F0C0080,0x0FFF0000
+#define IPU_ISP_TBPR_32__VCB_32              0x1F0C0080,0x00000FFF
+
+#define IPU_ISP_TBPR_33__ADDR                  0x1F0C0084
+#define IPU_ISP_TBPR_33__EMPTY      0x1F0C0084,0x00000000
+#define IPU_ISP_TBPR_33__FULL       0x1F0C0084,0xffffffff
+#define IPU_ISP_TBPR_33__HCB_33              0x1F0C0084,0x0FFF0000
+#define IPU_ISP_TBPR_33__VCB_33              0x1F0C0084,0x00000FFF
+
+#define IPU_ISP_TBPR_34__ADDR                  0x1F0C0088
+#define IPU_ISP_TBPR_34__EMPTY      0x1F0C0088,0x00000000
+#define IPU_ISP_TBPR_34__FULL       0x1F0C0088,0xffffffff
+#define IPU_ISP_TBPR_34__HCB_34              0x1F0C0088,0x0FFF0000
+#define IPU_ISP_TBPR_34__VCB_34              0x1F0C0088,0x00000FFF
+
+#define IPU_ISP_TBPR_35__ADDR                  0x1F0C008C
+#define IPU_ISP_TBPR_35__EMPTY      0x1F0C008C,0x00000000
+#define IPU_ISP_TBPR_35__FULL       0x1F0C008C,0xffffffff
+#define IPU_ISP_TBPR_35__HCB_35              0x1F0C008C,0x0FFF0000
+#define IPU_ISP_TBPR_35__VCB_35              0x1F0C008C,0x00000FFF
+
+#define IPU_ISP_TBPR_36__ADDR                  0x1F0C0090
+#define IPU_ISP_TBPR_36__EMPTY      0x1F0C0090,0x00000000
+#define IPU_ISP_TBPR_36__FULL       0x1F0C0090,0xffffffff
+#define IPU_ISP_TBPR_36__HCB_36              0x1F0C0090,0x0FFF0000
+#define IPU_ISP_TBPR_36__VCB_36              0x1F0C0090,0x00000FFF
+
+#define IPU_ISP_TBPR_37__ADDR                  0x1F0C0094
+#define IPU_ISP_TBPR_37__EMPTY      0x1F0C0094,0x00000000
+#define IPU_ISP_TBPR_37__FULL       0x1F0C0094,0xffffffff
+#define IPU_ISP_TBPR_37__HCB_37              0x1F0C0094,0x0FFF0000
+#define IPU_ISP_TBPR_37__VCB_37              0x1F0C0094,0x00000FFF
+
+#define IPU_ISP_TBPR_38__ADDR                  0x1F0C0098
+#define IPU_ISP_TBPR_38__EMPTY      0x1F0C0098,0x00000000
+#define IPU_ISP_TBPR_38__FULL       0x1F0C0098,0xffffffff
+#define IPU_ISP_TBPR_38__HCB_38              0x1F0C0098,0x0FFF0000
+#define IPU_ISP_TBPR_38__VCB_38              0x1F0C0098,0x00000FFF
+
+#define IPU_ISP_TBPR_39__ADDR                  0x1F0C009C
+#define IPU_ISP_TBPR_39__EMPTY      0x1F0C009C,0x00000000
+#define IPU_ISP_TBPR_39__FULL       0x1F0C009C,0xffffffff
+#define IPU_ISP_TBPR_39__HCB_39              0x1F0C009C,0x0FFF0000
+#define IPU_ISP_TBPR_39__VCB_39              0x1F0C009C,0x00000FFF
+
+#define IPU_ISP_TBPR_40__ADDR                  0x1F0C00A0
+#define IPU_ISP_TBPR_40__EMPTY      0x1F0C00A0,0x00000000
+#define IPU_ISP_TBPR_40__FULL       0x1F0C00A0,0xffffffff
+#define IPU_ISP_TBPR_40__HCB_40              0x1F0C00A0,0x0FFF0000
+#define IPU_ISP_TBPR_40__VCB_40              0x1F0C00A0,0x00000FFF
+
+#define IPU_ISP_TBPR_41__ADDR                  0x1F0C00A4
+#define IPU_ISP_TBPR_41__EMPTY      0x1F0C00A4,0x00000000
+#define IPU_ISP_TBPR_41__FULL       0x1F0C00A4,0xffffffff
+#define IPU_ISP_TBPR_41__HCB_41              0x1F0C00A4,0x0FFF0000
+#define IPU_ISP_TBPR_41__VCB_41              0x1F0C00A4,0x00000FFF
+
+#define IPU_ISP_TBPR_42__ADDR                  0x1F0C00A8
+#define IPU_ISP_TBPR_42__EMPTY      0x1F0C00A8,0x00000000
+#define IPU_ISP_TBPR_42__FULL       0x1F0C00A8,0xffffffff
+#define IPU_ISP_TBPR_42__HCB_42              0x1F0C00A8,0x0FFF0000
+#define IPU_ISP_TBPR_42__VCB_42              0x1F0C00A8,0x00000FFF
+
+#define IPU_ISP_TBPR_43__ADDR                  0x1F0C00AC
+#define IPU_ISP_TBPR_43__EMPTY      0x1F0C00AC,0x00000000
+#define IPU_ISP_TBPR_43__FULL       0x1F0C00AC,0xffffffff
+#define IPU_ISP_TBPR_43__HCB_43              0x1F0C00AC,0x0FFF0000
+#define IPU_ISP_TBPR_43__VCB_43              0x1F0C00AC,0x00000FFF
+
+#define IPU_ISP_TBPR_44__ADDR                  0x1F0C00B0
+#define IPU_ISP_TBPR_44__EMPTY      0x1F0C00B0,0x00000000
+#define IPU_ISP_TBPR_44__FULL       0x1F0C00B0,0xffffffff
+#define IPU_ISP_TBPR_44__HCB_44              0x1F0C00B0,0x0FFF0000
+#define IPU_ISP_TBPR_44__VCB_44              0x1F0C00B0,0x00000FFF
+
+#define IPU_ISP_TBPR_45__ADDR                  0x1F0C00B4
+#define IPU_ISP_TBPR_45__EMPTY      0x1F0C00B4,0x00000000
+#define IPU_ISP_TBPR_45__FULL       0x1F0C00B4,0xffffffff
+#define IPU_ISP_TBPR_45__HCB_45              0x1F0C00B4,0x0FFF0000
+#define IPU_ISP_TBPR_45__VCB_45              0x1F0C00B4,0x00000FFF
+
+#define IPU_ISP_TBPR_46__ADDR                  0x1F0C00B8
+#define IPU_ISP_TBPR_46__EMPTY      0x1F0C00B8,0x00000000
+#define IPU_ISP_TBPR_46__FULL       0x1F0C00B8,0xffffffff
+#define IPU_ISP_TBPR_46__HCB_46              0x1F0C00B8,0x0FFF0000
+#define IPU_ISP_TBPR_46__VCB_46              0x1F0C00B8,0x00000FFF
+
+#define IPU_ISP_TBPR_47__ADDR                  0x1F0C00BC
+#define IPU_ISP_TBPR_47__EMPTY      0x1F0C00BC,0x00000000
+#define IPU_ISP_TBPR_47__FULL       0x1F0C00BC,0xffffffff
+#define IPU_ISP_TBPR_47__HCB_47              0x1F0C00BC,0x0FFF0000
+#define IPU_ISP_TBPR_47__VCB_47              0x1F0C00BC,0x00000FFF
+
+#define IPU_ISP_TBPR_48__ADDR                  0x1F0C00C0
+#define IPU_ISP_TBPR_48__EMPTY      0x1F0C00C0,0x00000000
+#define IPU_ISP_TBPR_48__FULL       0x1F0C00C0,0xffffffff
+#define IPU_ISP_TBPR_48__HCB_48              0x1F0C00C0,0x0FFF0000
+#define IPU_ISP_TBPR_48__VCB_48              0x1F0C00C0,0x00000FFF
+
+#define IPU_ISP_TBPR_49__ADDR                  0x1F0C00C4
+#define IPU_ISP_TBPR_49__EMPTY      0x1F0C00C4,0x00000000
+#define IPU_ISP_TBPR_49__FULL       0x1F0C00C4,0xffffffff
+#define IPU_ISP_TBPR_49__HCB_49              0x1F0C00C4,0x0FFF0000
+#define IPU_ISP_TBPR_49__VCB_49              0x1F0C00C4,0x00000FFF
+
+#define IPU_ISP_TBPR_50__ADDR                  0x1F0C00C8
+#define IPU_ISP_TBPR_50__EMPTY      0x1F0C00C8,0x00000000
+#define IPU_ISP_TBPR_50__FULL       0x1F0C00C8,0xffffffff
+#define IPU_ISP_TBPR_50__HCB_50              0x1F0C00C8,0x0FFF0000
+#define IPU_ISP_TBPR_50__VCB_50              0x1F0C00C8,0x00000FFF
+
+#define IPU_ISP_TBPR_51__ADDR                  0x1F0C00CC
+#define IPU_ISP_TBPR_51__EMPTY      0x1F0C00CC,0x00000000
+#define IPU_ISP_TBPR_51__FULL       0x1F0C00CC,0xffffffff
+#define IPU_ISP_TBPR_51__HCB_51              0x1F0C00CC,0x0FFF0000
+#define IPU_ISP_TBPR_51__VCB_51              0x1F0C00CC,0x00000FFF
+
+#define IPU_ISP_TBPR_52__ADDR                  0x1F0C00D0
+#define IPU_ISP_TBPR_52__EMPTY      0x1F0C00D0,0x00000000
+#define IPU_ISP_TBPR_52__FULL       0x1F0C00D0,0xffffffff
+#define IPU_ISP_TBPR_52__HCB_52              0x1F0C00D0,0x0FFF0000
+#define IPU_ISP_TBPR_52__VCB_52              0x1F0C00D0,0x00000FFF
+
+#define IPU_ISP_TBPR_53__ADDR                  0x1F0C00D4
+#define IPU_ISP_TBPR_53__EMPTY      0x1F0C00D4,0x00000000
+#define IPU_ISP_TBPR_53__FULL       0x1F0C00D4,0xffffffff
+#define IPU_ISP_TBPR_53__HCB_53              0x1F0C00D4,0x0FFF0000
+#define IPU_ISP_TBPR_53__VCB_53              0x1F0C00D4,0x00000FFF
+
+#define IPU_ISP_TBPR_54__ADDR                  0x1F0C00D8
+#define IPU_ISP_TBPR_54__EMPTY      0x1F0C00D8,0x00000000
+#define IPU_ISP_TBPR_54__FULL       0x1F0C00D8,0xffffffff
+#define IPU_ISP_TBPR_54__HCB_54              0x1F0C00D8,0x0FFF0000
+#define IPU_ISP_TBPR_54__VCB_54              0x1F0C00D8,0x00000FFF
+
+#define IPU_ISP_TBPR_55__ADDR                  0x1F0C00DC
+#define IPU_ISP_TBPR_55__EMPTY      0x1F0C00DC,0x00000000
+#define IPU_ISP_TBPR_55__FULL       0x1F0C00DC,0xffffffff
+#define IPU_ISP_TBPR_55__HCB_55              0x1F0C00DC,0x0FFF0000
+#define IPU_ISP_TBPR_55__VCB_55              0x1F0C00DC,0x00000FFF
+
+#define IPU_ISP_TBPR_56__ADDR                  0x1F0C00E0
+#define IPU_ISP_TBPR_56__EMPTY      0x1F0C00E0,0x00000000
+#define IPU_ISP_TBPR_56__FULL       0x1F0C00E0,0xffffffff
+#define IPU_ISP_TBPR_56__HCB_56              0x1F0C00E0,0x0FFF0000
+#define IPU_ISP_TBPR_56__VCB_56              0x1F0C00E0,0x00000FFF
+
+#define IPU_ISP_TBPR_57__ADDR                  0x1F0C00E4
+#define IPU_ISP_TBPR_57__EMPTY      0x1F0C00E4,0x00000000
+#define IPU_ISP_TBPR_57__FULL       0x1F0C00E4,0xffffffff
+#define IPU_ISP_TBPR_57__HCB_57              0x1F0C00E4,0x0FFF0000
+#define IPU_ISP_TBPR_57__VCB_57              0x1F0C00E4,0x00000FFF
+
+#define IPU_ISP_TBPR_58__ADDR                  0x1F0C00E8
+#define IPU_ISP_TBPR_58__EMPTY      0x1F0C00E8,0x00000000
+#define IPU_ISP_TBPR_58__FULL       0x1F0C00E8,0xffffffff
+#define IPU_ISP_TBPR_58__HCB_58              0x1F0C00E8,0x0FFF0000
+#define IPU_ISP_TBPR_58__VCB_58              0x1F0C00E8,0x00000FFF
+
+#define IPU_ISP_TBPR_59__ADDR                  0x1F0C00EC
+#define IPU_ISP_TBPR_59__EMPTY      0x1F0C00EC,0x00000000
+#define IPU_ISP_TBPR_59__FULL       0x1F0C00EC,0xffffffff
+#define IPU_ISP_TBPR_59__HCB_59              0x1F0C00EC,0x0FFF0000
+#define IPU_ISP_TBPR_59__VCB_59              0x1F0C00EC,0x00000FFF
+
+#define IPU_ISP_TBPR_60__ADDR                  0x1F0C00F0
+#define IPU_ISP_TBPR_60__EMPTY      0x1F0C00F0,0x00000000
+#define IPU_ISP_TBPR_60__FULL       0x1F0C00F0,0xffffffff
+#define IPU_ISP_TBPR_60__HCB_60              0x1F0C00F0,0x0FFF0000
+#define IPU_ISP_TBPR_60__VCB_60              0x1F0C00F0,0x00000FFF
+
+#define IPU_ISP_TBPR_61__ADDR                  0x1F0C00F4
+#define IPU_ISP_TBPR_61__EMPTY      0x1F0C00F4,0x00000000
+#define IPU_ISP_TBPR_61__FULL       0x1F0C00F4,0xffffffff
+#define IPU_ISP_TBPR_61__HCB_61              0x1F0C00F4,0x0FFF0000
+#define IPU_ISP_TBPR_61__VCB_61              0x1F0C00F4,0x00000FFF
+
+#define IPU_ISP_TBPR_62__ADDR                  0x1F0C00F8
+#define IPU_ISP_TBPR_62__EMPTY      0x1F0C00F8,0x00000000
+#define IPU_ISP_TBPR_62__FULL       0x1F0C00F8,0xffffffff
+#define IPU_ISP_TBPR_62__HCB_62              0x1F0C00F8,0x0FFF0000
+#define IPU_ISP_TBPR_62__VCB_62              0x1F0C00F8,0x00000FFF
+
+#define IPU_ISP_TBPR_63__ADDR                  0x1F0C00FC
+#define IPU_ISP_TBPR_63__EMPTY      0x1F0C00FC,0x00000000
+#define IPU_ISP_TBPR_63__FULL       0x1F0C00FC,0xffffffff
+#define IPU_ISP_TBPR_63__HCB_63              0x1F0C00FC,0x0FFF0000
+#define IPU_ISP_TBPR_63__VCB_63              0x1F0C00FC,0x00000FFF
+
+#define SRM_ISP_TBPR_0__ADDR                  0x1F0C0100
+#define SRM_ISP_TBPR_0__EMPTY      0x1F0C0100,0x00000000
+#define SRM_ISP_TBPR_0__FULL       0x1F0C0100,0xffffffff
+#define SRM_ISP_TBPR_0__HCB_0      0x1F0C0100,0x0FFF0000
+#define SRM_ISP_TBPR_0__VCB_0      0x1F0C0100,0x00000FFF
+
+#define SRM_ISP_TBPR_1__ADDR                  0x1F0C0104
+#define SRM_ISP_TBPR_1__EMPTY      0x1F0C0104,0x00000000
+#define SRM_ISP_TBPR_1__FULL       0x1F0C0104,0xffffffff
+#define SRM_ISP_TBPR_1__HCB_1      0x1F0C0104,0x0FFF0000
+#define SRM_ISP_TBPR_1__VCB_1      0x1F0C0104,0x00000FFF
+
+#define SRM_ISP_TBPR_2__ADDR                  0x1F0C0108
+#define SRM_ISP_TBPR_2__EMPTY      0x1F0C0108,0x00000000
+#define SRM_ISP_TBPR_2__FULL       0x1F0C0108,0xffffffff
+#define SRM_ISP_TBPR_2__HCB_2      0x1F0C0108,0x0FFF0000
+#define SRM_ISP_TBPR_2__VCB_2      0x1F0C0108,0x00000FFF
+
+#define SRM_ISP_TBPR_3__ADDR                  0x1F0C010C
+#define SRM_ISP_TBPR_3__EMPTY      0x1F0C010C,0x00000000
+#define SRM_ISP_TBPR_3__FULL       0x1F0C010C,0xffffffff
+#define SRM_ISP_TBPR_3__HCB_3      0x1F0C010C,0x0FFF0000
+#define SRM_ISP_TBPR_3__VCB_3      0x1F0C010C,0x00000FFF
+
+#define SRM_ISP_TBPR_4__ADDR                  0x1F0C0110
+#define SRM_ISP_TBPR_4__EMPTY      0x1F0C0110,0x00000000
+#define SRM_ISP_TBPR_4__FULL       0x1F0C0110,0xffffffff
+#define SRM_ISP_TBPR_4__HCB_4      0x1F0C0110,0x0FFF0000
+#define SRM_ISP_TBPR_4__VCB_4      0x1F0C0110,0x00000FFF
+
+#define SRM_ISP_TBPR_5__ADDR                  0x1F0C0114
+#define SRM_ISP_TBPR_5__EMPTY      0x1F0C0114,0x00000000
+#define SRM_ISP_TBPR_5__FULL       0x1F0C0114,0xffffffff
+#define SRM_ISP_TBPR_5__HCB_5      0x1F0C0114,0x0FFF0000
+#define SRM_ISP_TBPR_5__VCB_5      0x1F0C0114,0x00000FFF
+
+#define SRM_ISP_TBPR_6__ADDR                  0x1F0C0118
+#define SRM_ISP_TBPR_6__EMPTY      0x1F0C0118,0x00000000
+#define SRM_ISP_TBPR_6__FULL       0x1F0C0118,0xffffffff
+#define SRM_ISP_TBPR_6__HCB_6      0x1F0C0118,0x0FFF0000
+#define SRM_ISP_TBPR_6__VCB_6      0x1F0C0118,0x00000FFF
+
+#define SRM_ISP_TBPR_7__ADDR                  0x1F0C011C
+#define SRM_ISP_TBPR_7__EMPTY      0x1F0C011C,0x00000000
+#define SRM_ISP_TBPR_7__FULL       0x1F0C011C,0xffffffff
+#define SRM_ISP_TBPR_7__HCB_7      0x1F0C011C,0x0FFF0000
+#define SRM_ISP_TBPR_7__VCB_7      0x1F0C011C,0x00000FFF
+
+#define SRM_ISP_TBPR_8__ADDR                  0x1F0C0120
+#define SRM_ISP_TBPR_8__EMPTY      0x1F0C0120,0x00000000
+#define SRM_ISP_TBPR_8__FULL       0x1F0C0120,0xffffffff
+#define SRM_ISP_TBPR_8__HCB_8      0x1F0C0120,0x0FFF0000
+#define SRM_ISP_TBPR_8__VCB_8      0x1F0C0120,0x00000FFF
+
+#define SRM_ISP_TBPR_9__ADDR                  0x1F0C0124
+#define SRM_ISP_TBPR_9__EMPTY      0x1F0C0124,0x00000000
+#define SRM_ISP_TBPR_9__FULL       0x1F0C0124,0xffffffff
+#define SRM_ISP_TBPR_9__HCB_9      0x1F0C0124,0x0FFF0000
+#define SRM_ISP_TBPR_9__VCB_9      0x1F0C0124,0x00000FFF
+
+#define SRM_ISP_TBPR_10__ADDR                  0x1F0C0128
+#define SRM_ISP_TBPR_10__EMPTY      0x1F0C0128,0x00000000
+#define SRM_ISP_TBPR_10__FULL       0x1F0C0128,0xffffffff
+#define SRM_ISP_TBPR_10__HCB_10              0x1F0C0128,0x0FFF0000
+#define SRM_ISP_TBPR_10__VCB_10              0x1F0C0128,0x00000FFF
+
+#define SRM_ISP_TBPR_11__ADDR                  0x1F0C012C
+#define SRM_ISP_TBPR_11__EMPTY      0x1F0C012C,0x00000000
+#define SRM_ISP_TBPR_11__FULL       0x1F0C012C,0xffffffff
+#define SRM_ISP_TBPR_11__HCB_11              0x1F0C012C,0x0FFF0000
+#define SRM_ISP_TBPR_11__VCB_11              0x1F0C012C,0x00000FFF
+
+#define SRM_ISP_TBPR_12__ADDR                  0x1F0C0130
+#define SRM_ISP_TBPR_12__EMPTY      0x1F0C0130,0x00000000
+#define SRM_ISP_TBPR_12__FULL       0x1F0C0130,0xffffffff
+#define SRM_ISP_TBPR_12__HCB_12              0x1F0C0130,0x0FFF0000
+#define SRM_ISP_TBPR_12__VCB_12              0x1F0C0130,0x00000FFF
+
+#define SRM_ISP_TBPR_13__ADDR                  0x1F0C0134
+#define SRM_ISP_TBPR_13__EMPTY      0x1F0C0134,0x00000000
+#define SRM_ISP_TBPR_13__FULL       0x1F0C0134,0xffffffff
+#define SRM_ISP_TBPR_13__HCB_13              0x1F0C0134,0x0FFF0000
+#define SRM_ISP_TBPR_13__VCB_13              0x1F0C0134,0x00000FFF
+
+#define SRM_ISP_TBPR_14__ADDR                  0x1F0C0138
+#define SRM_ISP_TBPR_14__EMPTY      0x1F0C0138,0x00000000
+#define SRM_ISP_TBPR_14__FULL       0x1F0C0138,0xffffffff
+#define SRM_ISP_TBPR_14__HCB_14              0x1F0C0138,0x0FFF0000
+#define SRM_ISP_TBPR_14__VCB_14              0x1F0C0138,0x00000FFF
+
+#define SRM_ISP_TBPR_15__ADDR                  0x1F0C013C
+#define SRM_ISP_TBPR_15__EMPTY      0x1F0C013C,0x00000000
+#define SRM_ISP_TBPR_15__FULL       0x1F0C013C,0xffffffff
+#define SRM_ISP_TBPR_15__HCB_15              0x1F0C013C,0x0FFF0000
+#define SRM_ISP_TBPR_15__VCB_15              0x1F0C013C,0x00000FFF
+
+#define SRM_ISP_TBPR_16__ADDR                  0x1F0C0140
+#define SRM_ISP_TBPR_16__EMPTY      0x1F0C0140,0x00000000
+#define SRM_ISP_TBPR_16__FULL       0x1F0C0140,0xffffffff
+#define SRM_ISP_TBPR_16__HCB_16              0x1F0C0140,0x0FFF0000
+#define SRM_ISP_TBPR_16__VCB_16              0x1F0C0140,0x00000FFF
+
+#define SRM_ISP_TBPR_17__ADDR                  0x1F0C0144
+#define SRM_ISP_TBPR_17__EMPTY      0x1F0C0144,0x00000000
+#define SRM_ISP_TBPR_17__FULL       0x1F0C0144,0xffffffff
+#define SRM_ISP_TBPR_17__HCB_17              0x1F0C0144,0x0FFF0000
+#define SRM_ISP_TBPR_17__VCB_17              0x1F0C0144,0x00000FFF
+
+#define SRM_ISP_TBPR_18__ADDR                  0x1F0C0148
+#define SRM_ISP_TBPR_18__EMPTY      0x1F0C0148,0x00000000
+#define SRM_ISP_TBPR_18__FULL       0x1F0C0148,0xffffffff
+#define SRM_ISP_TBPR_18__HCB_18              0x1F0C0148,0x0FFF0000
+#define SRM_ISP_TBPR_18__VCB_18              0x1F0C0148,0x00000FFF
+
+#define SRM_ISP_TBPR_19__ADDR                  0x1F0C014C
+#define SRM_ISP_TBPR_19__EMPTY      0x1F0C014C,0x00000000
+#define SRM_ISP_TBPR_19__FULL       0x1F0C014C,0xffffffff
+#define SRM_ISP_TBPR_19__HCB_19              0x1F0C014C,0x0FFF0000
+#define SRM_ISP_TBPR_19__VCB_19              0x1F0C014C,0x00000FFF
+
+#define SRM_ISP_TBPR_20__ADDR                  0x1F0C0150
+#define SRM_ISP_TBPR_20__EMPTY      0x1F0C0150,0x00000000
+#define SRM_ISP_TBPR_20__FULL       0x1F0C0150,0xffffffff
+#define SRM_ISP_TBPR_20__HCB_20              0x1F0C0150,0x0FFF0000
+#define SRM_ISP_TBPR_20__VCB_20              0x1F0C0150,0x00000FFF
+
+#define SRM_ISP_TBPR_21__ADDR                  0x1F0C0154
+#define SRM_ISP_TBPR_21__EMPTY      0x1F0C0154,0x00000000
+#define SRM_ISP_TBPR_21__FULL       0x1F0C0154,0xffffffff
+#define SRM_ISP_TBPR_21__HCB_21              0x1F0C0154,0x0FFF0000
+#define SRM_ISP_TBPR_21__VCB_21              0x1F0C0154,0x00000FFF
+
+#define SRM_ISP_TBPR_22__ADDR                  0x1F0C0158
+#define SRM_ISP_TBPR_22__EMPTY      0x1F0C0158,0x00000000
+#define SRM_ISP_TBPR_22__FULL       0x1F0C0158,0xffffffff
+#define SRM_ISP_TBPR_22__HCB_22              0x1F0C0158,0x0FFF0000
+#define SRM_ISP_TBPR_22__VCB_22              0x1F0C0158,0x00000FFF
+
+#define SRM_ISP_TBPR_23__ADDR                  0x1F0C015C
+#define SRM_ISP_TBPR_23__EMPTY      0x1F0C015C,0x00000000
+#define SRM_ISP_TBPR_23__FULL       0x1F0C015C,0xffffffff
+#define SRM_ISP_TBPR_23__HCB_23              0x1F0C015C,0x0FFF0000
+#define SRM_ISP_TBPR_23__VCB_23              0x1F0C015C,0x00000FFF
+
+#define SRM_ISP_TBPR_24__ADDR                  0x1F0C0160
+#define SRM_ISP_TBPR_24__EMPTY      0x1F0C0160,0x00000000
+#define SRM_ISP_TBPR_24__FULL       0x1F0C0160,0xffffffff
+#define SRM_ISP_TBPR_24__HCB_24              0x1F0C0160,0x0FFF0000
+#define SRM_ISP_TBPR_24__VCB_24              0x1F0C0160,0x00000FFF
+
+#define SRM_ISP_TBPR_25__ADDR                  0x1F0C0164
+#define SRM_ISP_TBPR_25__EMPTY      0x1F0C0164,0x00000000
+#define SRM_ISP_TBPR_25__FULL       0x1F0C0164,0xffffffff
+#define SRM_ISP_TBPR_25__HCB_25              0x1F0C0164,0x0FFF0000
+#define SRM_ISP_TBPR_25__VCB_25              0x1F0C0164,0x00000FFF
+
+#define SRM_ISP_TBPR_26__ADDR                  0x1F0C0168
+#define SRM_ISP_TBPR_26__EMPTY      0x1F0C0168,0x00000000
+#define SRM_ISP_TBPR_26__FULL       0x1F0C0168,0xffffffff
+#define SRM_ISP_TBPR_26__HCB_26              0x1F0C0168,0x0FFF0000
+#define SRM_ISP_TBPR_26__VCB_26              0x1F0C0168,0x00000FFF
+
+#define SRM_ISP_TBPR_27__ADDR                  0x1F0C016C
+#define SRM_ISP_TBPR_27__EMPTY      0x1F0C016C,0x00000000
+#define SRM_ISP_TBPR_27__FULL       0x1F0C016C,0xffffffff
+#define SRM_ISP_TBPR_27__HCB_27              0x1F0C016C,0x0FFF0000
+#define SRM_ISP_TBPR_27__VCB_27              0x1F0C016C,0x00000FFF
+
+#define SRM_ISP_TBPR_28__ADDR                  0x1F0C0170
+#define SRM_ISP_TBPR_28__EMPTY      0x1F0C0170,0x00000000
+#define SRM_ISP_TBPR_28__FULL       0x1F0C0170,0xffffffff
+#define SRM_ISP_TBPR_28__HCB_28              0x1F0C0170,0x0FFF0000
+#define SRM_ISP_TBPR_28__VCB_28              0x1F0C0170,0x00000FFF
+
+#define SRM_ISP_TBPR_29__ADDR                  0x1F0C0174
+#define SRM_ISP_TBPR_29__EMPTY      0x1F0C0174,0x00000000
+#define SRM_ISP_TBPR_29__FULL       0x1F0C0174,0xffffffff
+#define SRM_ISP_TBPR_29__HCB_29              0x1F0C0174,0x0FFF0000
+#define SRM_ISP_TBPR_29__VCB_29              0x1F0C0174,0x00000FFF
+
+#define SRM_ISP_TBPR_30__ADDR                  0x1F0C0178
+#define SRM_ISP_TBPR_30__EMPTY      0x1F0C0178,0x00000000
+#define SRM_ISP_TBPR_30__FULL       0x1F0C0178,0xffffffff
+#define SRM_ISP_TBPR_30__HCB_30              0x1F0C0178,0x0FFF0000
+#define SRM_ISP_TBPR_30__VCB_30              0x1F0C0178,0x00000FFF
+
+#define SRM_ISP_TBPR_31__ADDR                  0x1F0C017C
+#define SRM_ISP_TBPR_31__EMPTY      0x1F0C017C,0x00000000
+#define SRM_ISP_TBPR_31__FULL       0x1F0C017C,0xffffffff
+#define SRM_ISP_TBPR_31__HCB_31              0x1F0C017C,0x0FFF0000
+#define SRM_ISP_TBPR_31__VCB_31              0x1F0C017C,0x00000FFF
+
+#define SRM_ISP_TBPR_32__ADDR                  0x1F0C0180
+#define SRM_ISP_TBPR_32__EMPTY      0x1F0C0180,0x00000000
+#define SRM_ISP_TBPR_32__FULL       0x1F0C0180,0xffffffff
+#define SRM_ISP_TBPR_32__HCB_32              0x1F0C0180,0x0FFF0000
+#define SRM_ISP_TBPR_32__VCB_32              0x1F0C0180,0x00000FFF
+
+#define SRM_ISP_TBPR_33__ADDR                  0x1F0C0184
+#define SRM_ISP_TBPR_33__EMPTY      0x1F0C0184,0x00000000
+#define SRM_ISP_TBPR_33__FULL       0x1F0C0184,0xffffffff
+#define SRM_ISP_TBPR_33__HCB_33              0x1F0C0184,0x0FFF0000
+#define SRM_ISP_TBPR_33__VCB_33              0x1F0C0184,0x00000FFF
+
+#define SRM_ISP_TBPR_34__ADDR                  0x1F0C0188
+#define SRM_ISP_TBPR_34__EMPTY      0x1F0C0188,0x00000000
+#define SRM_ISP_TBPR_34__FULL       0x1F0C0188,0xffffffff
+#define SRM_ISP_TBPR_34__HCB_34              0x1F0C0188,0x0FFF0000
+#define SRM_ISP_TBPR_34__VCB_34              0x1F0C0188,0x00000FFF
+
+#define SRM_ISP_TBPR_35__ADDR                  0x1F0C018C
+#define SRM_ISP_TBPR_35__EMPTY      0x1F0C018C,0x00000000
+#define SRM_ISP_TBPR_35__FULL       0x1F0C018C,0xffffffff
+#define SRM_ISP_TBPR_35__HCB_35              0x1F0C018C,0x0FFF0000
+#define SRM_ISP_TBPR_35__VCB_35              0x1F0C018C,0x00000FFF
+
+#define SRM_ISP_TBPR_36__ADDR                  0x1F0C0190
+#define SRM_ISP_TBPR_36__EMPTY      0x1F0C0190,0x00000000
+#define SRM_ISP_TBPR_36__FULL       0x1F0C0190,0xffffffff
+#define SRM_ISP_TBPR_36__HCB_36              0x1F0C0190,0x0FFF0000
+#define SRM_ISP_TBPR_36__VCB_36              0x1F0C0190,0x00000FFF
+
+#define SRM_ISP_TBPR_37__ADDR                  0x1F0C0194
+#define SRM_ISP_TBPR_37__EMPTY      0x1F0C0194,0x00000000
+#define SRM_ISP_TBPR_37__FULL       0x1F0C0194,0xffffffff
+#define SRM_ISP_TBPR_37__HCB_37              0x1F0C0194,0x0FFF0000
+#define SRM_ISP_TBPR_37__VCB_37              0x1F0C0194,0x00000FFF
+
+#define SRM_ISP_TBPR_38__ADDR                  0x1F0C0198
+#define SRM_ISP_TBPR_38__EMPTY      0x1F0C0198,0x00000000
+#define SRM_ISP_TBPR_38__FULL       0x1F0C0198,0xffffffff
+#define SRM_ISP_TBPR_38__HCB_38              0x1F0C0198,0x0FFF0000
+#define SRM_ISP_TBPR_38__VCB_38              0x1F0C0198,0x00000FFF
+
+#define SRM_ISP_TBPR_39__ADDR                  0x1F0C019C
+#define SRM_ISP_TBPR_39__EMPTY      0x1F0C019C,0x00000000
+#define SRM_ISP_TBPR_39__FULL       0x1F0C019C,0xffffffff
+#define SRM_ISP_TBPR_39__HCB_39              0x1F0C019C,0x0FFF0000
+#define SRM_ISP_TBPR_39__VCB_39              0x1F0C019C,0x00000FFF
+
+#define SRM_ISP_TBPR_40__ADDR                  0x1F0C01A0
+#define SRM_ISP_TBPR_40__EMPTY      0x1F0C01A0,0x00000000
+#define SRM_ISP_TBPR_40__FULL       0x1F0C01A0,0xffffffff
+#define SRM_ISP_TBPR_40__HCB_40              0x1F0C01A0,0x0FFF0000
+#define SRM_ISP_TBPR_40__VCB_40              0x1F0C01A0,0x00000FFF
+
+#define SRM_ISP_TBPR_41__ADDR                  0x1F0C01A4
+#define SRM_ISP_TBPR_41__EMPTY      0x1F0C01A4,0x00000000
+#define SRM_ISP_TBPR_41__FULL       0x1F0C01A4,0xffffffff
+#define SRM_ISP_TBPR_41__HCB_41              0x1F0C01A4,0x0FFF0000
+#define SRM_ISP_TBPR_41__VCB_41              0x1F0C01A4,0x00000FFF
+
+#define SRM_ISP_TBPR_42__ADDR                  0x1F0C01A8
+#define SRM_ISP_TBPR_42__EMPTY      0x1F0C01A8,0x00000000
+#define SRM_ISP_TBPR_42__FULL       0x1F0C01A8,0xffffffff
+#define SRM_ISP_TBPR_42__HCB_42              0x1F0C01A8,0x0FFF0000
+#define SRM_ISP_TBPR_42__VCB_42              0x1F0C01A8,0x00000FFF
+
+#define SRM_ISP_TBPR_43__ADDR                  0x1F0C01AC
+#define SRM_ISP_TBPR_43__EMPTY      0x1F0C01AC,0x00000000
+#define SRM_ISP_TBPR_43__FULL       0x1F0C01AC,0xffffffff
+#define SRM_ISP_TBPR_43__HCB_43              0x1F0C01AC,0x0FFF0000
+#define SRM_ISP_TBPR_43__VCB_43              0x1F0C01AC,0x00000FFF
+
+#define SRM_ISP_TBPR_44__ADDR                  0x1F0C01B0
+#define SRM_ISP_TBPR_44__EMPTY      0x1F0C01B0,0x00000000
+#define SRM_ISP_TBPR_44__FULL       0x1F0C01B0,0xffffffff
+#define SRM_ISP_TBPR_44__HCB_44              0x1F0C01B0,0x0FFF0000
+#define SRM_ISP_TBPR_44__VCB_44              0x1F0C01B0,0x00000FFF
+
+#define SRM_ISP_TBPR_45__ADDR                  0x1F0C01B4
+#define SRM_ISP_TBPR_45__EMPTY      0x1F0C01B4,0x00000000
+#define SRM_ISP_TBPR_45__FULL       0x1F0C01B4,0xffffffff
+#define SRM_ISP_TBPR_45__HCB_45              0x1F0C01B4,0x0FFF0000
+#define SRM_ISP_TBPR_45__VCB_45              0x1F0C01B4,0x00000FFF
+
+#define SRM_ISP_TBPR_46__ADDR                  0x1F0C01B8
+#define SRM_ISP_TBPR_46__EMPTY      0x1F0C01B8,0x00000000
+#define SRM_ISP_TBPR_46__FULL       0x1F0C01B8,0xffffffff
+#define SRM_ISP_TBPR_46__HCB_46              0x1F0C01B8,0x0FFF0000
+#define SRM_ISP_TBPR_46__VCB_46              0x1F0C01B8,0x00000FFF
+
+#define SRM_ISP_TBPR_47__ADDR                  0x1F0C01BC
+#define SRM_ISP_TBPR_47__EMPTY      0x1F0C01BC,0x00000000
+#define SRM_ISP_TBPR_47__FULL       0x1F0C01BC,0xffffffff
+#define SRM_ISP_TBPR_47__HCB_47              0x1F0C01BC,0x0FFF0000
+#define SRM_ISP_TBPR_47__VCB_47              0x1F0C01BC,0x00000FFF
+
+#define SRM_ISP_TBPR_48__ADDR                  0x1F0C01C0
+#define SRM_ISP_TBPR_48__EMPTY      0x1F0C01C0,0x00000000
+#define SRM_ISP_TBPR_48__FULL       0x1F0C01C0,0xffffffff
+#define SRM_ISP_TBPR_48__HCB_48              0x1F0C01C0,0x0FFF0000
+#define SRM_ISP_TBPR_48__VCB_48              0x1F0C01C0,0x00000FFF
+
+#define SRM_ISP_TBPR_49__ADDR                  0x1F0C01C4
+#define SRM_ISP_TBPR_49__EMPTY      0x1F0C01C4,0x00000000
+#define SRM_ISP_TBPR_49__FULL       0x1F0C01C4,0xffffffff
+#define SRM_ISP_TBPR_49__HCB_49              0x1F0C01C4,0x0FFF0000
+#define SRM_ISP_TBPR_49__VCB_49              0x1F0C01C4,0x00000FFF
+
+#define SRM_ISP_TBPR_50__ADDR                  0x1F0C01C8
+#define SRM_ISP_TBPR_50__EMPTY      0x1F0C01C8,0x00000000
+#define SRM_ISP_TBPR_50__FULL       0x1F0C01C8,0xffffffff
+#define SRM_ISP_TBPR_50__HCB_50              0x1F0C01C8,0x0FFF0000
+#define SRM_ISP_TBPR_50__VCB_50              0x1F0C01C8,0x00000FFF
+
+#define SRM_ISP_TBPR_51__ADDR                  0x1F0C01CC
+#define SRM_ISP_TBPR_51__EMPTY      0x1F0C01CC,0x00000000
+#define SRM_ISP_TBPR_51__FULL       0x1F0C01CC,0xffffffff
+#define SRM_ISP_TBPR_51__HCB_51              0x1F0C01CC,0x0FFF0000
+#define SRM_ISP_TBPR_51__VCB_51              0x1F0C01CC,0x00000FFF
+
+#define SRM_ISP_TBPR_52__ADDR                  0x1F0C01D0
+#define SRM_ISP_TBPR_52__EMPTY      0x1F0C01D0,0x00000000
+#define SRM_ISP_TBPR_52__FULL       0x1F0C01D0,0xffffffff
+#define SRM_ISP_TBPR_52__HCB_52              0x1F0C01D0,0x0FFF0000
+#define SRM_ISP_TBPR_52__VCB_52              0x1F0C01D0,0x00000FFF
+
+#define SRM_ISP_TBPR_53__ADDR                  0x1F0C01D4
+#define SRM_ISP_TBPR_53__EMPTY      0x1F0C01D4,0x00000000
+#define SRM_ISP_TBPR_53__FULL       0x1F0C01D4,0xffffffff
+#define SRM_ISP_TBPR_53__HCB_53              0x1F0C01D4,0x0FFF0000
+#define SRM_ISP_TBPR_53__VCB_53              0x1F0C01D4,0x00000FFF
+
+#define SRM_ISP_TBPR_54__ADDR                  0x1F0C01D8
+#define SRM_ISP_TBPR_54__EMPTY      0x1F0C01D8,0x00000000
+#define SRM_ISP_TBPR_54__FULL       0x1F0C01D8,0xffffffff
+#define SRM_ISP_TBPR_54__HCB_54              0x1F0C01D8,0x0FFF0000
+#define SRM_ISP_TBPR_54__VCB_54              0x1F0C01D8,0x00000FFF
+
+#define SRM_ISP_TBPR_55__ADDR                  0x1F0C01DC
+#define SRM_ISP_TBPR_55__EMPTY      0x1F0C01DC,0x00000000
+#define SRM_ISP_TBPR_55__FULL       0x1F0C01DC,0xffffffff
+#define SRM_ISP_TBPR_55__HCB_55              0x1F0C01DC,0x0FFF0000
+#define SRM_ISP_TBPR_55__VCB_55              0x1F0C01DC,0x00000FFF
+
+#define SRM_ISP_TBPR_56__ADDR                  0x1F0C01E0
+#define SRM_ISP_TBPR_56__EMPTY      0x1F0C01E0,0x00000000
+#define SRM_ISP_TBPR_56__FULL       0x1F0C01E0,0xffffffff
+#define SRM_ISP_TBPR_56__HCB_56              0x1F0C01E0,0x0FFF0000
+#define SRM_ISP_TBPR_56__VCB_56              0x1F0C01E0,0x00000FFF
+
+#define SRM_ISP_TBPR_57__ADDR                  0x1F0C01E4
+#define SRM_ISP_TBPR_57__EMPTY      0x1F0C01E4,0x00000000
+#define SRM_ISP_TBPR_57__FULL       0x1F0C01E4,0xffffffff
+#define SRM_ISP_TBPR_57__HCB_57              0x1F0C01E4,0x0FFF0000
+#define SRM_ISP_TBPR_57__VCB_57              0x1F0C01E4,0x00000FFF
+
+#define SRM_ISP_TBPR_58__ADDR                  0x1F0C01E8
+#define SRM_ISP_TBPR_58__EMPTY      0x1F0C01E8,0x00000000
+#define SRM_ISP_TBPR_58__FULL       0x1F0C01E8,0xffffffff
+#define SRM_ISP_TBPR_58__HCB_58              0x1F0C01E8,0x0FFF0000
+#define SRM_ISP_TBPR_58__VCB_58              0x1F0C01E8,0x00000FFF
+
+#define SRM_ISP_TBPR_59__ADDR                  0x1F0C01EC
+#define SRM_ISP_TBPR_59__EMPTY      0x1F0C01EC,0x00000000
+#define SRM_ISP_TBPR_59__FULL       0x1F0C01EC,0xffffffff
+#define SRM_ISP_TBPR_59__HCB_59              0x1F0C01EC,0x0FFF0000
+#define SRM_ISP_TBPR_59__VCB_59              0x1F0C01EC,0x00000FFF
+
+#define SRM_ISP_TBPR_60__ADDR                  0x1F0C01F0
+#define SRM_ISP_TBPR_60__EMPTY      0x1F0C01F0,0x00000000
+#define SRM_ISP_TBPR_60__FULL       0x1F0C01F0,0xffffffff
+#define SRM_ISP_TBPR_60__HCB_60              0x1F0C01F0,0x0FFF0000
+#define SRM_ISP_TBPR_60__VCB_60              0x1F0C01F0,0x00000FFF
+
+#define SRM_ISP_TBPR_61__ADDR                  0x1F0C01F4
+#define SRM_ISP_TBPR_61__EMPTY      0x1F0C01F4,0x00000000
+#define SRM_ISP_TBPR_61__FULL       0x1F0C01F4,0xffffffff
+#define SRM_ISP_TBPR_61__HCB_61              0x1F0C01F4,0x0FFF0000
+#define SRM_ISP_TBPR_61__VCB_61              0x1F0C01F4,0x00000FFF
+
+#define SRM_ISP_TBPR_62__ADDR                  0x1F0C01F8
+#define SRM_ISP_TBPR_62__EMPTY      0x1F0C01F8,0x00000000
+#define SRM_ISP_TBPR_62__FULL       0x1F0C01F8,0xffffffff
+#define SRM_ISP_TBPR_62__HCB_62              0x1F0C01F8,0x0FFF0000
+#define SRM_ISP_TBPR_62__VCB_62              0x1F0C01F8,0x00000FFF
+
+#define SRM_ISP_TBPR_63__ADDR                  0x1F0C01FC
+#define SRM_ISP_TBPR_63__EMPTY      0x1F0C01FC,0x00000000
+#define SRM_ISP_TBPR_63__FULL       0x1F0C01FC,0xffffffff
+#define SRM_ISP_TBPR_63__HCB_63              0x1F0C01FC,0x0FFF0000
+#define SRM_ISP_TBPR_63__VCB_63              0x1F0C01FC,0x00000FFF
+
+#define LPM_MEM_DI0_GENERAL__ADDR                  0x1F0402C4
+#define LPM_MEM_DI0_GENERAL__EMPTY      0x1F0402C4,0x00000000
+#define LPM_MEM_DI0_GENERAL__FULL      0x1F0402C4,0xffffffff
+#define LPM_MEM_DI0_GENERAL__DI0_DISP_Y_SEL      0x1F0402C4,0x70000000
+#define LPM_MEM_DI0_GENERAL__DI0_CLOCK_STOP_MODE       0x1F0402C4,0x0F000000
+#define LPM_MEM_DI0_GENERAL__DI0_DISP_CLOCK_INIT       0x1F0402C4,0x00800000
+#define LPM_MEM_DI0_GENERAL__DI0_MASK_SEL      0x1F0402C4,0x00400000
+#define LPM_MEM_DI0_GENERAL__DI0_VSYNC_EXT      0x1F0402C4,0x00200000
+#define LPM_MEM_DI0_GENERAL__DI0_CLK_EXT       0x1F0402C4,0x00100000
+#define LPM_MEM_DI0_GENERAL__DI0_WATCHDOG_MODE      0x1F0402C4,0x000C0000
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_DISP_CLK      0x1F0402C4,0x00020000
+#define LPM_MEM_DI0_GENERAL__DI0_SYNC_COUNT_SEL              0x1F0402C4,0x0000F000
+#define LPM_MEM_DI0_GENERAL__DI0_ERR_TREATMENT      0x1F0402C4,0x00000800
+#define LPM_MEM_DI0_GENERAL__DI0_ERM_VSYNC_SEL    0x1F0402C4,0x00000400
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS1      0x1F0402C4,0x00000200
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_CS0      0x1F0402C4,0x00000100
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_8      0x1F0402C4,0x00000080
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_7      0x1F0402C4,0x00000040
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_6      0x1F0402C4,0x00000020
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_5      0x1F0402C4,0x00000010
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_4      0x1F0402C4,0x00000008
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_3      0x1F0402C4,0x00000004
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_2      0x1F0402C4,0x00000002
+#define LPM_MEM_DI0_GENERAL__DI0_POLARITY_1      0x1F0402C4,0x00000001
+
+#define LPM_MEM_DI0_BS_CLKGEN0__ADDR                  0x1F0402C8
+#define LPM_MEM_DI0_BS_CLKGEN0__EMPTY      0x1F0402C8,0x00000000
+#define LPM_MEM_DI0_BS_CLKGEN0__FULL      0x1F0402C8,0xffffffff
+#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET      0x1F0402C8,0x01FF0000
+#define LPM_MEM_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD      0x1F0402C8,0x00000FFF
+
+#define LPM_MEM_DI0_BS_CLKGEN1__ADDR                  0x1F0402CC
+#define LPM_MEM_DI0_BS_CLKGEN1__EMPTY      0x1F0402CC,0x00000000
+#define LPM_MEM_DI0_BS_CLKGEN1__FULL      0x1F0402CC,0xffffffff
+#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN      0x1F0402CC,0x01FF0000
+#define LPM_MEM_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP              0x1F0402CC,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN0_1__ADDR                  0x1F0402D0
+#define LPM_MEM_DI0_SW_GEN0_1__EMPTY      0x1F0402D0,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_1__FULL      0x1F0402D0,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_VALUE_M1_1      0x1F0402D0,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_RUN_RESOLUTION_1      0x1F0402D0,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_VALUE_1      0x1F0402D0,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_1__DI0_OFFSET_RESOLUTION_1      0x1F0402D0,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_2__ADDR                  0x1F0402D4
+#define LPM_MEM_DI0_SW_GEN0_2__EMPTY      0x1F0402D4,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_2__FULL      0x1F0402D4,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_VALUE_M1_2      0x1F0402D4,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_RUN_RESOLUTION_2      0x1F0402D4,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_VALUE_2      0x1F0402D4,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_2__DI0_OFFSET_RESOLUTION_2      0x1F0402D4,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_3__ADDR                  0x1F0402D8
+#define LPM_MEM_DI0_SW_GEN0_3__EMPTY      0x1F0402D8,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_3__FULL      0x1F0402D8,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_VALUE_M1_3      0x1F0402D8,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_RUN_RESOLUTION_3      0x1F0402D8,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_VALUE_3      0x1F0402D8,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_3__DI0_OFFSET_RESOLUTION_3      0x1F0402D8,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_4__ADDR                  0x1F0402DC
+#define LPM_MEM_DI0_SW_GEN0_4__EMPTY      0x1F0402DC,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_4__FULL      0x1F0402DC,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_VALUE_M1_4      0x1F0402DC,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_RUN_RESOLUTION_4      0x1F0402DC,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_VALUE_4      0x1F0402DC,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_4__DI0_OFFSET_RESOLUTION_4      0x1F0402DC,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_5__ADDR                  0x1F0402E0
+#define LPM_MEM_DI0_SW_GEN0_5__EMPTY      0x1F0402E0,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_5__FULL      0x1F0402E0,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_VALUE_M1_5      0x1F0402E0,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_RUN_RESOLUTION_5      0x1F0402E0,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_VALUE_5      0x1F0402E0,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_5__DI0_OFFSET_RESOLUTION_5      0x1F0402E0,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_6__ADDR                  0x1F0402E4
+#define LPM_MEM_DI0_SW_GEN0_6__EMPTY      0x1F0402E4,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_6__FULL      0x1F0402E4,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_VALUE_M1_6      0x1F0402E4,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_RUN_RESOLUTION_6      0x1F0402E4,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_VALUE_6      0x1F0402E4,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_6__DI0_OFFSET_RESOLUTION_6      0x1F0402E4,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_7__ADDR                  0x1F0402E8
+#define LPM_MEM_DI0_SW_GEN0_7__EMPTY      0x1F0402E8,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_7__FULL      0x1F0402E8,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_VALUE_M1_7      0x1F0402E8,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_RUN_RESOLUTION_7      0x1F0402E8,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_VALUE_7      0x1F0402E8,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_7__DI0_OFFSET_RESOLUTION_7      0x1F0402E8,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_8__ADDR                  0x1F0402EC
+#define LPM_MEM_DI0_SW_GEN0_8__EMPTY      0x1F0402EC,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_8__FULL      0x1F0402EC,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_VALUE_M1_8      0x1F0402EC,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_RUN_RESOLUTION_8      0x1F0402EC,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_VALUE_8      0x1F0402EC,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_8__DI0_OFFSET_RESOLUTION_8      0x1F0402EC,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN0_9__ADDR                  0x1F0402F0
+#define LPM_MEM_DI0_SW_GEN0_9__EMPTY      0x1F0402F0,0x00000000
+#define LPM_MEM_DI0_SW_GEN0_9__FULL      0x1F0402F0,0xffffffff
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_VALUE_M1_9      0x1F0402F0,0x7FF80000
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_RUN_RESOLUTION_9      0x1F0402F0,0x00070000
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_VALUE_9      0x1F0402F0,0x00007FF8
+#define LPM_MEM_DI0_SW_GEN0_9__DI0_OFFSET_RESOLUTION_9      0x1F0402F0,0x00000007
+
+#define LPM_MEM_DI0_SW_GEN1_1__ADDR                  0x1F0402F4
+#define LPM_MEM_DI0_SW_GEN1_1__EMPTY      0x1F0402F4,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_1__FULL      0x1F0402F4,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_GEN_EN_1       0x1F0402F4,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_AUTO_RELOAD_1      0x1F0402F4,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_CLR_SEL_1       0x1F0402F4,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_DOWN_1      0x1F0402F4,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_TRIGGER_SEL_1      0x1F0402F4,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_POLARITY_CLR_SEL_1      0x1F0402F4,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_1__DI0_CNT_UP_1      0x1F0402F4,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_2__ADDR                  0x1F0402F8
+#define LPM_MEM_DI0_SW_GEN1_2__EMPTY      0x1F0402F8,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_2__FULL      0x1F0402F8,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_GEN_EN_2       0x1F0402F8,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_AUTO_RELOAD_2      0x1F0402F8,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_CLR_SEL_2       0x1F0402F8,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_DOWN_2      0x1F0402F8,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_TRIGGER_SEL_2      0x1F0402F8,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_POLARITY_CLR_SEL_2      0x1F0402F8,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_2__DI0_CNT_UP_2      0x1F0402F8,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_3__ADDR                  0x1F0402FC
+#define LPM_MEM_DI0_SW_GEN1_3__EMPTY      0x1F0402FC,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_3__FULL      0x1F0402FC,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_GEN_EN_3       0x1F0402FC,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_AUTO_RELOAD_3      0x1F0402FC,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_CLR_SEL_3       0x1F0402FC,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_DOWN_3      0x1F0402FC,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_TRIGGER_SEL_3      0x1F0402FC,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_POLARITY_CLR_SEL_3      0x1F0402FC,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_3__DI0_CNT_UP_3      0x1F0402FC,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_4__ADDR                  0x1F040300
+#define LPM_MEM_DI0_SW_GEN1_4__EMPTY      0x1F040300,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_4__FULL      0x1F040300,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_GEN_EN_4       0x1F040300,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_AUTO_RELOAD_4      0x1F040300,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_CLR_SEL_4       0x1F040300,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_DOWN_4      0x1F040300,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_TRIGGER_SEL_4      0x1F040300,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_POLARITY_CLR_SEL_4      0x1F040300,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_4__DI0_CNT_UP_4      0x1F040300,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_5__ADDR                  0x1F040304
+#define LPM_MEM_DI0_SW_GEN1_5__EMPTY      0x1F040304,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_5__FULL      0x1F040304,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_GEN_EN_5       0x1F040304,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_AUTO_RELOAD_5      0x1F040304,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_CLR_SEL_5       0x1F040304,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_DOWN_5      0x1F040304,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_TRIGGER_SEL_5      0x1F040304,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_POLARITY_CLR_SEL_5      0x1F040304,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_5__DI0_CNT_UP_5      0x1F040304,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_6__ADDR                  0x1F040308
+#define LPM_MEM_DI0_SW_GEN1_6__EMPTY      0x1F040308,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_6__FULL      0x1F040308,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_GEN_EN_6       0x1F040308,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_AUTO_RELOAD_6      0x1F040308,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_CLR_SEL_6       0x1F040308,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_DOWN_6      0x1F040308,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_TRIGGER_SEL_6      0x1F040308,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_POLARITY_CLR_SEL_6      0x1F040308,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_6__DI0_CNT_UP_6      0x1F040308,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_7__ADDR                  0x1F04030C
+#define LPM_MEM_DI0_SW_GEN1_7__EMPTY      0x1F04030C,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_7__FULL      0x1F04030C,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_GEN_EN_7       0x1F04030C,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_AUTO_RELOAD_7      0x1F04030C,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_CLR_SEL_7       0x1F04030C,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_DOWN_7      0x1F04030C,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_TRIGGER_SEL_7      0x1F04030C,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_POLARITY_CLR_SEL_7      0x1F04030C,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_7__DI0_CNT_UP_7      0x1F04030C,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_8__ADDR                  0x1F040310
+#define LPM_MEM_DI0_SW_GEN1_8__EMPTY      0x1F040310,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_8__FULL      0x1F040310,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_GEN_EN_8       0x1F040310,0x60000000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_AUTO_RELOAD_8      0x1F040310,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_CLR_SEL_8       0x1F040310,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_DOWN_8      0x1F040310,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_TRIGGER_SEL_8      0x1F040310,0x00007000
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_POLARITY_CLR_SEL_8      0x1F040310,0x00000E00
+#define LPM_MEM_DI0_SW_GEN1_8__DI0_CNT_UP_8      0x1F040310,0x000001FF
+
+#define LPM_MEM_DI0_SW_GEN1_9__ADDR                  0x1F040314
+#define LPM_MEM_DI0_SW_GEN1_9__EMPTY      0x1F040314,0x00000000
+#define LPM_MEM_DI0_SW_GEN1_9__FULL      0x1F040314,0xffffffff
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_GENTIME_SEL_9       0x1F040314,0xE0000000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_AUTO_RELOAD_9      0x1F040314,0x10000000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_CLR_SEL_9       0x1F040314,0x0E000000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_DOWN_9      0x1F040314,0x01FF0000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_TAG_SEL_9      0x1F040314,0x00008000
+#define LPM_MEM_DI0_SW_GEN1_9__DI0_CNT_UP_9      0x1F040314,0x000001FF
+
+#define LPM_MEM_DI0_SYNC_AS_GEN__ADDR                  0x1F040318
+#define LPM_MEM_DI0_SYNC_AS_GEN__EMPTY      0x1F040318,0x00000000
+#define LPM_MEM_DI0_SYNC_AS_GEN__FULL      0x1F040318,0xffffffff
+#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START_EN      0x1F040318,0x10000000
+#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL      0x1F040318,0x0000E000
+#define LPM_MEM_DI0_SYNC_AS_GEN__DI0_SYNC_START              0x1F040318,0x00000FFF
+
+#define LPM_MEM_DI0_DW_GEN_0__ADDR                  0x1F04031C
+#define LPM_MEM_DI0_DW_GEN_0__EMPTY      0x1F04031C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_0__FULL      0x1F04031C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_0__DI0_ACCESS_SIZE_0              0x1F04031C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_COMPONNENT_SIZE_0      0x1F04031C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0              0x1F04031C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_6_0       0x1F04031C,0x00003000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_5_0       0x1F04031C,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_4_0       0x1F04031C,0x00000300
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_3_0       0x1F04031C,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_2_0       0x1F04031C,0x00000030
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_1_0       0x1F04031C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_0__DI0_PT_0_0       0x1F04031C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_0__ADDR                  0x1F04031C
+#define LPM_MEM_DI0_DW_GEN_0__EMPTY      0x1F04031C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_0__FULL      0x1F04031C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_PERIOD_0      0x1F04031C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_START_PERIOD_0       0x1F04031C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_CST_0              0x1F04031C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_VALID_BITS_0      0x1F04031C,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_RS_0      0x1F04031C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_0__DI0_SERIAL_CLK_0      0x1F04031C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_1__ADDR                  0x1F040320
+#define LPM_MEM_DI0_DW_GEN_1__EMPTY      0x1F040320,0x00000000
+#define LPM_MEM_DI0_DW_GEN_1__FULL      0x1F040320,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_1__DI0_ACCESS_SIZE_1              0x1F040320,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_COMPONNENT_SIZE_1      0x1F040320,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1              0x1F040320,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_6_1       0x1F040320,0x00003000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_5_1       0x1F040320,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_4_1       0x1F040320,0x00000300
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_3_1       0x1F040320,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_2_1       0x1F040320,0x00000030
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_1_1       0x1F040320,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_1__DI0_PT_0_1       0x1F040320,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_1__ADDR                  0x1F040320
+#define LPM_MEM_DI0_DW_GEN_1__EMPTY      0x1F040320,0x00000000
+#define LPM_MEM_DI0_DW_GEN_1__FULL      0x1F040320,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_PERIOD_1      0x1F040320,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_START_PERIOD_1       0x1F040320,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_CST_1              0x1F040320,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_VALID_BITS_1      0x1F040320,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_RS_1      0x1F040320,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_1__DI0_SERIAL_CLK_1      0x1F040320,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_2__ADDR                  0x1F040324
+#define LPM_MEM_DI0_DW_GEN_2__EMPTY      0x1F040324,0x00000000
+#define LPM_MEM_DI0_DW_GEN_2__FULL      0x1F040324,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_2__DI0_ACCESS_SIZE_2              0x1F040324,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_COMPONNENT_SIZE_2      0x1F040324,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2              0x1F040324,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_6_2       0x1F040324,0x00003000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_5_2       0x1F040324,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_4_2       0x1F040324,0x00000300
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_3_2       0x1F040324,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_2_2       0x1F040324,0x00000030
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_1_2       0x1F040324,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_2__DI0_PT_0_2       0x1F040324,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_2__ADDR                  0x1F040324
+#define LPM_MEM_DI0_DW_GEN_2__EMPTY      0x1F040324,0x00000000
+#define LPM_MEM_DI0_DW_GEN_2__FULL      0x1F040324,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_PERIOD_2      0x1F040324,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_START_PERIOD_2       0x1F040324,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_CST_2              0x1F040324,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_VALID_BITS_2      0x1F040324,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_RS_2      0x1F040324,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_2__DI0_SERIAL_CLK_2      0x1F040324,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_3__ADDR                  0x1F040328
+#define LPM_MEM_DI0_DW_GEN_3__EMPTY      0x1F040328,0x00000000
+#define LPM_MEM_DI0_DW_GEN_3__FULL      0x1F040328,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_3__DI0_ACCESS_SIZE_3              0x1F040328,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_COMPONNENT_SIZE_3      0x1F040328,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3              0x1F040328,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_6_3       0x1F040328,0x00003000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_5_3       0x1F040328,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_4_3       0x1F040328,0x00000300
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_3_3       0x1F040328,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_2_3       0x1F040328,0x00000030
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_1_3       0x1F040328,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_3__DI0_PT_0_3       0x1F040328,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_3__ADDR                  0x1F040328
+#define LPM_MEM_DI0_DW_GEN_3__EMPTY      0x1F040328,0x00000000
+#define LPM_MEM_DI0_DW_GEN_3__FULL      0x1F040328,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_PERIOD_3      0x1F040328,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_START_PERIOD_3       0x1F040328,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_CST_3              0x1F040328,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_VALID_BITS_3      0x1F040328,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_RS_3      0x1F040328,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_3__DI0_SERIAL_CLK_3      0x1F040328,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_4__ADDR                  0x1F04032C
+#define LPM_MEM_DI0_DW_GEN_4__EMPTY      0x1F04032C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_4__FULL      0x1F04032C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_4__DI0_ACCESS_SIZE_4              0x1F04032C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_COMPONNENT_SIZE_4      0x1F04032C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4              0x1F04032C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_6_4       0x1F04032C,0x00003000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_5_4       0x1F04032C,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_4_4       0x1F04032C,0x00000300
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_3_4       0x1F04032C,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_2_4       0x1F04032C,0x00000030
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_1_4       0x1F04032C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_4__DI0_PT_0_4       0x1F04032C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_4__ADDR                  0x1F04032C
+#define LPM_MEM_DI0_DW_GEN_4__EMPTY      0x1F04032C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_4__FULL      0x1F04032C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_PERIOD_4      0x1F04032C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_START_PERIOD_4       0x1F04032C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_CST_4              0x1F04032C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_VALID_BITS_4      0x1F04032C,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_RS_4      0x1F04032C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_4__DI0_SERIAL_CLK_4      0x1F04032C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_5__ADDR                  0x1F040330
+#define LPM_MEM_DI0_DW_GEN_5__EMPTY      0x1F040330,0x00000000
+#define LPM_MEM_DI0_DW_GEN_5__FULL      0x1F040330,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_5__DI0_ACCESS_SIZE_5              0x1F040330,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_COMPONNENT_SIZE_5      0x1F040330,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5              0x1F040330,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_6_5       0x1F040330,0x00003000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_5_5       0x1F040330,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_4_5       0x1F040330,0x00000300
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_3_5       0x1F040330,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_2_5       0x1F040330,0x00000030
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_1_5       0x1F040330,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_5__DI0_PT_0_5       0x1F040330,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_5__ADDR                  0x1F040330
+#define LPM_MEM_DI0_DW_GEN_5__EMPTY      0x1F040330,0x00000000
+#define LPM_MEM_DI0_DW_GEN_5__FULL      0x1F040330,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_PERIOD_5      0x1F040330,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_START_PERIOD_5       0x1F040330,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_CST_5              0x1F040330,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_VALID_BITS_5      0x1F040330,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_RS_5      0x1F040330,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_5__DI0_SERIAL_CLK_5      0x1F040330,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_6__ADDR                  0x1F040334
+#define LPM_MEM_DI0_DW_GEN_6__EMPTY      0x1F040334,0x00000000
+#define LPM_MEM_DI0_DW_GEN_6__FULL      0x1F040334,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_6__DI0_ACCESS_SIZE_6              0x1F040334,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_COMPONNENT_SIZE_6      0x1F040334,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6              0x1F040334,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_6_6       0x1F040334,0x00003000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_5_6       0x1F040334,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_4_6       0x1F040334,0x00000300
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_3_6       0x1F040334,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_2_6       0x1F040334,0x00000030
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_1_6       0x1F040334,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_6__DI0_PT_0_6       0x1F040334,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_6__ADDR                  0x1F040334
+#define LPM_MEM_DI0_DW_GEN_6__EMPTY      0x1F040334,0x00000000
+#define LPM_MEM_DI0_DW_GEN_6__FULL      0x1F040334,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6      0x1F040334,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_START_PERIOD_6       0x1F040334,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_CST_6              0x1F040334,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6      0x1F040334,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_RS_6      0x1F040334,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_6__DI0_SERIAL_CLK_6      0x1F040334,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_7__ADDR                  0x1F040338
+#define LPM_MEM_DI0_DW_GEN_7__EMPTY      0x1F040338,0x00000000
+#define LPM_MEM_DI0_DW_GEN_7__FULL      0x1F040338,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_7__DI0_ACCESS_SIZE_7              0x1F040338,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_COMPONNENT_SIZE_7      0x1F040338,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7              0x1F040338,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_6_7       0x1F040338,0x00003000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_5_7       0x1F040338,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_4_7       0x1F040338,0x00000300
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_3_7       0x1F040338,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_2_7       0x1F040338,0x00000030
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_1_7       0x1F040338,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_7__DI0_PT_0_7       0x1F040338,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_7__ADDR                  0x1F040338
+#define LPM_MEM_DI0_DW_GEN_7__EMPTY      0x1F040338,0x00000000
+#define LPM_MEM_DI0_DW_GEN_7__FULL      0x1F040338,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_PERIOD_7      0x1F040338,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_START_PERIOD_7       0x1F040338,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_CST_7              0x1F040338,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_VALID_BITS_7      0x1F040338,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_RS_7      0x1F040338,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_7__DI0_SERIAL_CLK_7      0x1F040338,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_8__ADDR                  0x1F04033C
+#define LPM_MEM_DI0_DW_GEN_8__EMPTY      0x1F04033C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_8__FULL      0x1F04033C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_8__DI0_ACCESS_SIZE_8              0x1F04033C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_COMPONNENT_SIZE_8      0x1F04033C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8              0x1F04033C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_6_8       0x1F04033C,0x00003000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_5_8       0x1F04033C,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_4_8       0x1F04033C,0x00000300
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_3_8       0x1F04033C,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_2_8       0x1F04033C,0x00000030
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_1_8       0x1F04033C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_8__DI0_PT_0_8       0x1F04033C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_8__ADDR                  0x1F04033C
+#define LPM_MEM_DI0_DW_GEN_8__EMPTY      0x1F04033C,0x00000000
+#define LPM_MEM_DI0_DW_GEN_8__FULL      0x1F04033C,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_PERIOD_8      0x1F04033C,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_START_PERIOD_8       0x1F04033C,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_CST_8              0x1F04033C,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_VALID_BITS_8      0x1F04033C,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_RS_8      0x1F04033C,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_8__DI0_SERIAL_CLK_8      0x1F04033C,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_9__ADDR                  0x1F040340
+#define LPM_MEM_DI0_DW_GEN_9__EMPTY      0x1F040340,0x00000000
+#define LPM_MEM_DI0_DW_GEN_9__FULL      0x1F040340,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_9__DI0_ACCESS_SIZE_9              0x1F040340,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_COMPONNENT_SIZE_9      0x1F040340,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9              0x1F040340,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_6_9       0x1F040340,0x00003000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_5_9       0x1F040340,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_4_9       0x1F040340,0x00000300
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_3_9       0x1F040340,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_2_9       0x1F040340,0x00000030
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_1_9       0x1F040340,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_9__DI0_PT_0_9       0x1F040340,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_9__ADDR                  0x1F040340
+#define LPM_MEM_DI0_DW_GEN_9__EMPTY      0x1F040340,0x00000000
+#define LPM_MEM_DI0_DW_GEN_9__FULL      0x1F040340,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_PERIOD_9      0x1F040340,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_START_PERIOD_9       0x1F040340,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_CST_9              0x1F040340,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_VALID_BITS_9      0x1F040340,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_RS_9      0x1F040340,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_9__DI0_SERIAL_CLK_9      0x1F040340,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_10__ADDR                  0x1F040344
+#define LPM_MEM_DI0_DW_GEN_10__EMPTY      0x1F040344,0x00000000
+#define LPM_MEM_DI0_DW_GEN_10__FULL      0x1F040344,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_10__DI0_ACCESS_SIZE_10      0x1F040344,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_COMPONNENT_SIZE_10      0x1F040344,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10      0x1F040344,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_6_10      0x1F040344,0x00003000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_5_10      0x1F040344,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_4_10      0x1F040344,0x00000300
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_3_10      0x1F040344,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_2_10      0x1F040344,0x00000030
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_1_10      0x1F040344,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_10__DI0_PT_0_10      0x1F040344,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_10__ADDR                  0x1F040344
+#define LPM_MEM_DI0_DW_GEN_10__EMPTY      0x1F040344,0x00000000
+#define LPM_MEM_DI0_DW_GEN_10__FULL      0x1F040344,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_PERIOD_10      0x1F040344,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_START_PERIOD_10      0x1F040344,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_CST_10      0x1F040344,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_VALID_BITS_10              0x1F040344,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_RS_10              0x1F040344,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_10__DI0_SERIAL_CLK_10       0x1F040344,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_11__ADDR                  0x1F040348
+#define LPM_MEM_DI0_DW_GEN_11__EMPTY      0x1F040348,0x00000000
+#define LPM_MEM_DI0_DW_GEN_11__FULL      0x1F040348,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_11__DI0_ACCESS_SIZE_11      0x1F040348,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_COMPONNENT_SIZE_11      0x1F040348,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11      0x1F040348,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_6_11      0x1F040348,0x00003000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_5_11      0x1F040348,0x00000C00
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_4_11      0x1F040348,0x00000300
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_3_11      0x1F040348,0x000000C0
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_2_11      0x1F040348,0x00000030
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_1_11      0x1F040348,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_11__DI0_PT_0_11      0x1F040348,0x00000003
+
+#define LPM_MEM_DI0_DW_GEN_11__ADDR                  0x1F040348
+#define LPM_MEM_DI0_DW_GEN_11__EMPTY      0x1F040348,0x00000000
+#define LPM_MEM_DI0_DW_GEN_11__FULL      0x1F040348,0xffffffff
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_PERIOD_11      0x1F040348,0xFF000000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_START_PERIOD_11      0x1F040348,0x00FF0000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_CST_11      0x1F040348,0x0000C000
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_VALID_BITS_11              0x1F040348,0x000001F0
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_RS_11              0x1F040348,0x0000000C
+#define LPM_MEM_DI0_DW_GEN_11__DI0_SERIAL_CLK_11       0x1F040348,0x00000003
+
+#define LPM_MEM_DI0_DW_SET0_0__ADDR                  0x1F04034C
+#define LPM_MEM_DI0_DW_SET0_0__EMPTY      0x1F04034C,0x00000000
+#define LPM_MEM_DI0_DW_SET0_0__FULL      0x1F04034C,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_DOWN0_0      0x1F04034C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_0__DI0_DATA_CNT_UP0_0      0x1F04034C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_1__ADDR                  0x1F040350
+#define LPM_MEM_DI0_DW_SET0_1__EMPTY      0x1F040350,0x00000000
+#define LPM_MEM_DI0_DW_SET0_1__FULL      0x1F040350,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_DOWN0_1      0x1F040350,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_1__DI0_DATA_CNT_UP0_1      0x1F040350,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_2__ADDR                  0x1F040354
+#define LPM_MEM_DI0_DW_SET0_2__EMPTY      0x1F040354,0x00000000
+#define LPM_MEM_DI0_DW_SET0_2__FULL      0x1F040354,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_DOWN0_2      0x1F040354,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_2__DI0_DATA_CNT_UP0_2      0x1F040354,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_3__ADDR                  0x1F040358
+#define LPM_MEM_DI0_DW_SET0_3__EMPTY      0x1F040358,0x00000000
+#define LPM_MEM_DI0_DW_SET0_3__FULL      0x1F040358,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_DOWN0_3      0x1F040358,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_3__DI0_DATA_CNT_UP0_3      0x1F040358,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_4__ADDR                  0x1F04035C
+#define LPM_MEM_DI0_DW_SET0_4__EMPTY      0x1F04035C,0x00000000
+#define LPM_MEM_DI0_DW_SET0_4__FULL      0x1F04035C,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_DOWN0_4      0x1F04035C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_4__DI0_DATA_CNT_UP0_4      0x1F04035C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_5__ADDR                  0x1F040360
+#define LPM_MEM_DI0_DW_SET0_5__EMPTY      0x1F040360,0x00000000
+#define LPM_MEM_DI0_DW_SET0_5__FULL      0x1F040360,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_DOWN0_5      0x1F040360,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_5__DI0_DATA_CNT_UP0_5      0x1F040360,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_6__ADDR                  0x1F040364
+#define LPM_MEM_DI0_DW_SET0_6__EMPTY      0x1F040364,0x00000000
+#define LPM_MEM_DI0_DW_SET0_6__FULL      0x1F040364,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_DOWN0_6      0x1F040364,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_6__DI0_DATA_CNT_UP0_6      0x1F040364,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_7__ADDR                  0x1F040368
+#define LPM_MEM_DI0_DW_SET0_7__EMPTY      0x1F040368,0x00000000
+#define LPM_MEM_DI0_DW_SET0_7__FULL      0x1F040368,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_DOWN0_7      0x1F040368,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_7__DI0_DATA_CNT_UP0_7      0x1F040368,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_8__ADDR                  0x1F04036C
+#define LPM_MEM_DI0_DW_SET0_8__EMPTY      0x1F04036C,0x00000000
+#define LPM_MEM_DI0_DW_SET0_8__FULL      0x1F04036C,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_DOWN0_8      0x1F04036C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_8__DI0_DATA_CNT_UP0_8      0x1F04036C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_9__ADDR                  0x1F040370
+#define LPM_MEM_DI0_DW_SET0_9__EMPTY      0x1F040370,0x00000000
+#define LPM_MEM_DI0_DW_SET0_9__FULL      0x1F040370,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_DOWN0_9      0x1F040370,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_9__DI0_DATA_CNT_UP0_9      0x1F040370,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_10__ADDR                  0x1F040374
+#define LPM_MEM_DI0_DW_SET0_10__EMPTY      0x1F040374,0x00000000
+#define LPM_MEM_DI0_DW_SET0_10__FULL      0x1F040374,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_DOWN0_10      0x1F040374,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_10__DI0_DATA_CNT_UP0_10      0x1F040374,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET0_11__ADDR                  0x1F040378
+#define LPM_MEM_DI0_DW_SET0_11__EMPTY      0x1F040378,0x00000000
+#define LPM_MEM_DI0_DW_SET0_11__FULL      0x1F040378,0xffffffff
+#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_DOWN0_11      0x1F040378,0x01FF0000
+#define LPM_MEM_DI0_DW_SET0_11__DI0_DATA_CNT_UP0_11      0x1F040378,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_0__ADDR                  0x1F04037C
+#define LPM_MEM_DI0_DW_SET1_0__EMPTY      0x1F04037C,0x00000000
+#define LPM_MEM_DI0_DW_SET1_0__FULL      0x1F04037C,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_DOWN1_0      0x1F04037C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_0__DI0_DATA_CNT_UP1_0      0x1F04037C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_1__ADDR                  0x1F040380
+#define LPM_MEM_DI0_DW_SET1_1__EMPTY      0x1F040380,0x00000000
+#define LPM_MEM_DI0_DW_SET1_1__FULL      0x1F040380,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_DOWN1_1      0x1F040380,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_1__DI0_DATA_CNT_UP1_1      0x1F040380,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_2__ADDR                  0x1F040384
+#define LPM_MEM_DI0_DW_SET1_2__EMPTY      0x1F040384,0x00000000
+#define LPM_MEM_DI0_DW_SET1_2__FULL      0x1F040384,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_DOWN1_2      0x1F040384,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_2__DI0_DATA_CNT_UP1_2      0x1F040384,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_3__ADDR                  0x1F040388
+#define LPM_MEM_DI0_DW_SET1_3__EMPTY      0x1F040388,0x00000000
+#define LPM_MEM_DI0_DW_SET1_3__FULL      0x1F040388,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_DOWN1_3      0x1F040388,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_3__DI0_DATA_CNT_UP1_3      0x1F040388,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_4__ADDR                  0x1F04038C
+#define LPM_MEM_DI0_DW_SET1_4__EMPTY      0x1F04038C,0x00000000
+#define LPM_MEM_DI0_DW_SET1_4__FULL      0x1F04038C,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_DOWN1_4      0x1F04038C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_4__DI0_DATA_CNT_UP1_4      0x1F04038C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_5__ADDR                  0x1F040390
+#define LPM_MEM_DI0_DW_SET1_5__EMPTY      0x1F040390,0x00000000
+#define LPM_MEM_DI0_DW_SET1_5__FULL      0x1F040390,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_DOWN1_5      0x1F040390,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_5__DI0_DATA_CNT_UP1_5      0x1F040390,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_6__ADDR                  0x1F040394
+#define LPM_MEM_DI0_DW_SET1_6__EMPTY      0x1F040394,0x00000000
+#define LPM_MEM_DI0_DW_SET1_6__FULL      0x1F040394,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_DOWN1_6      0x1F040394,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_6__DI0_DATA_CNT_UP1_6      0x1F040394,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_7__ADDR                  0x1F040398
+#define LPM_MEM_DI0_DW_SET1_7__EMPTY      0x1F040398,0x00000000
+#define LPM_MEM_DI0_DW_SET1_7__FULL      0x1F040398,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_DOWN1_7      0x1F040398,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_7__DI0_DATA_CNT_UP1_7      0x1F040398,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_8__ADDR                  0x1F04039C
+#define LPM_MEM_DI0_DW_SET1_8__EMPTY      0x1F04039C,0x00000000
+#define LPM_MEM_DI0_DW_SET1_8__FULL      0x1F04039C,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_DOWN1_8      0x1F04039C,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_8__DI0_DATA_CNT_UP1_8      0x1F04039C,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_9__ADDR                  0x1F0403A0
+#define LPM_MEM_DI0_DW_SET1_9__EMPTY      0x1F0403A0,0x00000000
+#define LPM_MEM_DI0_DW_SET1_9__FULL      0x1F0403A0,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_DOWN1_9      0x1F0403A0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_9__DI0_DATA_CNT_UP1_9      0x1F0403A0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_10__ADDR                  0x1F0403A4
+#define LPM_MEM_DI0_DW_SET1_10__EMPTY      0x1F0403A4,0x00000000
+#define LPM_MEM_DI0_DW_SET1_10__FULL      0x1F0403A4,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_DOWN1_10      0x1F0403A4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_10__DI0_DATA_CNT_UP1_10      0x1F0403A4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET1_11__ADDR                  0x1F0403A8
+#define LPM_MEM_DI0_DW_SET1_11__EMPTY      0x1F0403A8,0x00000000
+#define LPM_MEM_DI0_DW_SET1_11__FULL      0x1F0403A8,0xffffffff
+#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_DOWN1_11      0x1F0403A8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET1_11__DI0_DATA_CNT_UP1_11      0x1F0403A8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_0__ADDR                  0x1F0403AC
+#define LPM_MEM_DI0_DW_SET2_0__EMPTY      0x1F0403AC,0x00000000
+#define LPM_MEM_DI0_DW_SET2_0__FULL      0x1F0403AC,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_DOWN2_0      0x1F0403AC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_0__DI0_DATA_CNT_UP2_0      0x1F0403AC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_1__ADDR                  0x1F0403B0
+#define LPM_MEM_DI0_DW_SET2_1__EMPTY      0x1F0403B0,0x00000000
+#define LPM_MEM_DI0_DW_SET2_1__FULL      0x1F0403B0,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_DOWN2_1      0x1F0403B0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_1__DI0_DATA_CNT_UP2_1      0x1F0403B0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_2__ADDR                  0x1F0403B4
+#define LPM_MEM_DI0_DW_SET2_2__EMPTY      0x1F0403B4,0x00000000
+#define LPM_MEM_DI0_DW_SET2_2__FULL      0x1F0403B4,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_DOWN2_2      0x1F0403B4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_2__DI0_DATA_CNT_UP2_2      0x1F0403B4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_3__ADDR                  0x1F0403B8
+#define LPM_MEM_DI0_DW_SET2_3__EMPTY      0x1F0403B8,0x00000000
+#define LPM_MEM_DI0_DW_SET2_3__FULL      0x1F0403B8,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_DOWN2_3      0x1F0403B8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_3__DI0_DATA_CNT_UP2_3      0x1F0403B8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_4__ADDR                  0x1F0403BC
+#define LPM_MEM_DI0_DW_SET2_4__EMPTY      0x1F0403BC,0x00000000
+#define LPM_MEM_DI0_DW_SET2_4__FULL      0x1F0403BC,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_DOWN2_4      0x1F0403BC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_4__DI0_DATA_CNT_UP2_4      0x1F0403BC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_5__ADDR                  0x1F0403C0
+#define LPM_MEM_DI0_DW_SET2_5__EMPTY      0x1F0403C0,0x00000000
+#define LPM_MEM_DI0_DW_SET2_5__FULL      0x1F0403C0,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_DOWN2_5      0x1F0403C0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_5__DI0_DATA_CNT_UP2_5      0x1F0403C0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_6__ADDR                  0x1F0403C4
+#define LPM_MEM_DI0_DW_SET2_6__EMPTY      0x1F0403C4,0x00000000
+#define LPM_MEM_DI0_DW_SET2_6__FULL      0x1F0403C4,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_DOWN2_6      0x1F0403C4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_6__DI0_DATA_CNT_UP2_6      0x1F0403C4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_7__ADDR                  0x1F0403C8
+#define LPM_MEM_DI0_DW_SET2_7__EMPTY      0x1F0403C8,0x00000000
+#define LPM_MEM_DI0_DW_SET2_7__FULL      0x1F0403C8,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_DOWN2_7      0x1F0403C8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_7__DI0_DATA_CNT_UP2_7      0x1F0403C8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_8__ADDR                  0x1F0403CC
+#define LPM_MEM_DI0_DW_SET2_8__EMPTY      0x1F0403CC,0x00000000
+#define LPM_MEM_DI0_DW_SET2_8__FULL      0x1F0403CC,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_DOWN2_8      0x1F0403CC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_8__DI0_DATA_CNT_UP2_8      0x1F0403CC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_9__ADDR                  0x1F0403D0
+#define LPM_MEM_DI0_DW_SET2_9__EMPTY      0x1F0403D0,0x00000000
+#define LPM_MEM_DI0_DW_SET2_9__FULL      0x1F0403D0,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_DOWN2_9      0x1F0403D0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_9__DI0_DATA_CNT_UP2_9      0x1F0403D0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_10__ADDR                  0x1F0403D4
+#define LPM_MEM_DI0_DW_SET2_10__EMPTY      0x1F0403D4,0x00000000
+#define LPM_MEM_DI0_DW_SET2_10__FULL      0x1F0403D4,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_DOWN2_10      0x1F0403D4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_10__DI0_DATA_CNT_UP2_10      0x1F0403D4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET2_11__ADDR                  0x1F0403D8
+#define LPM_MEM_DI0_DW_SET2_11__EMPTY      0x1F0403D8,0x00000000
+#define LPM_MEM_DI0_DW_SET2_11__FULL      0x1F0403D8,0xffffffff
+#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_DOWN2_11      0x1F0403D8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET2_11__DI0_DATA_CNT_UP2_11      0x1F0403D8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_0__ADDR                  0x1F0403DC
+#define LPM_MEM_DI0_DW_SET3_0__EMPTY      0x1F0403DC,0x00000000
+#define LPM_MEM_DI0_DW_SET3_0__FULL      0x1F0403DC,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_DOWN3_0      0x1F0403DC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_0__DI0_DATA_CNT_UP3_0      0x1F0403DC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_1__ADDR                  0x1F0403E0
+#define LPM_MEM_DI0_DW_SET3_1__EMPTY      0x1F0403E0,0x00000000
+#define LPM_MEM_DI0_DW_SET3_1__FULL      0x1F0403E0,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_DOWN3_1      0x1F0403E0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_1__DI0_DATA_CNT_UP3_1      0x1F0403E0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_2__ADDR                  0x1F0403E4
+#define LPM_MEM_DI0_DW_SET3_2__EMPTY      0x1F0403E4,0x00000000
+#define LPM_MEM_DI0_DW_SET3_2__FULL      0x1F0403E4,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_DOWN3_2      0x1F0403E4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_2__DI0_DATA_CNT_UP3_2      0x1F0403E4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_3__ADDR                  0x1F0403E8
+#define LPM_MEM_DI0_DW_SET3_3__EMPTY      0x1F0403E8,0x00000000
+#define LPM_MEM_DI0_DW_SET3_3__FULL      0x1F0403E8,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_DOWN3_3      0x1F0403E8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_3__DI0_DATA_CNT_UP3_3      0x1F0403E8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_4__ADDR                  0x1F0403EC
+#define LPM_MEM_DI0_DW_SET3_4__EMPTY      0x1F0403EC,0x00000000
+#define LPM_MEM_DI0_DW_SET3_4__FULL      0x1F0403EC,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_DOWN3_4      0x1F0403EC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_4__DI0_DATA_CNT_UP3_4      0x1F0403EC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_5__ADDR                  0x1F0403F0
+#define LPM_MEM_DI0_DW_SET3_5__EMPTY      0x1F0403F0,0x00000000
+#define LPM_MEM_DI0_DW_SET3_5__FULL      0x1F0403F0,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_DOWN3_5      0x1F0403F0,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_5__DI0_DATA_CNT_UP3_5      0x1F0403F0,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_6__ADDR                  0x1F0403F4
+#define LPM_MEM_DI0_DW_SET3_6__EMPTY      0x1F0403F4,0x00000000
+#define LPM_MEM_DI0_DW_SET3_6__FULL      0x1F0403F4,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_DOWN3_6      0x1F0403F4,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_6__DI0_DATA_CNT_UP3_6      0x1F0403F4,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_7__ADDR                  0x1F0403F8
+#define LPM_MEM_DI0_DW_SET3_7__EMPTY      0x1F0403F8,0x00000000
+#define LPM_MEM_DI0_DW_SET3_7__FULL      0x1F0403F8,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_DOWN3_7      0x1F0403F8,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_7__DI0_DATA_CNT_UP3_7      0x1F0403F8,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_8__ADDR                  0x1F0403FC
+#define LPM_MEM_DI0_DW_SET3_8__EMPTY      0x1F0403FC,0x00000000
+#define LPM_MEM_DI0_DW_SET3_8__FULL      0x1F0403FC,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_DOWN3_8      0x1F0403FC,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_8__DI0_DATA_CNT_UP3_8      0x1F0403FC,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_9__ADDR                  0x1F040400
+#define LPM_MEM_DI0_DW_SET3_9__EMPTY      0x1F040400,0x00000000
+#define LPM_MEM_DI0_DW_SET3_9__FULL      0x1F040400,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_DOWN3_9      0x1F040400,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_9__DI0_DATA_CNT_UP3_9      0x1F040400,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_10__ADDR                  0x1F040404
+#define LPM_MEM_DI0_DW_SET3_10__EMPTY      0x1F040404,0x00000000
+#define LPM_MEM_DI0_DW_SET3_10__FULL      0x1F040404,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_DOWN3_10      0x1F040404,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_10__DI0_DATA_CNT_UP3_10      0x1F040404,0x000001FF
+
+#define LPM_MEM_DI0_DW_SET3_11__ADDR                  0x1F040408
+#define LPM_MEM_DI0_DW_SET3_11__EMPTY      0x1F040408,0x00000000
+#define LPM_MEM_DI0_DW_SET3_11__FULL      0x1F040408,0xffffffff
+#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_DOWN3_11      0x1F040408,0x01FF0000
+#define LPM_MEM_DI0_DW_SET3_11__DI0_DATA_CNT_UP3_11      0x1F040408,0x000001FF
+
+#define LPM_MEM_DI0_STP_REP_1__ADDR                  0x1F04040C
+#define LPM_MEM_DI0_STP_REP_1__EMPTY      0x1F04040C,0x00000000
+#define LPM_MEM_DI0_STP_REP_1__FULL      0x1F04040C,0xffffffff
+#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_2       0x1F04040C,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_1__DI0_STEP_REPEAT_1       0x1F04040C,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_2__ADDR                  0x1F040410
+#define LPM_MEM_DI0_STP_REP_2__EMPTY      0x1F040410,0x00000000
+#define LPM_MEM_DI0_STP_REP_2__FULL      0x1F040410,0xffffffff
+#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_4       0x1F040410,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_2__DI0_STEP_REPEAT_3       0x1F040410,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_3__ADDR                  0x1F040414
+#define LPM_MEM_DI0_STP_REP_3__EMPTY      0x1F040414,0x00000000
+#define LPM_MEM_DI0_STP_REP_3__FULL      0x1F040414,0xffffffff
+#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_6       0x1F040414,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_3__DI0_STEP_REPEAT_5       0x1F040414,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_4__ADDR                  0x1F040418
+#define LPM_MEM_DI0_STP_REP_4__EMPTY      0x1F040418,0x00000000
+#define LPM_MEM_DI0_STP_REP_4__FULL      0x1F040418,0xffffffff
+#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_8       0x1F040418,0x0FFF0000
+#define LPM_MEM_DI0_STP_REP_4__DI0_STEP_REPEAT_7       0x1F040418,0x00000FFF
+
+#define LPM_MEM_DI0_STP_REP_9__ADDR                  0x1F04041C
+#define LPM_MEM_DI0_STP_REP_9__EMPTY      0x1F04041C,0x00000000
+#define LPM_MEM_DI0_STP_REP_9__FULL      0x1F04041C,0xffffffff
+#define LPM_MEM_DI0_STP_REP_9__DI0_STEP_REPEAT_9       0x1F04041C,0x00000FFF
+
+#define LPM_MEM_DI0_SER_CONF__ADDR                  0x1F040420
+#define LPM_MEM_DI0_SER_CONF__EMPTY      0x1F040420,0x00000000
+#define LPM_MEM_DI0_SER_CONF__FULL      0x1F040420,0xffffffff
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_1       0x1F040420,0xF0000000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_R_0       0x1F040420,0x0F000000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_1       0x1F040420,0x00F00000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LLA_PNTR_RS_W_0       0x1F040420,0x000F0000
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_LATCH      0x1F040420,0x0000FF00
+#define LPM_MEM_DI0_SER_CONF__DI0_LLA_SER_ACCESS       0x1F040420,0x00000020
+#define LPM_MEM_DI0_SER_CONF__DI0_SER_CLK_POLARITY      0x1F040420,0x00000010
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_DATA_POLARITY      0x1F040420,0x00000008
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_RS_POLARITY      0x1F040420,0x00000004
+#define LPM_MEM_DI0_SER_CONF__DI0_SERIAL_CS_POLARITY      0x1F040420,0x00000002
+#define LPM_MEM_DI0_SER_CONF__DI0_WAIT4SERIAL      0x1F040420,0x00000001
+
+#define LPM_MEM_DI0_SSC__ADDR                  0x1F040424
+#define LPM_MEM_DI0_SSC__EMPTY      0x1F040424,0x00000000
+#define LPM_MEM_DI0_SSC__FULL      0x1F040424,0xffffffff
+#define LPM_MEM_DI0_SSC__DI0_PIN17_ERM      0x1F040424,0x00800000
+#define LPM_MEM_DI0_SSC__DI0_PIN16_ERM      0x1F040424,0x00400000
+#define LPM_MEM_DI0_SSC__DI0_PIN15_ERM      0x1F040424,0x00200000
+#define LPM_MEM_DI0_SSC__DI0_PIN14_ERM      0x1F040424,0x00100000
+#define LPM_MEM_DI0_SSC__DI0_PIN13_ERM      0x1F040424,0x00080000
+#define LPM_MEM_DI0_SSC__DI0_PIN12_ERM      0x1F040424,0x00040000
+#define LPM_MEM_DI0_SSC__DI0_PIN11_ERM      0x1F040424,0x00020000
+#define LPM_MEM_DI0_SSC__DI0_CS_ERM      0x1F040424,0x00010000
+#define LPM_MEM_DI0_SSC__DI0_WAIT_ON      0x1F040424,0x00000020
+#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_RD_IN      0x1F040424,0x00000008
+#define LPM_MEM_DI0_SSC__DI0_BYTE_EN_PNTR      0x1F040424,0x00000007
+
+#define LPM_MEM_DI0_POL__ADDR                  0x1F040428
+#define LPM_MEM_DI0_POL__EMPTY      0x1F040428,0x00000000
+#define LPM_MEM_DI0_POL__FULL      0x1F040428,0xffffffff
+#define LPM_MEM_DI0_POL__DI0_WAIT_POLARITY      0x1F040428,0x04000000
+#define LPM_MEM_DI0_POL__DI0_CS1_BYTE_EN_POLARITY      0x1F040428,0x02000000
+#define LPM_MEM_DI0_POL__DI0_CS0_BYTE_EN_POLARITY      0x1F040428,0x01000000
+#define LPM_MEM_DI0_POL__DI0_CS1_DATA_POLARITY      0x1F040428,0x00800000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_17      0x1F040428,0x00400000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_16      0x1F040428,0x00200000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_15      0x1F040428,0x00100000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_14      0x1F040428,0x00080000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_13      0x1F040428,0x00040000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_12      0x1F040428,0x00020000
+#define LPM_MEM_DI0_POL__DI0_CS1_POLARITY_11      0x1F040428,0x00010000
+#define LPM_MEM_DI0_POL__DI0_CS0_DATA_POLARITY      0x1F040428,0x00008000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_17      0x1F040428,0x00004000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_16      0x1F040428,0x00002000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_15      0x1F040428,0x00001000
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_14      0x1F040428,0x00000800
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_13      0x1F040428,0x00000400
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_12      0x1F040428,0x00000200
+#define LPM_MEM_DI0_POL__DI0_CS0_POLARITY_11      0x1F040428,0x00000100
+#define LPM_MEM_DI0_POL__DI0_DRDY_DATA_POLARITY              0x1F040428,0x00000080
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_17      0x1F040428,0x00000040
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_16      0x1F040428,0x00000020
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_15      0x1F040428,0x00000010
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_14      0x1F040428,0x00000008
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_13      0x1F040428,0x00000004
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_12      0x1F040428,0x00000002
+#define LPM_MEM_DI0_POL__DI0_DRDY_POLARITY_11      0x1F040428,0x00000001
+
+#define LPM_MEM_DI0_AW0__ADDR                  0x1F04042C
+#define LPM_MEM_DI0_AW0__EMPTY      0x1F04042C,0x00000000
+#define LPM_MEM_DI0_AW0__FULL      0x1F04042C,0xffffffff
+#define LPM_MEM_DI0_AW0__DI0_AW_TRIG_SEL       0x1F04042C,0xF0000000
+#define LPM_MEM_DI0_AW0__DI0_AW_HEND      0x1F04042C,0x0FFF0000
+#define LPM_MEM_DI0_AW0__DI0_AW_HCOUNT_SEL      0x1F04042C,0x0000F000
+#define LPM_MEM_DI0_AW0__DI0_AW_HSTART      0x1F04042C,0x00000FFF
+
+#define LPM_MEM_DI0_AW1__ADDR                  0x1F040430
+#define LPM_MEM_DI0_AW1__EMPTY      0x1F040430,0x00000000
+#define LPM_MEM_DI0_AW1__FULL      0x1F040430,0xffffffff
+#define LPM_MEM_DI0_AW1__DI0_AW_VEND      0x1F040430,0x0FFF0000
+#define LPM_MEM_DI0_AW1__DI0_AW_VCOUNT_SEL      0x1F040430,0x0000F000
+#define LPM_MEM_DI0_AW1__DI0_AW_VSTART      0x1F040430,0x00000FFF
+
+#define LPM_MEM_DI0_SCR_CONF__ADDR                  0x1F040434
+#define LPM_MEM_DI0_SCR_CONF__EMPTY      0x1F040434,0x00000000
+#define LPM_MEM_DI0_SCR_CONF__FULL      0x1F040434,0xffffffff
+#define LPM_MEM_DI0_SCR_CONF__DI0_SCREEN_HEIGHT              0x1F040434,0x00000FFF
+
+#define LPM_MEM_DI1_GENERAL__ADDR                  0x1F040438
+#define LPM_MEM_DI1_GENERAL__EMPTY      0x1F040438,0x00000000
+#define LPM_MEM_DI1_GENERAL__FULL      0x1F040438,0xffffffff
+#define LPM_MEM_DI1_GENERAL__DI1_DISP_Y_SEL      0x1F040438,0x70000000
+#define LPM_MEM_DI1_GENERAL__DI1_CLOCK_STOP_MODE       0x1F040438,0x0F000000
+#define LPM_MEM_DI1_GENERAL__DI1_DISP_CLOCK_INIT       0x1F040438,0x00800000
+#define LPM_MEM_DI1_GENERAL__DI1_MASK_SEL      0x1F040438,0x00400000
+#define LPM_MEM_DI1_GENERAL__DI1_VSYNC_EXT      0x1F040438,0x00200000
+#define LPM_MEM_DI1_GENERAL__DI1_CLK_EXT       0x1F040438,0x00100000
+#define LPM_MEM_DI1_GENERAL__DI1_WATCHDOG_MODE      0x1F040438,0x000C0000
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_DISP_CLK      0x1F040438,0x00020000
+#define LPM_MEM_DI1_GENERAL__DI1_SYNC_COUNT_SEL              0x1F040438,0x0000F000
+#define LPM_MEM_DI1_GENERAL__DI1_ERR_TREATMENT      0x1F040438,0x00000800
+#define LPM_MEM_DI1_GENERAL__DI1_ERM_VSYNC_SEL    0x1F040438,0x00000400
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS1      0x1F040438,0x00000200
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_CS0      0x1F040438,0x00000100
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_8      0x1F040438,0x00000080
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_7      0x1F040438,0x00000040
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_6      0x1F040438,0x00000020
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_5      0x1F040438,0x00000010
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_4      0x1F040438,0x00000008
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_3      0x1F040438,0x00000004
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_2      0x1F040438,0x00000002
+#define LPM_MEM_DI1_GENERAL__DI1_POLARITY_1      0x1F040438,0x00000001
+
+#define LPM_MEM_DI1_BS_CLKGEN0__ADDR                  0x1F04043C
+#define LPM_MEM_DI1_BS_CLKGEN0__EMPTY      0x1F04043C,0x00000000
+#define LPM_MEM_DI1_BS_CLKGEN0__FULL      0x1F04043C,0xffffffff
+#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET      0x1F04043C,0x01FF0000
+#define LPM_MEM_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD      0x1F04043C,0x00000FFF
+
+#define LPM_MEM_DI1_BS_CLKGEN1__ADDR                  0x1F040440
+#define LPM_MEM_DI1_BS_CLKGEN1__EMPTY      0x1F040440,0x00000000
+#define LPM_MEM_DI1_BS_CLKGEN1__FULL      0x1F040440,0xffffffff
+#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN      0x1F040440,0x01FF0000
+#define LPM_MEM_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP              0x1F040440,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN0_1__ADDR                  0x1F040444
+#define LPM_MEM_DI1_SW_GEN0_1__EMPTY      0x1F040444,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_1__FULL      0x1F040444,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_VALUE_M1_1      0x1F040444,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_RUN_RESOLUTION_1      0x1F040444,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_VALUE_1      0x1F040444,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_1__DI1_OFFSET_RESOLUTION_1      0x1F040444,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_2__ADDR                  0x1F040448
+#define LPM_MEM_DI1_SW_GEN0_2__EMPTY      0x1F040448,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_2__FULL      0x1F040448,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_VALUE_M1_2      0x1F040448,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_RUN_RESOLUTION_2      0x1F040448,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_VALUE_2      0x1F040448,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_2__DI1_OFFSET_RESOLUTION_2      0x1F040448,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_3__ADDR                  0x1F04044C
+#define LPM_MEM_DI1_SW_GEN0_3__EMPTY      0x1F04044C,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_3__FULL      0x1F04044C,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_VALUE_M1_3      0x1F04044C,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_RUN_RESOLUTION_3      0x1F04044C,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_VALUE_3      0x1F04044C,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_3__DI1_OFFSET_RESOLUTION_3      0x1F04044C,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_4__ADDR                  0x1F040450
+#define LPM_MEM_DI1_SW_GEN0_4__EMPTY      0x1F040450,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_4__FULL      0x1F040450,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_VALUE_M1_4      0x1F040450,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_RUN_RESOLUTION_4      0x1F040450,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_VALUE_4      0x1F040450,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_4__DI1_OFFSET_RESOLUTION_4      0x1F040450,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_5__ADDR                  0x1F040454
+#define LPM_MEM_DI1_SW_GEN0_5__EMPTY      0x1F040454,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_5__FULL      0x1F040454,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_VALUE_M1_5      0x1F040454,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_RUN_RESOLUTION_5      0x1F040454,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_VALUE_5      0x1F040454,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_5__DI1_OFFSET_RESOLUTION_5      0x1F040454,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_6__ADDR                  0x1F040458
+#define LPM_MEM_DI1_SW_GEN0_6__EMPTY      0x1F040458,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_6__FULL      0x1F040458,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_VALUE_M1_6      0x1F040458,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_RUN_RESOLUTION_6      0x1F040458,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_VALUE_6      0x1F040458,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_6__DI1_OFFSET_RESOLUTION_6      0x1F040458,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_7__ADDR                  0x1F04045C
+#define LPM_MEM_DI1_SW_GEN0_7__EMPTY      0x1F04045C,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_7__FULL      0x1F04045C,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_VALUE_M1_7      0x1F04045C,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_RUN_RESOLUTION_7      0x1F04045C,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_VALUE_7      0x1F04045C,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_7__DI1_OFFSET_RESOLUTION_7      0x1F04045C,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_8__ADDR                  0x1F040460
+#define LPM_MEM_DI1_SW_GEN0_8__EMPTY      0x1F040460,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_8__FULL      0x1F040460,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_VALUE_M1_8      0x1F040460,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_RUN_RESOLUTION_8      0x1F040460,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_VALUE_8      0x1F040460,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_8__DI1_OFFSET_RESOLUTION_8      0x1F040460,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN0_9__ADDR                  0x1F040464
+#define LPM_MEM_DI1_SW_GEN0_9__EMPTY      0x1F040464,0x00000000
+#define LPM_MEM_DI1_SW_GEN0_9__FULL      0x1F040464,0xffffffff
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_VALUE_M1_9      0x1F040464,0x7FF80000
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_RUN_RESOLUTION_9      0x1F040464,0x00070000
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_VALUE_9      0x1F040464,0x00007FF8
+#define LPM_MEM_DI1_SW_GEN0_9__DI1_OFFSET_RESOLUTION_9      0x1F040464,0x00000007
+
+#define LPM_MEM_DI1_SW_GEN1_1__ADDR                  0x1F040468
+#define LPM_MEM_DI1_SW_GEN1_1__EMPTY      0x1F040468,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_1__FULL      0x1F040468,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_GEN_EN_1       0x1F040468,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_AUTO_RELOAD_1      0x1F040468,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_CLR_SEL_1       0x1F040468,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_DOWN_1      0x1F040468,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_TRIGGER_SEL_1      0x1F040468,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_POLARITY_CLR_SEL_1      0x1F040468,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_1__DI1_CNT_UP_1      0x1F040468,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_2__ADDR                  0x1F04046C
+#define LPM_MEM_DI1_SW_GEN1_2__EMPTY      0x1F04046C,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_2__FULL      0x1F04046C,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_GEN_EN_2       0x1F04046C,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_AUTO_RELOAD_2      0x1F04046C,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_CLR_SEL_2       0x1F04046C,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_DOWN_2      0x1F04046C,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_TRIGGER_SEL_2      0x1F04046C,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_POLARITY_CLR_SEL_2      0x1F04046C,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_2__DI1_CNT_UP_2      0x1F04046C,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_3__ADDR                  0x1F040470
+#define LPM_MEM_DI1_SW_GEN1_3__EMPTY      0x1F040470,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_3__FULL      0x1F040470,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_GEN_EN_3       0x1F040470,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_AUTO_RELOAD_3      0x1F040470,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_CLR_SEL_3       0x1F040470,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_DOWN_3      0x1F040470,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_TRIGGER_SEL_3      0x1F040470,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_POLARITY_CLR_SEL_3      0x1F040470,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_3__DI1_CNT_UP_3      0x1F040470,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_4__ADDR                  0x1F040474
+#define LPM_MEM_DI1_SW_GEN1_4__EMPTY      0x1F040474,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_4__FULL      0x1F040474,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_GEN_EN_4       0x1F040474,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_AUTO_RELOAD_4      0x1F040474,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_CLR_SEL_4       0x1F040474,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_DOWN_4      0x1F040474,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_TRIGGER_SEL_4      0x1F040474,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_POLARITY_CLR_SEL_4      0x1F040474,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_4__DI1_CNT_UP_4      0x1F040474,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_5__ADDR                  0x1F040478
+#define LPM_MEM_DI1_SW_GEN1_5__EMPTY      0x1F040478,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_5__FULL      0x1F040478,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_GEN_EN_5       0x1F040478,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_AUTO_RELOAD_5      0x1F040478,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_CLR_SEL_5       0x1F040478,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_DOWN_5      0x1F040478,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_TRIGGER_SEL_5      0x1F040478,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_POLARITY_CLR_SEL_5      0x1F040478,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_5__DI1_CNT_UP_5      0x1F040478,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_6__ADDR                  0x1F04047C
+#define LPM_MEM_DI1_SW_GEN1_6__EMPTY      0x1F04047C,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_6__FULL      0x1F04047C,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_GEN_EN_6       0x1F04047C,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_AUTO_RELOAD_6      0x1F04047C,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_CLR_SEL_6       0x1F04047C,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_DOWN_6      0x1F04047C,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_TRIGGER_SEL_6      0x1F04047C,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_POLARITY_CLR_SEL_6      0x1F04047C,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_6__DI1_CNT_UP_6      0x1F04047C,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_7__ADDR                  0x1F040480
+#define LPM_MEM_DI1_SW_GEN1_7__EMPTY      0x1F040480,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_7__FULL      0x1F040480,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_GEN_EN_7       0x1F040480,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_AUTO_RELOAD_7      0x1F040480,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_CLR_SEL_7       0x1F040480,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_DOWN_7      0x1F040480,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_TRIGGER_SEL_7      0x1F040480,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_POLARITY_CLR_SEL_7      0x1F040480,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_7__DI1_CNT_UP_7      0x1F040480,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_8__ADDR                  0x1F040484
+#define LPM_MEM_DI1_SW_GEN1_8__EMPTY      0x1F040484,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_8__FULL      0x1F040484,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_GEN_EN_8       0x1F040484,0x60000000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_AUTO_RELOAD_8      0x1F040484,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_CLR_SEL_8       0x1F040484,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_DOWN_8      0x1F040484,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_TRIGGER_SEL_8      0x1F040484,0x00007000
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_POLARITY_CLR_SEL_8      0x1F040484,0x00000E00
+#define LPM_MEM_DI1_SW_GEN1_8__DI1_CNT_UP_8      0x1F040484,0x000001FF
+
+#define LPM_MEM_DI1_SW_GEN1_9__ADDR                  0x1F040488
+#define LPM_MEM_DI1_SW_GEN1_9__EMPTY      0x1F040488,0x00000000
+#define LPM_MEM_DI1_SW_GEN1_9__FULL      0x1F040488,0xffffffff
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_GENTIME_SEL_9       0x1F040488,0xE0000000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_AUTO_RELOAD_9      0x1F040488,0x10000000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_CLR_SEL_9       0x1F040488,0x0E000000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_DOWN_9      0x1F040488,0x01FF0000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_TAG_SEL_9      0x1F040488,0x00008000
+#define LPM_MEM_DI1_SW_GEN1_9__DI1_CNT_UP_9      0x1F040488,0x000001FF
+
+#define LPM_MEM_DI1_SYNC_AS_GEN__ADDR                  0x1F04048C
+#define LPM_MEM_DI1_SYNC_AS_GEN__EMPTY      0x1F04048C,0x00000000
+#define LPM_MEM_DI1_SYNC_AS_GEN__FULL      0x1F04048C,0xffffffff
+#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START_EN      0x1F04048C,0x10000000
+#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL      0x1F04048C,0x0000E000
+#define LPM_MEM_DI1_SYNC_AS_GEN__DI1_SYNC_START              0x1F04048C,0x00000FFF
+
+#define LPM_MEM_DI1_DW_GEN_0__ADDR                  0x1F040490
+#define LPM_MEM_DI1_DW_GEN_0__EMPTY      0x1F040490,0x00000000
+#define LPM_MEM_DI1_DW_GEN_0__FULL      0x1F040490,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_0__DI1_ACCESS_SIZE_0              0x1F040490,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_COMPONNENT_SIZE_0      0x1F040490,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0              0x1F040490,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_6_0       0x1F040490,0x00003000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_5_0       0x1F040490,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_4_0       0x1F040490,0x00000300
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_3_0       0x1F040490,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_2_0       0x1F040490,0x00000030
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_1_0       0x1F040490,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_0__DI1_PT_0_0       0x1F040490,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_0__ADDR                  0x1F040490
+#define LPM_MEM_DI1_DW_GEN_0__EMPTY      0x1F040490,0x00000000
+#define LPM_MEM_DI1_DW_GEN_0__FULL      0x1F040490,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_PERIOD_0      0x1F040490,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_START_PERIOD_0       0x1F040490,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_CST_0              0x1F040490,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_VALID_BITS_0      0x1F040490,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_RS_0      0x1F040490,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_0__DI1_SERIAL_CLK_0      0x1F040490,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_1__ADDR                  0x1F040494
+#define LPM_MEM_DI1_DW_GEN_1__EMPTY      0x1F040494,0x00000000
+#define LPM_MEM_DI1_DW_GEN_1__FULL      0x1F040494,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_1__DI1_ACCESS_SIZE_1              0x1F040494,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_COMPONNENT_SIZE_1      0x1F040494,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1              0x1F040494,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_6_1       0x1F040494,0x00003000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_5_1       0x1F040494,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_4_1       0x1F040494,0x00000300
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_3_1       0x1F040494,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_2_1       0x1F040494,0x00000030
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_1_1       0x1F040494,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_1__DI1_PT_0_1       0x1F040494,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_1__ADDR                  0x1F040494
+#define LPM_MEM_DI1_DW_GEN_1__EMPTY      0x1F040494,0x00000000
+#define LPM_MEM_DI1_DW_GEN_1__FULL      0x1F040494,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_PERIOD_1      0x1F040494,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_START_PERIOD_1       0x1F040494,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_CST_1              0x1F040494,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_VALID_BITS_1      0x1F040494,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_RS_1      0x1F040494,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_1__DI1_SERIAL_CLK_1      0x1F040494,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_2__ADDR                  0x1F040498
+#define LPM_MEM_DI1_DW_GEN_2__EMPTY      0x1F040498,0x00000000
+#define LPM_MEM_DI1_DW_GEN_2__FULL      0x1F040498,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_2__DI1_ACCESS_SIZE_2              0x1F040498,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_COMPONNENT_SIZE_2      0x1F040498,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2              0x1F040498,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_6_2       0x1F040498,0x00003000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_5_2       0x1F040498,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_4_2       0x1F040498,0x00000300
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_3_2       0x1F040498,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_2_2       0x1F040498,0x00000030
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_1_2       0x1F040498,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_2__DI1_PT_0_2       0x1F040498,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_2__ADDR                  0x1F040498
+#define LPM_MEM_DI1_DW_GEN_2__EMPTY      0x1F040498,0x00000000
+#define LPM_MEM_DI1_DW_GEN_2__FULL      0x1F040498,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_PERIOD_2      0x1F040498,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_START_PERIOD_2       0x1F040498,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_CST_2              0x1F040498,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_VALID_BITS_2      0x1F040498,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_RS_2      0x1F040498,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_2__DI1_SERIAL_CLK_2      0x1F040498,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_3__ADDR                  0x1F04049C
+#define LPM_MEM_DI1_DW_GEN_3__EMPTY      0x1F04049C,0x00000000
+#define LPM_MEM_DI1_DW_GEN_3__FULL      0x1F04049C,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_3__DI1_ACCESS_SIZE_3              0x1F04049C,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_COMPONNENT_SIZE_3      0x1F04049C,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3              0x1F04049C,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_6_3       0x1F04049C,0x00003000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_5_3       0x1F04049C,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_4_3       0x1F04049C,0x00000300
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_3_3       0x1F04049C,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_2_3       0x1F04049C,0x00000030
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_1_3       0x1F04049C,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_3__DI1_PT_0_3       0x1F04049C,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_3__ADDR                  0x1F04049C
+#define LPM_MEM_DI1_DW_GEN_3__EMPTY      0x1F04049C,0x00000000
+#define LPM_MEM_DI1_DW_GEN_3__FULL      0x1F04049C,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_PERIOD_3      0x1F04049C,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_START_PERIOD_3       0x1F04049C,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_CST_3              0x1F04049C,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_VALID_BITS_3      0x1F04049C,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_RS_3      0x1F04049C,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_3__DI1_SERIAL_CLK_3      0x1F04049C,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_4__ADDR                  0x1F0404A0
+#define LPM_MEM_DI1_DW_GEN_4__EMPTY      0x1F0404A0,0x00000000
+#define LPM_MEM_DI1_DW_GEN_4__FULL      0x1F0404A0,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_4__DI1_ACCESS_SIZE_4              0x1F0404A0,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_COMPONNENT_SIZE_4      0x1F0404A0,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4              0x1F0404A0,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_6_4       0x1F0404A0,0x00003000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_5_4       0x1F0404A0,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_4_4       0x1F0404A0,0x00000300
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_3_4       0x1F0404A0,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_2_4       0x1F0404A0,0x00000030
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_1_4       0x1F0404A0,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_4__DI1_PT_0_4       0x1F0404A0,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_4__ADDR                  0x1F0404A0
+#define LPM_MEM_DI1_DW_GEN_4__EMPTY      0x1F0404A0,0x00000000
+#define LPM_MEM_DI1_DW_GEN_4__FULL      0x1F0404A0,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_PERIOD_4      0x1F0404A0,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_START_PERIOD_4       0x1F0404A0,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_CST_4              0x1F0404A0,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_VALID_BITS_4      0x1F0404A0,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_RS_4      0x1F0404A0,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_4__DI1_SERIAL_CLK_4      0x1F0404A0,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_5__ADDR                  0x1F0404A4
+#define LPM_MEM_DI1_DW_GEN_5__EMPTY      0x1F0404A4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_5__FULL      0x1F0404A4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_5__DI1_ACCESS_SIZE_5              0x1F0404A4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_COMPONNENT_SIZE_5      0x1F0404A4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5              0x1F0404A4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_6_5       0x1F0404A4,0x00003000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_5_5       0x1F0404A4,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_4_5       0x1F0404A4,0x00000300
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_3_5       0x1F0404A4,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_2_5       0x1F0404A4,0x00000030
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_1_5       0x1F0404A4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_5__DI1_PT_0_5       0x1F0404A4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_5__ADDR                  0x1F0404A4
+#define LPM_MEM_DI1_DW_GEN_5__EMPTY      0x1F0404A4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_5__FULL      0x1F0404A4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_PERIOD_5      0x1F0404A4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_START_PERIOD_5       0x1F0404A4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_CST_5              0x1F0404A4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_VALID_BITS_5      0x1F0404A4,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_RS_5      0x1F0404A4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_5__DI1_SERIAL_CLK_5      0x1F0404A4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_6__ADDR                  0x1F0404A8
+#define LPM_MEM_DI1_DW_GEN_6__EMPTY      0x1F0404A8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_6__FULL      0x1F0404A8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_6__DI1_ACCESS_SIZE_6              0x1F0404A8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_COMPONNENT_SIZE_6      0x1F0404A8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6              0x1F0404A8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_6_6       0x1F0404A8,0x00003000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_5_6       0x1F0404A8,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_4_6       0x1F0404A8,0x00000300
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_3_6       0x1F0404A8,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_2_6       0x1F0404A8,0x00000030
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_1_6       0x1F0404A8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_6__DI1_PT_0_6       0x1F0404A8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_6__ADDR                  0x1F0404A8
+#define LPM_MEM_DI1_DW_GEN_6__EMPTY      0x1F0404A8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_6__FULL      0x1F0404A8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_PERIOD_6      0x1F0404A8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_START_PERIOD_6       0x1F0404A8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_CST_6              0x1F0404A8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_VALID_BITS_6      0x1F0404A8,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_RS_6      0x1F0404A8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_6__DI1_SERIAL_CLK_6      0x1F0404A8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_7__ADDR                  0x1F0404AC
+#define LPM_MEM_DI1_DW_GEN_7__EMPTY      0x1F0404AC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_7__FULL      0x1F0404AC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_7__DI1_ACCESS_SIZE_7              0x1F0404AC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_COMPONNENT_SIZE_7      0x1F0404AC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7              0x1F0404AC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_6_7       0x1F0404AC,0x00003000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_5_7       0x1F0404AC,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_4_7       0x1F0404AC,0x00000300
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_3_7       0x1F0404AC,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_2_7       0x1F0404AC,0x00000030
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_1_7       0x1F0404AC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_7__DI1_PT_0_7       0x1F0404AC,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_7__ADDR                  0x1F0404AC
+#define LPM_MEM_DI1_DW_GEN_7__EMPTY      0x1F0404AC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_7__FULL      0x1F0404AC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_PERIOD_7      0x1F0404AC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_START_PERIOD_7       0x1F0404AC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_CST_7              0x1F0404AC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_VALID_BITS_7      0x1F0404AC,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_RS_7      0x1F0404AC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_7__DI1_SERIAL_CLK_7      0x1F0404AC,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_8__ADDR                  0x1F0404B0
+#define LPM_MEM_DI1_DW_GEN_8__EMPTY      0x1F0404B0,0x00000000
+#define LPM_MEM_DI1_DW_GEN_8__FULL      0x1F0404B0,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_8__DI1_ACCESS_SIZE_8              0x1F0404B0,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_COMPONNENT_SIZE_8      0x1F0404B0,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8              0x1F0404B0,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_6_8       0x1F0404B0,0x00003000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_5_8       0x1F0404B0,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_4_8       0x1F0404B0,0x00000300
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_3_8       0x1F0404B0,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_2_8       0x1F0404B0,0x00000030
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_1_8       0x1F0404B0,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_8__DI1_PT_0_8       0x1F0404B0,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_8__ADDR                  0x1F0404B0
+#define LPM_MEM_DI1_DW_GEN_8__EMPTY      0x1F0404B0,0x00000000
+#define LPM_MEM_DI1_DW_GEN_8__FULL      0x1F0404B0,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_PERIOD_8      0x1F0404B0,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_START_PERIOD_8       0x1F0404B0,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_CST_8              0x1F0404B0,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_VALID_BITS_8      0x1F0404B0,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_RS_8      0x1F0404B0,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_8__DI1_SERIAL_CLK_8      0x1F0404B0,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_9__ADDR                  0x1F0404B4
+#define LPM_MEM_DI1_DW_GEN_9__EMPTY      0x1F0404B4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_9__FULL      0x1F0404B4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_9__DI1_ACCESS_SIZE_9              0x1F0404B4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_COMPONNENT_SIZE_9      0x1F0404B4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9              0x1F0404B4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_6_9       0x1F0404B4,0x00003000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_5_9       0x1F0404B4,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_4_9       0x1F0404B4,0x00000300
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_3_9       0x1F0404B4,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_2_9       0x1F0404B4,0x00000030
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_1_9       0x1F0404B4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_9__DI1_PT_0_9       0x1F0404B4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_9__ADDR                  0x1F0404B4
+#define LPM_MEM_DI1_DW_GEN_9__EMPTY      0x1F0404B4,0x00000000
+#define LPM_MEM_DI1_DW_GEN_9__FULL      0x1F0404B4,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_PERIOD_9      0x1F0404B4,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_START_PERIOD_9       0x1F0404B4,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_CST_9              0x1F0404B4,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_VALID_BITS_9      0x1F0404B4,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_RS_9      0x1F0404B4,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_9__DI1_SERIAL_CLK_9      0x1F0404B4,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_10__ADDR                  0x1F0404B8
+#define LPM_MEM_DI1_DW_GEN_10__EMPTY      0x1F0404B8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_10__FULL      0x1F0404B8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_10__DI1_ACCESS_SIZE_10      0x1F0404B8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_COMPONNENT_SIZE_10      0x1F0404B8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10      0x1F0404B8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_6_10      0x1F0404B8,0x00003000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_5_10      0x1F0404B8,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_4_10      0x1F0404B8,0x00000300
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_3_10      0x1F0404B8,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_2_10      0x1F0404B8,0x00000030
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_1_10      0x1F0404B8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_10__DI1_PT_0_10      0x1F0404B8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_10__ADDR                  0x1F0404B8
+#define LPM_MEM_DI1_DW_GEN_10__EMPTY      0x1F0404B8,0x00000000
+#define LPM_MEM_DI1_DW_GEN_10__FULL      0x1F0404B8,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_PERIOD_10      0x1F0404B8,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_START_PERIOD_10      0x1F0404B8,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_10__DI1_CST_10      0x1F0404B8,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_10__DI0_SERIAL_VALID_BITS_10              0x1F0404B8,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_RS_10              0x1F0404B8,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_10__DI1_SERIAL_CLK_10       0x1F0404B8,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_11__ADDR                  0x1F0404BC
+#define LPM_MEM_DI1_DW_GEN_11__EMPTY      0x1F0404BC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_11__FULL      0x1F0404BC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_11__DI1_ACCESS_SIZE_11      0x1F0404BC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_COMPONNENT_SIZE_11      0x1F0404BC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11      0x1F0404BC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_6_11      0x1F0404BC,0x00003000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_5_11      0x1F0404BC,0x00000C00
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_4_11      0x1F0404BC,0x00000300
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_3_11      0x1F0404BC,0x000000C0
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_2_11      0x1F0404BC,0x00000030
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_1_11      0x1F0404BC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_11__DI1_PT_0_11      0x1F0404BC,0x00000003
+
+#define LPM_MEM_DI1_DW_GEN_11__ADDR                  0x1F0404BC
+#define LPM_MEM_DI1_DW_GEN_11__EMPTY      0x1F0404BC,0x00000000
+#define LPM_MEM_DI1_DW_GEN_11__FULL      0x1F0404BC,0xffffffff
+#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_PERIOD_11      0x1F0404BC,0xFF000000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_START_PERIOD_11      0x1F0404BC,0x00FF0000
+#define LPM_MEM_DI1_DW_GEN_11__DI1_CST_11      0x1F0404BC,0x0000C000
+#define LPM_MEM_DI1_DW_GEN_11__DI0_SERIAL_VALID_BITS_11              0x1F0404BC,0x000001F0
+#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_RS_11              0x1F0404BC,0x0000000C
+#define LPM_MEM_DI1_DW_GEN_11__DI1_SERIAL_CLK_11       0x1F0404BC,0x00000003
+
+#define LPM_MEM_DI1_DW_SET0_0__ADDR                  0x1F0404C0
+#define LPM_MEM_DI1_DW_SET0_0__EMPTY      0x1F0404C0,0x00000000
+#define LPM_MEM_DI1_DW_SET0_0__FULL      0x1F0404C0,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_DOWN0_0      0x1F0404C0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_0__DI1_DATA_CNT_UP0_0      0x1F0404C0,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_1__ADDR                  0x1F0404C4
+#define LPM_MEM_DI1_DW_SET0_1__EMPTY      0x1F0404C4,0x00000000
+#define LPM_MEM_DI1_DW_SET0_1__FULL      0x1F0404C4,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_DOWN0_1      0x1F0404C4,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_1__DI1_DATA_CNT_UP0_1      0x1F0404C4,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_2__ADDR                  0x1F0404C8
+#define LPM_MEM_DI1_DW_SET0_2__EMPTY      0x1F0404C8,0x00000000
+#define LPM_MEM_DI1_DW_SET0_2__FULL      0x1F0404C8,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_DOWN0_2      0x1F0404C8,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_2__DI1_DATA_CNT_UP0_2      0x1F0404C8,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_3__ADDR                  0x1F0404CC
+#define LPM_MEM_DI1_DW_SET0_3__EMPTY      0x1F0404CC,0x00000000
+#define LPM_MEM_DI1_DW_SET0_3__FULL      0x1F0404CC,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_DOWN0_3      0x1F0404CC,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_3__DI1_DATA_CNT_UP0_3      0x1F0404CC,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_4__ADDR                  0x1F0404D0
+#define LPM_MEM_DI1_DW_SET0_4__EMPTY      0x1F0404D0,0x00000000
+#define LPM_MEM_DI1_DW_SET0_4__FULL      0x1F0404D0,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_DOWN0_4      0x1F0404D0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_4__DI1_DATA_CNT_UP0_4      0x1F0404D0,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_5__ADDR                  0x1F0404D4
+#define LPM_MEM_DI1_DW_SET0_5__EMPTY      0x1F0404D4,0x00000000
+#define LPM_MEM_DI1_DW_SET0_5__FULL      0x1F0404D4,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_DOWN0_5      0x1F0404D4,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_5__DI1_DATA_CNT_UP0_5      0x1F0404D4,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_6__ADDR                  0x1F0404D8
+#define LPM_MEM_DI1_DW_SET0_6__EMPTY      0x1F0404D8,0x00000000
+#define LPM_MEM_DI1_DW_SET0_6__FULL      0x1F0404D8,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_DOWN0_6      0x1F0404D8,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_6__DI1_DATA_CNT_UP0_6      0x1F0404D8,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_7__ADDR                  0x1F0404DC
+#define LPM_MEM_DI1_DW_SET0_7__EMPTY      0x1F0404DC,0x00000000
+#define LPM_MEM_DI1_DW_SET0_7__FULL      0x1F0404DC,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_DOWN0_7      0x1F0404DC,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_7__DI1_DATA_CNT_UP0_7      0x1F0404DC,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_8__ADDR                  0x1F0404E0
+#define LPM_MEM_DI1_DW_SET0_8__EMPTY      0x1F0404E0,0x00000000
+#define LPM_MEM_DI1_DW_SET0_8__FULL      0x1F0404E0,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_DOWN0_8      0x1F0404E0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_8__DI1_DATA_CNT_UP0_8      0x1F0404E0,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_9__ADDR                  0x1F0404E4
+#define LPM_MEM_DI1_DW_SET0_9__EMPTY      0x1F0404E4,0x00000000
+#define LPM_MEM_DI1_DW_SET0_9__FULL      0x1F0404E4,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_DOWN0_9      0x1F0404E4,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_9__DI1_DATA_CNT_UP0_9      0x1F0404E4,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_10__ADDR                  0x1F0404E8
+#define LPM_MEM_DI1_DW_SET0_10__EMPTY      0x1F0404E8,0x00000000
+#define LPM_MEM_DI1_DW_SET0_10__FULL      0x1F0404E8,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_DOWN0_10      0x1F0404E8,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_10__DI1_DATA_CNT_UP0_10      0x1F0404E8,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET0_11__ADDR                  0x1F0404EC
+#define LPM_MEM_DI1_DW_SET0_11__EMPTY      0x1F0404EC,0x00000000
+#define LPM_MEM_DI1_DW_SET0_11__FULL      0x1F0404EC,0xffffffff
+#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_DOWN0_11      0x1F0404EC,0x01FF0000
+#define LPM_MEM_DI1_DW_SET0_11__DI1_DATA_CNT_UP0_11      0x1F0404EC,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_0__ADDR                  0x1F0404F0
+#define LPM_MEM_DI1_DW_SET1_0__EMPTY      0x1F0404F0,0x00000000
+#define LPM_MEM_DI1_DW_SET1_0__FULL      0x1F0404F0,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_DOWN1_0      0x1F0404F0,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_0__DI1_DATA_CNT_UP1_0      0x1F0404F0,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_1__ADDR                  0x1F0404F4
+#define LPM_MEM_DI1_DW_SET1_1__EMPTY      0x1F0404F4,0x00000000
+#define LPM_MEM_DI1_DW_SET1_1__FULL      0x1F0404F4,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_DOWN1_1      0x1F0404F4,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_1__DI1_DATA_CNT_UP1_1      0x1F0404F4,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_2__ADDR                  0x1F0404F8
+#define LPM_MEM_DI1_DW_SET1_2__EMPTY      0x1F0404F8,0x00000000
+#define LPM_MEM_DI1_DW_SET1_2__FULL      0x1F0404F8,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_DOWN1_2      0x1F0404F8,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_2__DI1_DATA_CNT_UP1_2      0x1F0404F8,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_3__ADDR                  0x1F0404FC
+#define LPM_MEM_DI1_DW_SET1_3__EMPTY      0x1F0404FC,0x00000000
+#define LPM_MEM_DI1_DW_SET1_3__FULL      0x1F0404FC,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_DOWN1_3      0x1F0404FC,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_3__DI1_DATA_CNT_UP1_3      0x1F0404FC,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_4__ADDR                  0x1F040500
+#define LPM_MEM_DI1_DW_SET1_4__EMPTY      0x1F040500,0x00000000
+#define LPM_MEM_DI1_DW_SET1_4__FULL      0x1F040500,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_DOWN1_4      0x1F040500,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_4__DI1_DATA_CNT_UP1_4      0x1F040500,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_5__ADDR                  0x1F040504
+#define LPM_MEM_DI1_DW_SET1_5__EMPTY      0x1F040504,0x00000000
+#define LPM_MEM_DI1_DW_SET1_5__FULL      0x1F040504,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_DOWN1_5      0x1F040504,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_5__DI1_DATA_CNT_UP1_5      0x1F040504,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_6__ADDR                  0x1F040508
+#define LPM_MEM_DI1_DW_SET1_6__EMPTY      0x1F040508,0x00000000
+#define LPM_MEM_DI1_DW_SET1_6__FULL      0x1F040508,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_DOWN1_6      0x1F040508,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_6__DI1_DATA_CNT_UP1_6      0x1F040508,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_7__ADDR                  0x1F04050C
+#define LPM_MEM_DI1_DW_SET1_7__EMPTY      0x1F04050C,0x00000000
+#define LPM_MEM_DI1_DW_SET1_7__FULL      0x1F04050C,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_DOWN1_7      0x1F04050C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_7__DI1_DATA_CNT_UP1_7      0x1F04050C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_8__ADDR                  0x1F040510
+#define LPM_MEM_DI1_DW_SET1_8__EMPTY      0x1F040510,0x00000000
+#define LPM_MEM_DI1_DW_SET1_8__FULL      0x1F040510,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_DOWN1_8      0x1F040510,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_8__DI1_DATA_CNT_UP1_8      0x1F040510,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_9__ADDR                  0x1F040514
+#define LPM_MEM_DI1_DW_SET1_9__EMPTY      0x1F040514,0x00000000
+#define LPM_MEM_DI1_DW_SET1_9__FULL      0x1F040514,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_DOWN1_9      0x1F040514,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_9__DI1_DATA_CNT_UP1_9      0x1F040514,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_10__ADDR                  0x1F040518
+#define LPM_MEM_DI1_DW_SET1_10__EMPTY      0x1F040518,0x00000000
+#define LPM_MEM_DI1_DW_SET1_10__FULL      0x1F040518,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_DOWN1_10      0x1F040518,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_10__DI1_DATA_CNT_UP1_10      0x1F040518,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET1_11__ADDR                  0x1F04051C
+#define LPM_MEM_DI1_DW_SET1_11__EMPTY      0x1F04051C,0x00000000
+#define LPM_MEM_DI1_DW_SET1_11__FULL      0x1F04051C,0xffffffff
+#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_DOWN1_11      0x1F04051C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET1_11__DI1_DATA_CNT_UP1_11      0x1F04051C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_0__ADDR                  0x1F040520
+#define LPM_MEM_DI1_DW_SET2_0__EMPTY      0x1F040520,0x00000000
+#define LPM_MEM_DI1_DW_SET2_0__FULL      0x1F040520,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_DOWN2_0      0x1F040520,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_0__DI1_DATA_CNT_UP2_0      0x1F040520,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_1__ADDR                  0x1F040524
+#define LPM_MEM_DI1_DW_SET2_1__EMPTY      0x1F040524,0x00000000
+#define LPM_MEM_DI1_DW_SET2_1__FULL      0x1F040524,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_DOWN2_1      0x1F040524,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_1__DI1_DATA_CNT_UP2_1      0x1F040524,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_2__ADDR                  0x1F040528
+#define LPM_MEM_DI1_DW_SET2_2__EMPTY      0x1F040528,0x00000000
+#define LPM_MEM_DI1_DW_SET2_2__FULL      0x1F040528,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_DOWN2_2      0x1F040528,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_2__DI1_DATA_CNT_UP2_2      0x1F040528,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_3__ADDR                  0x1F04052C
+#define LPM_MEM_DI1_DW_SET2_3__EMPTY      0x1F04052C,0x00000000
+#define LPM_MEM_DI1_DW_SET2_3__FULL      0x1F04052C,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_DOWN2_3      0x1F04052C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_3__DI1_DATA_CNT_UP2_3      0x1F04052C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_4__ADDR                  0x1F040530
+#define LPM_MEM_DI1_DW_SET2_4__EMPTY      0x1F040530,0x00000000
+#define LPM_MEM_DI1_DW_SET2_4__FULL      0x1F040530,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_DOWN2_4      0x1F040530,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_4__DI1_DATA_CNT_UP2_4      0x1F040530,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_5__ADDR                  0x1F040534
+#define LPM_MEM_DI1_DW_SET2_5__EMPTY      0x1F040534,0x00000000
+#define LPM_MEM_DI1_DW_SET2_5__FULL      0x1F040534,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_DOWN2_5      0x1F040534,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_5__DI1_DATA_CNT_UP2_5      0x1F040534,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_6__ADDR                  0x1F040538
+#define LPM_MEM_DI1_DW_SET2_6__EMPTY      0x1F040538,0x00000000
+#define LPM_MEM_DI1_DW_SET2_6__FULL      0x1F040538,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_DOWN2_6      0x1F040538,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_6__DI1_DATA_CNT_UP2_6      0x1F040538,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_7__ADDR                  0x1F04053C
+#define LPM_MEM_DI1_DW_SET2_7__EMPTY      0x1F04053C,0x00000000
+#define LPM_MEM_DI1_DW_SET2_7__FULL      0x1F04053C,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_DOWN2_7      0x1F04053C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_7__DI1_DATA_CNT_UP2_7      0x1F04053C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_8__ADDR                  0x1F040540
+#define LPM_MEM_DI1_DW_SET2_8__EMPTY      0x1F040540,0x00000000
+#define LPM_MEM_DI1_DW_SET2_8__FULL      0x1F040540,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_DOWN2_8      0x1F040540,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_8__DI1_DATA_CNT_UP2_8      0x1F040540,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_9__ADDR                  0x1F040544
+#define LPM_MEM_DI1_DW_SET2_9__EMPTY      0x1F040544,0x00000000
+#define LPM_MEM_DI1_DW_SET2_9__FULL      0x1F040544,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_DOWN2_9      0x1F040544,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_9__DI1_DATA_CNT_UP2_9      0x1F040544,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_10__ADDR                  0x1F040548
+#define LPM_MEM_DI1_DW_SET2_10__EMPTY      0x1F040548,0x00000000
+#define LPM_MEM_DI1_DW_SET2_10__FULL      0x1F040548,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_DOWN2_10      0x1F040548,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_10__DI1_DATA_CNT_UP2_10      0x1F040548,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET2_11__ADDR                  0x1F04054C
+#define LPM_MEM_DI1_DW_SET2_11__EMPTY      0x1F04054C,0x00000000
+#define LPM_MEM_DI1_DW_SET2_11__FULL      0x1F04054C,0xffffffff
+#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_DOWN2_11      0x1F04054C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET2_11__DI1_DATA_CNT_UP2_11      0x1F04054C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_0__ADDR                  0x1F040550
+#define LPM_MEM_DI1_DW_SET3_0__EMPTY      0x1F040550,0x00000000
+#define LPM_MEM_DI1_DW_SET3_0__FULL      0x1F040550,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_DOWN3_0      0x1F040550,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_0__DI1_DATA_CNT_UP3_0      0x1F040550,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_1__ADDR                  0x1F040554
+#define LPM_MEM_DI1_DW_SET3_1__EMPTY      0x1F040554,0x00000000
+#define LPM_MEM_DI1_DW_SET3_1__FULL      0x1F040554,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_DOWN3_1      0x1F040554,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_1__DI1_DATA_CNT_UP3_1      0x1F040554,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_2__ADDR                  0x1F040558
+#define LPM_MEM_DI1_DW_SET3_2__EMPTY      0x1F040558,0x00000000
+#define LPM_MEM_DI1_DW_SET3_2__FULL      0x1F040558,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_DOWN3_2      0x1F040558,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_2__DI1_DATA_CNT_UP3_2      0x1F040558,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_3__ADDR                  0x1F04055C
+#define LPM_MEM_DI1_DW_SET3_3__EMPTY      0x1F04055C,0x00000000
+#define LPM_MEM_DI1_DW_SET3_3__FULL      0x1F04055C,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_DOWN3_3      0x1F04055C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_3__DI1_DATA_CNT_UP3_3      0x1F04055C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_4__ADDR                  0x1F040560
+#define LPM_MEM_DI1_DW_SET3_4__EMPTY      0x1F040560,0x00000000
+#define LPM_MEM_DI1_DW_SET3_4__FULL      0x1F040560,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_DOWN3_4      0x1F040560,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_4__DI1_DATA_CNT_UP3_4      0x1F040560,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_5__ADDR                  0x1F040564
+#define LPM_MEM_DI1_DW_SET3_5__EMPTY      0x1F040564,0x00000000
+#define LPM_MEM_DI1_DW_SET3_5__FULL      0x1F040564,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_DOWN3_5      0x1F040564,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_5__DI1_DATA_CNT_UP3_5      0x1F040564,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_6__ADDR                  0x1F040568
+#define LPM_MEM_DI1_DW_SET3_6__EMPTY      0x1F040568,0x00000000
+#define LPM_MEM_DI1_DW_SET3_6__FULL      0x1F040568,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_DOWN3_6      0x1F040568,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_6__DI1_DATA_CNT_UP3_6      0x1F040568,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_7__ADDR                  0x1F04056C
+#define LPM_MEM_DI1_DW_SET3_7__EMPTY      0x1F04056C,0x00000000
+#define LPM_MEM_DI1_DW_SET3_7__FULL      0x1F04056C,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_DOWN3_7      0x1F04056C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_7__DI1_DATA_CNT_UP3_7      0x1F04056C,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_8__ADDR                  0x1F040570
+#define LPM_MEM_DI1_DW_SET3_8__EMPTY      0x1F040570,0x00000000
+#define LPM_MEM_DI1_DW_SET3_8__FULL      0x1F040570,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_DOWN3_8      0x1F040570,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_8__DI1_DATA_CNT_UP3_8      0x1F040570,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_9__ADDR                  0x1F040574
+#define LPM_MEM_DI1_DW_SET3_9__EMPTY      0x1F040574,0x00000000
+#define LPM_MEM_DI1_DW_SET3_9__FULL      0x1F040574,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_DOWN3_9      0x1F040574,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_9__DI1_DATA_CNT_UP3_9      0x1F040574,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_10__ADDR                  0x1F040578
+#define LPM_MEM_DI1_DW_SET3_10__EMPTY      0x1F040578,0x00000000
+#define LPM_MEM_DI1_DW_SET3_10__FULL      0x1F040578,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_DOWN3_10      0x1F040578,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_10__DI1_DATA_CNT_UP3_10      0x1F040578,0x000001FF
+
+#define LPM_MEM_DI1_DW_SET3_11__ADDR                  0x1F04057C
+#define LPM_MEM_DI1_DW_SET3_11__EMPTY      0x1F04057C,0x00000000
+#define LPM_MEM_DI1_DW_SET3_11__FULL      0x1F04057C,0xffffffff
+#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_DOWN3_11      0x1F04057C,0x01FF0000
+#define LPM_MEM_DI1_DW_SET3_11__DI1_DATA_CNT_UP3_11      0x1F04057C,0x000001FF
+
+#define LPM_MEM_DI1_STP_REP_1__ADDR                  0x1F040580
+#define LPM_MEM_DI1_STP_REP_1__EMPTY      0x1F040580,0x00000000
+#define LPM_MEM_DI1_STP_REP_1__FULL      0x1F040580,0xffffffff
+#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_2       0x1F040580,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_1__DI1_STEP_REPEAT_1       0x1F040580,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_2__ADDR                  0x1F040584
+#define LPM_MEM_DI1_STP_REP_2__EMPTY      0x1F040584,0x00000000
+#define LPM_MEM_DI1_STP_REP_2__FULL      0x1F040584,0xffffffff
+#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_4       0x1F040584,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_2__DI1_STEP_REPEAT_3       0x1F040584,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_3__ADDR                  0x1F040588
+#define LPM_MEM_DI1_STP_REP_3__EMPTY      0x1F040588,0x00000000
+#define LPM_MEM_DI1_STP_REP_3__FULL      0x1F040588,0xffffffff
+#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_6       0x1F040588,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_3__DI1_STEP_REPEAT_5       0x1F040588,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_4__ADDR                  0x1F04058C
+#define LPM_MEM_DI1_STP_REP_4__EMPTY      0x1F04058C,0x00000000
+#define LPM_MEM_DI1_STP_REP_4__FULL      0x1F04058C,0xffffffff
+#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_8       0x1F04058C,0x0FFF0000
+#define LPM_MEM_DI1_STP_REP_4__DI1_STEP_REPEAT_7       0x1F04058C,0x00000FFF
+
+#define LPM_MEM_DI1_STP_REP_9__ADDR                  0x1F040590
+#define LPM_MEM_DI1_STP_REP_9__EMPTY      0x1F040590,0x00000000
+#define LPM_MEM_DI1_STP_REP_9__FULL      0x1F040590,0xffffffff
+#define LPM_MEM_DI1_STP_REP_9__DI1_STEP_REPEAT_9       0x1F040590,0x00000FFF
+
+#define LPM_MEM_DI1_SER_CONF__ADDR                  0x1F040594
+#define LPM_MEM_DI1_SER_CONF__EMPTY      0x1F040594,0x00000000
+#define LPM_MEM_DI1_SER_CONF__FULL      0x1F040594,0xffffffff
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_1       0x1F040594,0xF0000000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_R_0       0x1F040594,0x0F000000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_1       0x1F040594,0x00F00000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LLA_PNTR_RS_W_0       0x1F040594,0x000F0000
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_LATCH      0x1F040594,0x0000FF00
+#define LPM_MEM_DI1_SER_CONF__DI1_LLA_SER_ACCESS       0x1F040594,0x00000020
+#define LPM_MEM_DI1_SER_CONF__DI1_SER_CLK_POLARITY      0x1F040594,0x00000010
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_DATA_POLARITY      0x1F040594,0x00000008
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_RS_POLARITY      0x1F040594,0x00000004
+#define LPM_MEM_DI1_SER_CONF__DI1_SERIAL_CS_POLARITY      0x1F040594,0x00000002
+#define LPM_MEM_DI1_SER_CONF__DI1_WAIT4SERIAL      0x1F040594,0x00000001
+
+#define LPM_MEM_DI1_SSC__ADDR                  0x1F040598
+#define LPM_MEM_DI1_SSC__EMPTY      0x1F040598,0x00000000
+#define LPM_MEM_DI1_SSC__FULL      0x1F040598,0xffffffff
+#define LPM_MEM_DI1_SSC__DI1_PIN17_ERM      0x1F040598,0x00800000
+#define LPM_MEM_DI1_SSC__DI1_PIN16_ERM      0x1F040598,0x00400000
+#define LPM_MEM_DI1_SSC__DI1_PIN15_ERM      0x1F040598,0x00200000
+#define LPM_MEM_DI1_SSC__DI1_PIN14_ERM      0x1F040598,0x00100000
+#define LPM_MEM_DI1_SSC__DI1_PIN13_ERM      0x1F040598,0x00080000
+#define LPM_MEM_DI1_SSC__DI1_PIN12_ERM      0x1F040598,0x00040000
+#define LPM_MEM_DI1_SSC__DI1_PIN11_ERM      0x1F040598,0x00020000
+#define LPM_MEM_DI1_SSC__DI1_CS_ERM      0x1F040598,0x00010000
+#define LPM_MEM_DI1_SSC__DI1_WAIT_ON      0x1F040598,0x00000020
+#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_RD_IN      0x1F040598,0x00000008
+#define LPM_MEM_DI1_SSC__DI1_BYTE_EN_PNTR      0x1F040598,0x00000007
+
+#define LPM_MEM_DI1_POL__ADDR                  0x1F04059C
+#define LPM_MEM_DI1_POL__EMPTY      0x1F04059C,0x00000000
+#define LPM_MEM_DI1_POL__FULL      0x1F04059C,0xffffffff
+#define LPM_MEM_DI1_POL__DI1_WAIT_POLARITY      0x1F04059C,0x04000000
+#define LPM_MEM_DI1_POL__DI1_CS1_BYTE_EN_POLARITY      0x1F04059C,0x02000000
+#define LPM_MEM_DI1_POL__DI1_CS0_BYTE_EN_POLARITY      0x1F04059C,0x01000000
+#define LPM_MEM_DI1_POL__DI1_CS1_DATA_POLARITY      0x1F04059C,0x00800000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_17      0x1F04059C,0x00400000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_16      0x1F04059C,0x00200000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_15      0x1F04059C,0x00100000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_14      0x1F04059C,0x00080000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_13      0x1F04059C,0x00040000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_12      0x1F04059C,0x00020000
+#define LPM_MEM_DI1_POL__DI1_CS1_POLARITY_11      0x1F04059C,0x00010000
+#define LPM_MEM_DI1_POL__DI1_CS0_DATA_POLARITY      0x1F04059C,0x00008000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_17      0x1F04059C,0x00004000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_16      0x1F04059C,0x00002000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_15      0x1F04059C,0x00001000
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_14      0x1F04059C,0x00000800
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_13      0x1F04059C,0x00000400
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_12      0x1F04059C,0x00000200
+#define LPM_MEM_DI1_POL__DI1_CS0_POLARITY_11      0x1F04059C,0x00000100
+#define LPM_MEM_DI1_POL__DI1_DRDY_DATA_POLARITY              0x1F04059C,0x00000080
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_17      0x1F04059C,0x00000040
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_16      0x1F04059C,0x00000020
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_15      0x1F04059C,0x00000010
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_14      0x1F04059C,0x00000008
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_13      0x1F04059C,0x00000004
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_12      0x1F04059C,0x00000002
+#define LPM_MEM_DI1_POL__DI1_DRDY_POLARITY_11      0x1F04059C,0x00000001
+
+#define LPM_MEM_DI1_AW0__ADDR                  0x1F0405A0
+#define LPM_MEM_DI1_AW0__EMPTY      0x1F0405A0,0x00000000
+#define LPM_MEM_DI1_AW0__FULL      0x1F0405A0,0xffffffff
+#define LPM_MEM_DI1_AW0__DI1_AW_TRIG_SEL       0x1F0405A0,0xF0000000
+#define LPM_MEM_DI1_AW0__DI1_AW_HEND      0x1F0405A0,0x0FFF0000
+#define LPM_MEM_DI1_AW0__DI1_AW_HCOUNT_SEL      0x1F0405A0,0x0000F000
+#define LPM_MEM_DI1_AW0__DI1_AW_HSTART      0x1F0405A0,0x00000FFF
+
+#define LPM_MEM_DI1_AW1__ADDR                  0x1F0405A4
+#define LPM_MEM_DI1_AW1__EMPTY      0x1F0405A4,0x00000000
+#define LPM_MEM_DI1_AW1__FULL      0x1F0405A4,0xffffffff
+#define LPM_MEM_DI1_AW1__DI1_AW_VEND      0x1F0405A4,0x0FFF0000
+#define LPM_MEM_DI1_AW1__DI1_AW_VCOUNT_SEL      0x1F0405A4,0x0000F000
+#define LPM_MEM_DI1_AW1__DI1_AW_VSTART      0x1F0405A4,0x00000FFF
+
+#define LPM_MEM_DI1_SCR_CONF__ADDR                  0x1F0405A8
+#define LPM_MEM_DI1_SCR_CONF__EMPTY      0x1F0405A8,0x00000000
+#define LPM_MEM_DI1_SCR_CONF__FULL      0x1F0405A8,0xffffffff
+#define LPM_MEM_DI1_SCR_CONF__DI1_SCREEN_HEIGHT              0x1F0405A8,0x00000FFF
+
+#define LPM_MEM_DMFC_RD_CHAN__ADDR                  0x1F0405AC
+#define LPM_MEM_DMFC_RD_CHAN__EMPTY      0x1F0405AC,0x00000000
+#define LPM_MEM_DMFC_RD_CHAN__FULL      0x1F0405AC,0xffffffff
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_PPW_C       0x1F0405AC,0x03000000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_CLR_0      0x1F0405AC,0x00E00000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_SET_0      0x1F0405AC,0x001C0000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_WM_EN_0      0x1F0405AC,0x00020000
+#define LPM_MEM_DMFC_RD_CHAN__DMFC_BURST_SIZE_0              0x1F0405AC,0x000000C0
+
+#define LPM_MEM_DMFC_WR_CHAN__ADDR                  0x1F0405B0
+#define LPM_MEM_DMFC_WR_CHAN__EMPTY      0x1F0405B0,0x00000000
+#define LPM_MEM_DMFC_WR_CHAN__FULL      0x1F0405B0,0xffffffff
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2C       0x1F0405B0,0xC0000000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2C              0x1F0405B0,0x38000000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2C      0x1F0405B0,0x07000000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1C       0x1F0405B0,0x00C00000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1C              0x1F0405B0,0x00380000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1C      0x1F0405B0,0x00070000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_2              0x1F0405B0,0x0000C000
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_2      0x1F0405B0,0x00003800
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_2      0x1F0405B0,0x00000700
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_BURST_SIZE_1              0x1F0405B0,0x000000C0
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1      0x1F0405B0,0x00000038
+#define LPM_MEM_DMFC_WR_CHAN__DMFC_ST_ADDR_1      0x1F0405B0,0x00000007
+
+#define LPM_MEM_DMFC_WR_CHAN_DEF__ADDR                  0x1F0405B4
+#define LPM_MEM_DMFC_WR_CHAN_DEF__EMPTY              0x1F0405B4,0x00000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__FULL      0x1F0405B4,0xffffffff
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2C       0x1F0405B4,0xE0000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2C       0x1F0405B4,0x1C000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2C              0x1F0405B4,0x02000000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1C       0x1F0405B4,0x00E00000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1C       0x1F0405B4,0x001C0000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1C              0x1F0405B4,0x00020000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_2              0x1F0405B4,0x0000E000
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_2              0x1F0405B4,0x00001C00
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_2      0x1F0405B4,0x00000200
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1              0x1F0405B4,0x000000E0
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1              0x1F0405B4,0x0000001C
+#define LPM_MEM_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1      0x1F0405B4,0x00000002
+
+#define LPM_MEM_DMFC_DP_CHAN__ADDR                  0x1F0405B8
+#define LPM_MEM_DMFC_DP_CHAN__EMPTY      0x1F0405B8,0x00000000
+#define LPM_MEM_DMFC_DP_CHAN__FULL      0x1F0405B8,0xffffffff
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6F       0x1F0405B8,0xC0000000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6F              0x1F0405B8,0x38000000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6F      0x1F0405B8,0x07000000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_6B       0x1F0405B8,0x00C00000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_6B              0x1F0405B8,0x00380000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_6B      0x1F0405B8,0x00070000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F       0x1F0405B8,0x0000C000
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F              0x1F0405B8,0x00003800
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5F      0x1F0405B8,0x00000700
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B       0x1F0405B8,0x000000C0
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B              0x1F0405B8,0x00000038
+#define LPM_MEM_DMFC_DP_CHAN__DMFC_ST_ADDR_5B      0x1F0405B8,0x00000007
+
+#define LPM_MEM_DMFC_DP_CHAN_DEF__ADDR                  0x1F0405BC
+#define LPM_MEM_DMFC_DP_CHAN_DEF__EMPTY              0x1F0405BC,0x00000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__FULL      0x1F0405BC,0xffffffff
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6F       0x1F0405BC,0xE0000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6F       0x1F0405BC,0x1C000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6F              0x1F0405BC,0x02000000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_6B       0x1F0405BC,0x00E00000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_6B       0x1F0405BC,0x001C0000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_6B              0x1F0405BC,0x00020000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F       0x1F0405BC,0x0000E000
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F       0x1F0405BC,0x00001C00
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F              0x1F0405BC,0x00000200
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B       0x1F0405BC,0x000000E0
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B       0x1F0405BC,0x0000001C
+#define LPM_MEM_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B              0x1F0405BC,0x00000002
+
+#define LPM_MEM_DMFC_GENERAL1__ADDR                  0x1F0405C0
+#define LPM_MEM_DMFC_GENERAL1__EMPTY      0x1F0405C0,0x00000000
+#define LPM_MEM_DMFC_GENERAL1__FULL      0x1F0405C0,0xffffffff
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_9      0x1F0405C0,0x01000000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6F      0x1F0405C0,0x00800000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_6B      0x1F0405C0,0x00400000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5F      0x1F0405C0,0x00200000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_5B      0x1F0405C0,0x00100000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_4      0x1F0405C0,0x00080000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_3      0x1F0405C0,0x00040000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_2      0x1F0405C0,0x00020000
+#define LPM_MEM_DMFC_GENERAL1__WAIT4EOT_1      0x1F0405C0,0x00010000
+#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_CLR_9    0x1F0401C0,0x0000E000
+#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_SET_9    0x1F0401C0,0x00001C00
+#define LPM_MEM_DMFC_GENERAL1__DMFC_WM_EN_9     0x1F0401C0,0x00000200
+#define LPM_MEM_DMFC_GENERAL1__DMFC_BURST_SIZE_9 0x1F0401C0,0x00000060
+#define LPM_MEM_DMFC_GENERAL1__DMFC_DCDP_SYNC_PR 0x1F0401C0,0x00000003
+
+#define LPM_MEM_DMFC_GENERAL2__ADDR                  0x1F0405C4
+#define LPM_MEM_DMFC_GENERAL2__EMPTY      0x1F0405C4,0x00000000
+#define LPM_MEM_DMFC_GENERAL2__FULL      0x1F0405C4,0xffffffff
+#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_HEIGHT_RD      0x1F0405C4,0x1FFF0000
+#define LPM_MEM_DMFC_GENERAL2__DMFC_FRAME_WIDTH_RD      0x1F0405C4,0x00001FFF
+
+#define LPM_MEM_DMFC_IC_CTRL__ADDR                  0x1F0405C8
+#define LPM_MEM_DMFC_IC_CTRL__EMPTY      0x1F0405C8,0x00000000
+#define LPM_MEM_DMFC_IC_CTRL__FULL      0x1F0405C8,0xffffffff
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_HEIGHT_RD      0x1F0405C8,0xFFF80000
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_FRAME_WIDTH_RD      0x1F0405C8,0x0007FFC0
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_PPW_C      0x1F0405C8,0x00000030
+#define LPM_MEM_DMFC_IC_CTRL__DMFC_IC_IN_PORT    0x1F0405C8,0x00000007
+
+#define LPM_MEM_DC_READ_CH_CONF__ADDR                  0x1F0405CC
+#define LPM_MEM_DC_READ_CH_CONF__EMPTY      0x1F0405CC,0x00000000
+#define LPM_MEM_DC_READ_CH_CONF__FULL      0x1F0405CC,0xffffffff
+#define LPM_MEM_DC_READ_CH_CONF__TIME_OUT_VALUE              0x1F0405CC,0xFFFF0000
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_3       0x1F0405CC,0x00000800
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_2       0x1F0405CC,0x00000400
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_1       0x1F0405CC,0x00000200
+#define LPM_MEM_DC_READ_CH_CONF__CS_ID_0       0x1F0405CC,0x00000100
+#define LPM_MEM_DC_READ_CH_CONF__CHAN_MASK_DEFAULT_0      0x1F0405CC,0x00000040
+#define LPM_MEM_DC_READ_CH_CONF__W_SIZE_0      0x1F0405CC,0x00000030
+#define LPM_MEM_DC_READ_CH_CONF__PROG_DISP_ID_0              0x1F0405CC,0x0000000C
+#define LPM_MEM_DC_READ_CH_CONF__PROG_DI_ID_0      0x1F0405CC,0x00000002
+#define LPM_MEM_DC_READ_CH_CONF__RD_CHANNEL_EN      0x1F0405CC,0x00000001
+
+#define LPM_MEM_DC_READ_CH_ADDR__ADDR                  0x1F0405D0
+#define LPM_MEM_DC_READ_CH_ADDR__EMPTY      0x1F0405D0,0x00000000
+#define LPM_MEM_DC_READ_CH_ADDR__FULL      0x1F0405D0,0xffffffff
+#define LPM_MEM_DC_READ_CH_ADDR__ST_ADDR_0      0x1F0405D0,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_0__ADDR                  0x1F0405D4
+#define LPM_MEM_DC_RL0_CH_0__EMPTY      0x1F0405D4,0x00000000
+#define LPM_MEM_DC_RL0_CH_0__FULL      0x1F0405D4,0xffffffff
+#define LPM_MEM_DC_RL0_CH_0__COD_NL_START_CHAN_0       0x1F0405D4,0xFF000000
+#define LPM_MEM_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0      0x1F0405D4,0x000F0000
+#define LPM_MEM_DC_RL0_CH_0__COD_NF_START_CHAN_0       0x1F0405D4,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0      0x1F0405D4,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_0__ADDR                  0x1F0405D8
+#define LPM_MEM_DC_RL1_CH_0__EMPTY      0x1F0405D8,0x00000000
+#define LPM_MEM_DC_RL1_CH_0__FULL      0x1F0405D8,0xffffffff
+#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0      0x1F0405D8,0xFF000000
+#define LPM_MEM_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0              0x1F0405D8,0x000F0000
+#define LPM_MEM_DC_RL1_CH_0__COD_EOF_START_CHAN_0      0x1F0405D8,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0      0x1F0405D8,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_0__ADDR                  0x1F0405DC
+#define LPM_MEM_DC_RL2_CH_0__EMPTY      0x1F0405DC,0x00000000
+#define LPM_MEM_DC_RL2_CH_0__FULL      0x1F0405DC,0xffffffff
+#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0      0x1F0405DC,0xFF000000
+#define LPM_MEM_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0       0x1F0405DC,0x000F0000
+#define LPM_MEM_DC_RL2_CH_0__COD_EOL_START_CHAN_0      0x1F0405DC,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0      0x1F0405DC,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_0__ADDR                  0x1F0405E0
+#define LPM_MEM_DC_RL3_CH_0__EMPTY      0x1F0405E0,0x00000000
+#define LPM_MEM_DC_RL3_CH_0__FULL      0x1F0405E0,0xffffffff
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0      0x1F0405E0,0xFF000000
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0      0x1F0405E0,0x000F0000
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0      0x1F0405E0,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0      0x1F0405E0,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_0__ADDR                  0x1F0405E4
+#define LPM_MEM_DC_RL4_CH_0__EMPTY      0x1F0405E4,0x00000000
+#define LPM_MEM_DC_RL4_CH_0__FULL      0x1F0405E4,0xffffffff
+#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0      0x1F0405E4,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0      0x1F0405E4,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF_1__ADDR                  0x1F0405E8
+#define LPM_MEM_DC_WR_CH_CONF_1__EMPTY      0x1F0405E8,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_1__FULL      0x1F0405E8,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_START_TIME_1      0x1F0405E8,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_1__FIELD_MODE_1      0x1F0405E8,0x00000200
+#define LPM_MEM_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1      0x1F0405E8,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1       0x1F0405E8,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DISP_ID_1              0x1F0405E8,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_1__PROG_DI_ID_1      0x1F0405E8,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_1__W_SIZE_1      0x1F0405E8,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_1__ADDR                  0x1F0405EC
+#define LPM_MEM_DC_WR_CH_ADDR_1__EMPTY      0x1F0405EC,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_1__FULL      0x1F0405EC,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_1__ST_ADDR_1      0x1F0405EC,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_1__ADDR                  0x1F0405F0
+#define LPM_MEM_DC_RL0_CH_1__EMPTY      0x1F0405F0,0x00000000
+#define LPM_MEM_DC_RL0_CH_1__FULL      0x1F0405F0,0xffffffff
+#define LPM_MEM_DC_RL0_CH_1__COD_NL_START_CHAN_1       0x1F0405F0,0xFF000000
+#define LPM_MEM_DC_RL0_CH_1__COD_NL_PRIORITY_CHAN_1      0x1F0405F0,0x000F0000
+#define LPM_MEM_DC_RL0_CH_1__COD_NF_START_CHAN_1       0x1F0405F0,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_1__COD_NF_PRIORITY_CHAN_1      0x1F0405F0,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_1__ADDR                  0x1F0405F4
+#define LPM_MEM_DC_RL1_CH_1__EMPTY      0x1F0405F4,0x00000000
+#define LPM_MEM_DC_RL1_CH_1__FULL      0x1F0405F4,0xffffffff
+#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_START_CHAN_1      0x1F0405F4,0xFF000000
+#define LPM_MEM_DC_RL1_CH_1__COD_NFIELD_PRIORITY_CHAN_1              0x1F0405F4,0x000F0000
+#define LPM_MEM_DC_RL1_CH_1__COD_EOF_START_CHAN_1      0x1F0405F4,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_1__COD_EOF_PRIORITY_CHAN_1      0x1F0405F4,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_1__ADDR                  0x1F0405F8
+#define LPM_MEM_DC_RL2_CH_1__EMPTY      0x1F0405F8,0x00000000
+#define LPM_MEM_DC_RL2_CH_1__FULL      0x1F0405F8,0xffffffff
+#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_START_CHAN_1      0x1F0405F8,0xFF000000
+#define LPM_MEM_DC_RL2_CH_1__COD_EOFIELD_PRIORITY_CHAN_1       0x1F0405F8,0x000F0000
+#define LPM_MEM_DC_RL2_CH_1__COD_EOL_START_CHAN_1      0x1F0405F8,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_1__COD_EOL_PRIORITY_CHAN_1      0x1F0405F8,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_1__ADDR                  0x1F0405FC
+#define LPM_MEM_DC_RL3_CH_1__EMPTY      0x1F0405FC,0x00000000
+#define LPM_MEM_DC_RL3_CH_1__FULL      0x1F0405FC,0xffffffff
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_START_CHAN_1      0x1F0405FC,0xFF000000
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_CHAN_PRIORITY_CHAN_1      0x1F0405FC,0x000F0000
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_START_CHAN_1      0x1F0405FC,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_1__COD_NEW_ADDR_PRIORITY_CHAN_1      0x1F0405FC,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_1__ADDR                  0x1F040600
+#define LPM_MEM_DC_RL4_CH_1__EMPTY      0x1F040600,0x00000000
+#define LPM_MEM_DC_RL4_CH_1__FULL      0x1F040600,0xffffffff
+#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_START_CHAN_1      0x1F040600,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_1__COD_NEW_DATA_PRIORITY_CHAN_1      0x1F040600,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF_2__ADDR                  0x1F040604
+#define LPM_MEM_DC_WR_CH_CONF_2__EMPTY      0x1F040604,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_2__FULL      0x1F040604,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_START_TIME_2      0x1F040604,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_2__CHAN_MASK_DEFAULT_2      0x1F040604,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_CHAN_TYP_2       0x1F040604,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DISP_ID_2              0x1F040604,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_2__PROG_DI_ID_2      0x1F040604,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_2__W_SIZE_2      0x1F040604,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_2__ADDR                  0x1F040608
+#define LPM_MEM_DC_WR_CH_ADDR_2__EMPTY      0x1F040608,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_2__FULL      0x1F040608,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_2__ST_ADDR_2      0x1F040608,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_2__ADDR                  0x1F04060C
+#define LPM_MEM_DC_RL0_CH_2__EMPTY      0x1F04060C,0x00000000
+#define LPM_MEM_DC_RL0_CH_2__FULL      0x1F04060C,0xffffffff
+#define LPM_MEM_DC_RL0_CH_2__COD_NL_START_CHAN_2       0x1F04060C,0xFF000000
+#define LPM_MEM_DC_RL0_CH_2__COD_NL_PRIORITY_CHAN_2      0x1F04060C,0x000F0000
+#define LPM_MEM_DC_RL0_CH_2__COD_NF_START_CHAN_2       0x1F04060C,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_2__COD_NF_PRIORITY_CHAN_2      0x1F04060C,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_2__ADDR                  0x1F040610
+#define LPM_MEM_DC_RL1_CH_2__EMPTY      0x1F040610,0x00000000
+#define LPM_MEM_DC_RL1_CH_2__FULL      0x1F040610,0xffffffff
+#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_START_CHAN_2      0x1F040610,0xFF000000
+#define LPM_MEM_DC_RL1_CH_2__COD_NFIELD_PRIORITY_CHAN_2              0x1F040610,0x000F0000
+#define LPM_MEM_DC_RL1_CH_2__COD_EOF_START_CHAN_2      0x1F040610,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_2__COD_EOF_PRIORITY_CHAN_2      0x1F040610,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_2__ADDR                  0x1F040614
+#define LPM_MEM_DC_RL2_CH_2__EMPTY      0x1F040614,0x00000000
+#define LPM_MEM_DC_RL2_CH_2__FULL      0x1F040614,0xffffffff
+#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_START_CHAN_2      0x1F040614,0xFF000000
+#define LPM_MEM_DC_RL2_CH_2__COD_EOFIELD_PRIORITY_CHAN_2       0x1F040614,0x000F0000
+#define LPM_MEM_DC_RL2_CH_2__COD_EOL_START_CHAN_2      0x1F040614,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_2__COD_EOL_PRIORITY_CHAN_2      0x1F040614,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_2__ADDR                  0x1F040618
+#define LPM_MEM_DC_RL3_CH_2__EMPTY      0x1F040618,0x00000000
+#define LPM_MEM_DC_RL3_CH_2__FULL      0x1F040618,0xffffffff
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_START_CHAN_2      0x1F040618,0xFF000000
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_CHAN_PRIORITY_CHAN_2      0x1F040618,0x000F0000
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_START_CHAN_2      0x1F040618,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_2__COD_NEW_ADDR_PRIORITY_CHAN_2      0x1F040618,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_2__ADDR                  0x1F04061C
+#define LPM_MEM_DC_RL4_CH_2__EMPTY      0x1F04061C,0x00000000
+#define LPM_MEM_DC_RL4_CH_2__FULL      0x1F04061C,0xffffffff
+#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_START_CHAN_2      0x1F04061C,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_2__COD_NEW_DATA_PRIORITY_CHAN_2      0x1F04061C,0x0000000F
+
+#define LPM_MEM_DC_CMD_CH_CONF_3__ADDR                  0x1F040620
+#define LPM_MEM_DC_CMD_CH_CONF_3__EMPTY              0x1F040620,0x00000000
+#define LPM_MEM_DC_CMD_CH_CONF_3__FULL      0x1F040620,0xffffffff
+#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS1_3      0x1F040620,0xFF000000
+#define LPM_MEM_DC_CMD_CH_CONF_3__COD_CMND_START_CHAN_RS0_3      0x1F040620,0x0000FF00
+#define LPM_MEM_DC_CMD_CH_CONF_3__W_SIZE_3      0x1F040620,0x00000003
+
+#define LPM_MEM_DC_CMD_CH_CONF_4__ADDR                  0x1F040624
+#define LPM_MEM_DC_CMD_CH_CONF_4__EMPTY              0x1F040624,0x00000000
+#define LPM_MEM_DC_CMD_CH_CONF_4__FULL      0x1F040624,0xffffffff
+#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS1_4      0x1F040624,0xFF000000
+#define LPM_MEM_DC_CMD_CH_CONF_4__COD_CMND_START_CHAN_RS0_4      0x1F040624,0x0000FF00
+#define LPM_MEM_DC_CMD_CH_CONF_4__W_SIZE_4      0x1F040624,0x00000003
+
+#define LPM_MEM_DC_WR_CH_CONF_5__ADDR                  0x1F040628
+#define LPM_MEM_DC_WR_CH_CONF_5__EMPTY      0x1F040628,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_5__FULL      0x1F040628,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_START_TIME_5      0x1F040628,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_5__FIELD_MODE_5      0x1F040628,0x00000200
+#define LPM_MEM_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5      0x1F040628,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5       0x1F040628,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DISP_ID_5              0x1F040628,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_5__PROG_DI_ID_5      0x1F040628,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_5__W_SIZE_5      0x1F040628,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_5__ADDR                  0x1F04062C
+#define LPM_MEM_DC_WR_CH_ADDR_5__EMPTY      0x1F04062C,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_5__FULL      0x1F04062C,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_5__ST_ADDR_5      0x1F04062C,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_5__ADDR                  0x1F040630
+#define LPM_MEM_DC_RL0_CH_5__EMPTY      0x1F040630,0x00000000
+#define LPM_MEM_DC_RL0_CH_5__FULL      0x1F040630,0xffffffff
+#define LPM_MEM_DC_RL0_CH_5__COD_NL_START_CHAN_5       0x1F040630,0xFF000000
+#define LPM_MEM_DC_RL0_CH_5__COD_NL_PRIORITY_CHAN_5      0x1F040630,0x000F0000
+#define LPM_MEM_DC_RL0_CH_5__COD_NF_START_CHAN_5       0x1F040630,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_5__COD_NF_PRIORITY_CHAN_5      0x1F040630,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_5__ADDR                  0x1F040634
+#define LPM_MEM_DC_RL1_CH_5__EMPTY      0x1F040634,0x00000000
+#define LPM_MEM_DC_RL1_CH_5__FULL      0x1F040634,0xffffffff
+#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_START_CHAN_5      0x1F040634,0xFF000000
+#define LPM_MEM_DC_RL1_CH_5__COD_NFIELD_PRIORITY_CHAN_5              0x1F040634,0x000F0000
+#define LPM_MEM_DC_RL1_CH_5__COD_EOF_START_CHAN_5      0x1F040634,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_5__COD_EOF_PRIORITY_CHAN_5      0x1F040634,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_5__ADDR                  0x1F040638
+#define LPM_MEM_DC_RL2_CH_5__EMPTY      0x1F040638,0x00000000
+#define LPM_MEM_DC_RL2_CH_5__FULL      0x1F040638,0xffffffff
+#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_START_CHAN_5      0x1F040638,0xFF000000
+#define LPM_MEM_DC_RL2_CH_5__COD_EOFIELD_PRIORITY_CHAN_5       0x1F040638,0x000F0000
+#define LPM_MEM_DC_RL2_CH_5__COD_EOL_START_CHAN_5      0x1F040638,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_5__COD_EOL_PRIORITY_CHAN_5      0x1F040638,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_5__ADDR                  0x1F04063C
+#define LPM_MEM_DC_RL3_CH_5__EMPTY      0x1F04063C,0x00000000
+#define LPM_MEM_DC_RL3_CH_5__FULL      0x1F04063C,0xffffffff
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_START_CHAN_5      0x1F04063C,0xFF000000
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_CHAN_PRIORITY_CHAN_5      0x1F04063C,0x000F0000
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_START_CHAN_5      0x1F04063C,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_5__COD_NEW_ADDR_PRIORITY_CHAN_5      0x1F04063C,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_5__ADDR                  0x1F040640
+#define LPM_MEM_DC_RL4_CH_5__EMPTY      0x1F040640,0x00000000
+#define LPM_MEM_DC_RL4_CH_5__FULL      0x1F040640,0xffffffff
+#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_START_CHAN_5      0x1F040640,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_5__COD_NEW_DATA_PRIORITY_CHAN_5      0x1F040640,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF_6__ADDR                  0x1F040644
+#define LPM_MEM_DC_WR_CH_CONF_6__EMPTY      0x1F040644,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF_6__FULL      0x1F040644,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_START_TIME_6      0x1F040644,0x07FF0000
+#define LPM_MEM_DC_WR_CH_CONF_6__CHAN_MASK_DEFAULT_6      0x1F040644,0x00000100
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_CHAN_TYP_6       0x1F040644,0x000000E0
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DISP_ID_6              0x1F040644,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF_6__PROG_DI_ID_6      0x1F040644,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF_6__W_SIZE_6      0x1F040644,0x00000003
+
+#define LPM_MEM_DC_WR_CH_ADDR_6__ADDR                  0x1F040648
+#define LPM_MEM_DC_WR_CH_ADDR_6__EMPTY      0x1F040648,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_6__FULL      0x1F040648,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_6__ST_ADDR_6      0x1F040648,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL0_CH_6__ADDR                  0x1F04064C
+#define LPM_MEM_DC_RL0_CH_6__EMPTY      0x1F04064C,0x00000000
+#define LPM_MEM_DC_RL0_CH_6__FULL      0x1F04064C,0xffffffff
+#define LPM_MEM_DC_RL0_CH_6__COD_NL_START_CHAN_6       0x1F04064C,0xFF000000
+#define LPM_MEM_DC_RL0_CH_6__COD_NL_PRIORITY_CHAN_6      0x1F04064C,0x000F0000
+#define LPM_MEM_DC_RL0_CH_6__COD_NF_START_CHAN_6       0x1F04064C,0x0000FF00
+#define LPM_MEM_DC_RL0_CH_6__COD_NF_PRIORITY_CHAN_6      0x1F04064C,0x0000000F
+
+#define LPM_MEM_DC_RL1_CH_6__ADDR                  0x1F040650
+#define LPM_MEM_DC_RL1_CH_6__EMPTY      0x1F040650,0x00000000
+#define LPM_MEM_DC_RL1_CH_6__FULL      0x1F040650,0xffffffff
+#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_START_CHAN_6      0x1F040650,0xFF000000
+#define LPM_MEM_DC_RL1_CH_6__COD_NFIELD_PRIORITY_CHAN_6              0x1F040650,0x000F0000
+#define LPM_MEM_DC_RL1_CH_6__COD_EOF_START_CHAN_6      0x1F040650,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_6__COD_EOF_PRIORITY_CHAN_6      0x1F040650,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_6__ADDR                  0x1F040654
+#define LPM_MEM_DC_RL2_CH_6__EMPTY      0x1F040654,0x00000000
+#define LPM_MEM_DC_RL2_CH_6__FULL      0x1F040654,0xffffffff
+#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_START_CHAN_6      0x1F040654,0xFF000000
+#define LPM_MEM_DC_RL2_CH_6__COD_EOFIELD_PRIORITY_CHAN_6       0x1F040654,0x000F0000
+#define LPM_MEM_DC_RL2_CH_6__COD_EOL_START_CHAN_6      0x1F040654,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_6__COD_EOL_PRIORITY_CHAN_6      0x1F040654,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_6__ADDR                  0x1F040658
+#define LPM_MEM_DC_RL3_CH_6__EMPTY      0x1F040658,0x00000000
+#define LPM_MEM_DC_RL3_CH_6__FULL      0x1F040658,0xffffffff
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_START_CHAN_6      0x1F040658,0xFF000000
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_CHAN_PRIORITY_CHAN_6      0x1F040658,0x000F0000
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_START_CHAN_6      0x1F040658,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_6__COD_NEW_ADDR_PRIORITY_CHAN_6      0x1F040658,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_6__ADDR                  0x1F04065C
+#define LPM_MEM_DC_RL4_CH_6__EMPTY      0x1F04065C,0x00000000
+#define LPM_MEM_DC_RL4_CH_6__FULL      0x1F04065C,0xffffffff
+#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_START_CHAN_6      0x1F04065C,0x0000FF00
+#define LPM_MEM_DC_RL4_CH_6__COD_NEW_DATA_PRIORITY_CHAN_6      0x1F04065C,0x0000000F
+
+#define LPM_MEM_DC_WR_CH_CONF1_8__ADDR                  0x1F040660
+#define LPM_MEM_DC_WR_CH_CONF1_8__EMPTY              0x1F040660,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF1_8__FULL      0x1F040660,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF1_8__MCU_DISP_ID_8              0x1F040660,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF1_8__CHAN_MASK_DEFAULT_8      0x1F040660,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF1_8__W_SIZE_8      0x1F040660,0x00000003
+
+#define LPM_MEM_DC_WR_CH_CONF2_8__ADDR                  0x1F040664
+#define LPM_MEM_DC_WR_CH_CONF2_8__EMPTY              0x1F040664,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF2_8__FULL      0x1F040664,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF2_8__NEW_ADDR_SPACE_SA_8      0x1F040664,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL1_CH_8__ADDR                  0x1F040668
+#define LPM_MEM_DC_RL1_CH_8__EMPTY      0x1F040668,0x00000000
+#define LPM_MEM_DC_RL1_CH_8__FULL      0x1F040668,0xffffffff
+#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_1      0x1F040668,0xFF000000
+#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_START_CHAN_W_8_0      0x1F040668,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_8__COD_NEW_ADDR_PRIORITY_CHAN_8      0x1F040668,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_8__ADDR                  0x1F04066C
+#define LPM_MEM_DC_RL2_CH_8__EMPTY      0x1F04066C,0x00000000
+#define LPM_MEM_DC_RL2_CH_8__FULL      0x1F04066C,0xffffffff
+#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_1      0x1F04066C,0xFF000000
+#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_START_CHAN_W_8_0      0x1F04066C,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_8__COD_NEW_CHAN_PRIORITY_CHAN_8      0x1F04066C,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_8__ADDR                  0x1F040670
+#define LPM_MEM_DC_RL3_CH_8__EMPTY      0x1F040670,0x00000000
+#define LPM_MEM_DC_RL3_CH_8__FULL      0x1F040670,0xffffffff
+#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1      0x1F040670,0xFF000000
+#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0      0x1F040670,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8      0x1F040670,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_8__ADDR                  0x1F040674
+#define LPM_MEM_DC_RL4_CH_8__EMPTY      0x1F040674,0x00000000
+#define LPM_MEM_DC_RL4_CH_8__FULL      0x1F040674,0xffffffff
+#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_1      0x1F040674,0xFF000000
+#define LPM_MEM_DC_RL4_CH_8__COD_NEW_ADDR_START_CHAN_R_8_0      0x1F040674,0x0000FF00
+
+#define LPM_MEM_DC_RL5_CH_8__ADDR                  0x1F040678
+#define LPM_MEM_DC_RL5_CH_8__EMPTY      0x1F040678,0x00000000
+#define LPM_MEM_DC_RL5_CH_8__FULL      0x1F040678,0xffffffff
+#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_1      0x1F040678,0xFF000000
+#define LPM_MEM_DC_RL5_CH_8__COD_NEW_CHAN_START_CHAN_R_8_0      0x1F040678,0x0000FF00
+
+#define LPM_MEM_DC_RL6_CH_8__ADDR                  0x1F04067C
+#define LPM_MEM_DC_RL6_CH_8__EMPTY      0x1F04067C,0x00000000
+#define LPM_MEM_DC_RL6_CH_8__FULL      0x1F04067C,0xffffffff
+#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_1      0x1F04067C,0xFF000000
+#define LPM_MEM_DC_RL6_CH_8__COD_NEW_DATA_START_CHAN_R_8_0      0x1F04067C,0x0000FF00
+
+#define LPM_MEM_DC_WR_CH_CONF1_9__ADDR                  0x1F040680
+#define LPM_MEM_DC_WR_CH_CONF1_9__EMPTY              0x1F040680,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF1_9__FULL      0x1F040680,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF1_9__MCU_DISP_ID_9              0x1F040680,0x00000018
+#define LPM_MEM_DC_WR_CH_CONF1_9__CHAN_MASK_DEFAULT_9      0x1F040680,0x00000004
+#define LPM_MEM_DC_WR_CH_CONF1_9__W_SIZE_9      0x1F040680,0x00000003
+
+#define LPM_MEM_DC_WR_CH_CONF2_9__ADDR                  0x1F040684
+#define LPM_MEM_DC_WR_CH_CONF2_9__EMPTY              0x1F040684,0x00000000
+#define LPM_MEM_DC_WR_CH_CONF2_9__FULL      0x1F040684,0xffffffff
+#define LPM_MEM_DC_WR_CH_CONF2_9__NEW_ADDR_SPACE_SA_9      0x1F040684,0x1FFFFFFF
+
+#define LPM_MEM_DC_RL1_CH_9__ADDR                  0x1F040688
+#define LPM_MEM_DC_RL1_CH_9__EMPTY      0x1F040688,0x00000000
+#define LPM_MEM_DC_RL1_CH_9__FULL      0x1F040688,0xffffffff
+#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_1      0x1F040688,0xFF000000
+#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_START_CHAN_W_9_0      0x1F040688,0x0000FF00
+#define LPM_MEM_DC_RL1_CH_9__COD_NEW_ADDR_PRIORITY_CHAN_9      0x1F040688,0x0000000F
+
+#define LPM_MEM_DC_RL2_CH_9__ADDR                  0x1F04068C
+#define LPM_MEM_DC_RL2_CH_9__EMPTY      0x1F04068C,0x00000000
+#define LPM_MEM_DC_RL2_CH_9__FULL      0x1F04068C,0xffffffff
+#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_1      0x1F04068C,0xFF000000
+#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_START_CHAN_W_9_0      0x1F04068C,0x0000FF00
+#define LPM_MEM_DC_RL2_CH_9__COD_NEW_CHAN_PRIORITY_CHAN_9      0x1F04068C,0x0000000F
+
+#define LPM_MEM_DC_RL3_CH_9__ADDR                  0x1F040690
+#define LPM_MEM_DC_RL3_CH_9__EMPTY      0x1F040690,0x00000000
+#define LPM_MEM_DC_RL3_CH_9__FULL      0x1F040690,0xffffffff
+#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_1      0x1F040690,0xFF000000
+#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_START_CHAN_W_9_0      0x1F040690,0x0000FF00
+#define LPM_MEM_DC_RL3_CH_9__COD_NEW_DATA_PRIORITY_CHAN_9      0x1F040690,0x0000000F
+
+#define LPM_MEM_DC_RL4_CH_9__ADDR                  0x1F040694
+#define LPM_MEM_DC_RL4_CH_9__EMPTY      0x1F040694,0x00000000
+#define LPM_MEM_DC_RL4_CH_9__FULL      0x1F040694,0xffffffff
+#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_1      0x1F040694,0xFF000000
+#define LPM_MEM_DC_RL4_CH_9__COD_NEW_ADDR_START_CHAN_R_9_0      0x1F040694,0x0000FF00
+
+#define LPM_MEM_DC_RL5_CH_9__ADDR                  0x1F040698
+#define LPM_MEM_DC_RL5_CH_9__EMPTY      0x1F040698,0x00000000
+#define LPM_MEM_DC_RL5_CH_9__FULL      0x1F040698,0xffffffff
+#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_1      0x1F040698,0xFF000000
+#define LPM_MEM_DC_RL5_CH_9__COD_NEW_CHAN_START_CHAN_R_9_0      0x1F040698,0x0000FF00
+
+#define LPM_MEM_DC_RL6_CH_9__ADDR                  0x1F04069C
+#define LPM_MEM_DC_RL6_CH_9__EMPTY      0x1F04069C,0x00000000
+#define LPM_MEM_DC_RL6_CH_9__FULL      0x1F04069C,0xffffffff
+#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_1      0x1F04069C,0xFF000000
+#define LPM_MEM_DC_RL6_CH_9__COD_NEW_DATA_START_CHAN_R_9_0      0x1F04069C,0x0000FF00
+
+#define LPM_MEM_DC_GEN__ADDR                  0x1F0406A0
+#define LPM_MEM_DC_GEN__EMPTY      0x1F0406A0,0x00000000
+#define LPM_MEM_DC_GEN__FULL      0x1F0406A0,0xffffffff
+#define LPM_MEM_DC_GEN__DC_BK_EN       0x1F0406A0,0x01000000
+#define LPM_MEM_DC_GEN__DC_BKDIV       0x1F0406A0,0x00FF0000
+#define LPM_MEM_DC_GEN__DC_CH5_TYPE      0x1F0406A0,0x00000100
+#define LPM_MEM_DC_GEN__SYNC_PRIORITY_1              0x1F0406A0,0x00000080
+#define LPM_MEM_DC_GEN__SYNC_PRIORITY_5              0x1F0406A0,0x00000040
+#define LPM_MEM_DC_GEN__MASK4CHAN_5      0x1F0406A0,0x00000020
+#define LPM_MEM_DC_GEN__MASK_EN              0x1F0406A0,0x00000010
+#define LPM_MEM_DC_GEN__SYNC_1_6       0x1F0406A0,0x00000006
+
+#define LPM_MEM_DC_DISP_CONF1_0__ADDR               0x1F0406A4
+#define LPM_MEM_DC_DISP_CONF1_0__EMPTY              0x1F0406A4,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_0__FULL               0x1F0406A4,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_0__DISP_RD_VALUE_PTR_0 0x1F0406A4,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_0__MCU_ACC_LB_MASK_0   0x1F0406A4,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_0__ADDR_BE_L_INC_0     0x1F0406A4,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_0__ADDR_INCREMENT_0    0x1F0406A4,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_0__DISP_TYP_0         0x1F0406A4,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF1_1__ADDR               0x1F0406A8
+#define LPM_MEM_DC_DISP_CONF1_1__EMPTY              0x1F0406A8,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_1__FULL               0x1F0406A8,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_1__DISP_RD_VALUE_PTR_1 0x1F0406A8,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_1__MCU_ACC_LB_MASK_1   0x1F0406A8,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_1__ADDR_BE_L_INC_1     0x1F0406A8,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_1__ADDR_INCREMENT_1    0x1F0406A8,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_1__DISP_TYP_1         0x1F0406A8,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF1_2__ADDR               0x1F0406AC
+#define LPM_MEM_DC_DISP_CONF1_2__EMPTY              0x1F0406AC,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_2__FULL               0x1F0406AC,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_2__DISP_RD_VALUE_PTR_2 0x1F0406AC,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_2__MCU_ACC_LB_MASK_2   0x1F0406AC,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_2__ADDR_BE_L_INC_2     0x1F0406AC,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_2__ADDR_INCREMENT_2    0x1F0406AC,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_2__DISP_TYP_2         0x1F0406AC,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF1_3__ADDR               0x1F0406B0
+#define LPM_MEM_DC_DISP_CONF1_3__EMPTY              0x1F0406B0,0x00000000
+#define LPM_MEM_DC_DISP_CONF1_3__FULL               0x1F0406B0,0xffffffff
+#define LPM_MEM_DC_DISP_CONF1_3__DISP_RD_VALUE_PTR_3 0x1F0406B0,0x00000080
+#define LPM_MEM_DC_DISP_CONF1_3__MCU_ACC_LB_MASK_3   0x1F0406B0,0x00000040
+#define LPM_MEM_DC_DISP_CONF1_3__ADDR_BE_L_INC_3     0x1F0406B0,0x00000030
+#define LPM_MEM_DC_DISP_CONF1_3__ADDR_INCREMENT_3    0x1F0406B0,0x0000000C
+#define LPM_MEM_DC_DISP_CONF1_3__DISP_TYP_3         0x1F0406B0,0x00000003
+
+#define LPM_MEM_DC_DISP_CONF2_0__ADDR                  0x1F0406B4
+#define LPM_MEM_DC_DISP_CONF2_0__EMPTY      0x1F0406B4,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_0__FULL      0x1F0406B4,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_0__SL_0      0x1F0406B4,0x1FFFFFFF
+
+#define LPM_MEM_DC_DISP_CONF2_1__ADDR                  0x1F0406B8
+#define LPM_MEM_DC_DISP_CONF2_1__EMPTY      0x1F0406B8,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_1__FULL      0x1F0406B8,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_1__SL_1      0x1F0406B8,0x1FFFFFFF
+
+#define LPM_MEM_DC_DISP_CONF2_2__ADDR                  0x1F0406BC
+#define LPM_MEM_DC_DISP_CONF2_2__EMPTY      0x1F0406BC,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_2__FULL      0x1F0406BC,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_2__SL_2      0x1F0406BC,0x1FFFFFFF
+
+#define LPM_MEM_DC_DISP_CONF2_3__ADDR                  0x1F0406C0
+#define LPM_MEM_DC_DISP_CONF2_3__EMPTY      0x1F0406C0,0x00000000
+#define LPM_MEM_DC_DISP_CONF2_3__FULL      0x1F0406C0,0xffffffff
+#define LPM_MEM_DC_DISP_CONF2_3__SL_3      0x1F0406C0,0x1FFFFFFF
+
+#define LPM_MEM_DC_DI0_CONF_1__ADDR                  0x1F0406C4
+#define LPM_MEM_DC_DI0_CONF_1__EMPTY      0x1F0406C4,0x00000000
+#define LPM_MEM_DC_DI0_CONF_1__FULL      0x1F0406C4,0xffffffff
+#define LPM_MEM_DC_DI0_CONF_1__DI_READ_DATA_MASK_0      0x1F0406C4,0xFFFFFFFF
+
+#define LPM_MEM_DC_DI0_CONF_2__ADDR                  0x1F0406C8
+#define LPM_MEM_DC_DI0_CONF_2__EMPTY      0x1F0406C8,0x00000000
+#define LPM_MEM_DC_DI0_CONF_2__FULL      0x1F0406C8,0xffffffff
+#define LPM_MEM_DC_DI0_CONF_2__DI_READ_DATA_ACK_VALUE_0              0x1F0406C8,0xFFFFFFFF
+
+#define LPM_MEM_DC_DI1_CONF_1__ADDR                  0x1F0406CC
+#define LPM_MEM_DC_DI1_CONF_1__EMPTY      0x1F0406CC,0x00000000
+#define LPM_MEM_DC_DI1_CONF_1__FULL      0x1F0406CC,0xffffffff
+#define LPM_MEM_DC_DI1_CONF_1__DI_READ_DATA_MASK_1      0x1F0406CC,0xFFFFFFFF
+
+#define LPM_MEM_DC_DI1_CONF_2__ADDR                  0x1F0406D0
+#define LPM_MEM_DC_DI1_CONF_2__EMPTY      0x1F0406D0,0x00000000
+#define LPM_MEM_DC_DI1_CONF_2__FULL      0x1F0406D0,0xffffffff
+#define LPM_MEM_DC_DI1_CONF_2__DI_READ_DATA_ACK_VALUE_1              0x1F0406D0,0xFFFFFFFF
+
+#define LPM_MEM_DC_MAP_CONF_0__ADDR                  0x1F0406D4
+#define LPM_MEM_DC_MAP_CONF_0__EMPTY      0x1F0406D4,0x00000000
+#define LPM_MEM_DC_MAP_CONF_0__FULL      0x1F0406D4,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1      0x1F0406D4,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1      0x1F0406D4,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1      0x1F0406D4,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0      0x1F0406D4,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0      0x1F0406D4,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0      0x1F0406D4,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_1__ADDR                  0x1F0406D8
+#define LPM_MEM_DC_MAP_CONF_1__EMPTY      0x1F0406D8,0x00000000
+#define LPM_MEM_DC_MAP_CONF_1__FULL      0x1F0406D8,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_3      0x1F0406D8,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_3      0x1F0406D8,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_3      0x1F0406D8,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE2_2      0x1F0406D8,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE1_2      0x1F0406D8,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_1__MAPPING_PNTR_BYTE0_2      0x1F0406D8,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_2__ADDR                  0x1F0406DC
+#define LPM_MEM_DC_MAP_CONF_2__EMPTY      0x1F0406DC,0x00000000
+#define LPM_MEM_DC_MAP_CONF_2__FULL      0x1F0406DC,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_5      0x1F0406DC,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_5      0x1F0406DC,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_5      0x1F0406DC,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4      0x1F0406DC,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4      0x1F0406DC,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4      0x1F0406DC,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_3__ADDR                  0x1F0406E0
+#define LPM_MEM_DC_MAP_CONF_3__EMPTY      0x1F0406E0,0x00000000
+#define LPM_MEM_DC_MAP_CONF_3__FULL      0x1F0406E0,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_7      0x1F0406E0,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_7      0x1F0406E0,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_7      0x1F0406E0,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE2_6      0x1F0406E0,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE1_6      0x1F0406E0,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_3__MAPPING_PNTR_BYTE0_6      0x1F0406E0,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_4__ADDR                  0x1F0406E4
+#define LPM_MEM_DC_MAP_CONF_4__EMPTY      0x1F0406E4,0x00000000
+#define LPM_MEM_DC_MAP_CONF_4__FULL      0x1F0406E4,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_9      0x1F0406E4,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_9      0x1F0406E4,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_9      0x1F0406E4,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE2_8      0x1F0406E4,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE1_8      0x1F0406E4,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_4__MAPPING_PNTR_BYTE0_8      0x1F0406E4,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_5__ADDR                  0x1F0406E8
+#define LPM_MEM_DC_MAP_CONF_5__EMPTY      0x1F0406E8,0x00000000
+#define LPM_MEM_DC_MAP_CONF_5__FULL      0x1F0406E8,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_11      0x1F0406E8,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_11      0x1F0406E8,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_11      0x1F0406E8,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE2_10      0x1F0406E8,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE1_10      0x1F0406E8,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_5__MAPPING_PNTR_BYTE0_10      0x1F0406E8,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_6__ADDR                  0x1F0406EC
+#define LPM_MEM_DC_MAP_CONF_6__EMPTY      0x1F0406EC,0x00000000
+#define LPM_MEM_DC_MAP_CONF_6__FULL      0x1F0406EC,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_13      0x1F0406EC,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_13      0x1F0406EC,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_13      0x1F0406EC,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE2_12      0x1F0406EC,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE1_12      0x1F0406EC,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_6__MAPPING_PNTR_BYTE0_12      0x1F0406EC,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_7__ADDR                  0x1F0406F0
+#define LPM_MEM_DC_MAP_CONF_7__EMPTY      0x1F0406F0,0x00000000
+#define LPM_MEM_DC_MAP_CONF_7__FULL      0x1F0406F0,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_15      0x1F0406F0,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_15      0x1F0406F0,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_15      0x1F0406F0,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE2_14      0x1F0406F0,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE1_14      0x1F0406F0,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_7__MAPPING_PNTR_BYTE0_14      0x1F0406F0,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_8__ADDR                  0x1F0406F4
+#define LPM_MEM_DC_MAP_CONF_8__EMPTY      0x1F0406F4,0x00000000
+#define LPM_MEM_DC_MAP_CONF_8__FULL      0x1F0406F4,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_17      0x1F0406F4,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_17      0x1F0406F4,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_17      0x1F0406F4,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE2_16      0x1F0406F4,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE1_16      0x1F0406F4,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_8__MAPPING_PNTR_BYTE0_16      0x1F0406F4,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_9__ADDR                  0x1F0406F8
+#define LPM_MEM_DC_MAP_CONF_9__EMPTY      0x1F0406F8,0x00000000
+#define LPM_MEM_DC_MAP_CONF_9__FULL      0x1F0406F8,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_19      0x1F0406F8,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_19      0x1F0406F8,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_19      0x1F0406F8,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE2_18      0x1F0406F8,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE1_18      0x1F0406F8,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_9__MAPPING_PNTR_BYTE0_18      0x1F0406F8,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_10__ADDR                  0x1F0406FC
+#define LPM_MEM_DC_MAP_CONF_10__EMPTY      0x1F0406FC,0x00000000
+#define LPM_MEM_DC_MAP_CONF_10__FULL      0x1F0406FC,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_21      0x1F0406FC,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_21      0x1F0406FC,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_21      0x1F0406FC,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE2_20      0x1F0406FC,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE1_20      0x1F0406FC,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_10__MAPPING_PNTR_BYTE0_20      0x1F0406FC,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_11__ADDR                  0x1F040700
+#define LPM_MEM_DC_MAP_CONF_11__EMPTY      0x1F040700,0x00000000
+#define LPM_MEM_DC_MAP_CONF_11__FULL      0x1F040700,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_23      0x1F040700,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_23      0x1F040700,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_23      0x1F040700,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE2_22      0x1F040700,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE1_22      0x1F040700,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_11__MAPPING_PNTR_BYTE0_22      0x1F040700,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_12__ADDR                  0x1F040704
+#define LPM_MEM_DC_MAP_CONF_12__EMPTY      0x1F040704,0x00000000
+#define LPM_MEM_DC_MAP_CONF_12__FULL      0x1F040704,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_25      0x1F040704,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_25      0x1F040704,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_25      0x1F040704,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE2_24      0x1F040704,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE1_24      0x1F040704,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_12__MAPPING_PNTR_BYTE0_24      0x1F040704,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_13__ADDR                  0x1F040708
+#define LPM_MEM_DC_MAP_CONF_13__EMPTY      0x1F040708,0x00000000
+#define LPM_MEM_DC_MAP_CONF_13__FULL      0x1F040708,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_27      0x1F040708,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_27      0x1F040708,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_27      0x1F040708,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE2_26      0x1F040708,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE1_26      0x1F040708,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_13__MAPPING_PNTR_BYTE0_26      0x1F040708,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_14__ADDR                  0x1F04070C
+#define LPM_MEM_DC_MAP_CONF_14__EMPTY      0x1F04070C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_14__FULL      0x1F04070C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_29      0x1F04070C,0x7C000000
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_29      0x1F04070C,0x03E00000
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_29      0x1F04070C,0x001F0000
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE2_28      0x1F04070C,0x00007C00
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE1_28      0x1F04070C,0x000003E0
+#define LPM_MEM_DC_MAP_CONF_14__MAPPING_PNTR_BYTE0_28      0x1F04070C,0x0000001F
+
+#define LPM_MEM_DC_MAP_CONF_15__ADDR                  0x1F040710
+#define LPM_MEM_DC_MAP_CONF_15__EMPTY      0x1F040710,0x00000000
+#define LPM_MEM_DC_MAP_CONF_15__FULL      0x1F040710,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_1      0x1F040710,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_1      0x1F040710,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_15__MD_OFFSET_0      0x1F040710,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_15__MD_MASK_0      0x1F040710,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_16__ADDR                  0x1F040714
+#define LPM_MEM_DC_MAP_CONF_16__EMPTY      0x1F040714,0x00000000
+#define LPM_MEM_DC_MAP_CONF_16__FULL      0x1F040714,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_3      0x1F040714,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_3      0x1F040714,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_16__MD_OFFSET_2      0x1F040714,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_16__MD_MASK_2      0x1F040714,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_17__ADDR                  0x1F040718
+#define LPM_MEM_DC_MAP_CONF_17__EMPTY      0x1F040718,0x00000000
+#define LPM_MEM_DC_MAP_CONF_17__FULL      0x1F040718,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_5      0x1F040718,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_5      0x1F040718,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_17__MD_OFFSET_4      0x1F040718,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_17__MD_MASK_4      0x1F040718,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_18__ADDR                  0x1F04071C
+#define LPM_MEM_DC_MAP_CONF_18__EMPTY      0x1F04071C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_18__FULL      0x1F04071C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_7      0x1F04071C,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_7      0x1F04071C,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_18__MD_OFFSET_6      0x1F04071C,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_18__MD_MASK_6      0x1F04071C,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_19__ADDR                  0x1F040720
+#define LPM_MEM_DC_MAP_CONF_19__EMPTY      0x1F040720,0x00000000
+#define LPM_MEM_DC_MAP_CONF_19__FULL      0x1F040720,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_9      0x1F040720,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_9      0x1F040720,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_19__MD_OFFSET_8      0x1F040720,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_19__MD_MASK_8      0x1F040720,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_20__ADDR                  0x1F040724
+#define LPM_MEM_DC_MAP_CONF_20__EMPTY      0x1F040724,0x00000000
+#define LPM_MEM_DC_MAP_CONF_20__FULL      0x1F040724,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_11      0x1F040724,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_11      0x1F040724,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_20__MD_OFFSET_10      0x1F040724,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_20__MD_MASK_10      0x1F040724,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_21__ADDR                  0x1F040728
+#define LPM_MEM_DC_MAP_CONF_21__EMPTY      0x1F040728,0x00000000
+#define LPM_MEM_DC_MAP_CONF_21__FULL      0x1F040728,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_13      0x1F040728,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_13      0x1F040728,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_21__MD_OFFSET_12      0x1F040728,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_21__MD_MASK_12      0x1F040728,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_22__ADDR                  0x1F04072C
+#define LPM_MEM_DC_MAP_CONF_22__EMPTY      0x1F04072C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_22__FULL      0x1F04072C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_15      0x1F04072C,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_15      0x1F04072C,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_22__MD_OFFSET_14      0x1F04072C,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_22__MD_MASK_14      0x1F04072C,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_23__ADDR                  0x1F040730
+#define LPM_MEM_DC_MAP_CONF_23__EMPTY      0x1F040730,0x00000000
+#define LPM_MEM_DC_MAP_CONF_23__FULL      0x1F040730,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_17      0x1F040730,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_17      0x1F040730,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_23__MD_OFFSET_16      0x1F040730,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_23__MD_MASK_16      0x1F040730,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_24__ADDR                  0x1F040734
+#define LPM_MEM_DC_MAP_CONF_24__EMPTY      0x1F040734,0x00000000
+#define LPM_MEM_DC_MAP_CONF_24__FULL      0x1F040734,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_19      0x1F040734,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_19      0x1F040734,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_24__MD_OFFSET_18      0x1F040734,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_24__MD_MASK_18      0x1F040734,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_25__ADDR                  0x1F040738
+#define LPM_MEM_DC_MAP_CONF_25__EMPTY      0x1F040738,0x00000000
+#define LPM_MEM_DC_MAP_CONF_25__FULL      0x1F040738,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_21      0x1F040738,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_21      0x1F040738,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_25__MD_OFFSET_20      0x1F040738,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_25__MD_MASK_20      0x1F040738,0x000000FF
+
+#define LPM_MEM_DC_MAP_CONF_26__ADDR                  0x1F04073C
+#define LPM_MEM_DC_MAP_CONF_26__EMPTY      0x1F04073C,0x00000000
+#define LPM_MEM_DC_MAP_CONF_26__FULL      0x1F04073C,0xffffffff
+#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_23      0x1F04073C,0x1F000000
+#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_23      0x1F04073C,0x00FF0000
+#define LPM_MEM_DC_MAP_CONF_26__MD_OFFSET_22      0x1F04073C,0x00001F00
+#define LPM_MEM_DC_MAP_CONF_26__MD_MASK_22      0x1F04073C,0x000000FF
+
+#define LPM_MEM_DC_UGDE0_0__ADDR                  0x1F040740
+#define LPM_MEM_DC_UGDE0_0__EMPTY      0x1F040740,0x00000000
+#define LPM_MEM_DC_UGDE0_0__FULL       0x1F040740,0xffffffff
+#define LPM_MEM_DC_UGDE0_0__NF_NL_0      0x1F040740,0x18000000
+#define LPM_MEM_DC_UGDE0_0__AUTORESTART_0      0x1F040740,0x04000000
+#define LPM_MEM_DC_UGDE0_0__ODD_EN_0      0x1F040740,0x02000000
+#define LPM_MEM_DC_UGDE0_0__COD_ODD_START_0      0x1F040740,0x00FF0000
+#define LPM_MEM_DC_UGDE0_0__COD_EV_START_0      0x1F040740,0x0000FF00
+#define LPM_MEM_DC_UGDE0_0__COD_EV_PRIORITY_0      0x1F040740,0x00000078
+#define LPM_MEM_DC_UGDE0_0__ID_CODED_0      0x1F040740,0x00000007
+
+#define LPM_MEM_DC_UGDE0_1__ADDR                  0x1F040744
+#define LPM_MEM_DC_UGDE0_1__EMPTY      0x1F040744,0x00000000
+#define LPM_MEM_DC_UGDE0_1__FULL       0x1F040744,0xffffffff
+#define LPM_MEM_DC_UGDE0_1__STEP_0      0x1F040744,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE0_2__ADDR                  0x1F040748
+#define LPM_MEM_DC_UGDE0_2__EMPTY      0x1F040748,0x00000000
+#define LPM_MEM_DC_UGDE0_2__FULL       0x1F040748,0xffffffff
+#define LPM_MEM_DC_UGDE0_2__OFFSET_DT_0              0x1F040748,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE0_3__ADDR                  0x1F04074C
+#define LPM_MEM_DC_UGDE0_3__EMPTY      0x1F04074C,0x00000000
+#define LPM_MEM_DC_UGDE0_3__FULL       0x1F04074C,0xffffffff
+#define LPM_MEM_DC_UGDE0_3__STEP_REPEAT_0      0x1F04074C,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE1_0__ADDR                  0x1F040750
+#define LPM_MEM_DC_UGDE1_0__EMPTY      0x1F040750,0x00000000
+#define LPM_MEM_DC_UGDE1_0__FULL       0x1F040750,0xffffffff
+#define LPM_MEM_DC_UGDE1_0__NF_NL_1      0x1F040750,0x18000000
+#define LPM_MEM_DC_UGDE1_0__AUTORESTART_1      0x1F040750,0x04000000
+#define LPM_MEM_DC_UGDE1_0__ODD_EN_1      0x1F040750,0x02000000
+#define LPM_MEM_DC_UGDE1_0__COD_ODD_START_1      0x1F040750,0x00FF0000
+#define LPM_MEM_DC_UGDE1_0__COD_EV_START_1      0x1F040750,0x00007F80
+#define LPM_MEM_DC_UGDE1_0__COD_EV_PRIORITY_1      0x1F040750,0x00000078
+#define LPM_MEM_DC_UGDE1_0__ID_CODED_1      0x1F040750,0x00000007
+
+#define LPM_MEM_DC_UGDE1_1__ADDR                  0x1F040754
+#define LPM_MEM_DC_UGDE1_1__EMPTY      0x1F040754,0x00000000
+#define LPM_MEM_DC_UGDE1_1__FULL       0x1F040754,0xffffffff
+#define LPM_MEM_DC_UGDE1_1__STEP_1      0x1F040754,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE1_2__ADDR                  0x1F040758
+#define LPM_MEM_DC_UGDE1_2__EMPTY      0x1F040758,0x00000000
+#define LPM_MEM_DC_UGDE1_2__FULL       0x1F040758,0xffffffff
+#define LPM_MEM_DC_UGDE1_2__OFFSET_DT_1              0x1F040758,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE1_3__ADDR                  0x1F04075C
+#define LPM_MEM_DC_UGDE1_3__EMPTY      0x1F04075C,0x00000000
+#define LPM_MEM_DC_UGDE1_3__FULL       0x1F04075C,0xffffffff
+#define LPM_MEM_DC_UGDE1_3__STEP_REPEAT_1      0x1F04075C,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE2_0__ADDR                  0x1F040760
+#define LPM_MEM_DC_UGDE2_0__EMPTY      0x1F040760,0x00000000
+#define LPM_MEM_DC_UGDE2_0__FULL       0x1F040760,0xffffffff
+#define LPM_MEM_DC_UGDE2_0__NF_NL_2      0x1F040760,0x18000000
+#define LPM_MEM_DC_UGDE2_0__AUTORESTART_2      0x1F040760,0x04000000
+#define LPM_MEM_DC_UGDE2_0__ODD_EN_2      0x1F040760,0x02000000
+#define LPM_MEM_DC_UGDE2_0__COD_ODD_START_2      0x1F040760,0x00FF0000
+#define LPM_MEM_DC_UGDE2_0__COD_EV_START_2      0x1F040760,0x00007F80
+#define LPM_MEM_DC_UGDE2_0__COD_EV_PRIORITY_2      0x1F040760,0x00000078
+#define LPM_MEM_DC_UGDE2_0__ID_CODED_2      0x1F040760,0x00000007
+
+#define LPM_MEM_DC_UGDE2_1__ADDR                  0x1F040764
+#define LPM_MEM_DC_UGDE2_1__EMPTY      0x1F040764,0x00000000
+#define LPM_MEM_DC_UGDE2_1__FULL       0x1F040764,0xffffffff
+#define LPM_MEM_DC_UGDE2_1__STEP_2      0x1F040764,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE2_2__ADDR                  0x1F040768
+#define LPM_MEM_DC_UGDE2_2__EMPTY      0x1F040768,0x00000000
+#define LPM_MEM_DC_UGDE2_2__FULL       0x1F040768,0xffffffff
+#define LPM_MEM_DC_UGDE2_2__OFFSET_DT_2              0x1F040768,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE2_3__ADDR                  0x1F04076C
+#define LPM_MEM_DC_UGDE2_3__EMPTY      0x1F04076C,0x00000000
+#define LPM_MEM_DC_UGDE2_3__FULL       0x1F04076C,0xffffffff
+#define LPM_MEM_DC_UGDE2_3__STEP_REPEAT_2      0x1F04076C,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE3_0__ADDR                  0x1F040770
+#define LPM_MEM_DC_UGDE3_0__EMPTY      0x1F040770,0x00000000
+#define LPM_MEM_DC_UGDE3_0__FULL       0x1F040770,0xffffffff
+#define LPM_MEM_DC_UGDE3_0__NF_NL_3      0x1F040770,0x18000000
+#define LPM_MEM_DC_UGDE3_0__AUTORESTART_3      0x1F040770,0x04000000
+#define LPM_MEM_DC_UGDE3_0__ODD_EN_3      0x1F040770,0x02000000
+#define LPM_MEM_DC_UGDE3_0__COD_ODD_START_3      0x1F040770,0x00FF0000
+#define LPM_MEM_DC_UGDE3_0__COD_EV_START_3      0x1F040770,0x00007F80
+#define LPM_MEM_DC_UGDE3_0__COD_EV_PRIORITY_3      0x1F040770,0x00000078
+#define LPM_MEM_DC_UGDE3_0__ID_CODED_3      0x1F040770,0x00000007
+
+#define LPM_MEM_DC_UGDE3_1__ADDR                  0x1F040774
+#define LPM_MEM_DC_UGDE3_1__EMPTY      0x1F040774,0x00000000
+#define LPM_MEM_DC_UGDE3_1__FULL       0x1F040774,0xffffffff
+#define LPM_MEM_DC_UGDE3_1__STEP_3      0x1F040774,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE3_2__ADDR                  0x1F040778
+#define LPM_MEM_DC_UGDE3_2__EMPTY      0x1F040778,0x00000000
+#define LPM_MEM_DC_UGDE3_2__FULL       0x1F040778,0xffffffff
+#define LPM_MEM_DC_UGDE3_2__OFFSET_DT_3              0x1F040778,0x1FFFFFFF
+
+#define LPM_MEM_DC_UGDE3_3__ADDR                  0x1F04077C
+#define LPM_MEM_DC_UGDE3_3__EMPTY      0x1F04077C,0x00000000
+#define LPM_MEM_DC_UGDE3_3__FULL       0x1F04077C,0xffffffff
+#define LPM_MEM_DC_UGDE3_3__STEP_REPEAT_3      0x1F04077C,0x1FFFFFFF
+
+#define LPM_MEM_DC_LLA0__ADDR                  0x1F040780
+#define LPM_MEM_DC_LLA0__EMPTY      0x1F040780,0x00000000
+#define LPM_MEM_DC_LLA0__FULL      0x1F040780,0xffffffff
+#define LPM_MEM_DC_LLA0__MCU_RS_3_0      0x1F040780,0xFF000000
+#define LPM_MEM_DC_LLA0__MCU_RS_2_0      0x1F040780,0x00FF0000
+#define LPM_MEM_DC_LLA0__MCU_RS_1_0      0x1F040780,0x0000FF00
+#define LPM_MEM_DC_LLA0__MCU_RS_0_0      0x1F040780,0x000000FF
+
+#define LPM_MEM_DC_LLA1__ADDR                  0x1F040784
+#define LPM_MEM_DC_LLA1__EMPTY      0x1F040784,0x00000000
+#define LPM_MEM_DC_LLA1__FULL      0x1F040784,0xffffffff
+#define LPM_MEM_DC_LLA1__MCU_RS_3_1      0x1F040784,0xFF000000
+#define LPM_MEM_DC_LLA1__MCU_RS_2_1      0x1F040784,0x00FF0000
+#define LPM_MEM_DC_LLA1__MCU_RS_1_1      0x1F040784,0x0000FF00
+#define LPM_MEM_DC_LLA1__MCU_RS_0_1      0x1F040784,0x000000FF
+
+#define LPM_MEM_DC_R_LLA0__ADDR                          0x1F040788
+#define LPM_MEM_DC_R_LLA0__EMPTY       0x1F040788,0x00000000
+#define LPM_MEM_DC_R_LLA0__FULL              0x1F040788,0xffffffff
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_3_0              0x1F040788,0xFF000000
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_2_0              0x1F040788,0x00FF0000
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_1_0              0x1F040788,0x0000FF00
+#define LPM_MEM_DC_R_LLA0__MCU_RS_R_0_0              0x1F040788,0x000000FF
+
+#define LPM_MEM_DC_R_LLA1__ADDR                          0x1F04078C
+#define LPM_MEM_DC_R_LLA1__EMPTY       0x1F04078C,0x00000000
+#define LPM_MEM_DC_R_LLA1__FULL              0x1F04078C,0xffffffff
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_3_1              0x1F04078C,0xFF000000
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_2_1              0x1F04078C,0x00FF0000
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_1_1              0x1F04078C,0x0000FF00
+#define LPM_MEM_DC_R_LLA1__MCU_RS_R_0_1              0x1F04078C,0x000000FF
+
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ADDR                  0x1F040790
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__EMPTY      0x1F040790,0x00000000
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__FULL      0x1F040790,0xffffffff
+#define LPM_MEM_DC_WR_CH_ADDR_5_ALT__ST_ADDR_5_ALT      0x1F040790,0x1FFFFFFF
+
+#define LPM_MEM_IDMAC_CONF__ADDR                  0x1F040794
+#define LPM_MEM_IDMAC_CONF__EMPTY      0x1F040794,0x00000000
+#define LPM_MEM_IDMAC_CONF__FULL       0x1F040794,0xffffffff
+#define LPM_MEM_IDMAC_CONF__P_ENDIAN      0x1F040794,0x00010000
+#define LPM_MEM_IDMAC_CONF__RDI                 0x1F040794,0x00000020
+#define LPM_MEM_IDMAC_CONF__WIDPT      0x1F040794,0x00000018
+#define LPM_MEM_IDMAC_CONF__MAX_REQ_READ       0x1F040794,0x00000007
+
+#define LPM_MEM_IDMAC_CH_EN_1__ADDR                  0x1F040798
+#define LPM_MEM_IDMAC_CH_EN_1__EMPTY      0x1F040798,0x00000000
+#define LPM_MEM_IDMAC_CH_EN_1__FULL      0x1F040798,0xffffffff
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_31      0x1F040798,0x80000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_29      0x1F040798,0x20000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_28      0x1F040798,0x10000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_27      0x1F040798,0x08000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_24      0x1F040798,0x01000000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_23      0x1F040798,0x00800000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_22      0x1F040798,0x00400000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_21      0x1F040798,0x00200000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_20      0x1F040798,0x00100000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_18      0x1F040798,0x00040000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_17      0x1F040798,0x00020000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_15      0x1F040798,0x00008000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_14      0x1F040798,0x00004000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_12      0x1F040798,0x00001000
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_11      0x1F040798,0x00000800
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_7      0x1F040798,0x00000080
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_6      0x1F040798,0x00000040
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_5      0x1F040798,0x00000020
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_4      0x1F040798,0x00000010
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_3      0x1F040798,0x00000008
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_2      0x1F040798,0x00000004
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_1      0x1F040798,0x00000002
+#define LPM_MEM_IDMAC_CH_EN_1__IDMAC_CH_EN_0      0x1F040798,0x00000001
+
+#define LPM_MEM_IDMAC_CH_EN_2__ADDR                  0x1F04079C
+#define LPM_MEM_IDMAC_CH_EN_2__EMPTY      0x1F04079C,0x00000000
+#define LPM_MEM_IDMAC_CH_EN_2__FULL      0x1F04079C,0xffffffff
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_52      0x1F04079C,0x00100000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_51      0x1F04079C,0x00080000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_50      0x1F04079C,0x00040000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_49      0x1F04079C,0x00020000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_48      0x1F04079C,0x00010000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_47      0x1F04079C,0x00008000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_46      0x1F04079C,0x00004000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_45      0x1F04079C,0x00002000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_44      0x1F04079C,0x00001000
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_43      0x1F04079C,0x00000800
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_42      0x1F04079C,0x00000400
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_41      0x1F04079C,0x00000200
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_40      0x1F04079C,0x00000100
+#define LPM_MEM_IDMAC_CH_EN_2__IDMAC_CH_EN_33      0x1F04079C,0x00000002
+
+#define LPM_MEM_IDMAC_SEP_ALPHA__ADDR                  0x1F0407A0
+#define LPM_MEM_IDMAC_SEP_ALPHA__EMPTY      0x1F0407A0,0x00000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__FULL      0x1F0407A0,0xffffffff
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_29       0x1F0407A0,0x20000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_27       0x1F0407A0,0x08000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_24       0x1F0407A0,0x01000000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_23       0x1F0407A0,0x00800000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_15       0x1F0407A0,0x00008000
+#define LPM_MEM_IDMAC_SEP_ALPHA__IDMAC_SEP_AL_14       0x1F0407A0,0x00004000
+
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__ADDR                  0x1F0407A4
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__EMPTY      0x1F0407A4,0x00000000
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__FULL      0x1F0407A4,0xffffffff
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_29       0x1F0407A4,0x20000000
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_24       0x1F0407A4,0x01000000
+#define LPM_MEM_IDMAC_ALT_SEP_ALPHA__IDMAC_ALT_SEP_AL_23       0x1F0407A4,0x00800000
+
+#define LPM_MEM_IDMAC_CH_PRI_1__ADDR                  0x1F0407A8
+#define LPM_MEM_IDMAC_CH_PRI_1__EMPTY      0x1F0407A8,0x00000000
+#define LPM_MEM_IDMAC_CH_PRI_1__FULL      0x1F0407A8,0xffffffff
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_29              0x1F0407A8,0x20000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_28              0x1F0407A8,0x10000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_27              0x1F0407A8,0x08000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_24              0x1F0407A8,0x01000000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_23              0x1F0407A8,0x00800000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_22              0x1F0407A8,0x00400000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_21              0x1F0407A8,0x00200000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_20              0x1F0407A8,0x00100000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_15              0x1F0407A8,0x00008000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_14              0x1F0407A8,0x00004000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_12              0x1F0407A8,0x00001000
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_11              0x1F0407A8,0x00000800
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_7      0x1F0407A8,0x00000080
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_6      0x1F0407A8,0x00000040
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_5      0x1F0407A8,0x00000020
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_4      0x1F0407A8,0x00000010
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_3      0x1F0407A8,0x00000008
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_2      0x1F0407A8,0x00000004
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_1      0x1F0407A8,0x00000002
+#define LPM_MEM_IDMAC_CH_PRI_1__IDMAC_CH_PRI_0      0x1F0407A8,0x00000001
+
+#define LPM_MEM_IDMAC_CH_PRI_2__ADDR                  0x1F0407AC
+#define LPM_MEM_IDMAC_CH_PRI_2__EMPTY      0x1F0407AC,0x00000000
+#define LPM_MEM_IDMAC_CH_PRI_2__FULL      0x1F0407AC,0xffffffff
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_50              0x1F0407AC,0x00040000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_49              0x1F0407AC,0x00020000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_48              0x1F0407AC,0x00010000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_47              0x1F0407AC,0x00008000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_46              0x1F0407AC,0x00004000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_45              0x1F0407AC,0x00002000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_44              0x1F0407AC,0x00001000
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_43              0x1F0407AC,0x00000800
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_42              0x1F0407AC,0x00000400
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_41              0x1F0407AC,0x00000200
+#define LPM_MEM_IDMAC_CH_PRI_2__IDMAC_CH_PRI_40              0x1F0407AC,0x00000100
+
+#define LPM_MEM_IDMAC_WM_EN_1__ADDR                  0x1F0407B0
+#define LPM_MEM_IDMAC_WM_EN_1__EMPTY      0x1F0407B0,0x00000000
+#define LPM_MEM_IDMAC_WM_EN_1__FULL      0x1F0407B0,0xffffffff
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_29      0x1F0407B0,0x20000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_28      0x1F0407B0,0x10000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_27      0x1F0407B0,0x08000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_24      0x1F0407B0,0x01000000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_23      0x1F0407B0,0x00800000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_14      0x1F0407B0,0x00004000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_12      0x1F0407B0,0x00001000
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_3      0x1F0407B0,0x00000008
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_2      0x1F0407B0,0x00000004
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_1      0x1F0407B0,0x00000002
+#define LPM_MEM_IDMAC_WM_EN_1__IDMAC_WM_EN_0      0x1F0407B0,0x00000001
+
+#define LPM_MEM_IDMAC_WM_EN_2__ADDR                  0x1F0407B4
+#define LPM_MEM_IDMAC_WM_EN_2__EMPTY      0x1F0407B4,0x00000000
+#define LPM_MEM_IDMAC_WM_EN_2__FULL      0x1F0407B4,0xffffffff
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_44      0x1F0407B4,0x00001000
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_43      0x1F0407B4,0x00000800
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_42      0x1F0407B4,0x00000400
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_41      0x1F0407B4,0x00000200
+#define LPM_MEM_IDMAC_WM_EN_2__IDMAC_WM_EN_40      0x1F0407B4,0x00000100
+
+#define LPM_MEM_IDMAC_LOCK_EN_2__ADDR                  0x1F0407B8
+#define LPM_MEM_IDMAC_LOCK_EN_2__EMPTY      0x1F0407B8,0x00000000
+#define LPM_MEM_IDMAC_LOCK_EN_2__FULL      0x1F0407B8,0xffffffff
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_50      0x1F0407B8,0x00040000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_49      0x1F0407B8,0x00020000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_48      0x1F0407B8,0x00010000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_47      0x1F0407B8,0x00008000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_46      0x1F0407B8,0x00004000
+#define LPM_MEM_IDMAC_LOCK_EN_2__IDMAC_LOCK_EN_45      0x1F0407B8,0x00002000
+
+#define LPM_MEM_IDMAC_SUB_ADDR_0__ADDR                  0x1F0407BC
+#define LPM_MEM_IDMAC_SUB_ADDR_0__EMPTY              0x1F0407BC,0x00000000
+#define LPM_MEM_IDMAC_SUB_ADDR_0__FULL      0x1F0407BC,0xffffffff
+#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_7      0x1F0407BC,0x7F000000
+#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_6      0x1F0407BC,0x007F0000
+#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_5      0x1F0407BC,0x00007F00
+#define LPM_MEM_IDMAC_SUB_ADDR_0__IDMAC_SUB_ADDR_4      0x1F0407BC,0x0000007F
+
+#define LPM_MEM_IDMAC_SUB_ADDR_1__ADDR                  0x1F0407C0
+#define LPM_MEM_IDMAC_SUB_ADDR_1__EMPTY              0x1F0407C0,0x00000000
+#define LPM_MEM_IDMAC_SUB_ADDR_1__FULL      0x1F0407C0,0xffffffff
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_33      0x1F0407C0,0x7F000000
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_29      0x1F0407C0,0x007F0000
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_24      0x1F0407C0,0x00007F00
+#define LPM_MEM_IDMAC_SUB_ADDR_1__IDMAC_SUB_ADDR_23      0x1F0407C0,0x0000007F
+
+#define LPM_MEM_IDMAC_SUB_ADDR_2__ADDR                  0x1F0407C4
+#define LPM_MEM_IDMAC_SUB_ADDR_2__EMPTY              0x1F0407C4,0x00000000
+#define LPM_MEM_IDMAC_SUB_ADDR_2__FULL      0x1F0407C4,0xffffffff
+#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_52      0x1F0407C4,0x007F0000
+#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_51      0x1F0407C4,0x00007F00
+#define LPM_MEM_IDMAC_SUB_ADDR_2__IDMAC_SUB_ADDR_41      0x1F0407C4,0x0000007F
+
+#define LPM_MEM_IDMAC_BNDM_EN_1__ADDR                  0x1F0407C8
+#define LPM_MEM_IDMAC_BNDM_EN_1__EMPTY      0x1F0407C8,0x00000000
+#define LPM_MEM_IDMAC_BNDM_EN_1__FULL      0x1F0407C8,0xffffffff
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_22      0x1F0407C8,0x00400000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_21      0x1F0407C8,0x00200000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_20      0x1F0407C8,0x00100000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_12      0x1F0407C8,0x00001000
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_11      0x1F0407C8,0x00000800
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_5       0x1F0407C8,0x00000020
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_3       0x1F0407C8,0x00000008
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_2       0x1F0407C8,0x00000004
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_1       0x1F0407C8,0x00000002
+#define LPM_MEM_IDMAC_BNDM_EN_1__IDMAC_BNDM_EN_0       0x1F0407C8,0x00000001
+
+#define LPM_MEM_IDMAC_BNDM_EN_2__ADDR                  0x1F0407CC
+#define LPM_MEM_IDMAC_BNDM_EN_2__EMPTY      0x1F0407CC,0x00000000
+#define LPM_MEM_IDMAC_BNDM_EN_2__FULL      0x1F0407CC,0xffffffff
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_50      0x1F0407CC,0x00040000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_49      0x1F0407CC,0x00020000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_48      0x1F0407CC,0x00010000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_47      0x1F0407CC,0x00008000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_46      0x1F0407CC,0x00004000
+#define LPM_MEM_IDMAC_BNDM_EN_2__IDMAC_BNDM_EN_45      0x1F0407CC,0x00002000
+
+#define LPM_MEM_IDMAC_SC_CORD__ADDR                  0x1F0407D0
+#define LPM_MEM_IDMAC_SC_CORD__EMPTY      0x1F0407D0,0x00000000
+#define LPM_MEM_IDMAC_SC_CORD__FULL      0x1F0407D0,0xffffffff
+#define LPM_MEM_IDMAC_SC_CORD__SX0      0x1F0407D0,0x0FFF0000
+#define LPM_MEM_IDMAC_SC_CORD__SY0      0x1F0407D0,0x000007FF
+
+#define LPM_MEM_IPU_CONF__ADDR            0x1F0407D4
+#define LPM_MEM_IPU_CONF__EMPTY                   0x1F0407D4,0x00000000
+#define LPM_MEM_IPU_CONF__FULL            0x1F0407D4,0xffffffff
+#define LPM_MEM_IPU_CONF__CSI_SEL         0x1F0407D4,0x80000000
+#define LPM_MEM_IPU_CONF__IC_INPUT        0x1F0407D4,0x40000000
+#define LPM_MEM_IPU_CONF__CSI1_DATA_SOURCE 0x1F0407D4,0x20000000
+#define LPM_MEM_IPU_CONF__CSI0_DATA_SOURCE 0x1F0407D4,0x10000000
+#define LPM_MEM_IPU_CONF__IC_DMFC_SYNC    0x1F0407D4,0x04000000
+#define LPM_MEM_IPU_CONF__IC_DMFC_SEL     0x1F0407D4,0x02000000
+#define LPM_MEM_IPU_CONF__ISP_DOUBLE_FLOW  0x1F0407D4,0x01000000
+#define LPM_MEM_IPU_CONF__IDMAC_DISABLE           0x1F0407D4,0x00400000
+#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_ON   0x1F0407D4,0x00200000
+#define LPM_MEM_IPU_CONF__IPU_DIAGBUS_MODE 0x1F0407D4,0x001F0000
+#define LPM_MEM_IPU_CONF__IPU_HSP_CLK_EN   0x1F0407D4,0x00008000
+#define LPM_MEM_IPU_CONF__SISG_EN         0x1F0407D4,0x00000800
+#define LPM_MEM_IPU_CONF__DMFC_EN         0x1F0407D4,0x00000400
+#define LPM_MEM_IPU_CONF__DC_EN                   0x1F0407D4,0x00000200
+#define LPM_MEM_IPU_CONF__SMFC_EN         0x1F0407D4,0x00000100
+#define LPM_MEM_IPU_CONF__DI1_EN          0x1F0407D4,0x00000080
+#define LPM_MEM_IPU_CONF__DI0_EN          0x1F0407D4,0x00000040
+#define LPM_MEM_IPU_CONF__DP_EN                   0x1F0407D4,0x00000020
+#define LPM_MEM_IPU_CONF__ISP_EN          0x1F0407D4,0x00000010
+#define LPM_MEM_IPU_CONF__IRT_EN          0x1F0407D4,0x00000008
+#define LPM_MEM_IPU_CONF__IC_EN                   0x1F0407D4,0x00000004
+#define LPM_MEM_IPU_CONF__CSI1_EN         0x1F0407D4,0x00000002
+#define LPM_MEM_IPU_CONF__CSI0_EN         0x1F0407D4,0x00000001
+
+#define LPM_MEM_SISG_CTRL0__ADDR                  0x1F0407D8
+#define LPM_MEM_SISG_CTRL0__EMPTY      0x1F0407D8,0x00000000
+#define LPM_MEM_SISG_CTRL0__FULL       0x1F0407D8,0xffffffff
+#define LPM_MEM_SISG_CTRL0__EXT_ACTV      0x1F0407D8,0x40000000
+#define LPM_MEM_SISG_CTRL0__MCU_ACTV_TRIG      0x1F0407D8,0x20000000
+#define LPM_MEM_SISG_CTRL0__VAL_STOP_SISG_COUNTER      0x1F0407D8,0x1FFFFFF0
+#define LPM_MEM_SISG_CTRL0__NO_OF_VSYNC              0x1F0407D8,0x0000000E
+#define LPM_MEM_SISG_CTRL0__VSYNC_RESET_COUNTER              0x1F0407D8,0x00000001
+
+#define LPM_MEM_SISG_CTRL1__ADDR                  0x1F0407DC
+#define LPM_MEM_SISG_CTRL1__EMPTY      0x1F0407DC,0x00000000
+#define LPM_MEM_SISG_CTRL1__FULL       0x1F0407DC,0xffffffff
+#define LPM_MEM_SISG_CTRL1__SISG_OUT_POL       0x1F0407DC,0x00003F00
+#define LPM_MEM_SISG_CTRL1__SISG_STROBE_CNT      0x1F0407DC,0x0000001F
+
+#define LPM_MEM_SISG_SET_1__ADDR                  0x1F0407E0
+#define LPM_MEM_SISG_SET_1__EMPTY      0x1F0407E0,0x00000000
+#define LPM_MEM_SISG_SET_1__FULL       0x1F0407E0,0xffffffff
+#define LPM_MEM_SISG_SET_1__SISG_SET_1      0x1F0407E0,0x01FFFFFF
+
+#define LPM_MEM_SISG_SET_2__ADDR                  0x1F0407E4
+#define LPM_MEM_SISG_SET_2__EMPTY      0x1F0407E4,0x00000000
+#define LPM_MEM_SISG_SET_2__FULL       0x1F0407E4,0xffffffff
+#define LPM_MEM_SISG_SET_2__SISG_SET_2      0x1F0407E4,0x01FFFFFF
+
+#define LPM_MEM_SISG_SET_3__ADDR                  0x1F0407E8
+#define LPM_MEM_SISG_SET_3__EMPTY      0x1F0407E8,0x00000000
+#define LPM_MEM_SISG_SET_3__FULL       0x1F0407E8,0xffffffff
+#define LPM_MEM_SISG_SET_3__SISG_SET_3      0x1F0407E8,0x01FFFFFF
+
+#define LPM_MEM_SISG_SET_4__ADDR                  0x1F0407EC
+#define LPM_MEM_SISG_SET_4__EMPTY      0x1F0407EC,0x00000000
+#define LPM_MEM_SISG_SET_4__FULL       0x1F0407EC,0xffffffff
+#define LPM_MEM_SISG_SET_4__SISG_SET_4      0x1F0407EC,0x01FFFFFF
+
+#define LPM_MEM_SISG_SET_5__ADDR                  0x1F0407F0
+#define LPM_MEM_SISG_SET_5__EMPTY      0x1F0407F0,0x00000000
+#define LPM_MEM_SISG_SET_5__FULL       0x1F0407F0,0xffffffff
+#define LPM_MEM_SISG_SET_5__SISG_SET_5      0x1F0407F0,0x01FFFFFF
+
+#define LPM_MEM_SISG_SET_6__ADDR                  0x1F0407F4
+#define LPM_MEM_SISG_SET_6__EMPTY      0x1F0407F4,0x00000000
+#define LPM_MEM_SISG_SET_6__FULL       0x1F0407F4,0xffffffff
+#define LPM_MEM_SISG_SET_6__SISG_SET_6      0x1F0407F4,0x01FFFFFF
+
+#define LPM_MEM_SISG_CLR_1__ADDR                  0x1F0407F8
+#define LPM_MEM_SISG_CLR_1__EMPTY      0x1F0407F8,0x00000000
+#define LPM_MEM_SISG_CLR_1__FULL       0x1F0407F8,0xffffffff
+#define LPM_MEM_SISG_CLR_1__SISG_CLEAR_1       0x1F0407F8,0x01FFFFFF
+
+#define LPM_MEM_SISG_CLR_2__ADDR                  0x1F0407FC
+#define LPM_MEM_SISG_CLR_2__EMPTY      0x1F0407FC,0x00000000
+#define LPM_MEM_SISG_CLR_2__FULL       0x1F0407FC,0xffffffff
+#define LPM_MEM_SISG_CLR_2__SISG_CLEAR_2       0x1F0407FC,0x01FFFFFF
+
+#define LPM_MEM_SISG_CLR_3__ADDR                  0x1F040800
+#define LPM_MEM_SISG_CLR_3__EMPTY      0x1F040800,0x00000000
+#define LPM_MEM_SISG_CLR_3__FULL       0x1F040800,0xffffffff
+#define LPM_MEM_SISG_CLR_3__SISG_CLEAR_3       0x1F040800,0x01FFFFFF
+
+#define LPM_MEM_SISG_CLR_4__ADDR                  0x1F040804
+#define LPM_MEM_SISG_CLR_4__EMPTY      0x1F040804,0x00000000
+#define LPM_MEM_SISG_CLR_4__FULL       0x1F040804,0xffffffff
+#define LPM_MEM_SISG_CLR_4__SISG_CLEAR_4       0x1F040804,0x01FFFFFF
+
+#define LPM_MEM_SISG_CLR_5__ADDR                  0x1F040808
+#define LPM_MEM_SISG_CLR_5__EMPTY      0x1F040808,0x00000000
+#define LPM_MEM_SISG_CLR_5__FULL       0x1F040808,0xffffffff
+#define LPM_MEM_SISG_CLR_5__SISG_CLEAR_5       0x1F040808,0x01FFFFFF
+
+#define LPM_MEM_SISG_CLR_6__ADDR                  0x1F04080C
+#define LPM_MEM_SISG_CLR_6__EMPTY      0x1F04080C,0x00000000
+#define LPM_MEM_SISG_CLR_6__FULL       0x1F04080C,0xffffffff
+#define LPM_MEM_SISG_CLR_6__SISG_CLEAR_6       0x1F04080C,0x01FFFFFF
+
+#define LPM_MEM_IPU_INT_CTRL_1__ADDR                  0x1F040810
+#define LPM_MEM_IPU_INT_CTRL_1__EMPTY      0x1F040810,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_1__FULL      0x1F040810,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_31              0x1F040810,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_29              0x1F040810,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_28              0x1F040810,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_27              0x1F040810,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_24              0x1F040810,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_23              0x1F040810,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_22              0x1F040810,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_21              0x1F040810,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_20              0x1F040810,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_18              0x1F040810,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_17              0x1F040810,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_15              0x1F040810,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_14              0x1F040810,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_12              0x1F040810,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_11              0x1F040810,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_7      0x1F040810,0x00000080
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_6      0x1F040810,0x00000040
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_5      0x1F040810,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_4      0x1F040810,0x00000010
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_3      0x1F040810,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_2      0x1F040810,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_1      0x1F040810,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_1__IDMAC_EOF_EN_0      0x1F040810,0x00000001
+
+#define LPM_MEM_IPU_INT_CTRL_2__ADDR                  0x1F040814
+#define LPM_MEM_IPU_INT_CTRL_2__EMPTY      0x1F040814,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_2__FULL      0x1F040814,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_52              0x1F040814,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_51              0x1F040814,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_50              0x1F040814,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_49              0x1F040814,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_48              0x1F040814,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_47              0x1F040814,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_46              0x1F040814,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_45              0x1F040814,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_44              0x1F040814,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_43              0x1F040814,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_42              0x1F040814,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_41              0x1F040814,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_40              0x1F040814,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_2__IDMAC_EOF_EN_33              0x1F040814,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_3__ADDR                  0x1F040818
+#define LPM_MEM_IPU_INT_CTRL_3__EMPTY      0x1F040818,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_3__FULL      0x1F040818,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_31      0x1F040818,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_29      0x1F040818,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_28      0x1F040818,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_27      0x1F040818,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_24      0x1F040818,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_23      0x1F040818,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_22      0x1F040818,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_21      0x1F040818,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_20      0x1F040818,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_18      0x1F040818,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_17      0x1F040818,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_15      0x1F040818,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_14      0x1F040818,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_12      0x1F040818,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_11      0x1F040818,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_7       0x1F040818,0x00000080
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_6       0x1F040818,0x00000040
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_5       0x1F040818,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_4       0x1F040818,0x00000010
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_3       0x1F040818,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_2       0x1F040818,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_1       0x1F040818,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_3__IDMAC_NFACK_EN_0       0x1F040818,0x00000001
+
+#define LPM_MEM_IPU_INT_CTRL_4__ADDR                  0x1F04081C
+#define LPM_MEM_IPU_INT_CTRL_4__EMPTY      0x1F04081C,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_4__FULL      0x1F04081C,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_52      0x1F04081C,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_51      0x1F04081C,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_50      0x1F04081C,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_49      0x1F04081C,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_48      0x1F04081C,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_47      0x1F04081C,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_46      0x1F04081C,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_45      0x1F04081C,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_44      0x1F04081C,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_43      0x1F04081C,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_42      0x1F04081C,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_41      0x1F04081C,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_40      0x1F04081C,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_4__IDMAC_NFACK_EN_33      0x1F04081C,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_5__ADDR                  0x1F040820
+#define LPM_MEM_IPU_INT_CTRL_5__EMPTY      0x1F040820,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_5__FULL      0x1F040820,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_31      0x1F040820,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_29      0x1F040820,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_28      0x1F040820,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_27      0x1F040820,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_24      0x1F040820,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_23      0x1F040820,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_22      0x1F040820,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_21      0x1F040820,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_20      0x1F040820,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_18      0x1F040820,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_17      0x1F040820,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_15      0x1F040820,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_14      0x1F040820,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_12      0x1F040820,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_11      0x1F040820,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_7      0x1F040820,0x00000080
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_6      0x1F040820,0x00000040
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_5      0x1F040820,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_4      0x1F040820,0x00000010
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_3      0x1F040820,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_2      0x1F040820,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_1      0x1F040820,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_5__IDMAC_NFB4EOF_EN_0      0x1F040820,0x00000001
+
+#define LPM_MEM_IPU_INT_CTRL_6__ADDR                  0x1F040824
+#define LPM_MEM_IPU_INT_CTRL_6__EMPTY      0x1F040824,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_6__FULL      0x1F040824,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_52      0x1F040824,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_51      0x1F040824,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_50      0x1F040824,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_49      0x1F040824,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_48      0x1F040824,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_47      0x1F040824,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_46      0x1F040824,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_45      0x1F040824,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_44      0x1F040824,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_43      0x1F040824,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_42      0x1F040824,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_41      0x1F040824,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_40      0x1F040824,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_6__IDMAC_NFB4EOF_EN_33      0x1F040824,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_7__ADDR           0x1F040828
+#define LPM_MEM_IPU_INT_CTRL_7__EMPTY          0x1F040828,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_7__FULL           0x1F040828,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_31 0x1F040828,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_29 0x1F040828,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_28 0x1F040828,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_27 0x1F040828,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_24 0x1F040828,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_7__IDMAC_EOS_EN_23 0x1F040828,0x00800000
+
+#define LPM_MEM_IPU_INT_CTRL_8__ADDR           0x1F04082C
+#define LPM_MEM_IPU_INT_CTRL_8__EMPTY          0x1F04082C,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_8__FULL           0x1F04082C,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_52 0x1F04082C,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_51 0x1F04082C,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_44 0x1F04082C,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_43 0x1F04082C,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_42 0x1F04082C,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_41 0x1F04082C,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_8__IDMAC_EOS_EN_33 0x1F04082C,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_9__ADDR                  0x1F040830
+#define LPM_MEM_IPU_INT_CTRL_9__EMPTY      0x1F040830,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_9__FULL      0x1F040830,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_9__CSI1_PUPE_EN      0x1F040830,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_9__CSI0_PUPE_EN      0x1F040830,0x40000000
+#define LPM_MEM_IPU_INT_CTRL_9__ISP_PUPE_EN      0x1F040830,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_9__IC_VF_BUF_OVF_EN       0x1F040830,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_9__IC_ENC_BUF_OVF_EN      0x1F040830,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_9__IC_BAYER_BUF_OVF_EN      0x1F040830,0x04000000
+
+#define LPM_MEM_IPU_INT_CTRL_10__ADDR                  0x1F040834
+#define LPM_MEM_IPU_INT_CTRL_10__EMPTY      0x1F040834,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_10__FULL      0x1F040834,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_10__AXIR_ERR_EN      0x1F040834,0x40000000
+#define LPM_MEM_IPU_INT_CTRL_10__AXIW_ERR_EN      0x1F040834,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_10__NON_PRIVILEGED_ACC_ERR_EN      0x1F040834,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_10__IC_BAYER_FRM_LOST_ERR_EN      0x1F040834,0x04000000
+#define LPM_MEM_IPU_INT_CTRL_10__IC_ENC_FRM_LOST_ERR_EN              0x1F040834,0x02000000
+#define LPM_MEM_IPU_INT_CTRL_10__IC_VF_FRM_LOST_ERR_EN      0x1F040834,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_10__DI1_TIME_OUT_ERR_EN      0x1F040834,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_10__DI0_TIME_OUT_ERR_EN      0x1F040834,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_10__DI1_SYNC_DISP_ERR_EN      0x1F040834,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_10__DI0_SYNC_DISP_ERR_EN      0x1F040834,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_6_EN      0x1F040834,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_2_EN      0x1F040834,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_10__DC_TEARING_ERR_1_EN      0x1F040834,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_10__ISP_RAM_HIST_OF_EN      0x1F040834,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_10__ISP_RAM_ST_OF_EN      0x1F040834,0x00000010
+#define LPM_MEM_IPU_INT_CTRL_10__SMFC3_FRM_LOST_EN      0x1F040834,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_10__SMFC2_FRM_LOST_EN      0x1F040834,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_10__SMFC1_FRM_LOST_EN      0x1F040834,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_10__SMFC0_FRM_LOST_EN      0x1F040834,0x00000001
+
+#define LPM_MEM_IPU_INT_CTRL_11__ADDR                  0x1F040838
+#define LPM_MEM_IPU_INT_CTRL_11__EMPTY      0x1F040838,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_11__FULL      0x1F040838,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_22      0x1F040838,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_21      0x1F040838,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_20      0x1F040838,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_12      0x1F040838,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_11      0x1F040838,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_5      0x1F040838,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_3      0x1F040838,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_2      0x1F040838,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_1      0x1F040838,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_11__IDMAC_EOBND_EN_0      0x1F040838,0x00000001
+
+#define LPM_MEM_IPU_INT_CTRL_12__ADDR                  0x1F04083C
+#define LPM_MEM_IPU_INT_CTRL_12__EMPTY      0x1F04083C,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_12__FULL      0x1F04083C,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_50      0x1F04083C,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_49      0x1F04083C,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_48      0x1F04083C,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_47      0x1F04083C,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_46      0x1F04083C,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_12__IDMAC_EOBND_EN_45      0x1F04083C,0x00002000
+
+#define LPM_MEM_IPU_INT_CTRL_13__ADDR                  0x1F040840
+#define LPM_MEM_IPU_INT_CTRL_13__EMPTY      0x1F040840,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_13__FULL      0x1F040840,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_31              0x1F040840,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_29              0x1F040840,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_28              0x1F040840,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_27              0x1F040840,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_24              0x1F040840,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_23              0x1F040840,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_22              0x1F040840,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_21              0x1F040840,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_20              0x1F040840,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_18              0x1F040840,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_17              0x1F040840,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_15              0x1F040840,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_14              0x1F040840,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_12              0x1F040840,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_11              0x1F040840,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_7      0x1F040840,0x00000080
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_6      0x1F040840,0x00000040
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_5      0x1F040840,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_4      0x1F040840,0x00000010
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_3      0x1F040840,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_2      0x1F040840,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_1      0x1F040840,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_13__IDMAC_TH_EN_0      0x1F040840,0x00000001
+
+#define LPM_MEM_IPU_INT_CTRL_14__ADDR                  0x1F040844
+#define LPM_MEM_IPU_INT_CTRL_14__EMPTY      0x1F040844,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_14__FULL      0x1F040844,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_52              0x1F040844,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_51              0x1F040844,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_50              0x1F040844,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_49              0x1F040844,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_48              0x1F040844,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_47              0x1F040844,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_46              0x1F040844,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_45              0x1F040844,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_44              0x1F040844,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_43              0x1F040844,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_42              0x1F040844,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_41              0x1F040844,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_40              0x1F040844,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_14__IDMAC_TH_EN_33              0x1F040844,0x00000002
+
+#define LPM_MEM_IPU_INT_CTRL_15__ADDR                  0x1F040848
+#define LPM_MEM_IPU_INT_CTRL_15__EMPTY      0x1F040848,0x00000000
+#define LPM_MEM_IPU_INT_CTRL_15__FULL      0x1F040848,0xffffffff
+#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_8_EN      0x1F040848,0x80000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI1_CNT_EN_PRE_3_EN      0x1F040848,0x40000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI1_DISP_CLK_EN_PRE_EN              0x1F040848,0x20000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_10_EN      0x1F040848,0x10000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_9_EN      0x1F040848,0x08000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_8_EN      0x1F040848,0x04000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_7_EN      0x1F040848,0x02000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_6_EN      0x1F040848,0x01000000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_5_EN      0x1F040848,0x00800000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_4_EN      0x1F040848,0x00400000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_3_EN      0x1F040848,0x00200000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_2_EN      0x1F040848,0x00100000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_CNT_EN_PRE_1_EN      0x1F040848,0x00080000
+#define LPM_MEM_IPU_INT_CTRL_15__DI0_DISP_CLK_EN_PRE_EN              0x1F040848,0x00040000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_ASYNC_STOP_EN      0x1F040848,0x00020000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_DP_START_EN              0x1F040848,0x00010000
+#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_1_EN      0x1F040848,0x00008000
+#define LPM_MEM_IPU_INT_CTRL_15__DI_VSYNC_PRE_0_EN      0x1F040848,0x00004000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_6_EN      0x1F040848,0x00002000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_4_EN      0x1F040848,0x00001000
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_3_EN      0x1F040848,0x00000800
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_2_EN      0x1F040848,0x00000400
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_1_EN      0x1F040848,0x00000200
+#define LPM_MEM_IPU_INT_CTRL_15__DC_FC_0_EN      0x1F040848,0x00000100
+#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_BRAKE_EN       0x1F040848,0x00000080
+#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_BRAKE_EN              0x1F040848,0x00000040
+#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_END_EN      0x1F040848,0x00000020
+#define LPM_MEM_IPU_INT_CTRL_15__DP_ASF_START_EN       0x1F040848,0x00000010
+#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_END_EN      0x1F040848,0x00000008
+#define LPM_MEM_IPU_INT_CTRL_15__DP_SF_START_EN              0x1F040848,0x00000004
+#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING2_INT_EN      0x1F040848,0x00000002
+#define LPM_MEM_IPU_INT_CTRL_15__IPU_SNOOPING1_INT_EN      0x1F040848,0x00000001
+
+#define LPM_MEM_IPU_SDMA_EVENT_1__ADDR                  0x1F04084C
+#define LPM_MEM_IPU_SDMA_EVENT_1__EMPTY              0x1F04084C,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__FULL      0x1F04084C,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_31      0x1F04084C,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_29      0x1F04084C,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_28      0x1F04084C,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_27      0x1F04084C,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_24      0x1F04084C,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_23      0x1F04084C,0x00800000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_22      0x1F04084C,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_21      0x1F04084C,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_20      0x1F04084C,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_18      0x1F04084C,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_17      0x1F04084C,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_15      0x1F04084C,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_14      0x1F04084C,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_12      0x1F04084C,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_11      0x1F04084C,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_7      0x1F04084C,0x00000080
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_6      0x1F04084C,0x00000040
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_5      0x1F04084C,0x00000020
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_4      0x1F04084C,0x00000010
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_3      0x1F04084C,0x00000008
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_2      0x1F04084C,0x00000004
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_1      0x1F04084C,0x00000002
+#define LPM_MEM_IPU_SDMA_EVENT_1__IDMAC_EOF_SDMA_EN_0      0x1F04084C,0x00000001
+
+#define LPM_MEM_IPU_SDMA_EVENT_2__ADDR                  0x1F040850
+#define LPM_MEM_IPU_SDMA_EVENT_2__EMPTY              0x1F040850,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_2__FULL      0x1F040850,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_52      0x1F040850,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_51      0x1F040850,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_50      0x1F040850,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_49      0x1F040850,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_48      0x1F040850,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_47      0x1F040850,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_46      0x1F040850,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_45      0x1F040850,0x00002000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_44      0x1F040850,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_43      0x1F040850,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_42      0x1F040850,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_41      0x1F040850,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_40      0x1F040850,0x00000100
+#define LPM_MEM_IPU_SDMA_EVENT_2__IDMAC_EOF_SDMA_EN_33      0x1F040850,0x00000002
+
+#define LPM_MEM_IPU_SDMA_EVENT_3__ADDR                  0x1F040854
+#define LPM_MEM_IPU_SDMA_EVENT_3__EMPTY              0x1F040854,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__FULL      0x1F040854,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_31       0x1F040854,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_29       0x1F040854,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_28       0x1F040854,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_27       0x1F040854,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_24       0x1F040854,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_23       0x1F040854,0x00800000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_22       0x1F040854,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_21       0x1F040854,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_20       0x1F040854,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_18       0x1F040854,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_17       0x1F040854,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_15       0x1F040854,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_14       0x1F040854,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_12       0x1F040854,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_11       0x1F040854,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_7              0x1F040854,0x00000080
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_6              0x1F040854,0x00000040
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_5              0x1F040854,0x00000020
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_4              0x1F040854,0x00000010
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_3              0x1F040854,0x00000008
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_2              0x1F040854,0x00000004
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_1              0x1F040854,0x00000002
+#define LPM_MEM_IPU_SDMA_EVENT_3__IDMAC_NFACK_SDMA_EN_0              0x1F040854,0x00000001
+
+#define LPM_MEM_IPU_SDMA_EVENT_4__ADDR                  0x1F040858
+#define LPM_MEM_IPU_SDMA_EVENT_4__EMPTY              0x1F040858,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_4__FULL      0x1F040858,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_52       0x1F040858,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_51       0x1F040858,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_50       0x1F040858,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_49       0x1F040858,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_48       0x1F040858,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_47       0x1F040858,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_46       0x1F040858,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_45       0x1F040858,0x00002000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_44       0x1F040858,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_43       0x1F040858,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_42       0x1F040858,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_41       0x1F040858,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_40       0x1F040858,0x00000100
+#define LPM_MEM_IPU_SDMA_EVENT_4__IDMAC_NFACK_SDMA_EN_33       0x1F040858,0x00000002
+
+#define LPM_MEM_IPU_SDMA_EVENT_7__ADDR                0x1F04085C
+#define LPM_MEM_IPU_SDMA_EVENT_7__EMPTY                       0x1F04085C,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__FULL                0x1F04085C,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_31 0x1F04085C,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_29 0x1F04085C,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_28 0x1F04085C,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_27 0x1F04085C,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_24 0x1F04085C,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_7__IDMAC_EOS_SDMA_EN_23 0x1F04085C,0x00800000
+
+#define LPM_MEM_IPU_SDMA_EVENT_8__ADDR                0x1F040860
+#define LPM_MEM_IPU_SDMA_EVENT_8__EMPTY                       0x1F040860,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_8__FULL                0x1F040860,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_52 0x1F040860,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_51 0x1F040860,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_44 0x1F040860,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_43 0x1F040860,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_42 0x1F040860,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_41 0x1F040860,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_8__IDMAC_EOS_SDMA_EN_32 0x1F040860,0x00000002
+
+#define LPM_MEM_IPU_SDMA_EVENT_11__ADDR                          0x1F040864
+#define LPM_MEM_IPU_SDMA_EVENT_11__EMPTY       0x1F040864,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_11__FULL              0x1F040864,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_22      0x1F040864,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_21      0x1F040864,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_20      0x1F040864,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_12      0x1F040864,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_11      0x1F040864,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_5       0x1F040864,0x00000020
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_3       0x1F040864,0x00000008
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_2       0x1F040864,0x00000004
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_1       0x1F040864,0x00000002
+#define LPM_MEM_IPU_SDMA_EVENT_11__IDMAC_EOBND_SDMA_EN_0       0x1F040864,0x00000001
+
+#define LPM_MEM_IPU_SDMA_EVENT_12__ADDR                          0x1F040868
+#define LPM_MEM_IPU_SDMA_EVENT_12__EMPTY       0x1F040868,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_12__FULL              0x1F040868,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_50      0x1F040868,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_49      0x1F040868,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_48      0x1F040868,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_47      0x1F040868,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_46      0x1F040868,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_12__IDMAC_EOBND_SDMA_EN_45      0x1F040868,0x00002000
+
+#define LPM_MEM_IPU_SDMA_EVENT_13__ADDR                          0x1F04086C
+#define LPM_MEM_IPU_SDMA_EVENT_13__EMPTY       0x1F04086C,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__FULL              0x1F04086C,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_31      0x1F04086C,0x80000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_29      0x1F04086C,0x20000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_28      0x1F04086C,0x10000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_27      0x1F04086C,0x08000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_24      0x1F04086C,0x01000000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_23      0x1F04086C,0x00800000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_22      0x1F04086C,0x00400000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_21      0x1F04086C,0x00200000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_20      0x1F04086C,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_18      0x1F04086C,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_17      0x1F04086C,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_15      0x1F04086C,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_14      0x1F04086C,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_12      0x1F04086C,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_11      0x1F04086C,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_7      0x1F04086C,0x00000080
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_6      0x1F04086C,0x00000040
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_5      0x1F04086C,0x00000020
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_4      0x1F04086C,0x00000010
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_3      0x1F04086C,0x00000008
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_2      0x1F04086C,0x00000004
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_1      0x1F04086C,0x00000002
+#define LPM_MEM_IPU_SDMA_EVENT_13__IDMAC_TH_SDMA_EN_0      0x1F04086C,0x00000001
+
+#define LPM_MEM_IPU_SDMA_EVENT_14__ADDR                          0x1F040870
+#define LPM_MEM_IPU_SDMA_EVENT_14__EMPTY       0x1F040870,0x00000000
+#define LPM_MEM_IPU_SDMA_EVENT_14__FULL              0x1F040870,0xffffffff
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_52      0x1F040870,0x00100000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_51      0x1F040870,0x00080000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_50      0x1F040870,0x00040000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_49      0x1F040870,0x00020000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_48      0x1F040870,0x00010000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_47      0x1F040870,0x00008000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_46      0x1F040870,0x00004000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_45      0x1F040870,0x00002000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_44      0x1F040870,0x00001000
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_43      0x1F040870,0x00000800
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_42      0x1F040870,0x00000400
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_41      0x1F040870,0x00000200
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_40      0x1F040870,0x00000100
+#define LPM_MEM_IPU_SDMA_EVENT_14__IDMAC_TH_SDMA_EN_33      0x1F040870,0x00000002
+
+#define LPM_MEM_IPU_SRM_PRI1__ADDR                  0x1F000874
+#define LPM_MEM_IPU_SRM_PRI1__EMPTY      0x1F000874,0x00000000
+#define LPM_MEM_IPU_SRM_PRI1__FULL      0x1F000874,0xffffffff
+#define LPM_MEM_IPU_SRM_PRI1__ISP_SRM_MODE      0x1F000874,0x00180000
+#define LPM_MEM_IPU_SRM_PRI1__ISP_SRM_PRI      0x1F000874,0x00070000
+#define LPM_MEM_IPU_SRM_PRI1__CSI0_SRM_MODE      0x1F000874,0x00001800
+#define LPM_MEM_IPU_SRM_PRI1__CSI0_SRM_PRI      0x1F000874,0x00000700
+#define LPM_MEM_IPU_SRM_PRI1__CSI1_SRM_MODE      0x1F000874,0x00000018
+#define LPM_MEM_IPU_SRM_PRI1__CSI1_SRM_PRI      0x1F000874,0x00000007
+
+#define LPM_MEM_IPU_SRM_PRI2__ADDR                  0x1F000878
+#define LPM_MEM_IPU_SRM_PRI2__EMPTY      0x1F000878,0x00000000
+#define LPM_MEM_IPU_SRM_PRI2__FULL      0x1F000878,0xffffffff
+#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_MODE      0x1F000878,0x18000000
+#define LPM_MEM_IPU_SRM_PRI2__DI1_SRM_PRI      0x1F000878,0x07000000
+#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_MODE      0x1F000878,0x00180000
+#define LPM_MEM_IPU_SRM_PRI2__DI0_SRM_PRI      0x1F000878,0x00070000
+#define LPM_MEM_IPU_SRM_PRI2__DC_6_SRM_MODE      0x1F000878,0x0000C000
+#define LPM_MEM_IPU_SRM_PRI2__DC_2_SRM_MODE      0x1F000878,0x00003000
+#define LPM_MEM_IPU_SRM_PRI2__DC_SRM_PRI       0x1F000878,0x00000E00
+#define LPM_MEM_IPU_SRM_PRI2__DP_A1_SRM_MODE      0x1F000878,0x00000180
+#define LPM_MEM_IPU_SRM_PRI2__DP_A0_SRM_MODE      0x1F000878,0x00000060
+#define LPM_MEM_IPU_SRM_PRI2__DP_S_SRM_MODE      0x1F000878,0x00000018
+#define LPM_MEM_IPU_SRM_PRI2__DP_SRM_PRI       0x1F000878,0x00000007
+
+#define LPM_MEM_IPU_FS_PROC_FLOW1__ADDR                          0x1F04087C
+#define LPM_MEM_IPU_FS_PROC_FLOW1__EMPTY       0x1F04087C,0x00000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__FULL              0x1F04087C,0xffffffff
+#define LPM_MEM_IPU_FS_PROC_FLOW1__VF_IN_VALID      0x1F04087C,0x80000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__ENC_IN_VALID              0x1F04087C,0x40000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PRP_SRC_SEL      0x1F04087C,0x0F000000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__ISP_SRC_SEL      0x1F04087C,0x00F00000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_ROT_SRC_SEL      0x1F04087C,0x000F0000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PP_SRC_SEL      0x1F04087C,0x0000F000
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPVF_ROT_SRC_SEL      0x1F04087C,0x00000F00
+#define LPM_MEM_IPU_FS_PROC_FLOW1__ALT_ISP_SRC_SEL      0x1F04087C,0x000000F0
+#define LPM_MEM_IPU_FS_PROC_FLOW1__PRPENC_ROT_SRC_SEL      0x1F04087C,0x0000000F
+
+#define LPM_MEM_IPU_FS_PROC_FLOW2__ADDR                          0x1F040880
+#define LPM_MEM_IPU_FS_PROC_FLOW2__EMPTY       0x1F040880,0x00000000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__FULL              0x1F040880,0xffffffff
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ALT_DEST_SEL      0x1F040880,0xF0000000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_DEST_SEL              0x1F040880,0x0F000000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPENC_ROT_DEST_SEL      0x1F040880,0x00F00000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_ROT_DEST_SEL      0x1F040880,0x000F0000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PP_DEST_SEL      0x1F040880,0x0000F000
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_ROT_DEST_SEL      0x1F040880,0x00000F00
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRPVF_DEST_SEL      0x1F040880,0x000000F0
+#define LPM_MEM_IPU_FS_PROC_FLOW2__PRP_ENC_DEST_SEL      0x1F040880,0x0000000F
+
+#define LPM_MEM_IPU_FS_PROC_FLOW3__ADDR                          0x1F040884
+#define LPM_MEM_IPU_FS_PROC_FLOW3__EMPTY       0x1F040884,0x00000000
+#define LPM_MEM_IPU_FS_PROC_FLOW3__FULL              0x1F040884,0xffffffff
+#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC3_DEST_SEL      0x1F040884,0x00003800
+#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC2_DEST_SEL      0x1F040884,0x00000780
+#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC1_DEST_SEL      0x1F040884,0x00000070
+#define LPM_MEM_IPU_FS_PROC_FLOW3__SMFC0_DEST_SEL      0x1F040884,0x0000000F
+
+#define LPM_MEM_IPU_FS_DISP_FLOW1__ADDR                          0x1F040888
+#define LPM_MEM_IPU_FS_DISP_FLOW1__EMPTY       0x1F040888,0x00000000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__FULL              0x1F040888,0xffffffff
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DC1_SRC_SEL      0x1F040888,0x00F00000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DC2_SRC_SEL      0x1F040888,0x000F0000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC1_SRC_SEL      0x1F040888,0x0000F000
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_ASYNC0_SRC_SEL      0x1F040888,0x00000F00
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC1_SRC_SEL      0x1F040888,0x000000F0
+#define LPM_MEM_IPU_FS_DISP_FLOW1__DP_SYNC0_SRC_SEL      0x1F040888,0x0000000F
+
+#define LPM_MEM_IPU_FS_DISP_FLOW2__ADDR                          0x1F04088C
+#define LPM_MEM_IPU_FS_DISP_FLOW2__EMPTY       0x1F04088C,0x00000000
+#define LPM_MEM_IPU_FS_DISP_FLOW2__FULL              0x1F04088C,0xffffffff
+#define LPM_MEM_IPU_FS_DISP_FLOW2__DC2_ALT_SRC_SEL      0x1F04088C,0x000F0000
+#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC0_ALT_SRC_SEL       0x1F04088C,0x000000F0
+#define LPM_MEM_IPU_FS_DISP_FLOW2__DP_ASYNC1_ALT_SRC_SEL       0x1F04088C,0x0000000F
+
+#define LPM_MEM_IPU_SKIP__ADDR                  0x1F040890
+#define LPM_MEM_IPU_SKIP__EMPTY              0x1F040890,0x00000000
+#define LPM_MEM_IPU_SKIP__FULL      0x1F040890,0xffffffff
+#define LPM_MEM_IPU_SKIP__CSI_SKIP_IC_VF       0x1F040890,0x0000F800
+#define LPM_MEM_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_VF      0x1F040890,0x00000700
+#define LPM_MEM_IPU_SKIP__CSI_SKIP_IC_ENC      0x1F040890,0x000000F8
+#define LPM_MEM_IPU_SKIP__CSI_MAX_RATIO_SKIP_IC_ENC      0x1F040890,0x00000007
+
+#define LPM_MEM_IPU_DISP_ALT_CONF__ADDR                          0x1F040894
+#define LPM_MEM_IPU_DISP_ALT_CONF__EMPTY       0x1F040894,0x00000000
+#define LPM_MEM_IPU_DISP_ALT_CONF__FULL              0x1F040894,0xffffffff
+
+#define LPM_MEM_IPU_DISP_GEN__ADDR                  0x1F040898
+#define LPM_MEM_IPU_DISP_GEN__EMPTY      0x1F040898,0x00000000
+#define LPM_MEM_IPU_DISP_GEN__FULL      0x1F040898,0xffffffff
+#define LPM_MEM_IPU_DISP_GEN__DI1_COUNTER_RELEASE      0x1F040898,0x02000000
+#define LPM_MEM_IPU_DISP_GEN__DI0_COUNTER_RELEASE      0x1F040898,0x01000000
+#define LPM_MEM_IPU_DISP_GEN__CSI_VSYNC_DEST      0x1F040898,0x00800000
+#define LPM_MEM_IPU_DISP_GEN__MCU_MAX_BURST_STOP       0x1F040898,0x00400000
+#define LPM_MEM_IPU_DISP_GEN__MCU_T      0x1F040898,0x003C0000
+#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_9      0x1F040898,0x00020000
+#define LPM_MEM_IPU_DISP_GEN__MCU_DI_ID_8      0x1F040898,0x00010000
+#define LPM_MEM_IPU_DISP_GEN__DP_PIPE_CLR      0x1F040898,0x00000040
+#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC1      0x1F040898,0x00000020
+#define LPM_MEM_IPU_DISP_GEN__DP_FG_EN_ASYNC0      0x1F040898,0x00000010
+#define LPM_MEM_IPU_DISP_GEN__DP_ASYNC_DOUBLE_FLOW      0x1F040898,0x00000008
+#define LPM_MEM_IPU_DISP_GEN__DC2_DOUBLE_FLOW      0x1F040898,0x00000004
+#define LPM_MEM_IPU_DISP_GEN__DI1_DUAL_MODE      0x1F040898,0x00000002
+#define LPM_MEM_IPU_DISP_GEN__DI0_DUAL_MODE      0x1F040898,0x00000001
+
+#define LPM_MEM_IPU_DISP_ALT1__ADDR                  0x1F04089C
+#define LPM_MEM_IPU_DISP_ALT1__EMPTY      0x1F04089C,0x00000000
+#define LPM_MEM_IPU_DISP_ALT1__FULL      0x1F04089C,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT1__SEL_ALT_0       0x1F04089C,0xF0000000
+#define LPM_MEM_IPU_DISP_ALT1__STEP_REPEAT_ALT_0       0x1F04089C,0x0FFF0000
+#define LPM_MEM_IPU_DISP_ALT1__CNT_AUTO_RELOAD_ALT_0      0x1F04089C,0x00008000
+#define LPM_MEM_IPU_DISP_ALT1__CNT_CLR_SEL_ALT_0       0x1F04089C,0x00007000
+#define LPM_MEM_IPU_DISP_ALT1__RUN_VALUE_M1_ALT_0      0x1F04089C,0x00000FFF
+
+#define LPM_MEM_IPU_DISP_ALT2__ADDR                  0x1F0408A0
+#define LPM_MEM_IPU_DISP_ALT2__EMPTY      0x1F0408A0,0x00000000
+#define LPM_MEM_IPU_DISP_ALT2__FULL      0x1F0408A0,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT2__RUN_RESOLUTION_ALT_0      0x1F0408A0,0x00070000
+#define LPM_MEM_IPU_DISP_ALT2__OFFSET_RESOLUTION_ALT_0      0x1F0408A0,0x00007000
+#define LPM_MEM_IPU_DISP_ALT2__OFFSET_VALUE_ALT_0      0x1F0408A0,0x00000FFF
+
+#define LPM_MEM_IPU_DISP_ALT3__ADDR                  0x1F0408A4
+#define LPM_MEM_IPU_DISP_ALT3__EMPTY      0x1F0408A4,0x00000000
+#define LPM_MEM_IPU_DISP_ALT3__FULL      0x1F0408A4,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT3__SEL_ALT_1       0x1F0408A4,0xF0000000
+#define LPM_MEM_IPU_DISP_ALT3__STEP_REPEAT_ALT_1       0x1F0408A4,0x0FFF0000
+#define LPM_MEM_IPU_DISP_ALT3__CNT_AUTO_RELOAD_ALT_1      0x1F0408A4,0x00008000
+#define LPM_MEM_IPU_DISP_ALT3__CNT_CLR_SEL_ALT_1       0x1F0408A4,0x00007000
+#define LPM_MEM_IPU_DISP_ALT3__RUN_VALUE_M1_ALT_1      0x1F0408A4,0x00000FFF
+
+#define LPM_MEM_IPU_DISP_ALT4__ADDR                  0x1F0408A8
+#define LPM_MEM_IPU_DISP_ALT4__EMPTY      0x1F0408A8,0x00000000
+#define LPM_MEM_IPU_DISP_ALT4__FULL      0x1F0408A8,0xffffffff
+#define LPM_MEM_IPU_DISP_ALT4__RUN_RESOLUTION_ALT_1      0x1F0408A8,0x00070000
+#define LPM_MEM_IPU_DISP_ALT4__OFFSET_RESOLUTION_ALT_1      0x1F0408A8,0x00007000
+#define LPM_MEM_IPU_DISP_ALT4__OFFSET_VALUE_ALT_1      0x1F0408A8,0x00000FFF
+
+#define LPM_MEM_IPU_SNOOP__ADDR                          0x1F0408AC
+#define LPM_MEM_IPU_SNOOP__EMPTY       0x1F0408AC,0x00000000
+#define LPM_MEM_IPU_SNOOP__FULL              0x1F0408AC,0xffffffff
+#define LPM_MEM_IPU_SNOOP__SNOOP2_SYNC_BYP      0x1F0408AC,0x00010000
+#define LPM_MEM_IPU_SNOOP__AUTOREF_PER      0x1F0408AC,0x000003FF
+
+#define LPM_MEM_IPU_MEM_RST__ADDR                  0x1F0408B0
+#define LPM_MEM_IPU_MEM_RST__EMPTY      0x1F0408B0,0x00000000
+#define LPM_MEM_IPU_MEM_RST__FULL      0x1F0408B0,0xffffffff
+#define LPM_MEM_IPU_MEM_RST__RST_MEM_START      0x1F0408B0,0x80000000
+#define LPM_MEM_IPU_MEM_RST__RST_MEM_EN              0x1F0408B0,0x007FFFFF
+
+#define LPM_MEM_IPU_PM__ADDR                  0x1F0408B4
+#define LPM_MEM_IPU_PM__EMPTY      0x1F0408B4,0x00000000
+#define LPM_MEM_IPU_PM__FULL      0x1F0408B4,0xffffffff
+#define LPM_MEM_IPU_PM__LPSR_MODE      0x1F0408B4,0x80000000
+#define LPM_MEM_IPU_PM__DI1_SRM_CLOCK_CHANGE_MODE      0x1F0408B4,0x40000000
+#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_1       0x1F0408B4,0x3F800000
+#define LPM_MEM_IPU_PM__DI1_CLK_PERIOD_0       0x1F0408B4,0x007F0000
+#define LPM_MEM_IPU_PM__CLOCK_MODE_STAT              0x1F0408B4,0x00008000
+#define LPM_MEM_IPU_PM__DI0_SRM_CLOCK_CHANGE_MODE      0x1F0408B4,0x00004000
+#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_1       0x1F0408B4,0x00003F80
+#define LPM_MEM_IPU_PM__DI0_CLK_PERIOD_0       0x1F0408B4,0x0000007F
+
+#define LPM_MEM_IPU_GPR__ADDR                    0x1F0408B8
+#define LPM_MEM_IPU_GPR__EMPTY                   0x1F0408B8,0x00000000
+#define LPM_MEM_IPU_GPR__FULL                    0x1F0408B8,0xffffffff
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY1_CLR    0x1F0408B8,0x80000000
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF1_RDY0_CLR    0x1F0408B8,0x40000000
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY1_CLR    0x1F0408B8,0x20000000
+#define LPM_MEM_IPU_GPR__IPU_CH_BUF0_RDY0_CLR    0x1F0408B8,0x10000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY1_CLR 0x1F0408B8,0x08000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF1_RDY0_CLR 0x1F0408B8,0x04000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY1_CLR 0x1F0408B8,0x02000000
+#define LPM_MEM_IPU_GPR__IPU_ALT_CH_BUF0_RDY0_CLR 0x1F0408B8,0x01000000
+#define LPM_MEM_IPU_GPR__IPU_GP23                0x1F0408B8,0x00800000
+#define LPM_MEM_IPU_GPR__IPU_GP22                0x1F0408B8,0x00400000
+#define LPM_MEM_IPU_GPR__IPU_GP21                0x1F0408B8,0x00200000
+#define LPM_MEM_IPU_GPR__IPU_GP20                0x1F0408B8,0x00100000
+#define LPM_MEM_IPU_GPR__IPU_GP19                0x1F0408B8,0x00080000
+#define LPM_MEM_IPU_GPR__IPU_GP18                0x1F0408B8,0x00040000
+#define LPM_MEM_IPU_GPR__IPU_GP17                0x1F0408B8,0x00020000
+#define LPM_MEM_IPU_GPR__IPU_GP16                0x1F0408B8,0x00010000
+#define LPM_MEM_IPU_GPR__IPU_GP15                0x1F0408B8,0x00008000
+#define LPM_MEM_IPU_GPR__IPU_GP14                0x1F0408B8,0x00004000
+#define LPM_MEM_IPU_GPR__IPU_GP13                0x1F0408B8,0x00002000
+#define LPM_MEM_IPU_GPR__IPU_GP12                0x1F0408B8,0x00001000
+#define LPM_MEM_IPU_GPR__IPU_GP11                0x1F0408B8,0x00000800
+#define LPM_MEM_IPU_GPR__IPU_GP10                0x1F0408B8,0x00000400
+#define LPM_MEM_IPU_GPR__IPU_GP9                 0x1F0408B8,0x00000200
+#define LPM_MEM_IPU_GPR__IPU_GP8                 0x1F0408B8,0x00000100
+#define LPM_MEM_IPU_GPR__IPU_GP7                 0x1F0408B8,0x00000080
+#define LPM_MEM_IPU_GPR__IPU_GP6                 0x1F0408B8,0x00000040
+#define LPM_MEM_IPU_GPR__IPU_GP5                 0x1F0408B8,0x00000020
+#define LPM_MEM_IPU_GPR__IPU_GP4                 0x1F0408B8,0x00000010
+#define LPM_MEM_IPU_GPR__IPU_GP3                 0x1F0408B8,0x00000008
+#define LPM_MEM_IPU_GPR__IPU_GP2                 0x1F0408B8,0x00000004
+#define LPM_MEM_IPU_GPR__IPU_GP1                 0x1F0408B8,0x00000002
+#define LPM_MEM_IPU_GPR__IPU_GP0                 0x1F0408B8,0x00000001
+
+#define LPM_MEM_IC_CONF__ADDR                  0x1F0408BC
+#define LPM_MEM_IC_CONF__EMPTY                 0x1F0408BC,0x00000000
+#define LPM_MEM_IC_CONF__FULL                  0x1F0408BC,0xffffffff
+#define LPM_MEM_IC_CONF__CSI_MEM_WR_EN         0x1F0408BC,0x80000000
+#define LPM_MEM_IC_CONF__RWS_EN                        0x1F0408BC,0x40000000
+#define LPM_MEM_IC_CONF__IC_KEY_COLOR_EN       0x1F0408BC,0x20000000
+#define LPM_MEM_IC_CONF__IC_GLB_LOC_A          0x1F0408BC,0x10000000
+#define LPM_MEM_IC_CONF__PP_ROT_EN             0x1F0408BC,0x00100000
+#define LPM_MEM_IC_CONF__PP_CMB                        0x1F0408BC,0x00080000
+#define LPM_MEM_IC_CONF__PP_CSC2               0x1F0408BC,0x00040000
+#define LPM_MEM_IC_CONF__PP_CSC1               0x1F0408BC,0x00020000
+#define LPM_MEM_IC_CONF__PP_EN                 0x1F0408BC,0x00010000
+#define LPM_MEM_IC_CONF__PRPVF_ROT_EN          0x1F0408BC,0x00001000
+#define LPM_MEM_IC_CONF__PRPVF_CMB             0x1F0408BC,0x00000800
+#define LPM_MEM_IC_CONF__PRPVF_CSC2            0x1F0408BC,0x00000400
+#define LPM_MEM_IC_CONF__PRPVF_CSC1            0x1F0408BC,0x00000200
+#define LPM_MEM_IC_CONF__PRPVF_EN              0x1F0408BC,0x00000100
+#define LPM_MEM_IC_CONF__PRPENC_ROT_EN         0x1F0408BC,0x00000004
+#define LPM_MEM_IC_CONF__PRPENC_CSC1           0x1F0408BC,0x00000002
+#define LPM_MEM_IC_CONF__PRPENC_EN             0x1F0408BC,0x00000001
+
+#define LPM_MEM_IC_PRP_ENC_RSC__ADDR           0x1F0408C0
+#define LPM_MEM_IC_PRP_ENC_RSC__EMPTY          0x1F0408C0,0x00000000
+#define LPM_MEM_IC_PRP_ENC_RSC__FULL           0x1F0408C0,0xffffffff
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_V  0x1F0408C0,0xC0000000
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_V  0x1F0408C0,0x3FFF0000
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_DS_R_H  0x1F0408C0,0x0000C000
+#define LPM_MEM_IC_PRP_ENC_RSC__PRPENC_RS_R_H  0x1F0408C0,0x00003FFF
+
+#define LPM_MEM_IC_PRP_VF_RSC__ADDR            0x1F0408C4
+#define LPM_MEM_IC_PRP_VF_RSC__EMPTY           0x1F0408C4,0x00000000
+#define LPM_MEM_IC_PRP_VF_RSC__FULL            0x1F0408C4,0xffffffff
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_V    0x1F0408C4,0xC0000000
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_V    0x1F0408C4,0x3FFF0000
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_DS_R_H    0x1F0408C4,0x0000C000
+#define LPM_MEM_IC_PRP_VF_RSC__PRPVF_RS_R_H    0x1F0408C4,0x00003FFF
+
+#define LPM_MEM_IC_PP_RSC__ADDR                        0x1F0408C8
+#define LPM_MEM_IC_PP_RSC__EMPTY               0x1F0408C8,0x00000000
+#define LPM_MEM_IC_PP_RSC__FULL                        0x1F0408C8,0xffffffff
+#define LPM_MEM_IC_PP_RSC__PP_DS_R_V           0x1F0408C8,0xC0000000
+#define LPM_MEM_IC_PP_RSC__PP_RS_R_V           0x1F0408C8,0x3FFF0000
+#define LPM_MEM_IC_PP_RSC__PP_DS_R_H           0x1F0408C8,0x0000C000
+#define LPM_MEM_IC_PP_RSC__PP_RS_R_H           0x1F0408C8,0x00003FFF
+
+#define LPM_MEM_IC_CMBP_1__ADDR                        0x1F0408CC
+#define LPM_MEM_IC_CMBP_1__EMPTY               0x1F0408CC,0x00000000
+#define LPM_MEM_IC_CMBP_1__FULL                        0x1F0408CC,0xffffffff
+#define LPM_MEM_IC_CMBP_1__IC_PP_ALPHA_V       0x1F0408CC,0x0000FF00
+#define LPM_MEM_IC_CMBP_1__IC_PRPVF_ALPHA_V    0x1F0408CC,0x000000FF
+
+#define LPM_MEM_IC_CMBP_2__ADDR                        0x1F0408D0
+#define LPM_MEM_IC_CMBP_2__EMPTY               0x1F0408D0,0x00000000
+#define LPM_MEM_IC_CMBP_2__FULL                        0x1F0408D0,0xffffffff
+#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_R      0x1F0408D0,0x00FF0000
+#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_G      0x1F0408D0,0x0000FF00
+#define LPM_MEM_IC_CMBP_2__IC_KEY_COLOR_B      0x1F0408D0,0x000000FF
+
+#define LPM_MEM_IC_IDMAC_1__ADDR               0x1F0408D4
+#define LPM_MEM_IC_IDMAC_1__EMPTY              0x1F0408D4,0x00000000
+#define LPM_MEM_IC_IDMAC_1__FULL               0x1F0408D4,0xffffffff
+#define LPM_MEM_IC_IDMAC_1__ALT_CB7_BURST_16   0x1F0408D4,0x02000000
+#define LPM_MEM_IC_IDMAC_1__ALT_CB6_BURST_16   0x1F0408D4,0x01000000
+#define LPM_MEM_IC_IDMAC_1__T3_FLIP_RS      0x1F0408D4,0x00400000
+#define LPM_MEM_IC_IDMAC_1__T2_FLIP_RS      0x1F0408D4,0x00200000
+#define LPM_MEM_IC_IDMAC_1__T1_FLIP_RS      0x1F0408D4,0x00100000
+#define LPM_MEM_IC_IDMAC_1__T3_FLIP_UD         0x1F0408D4,0x00080000
+#define LPM_MEM_IC_IDMAC_1__T3_FLIP_LR         0x1F0408D4,0x00040000
+#define LPM_MEM_IC_IDMAC_1__T3_ROT             0x1F0408D4,0x00020000
+#define LPM_MEM_IC_IDMAC_1__T2_FLIP_UD         0x1F0408D4,0x00010000
+#define LPM_MEM_IC_IDMAC_1__T2_FLIP_LR         0x1F0408D4,0x00008000
+#define LPM_MEM_IC_IDMAC_1__T2_ROT             0x1F0408D4,0x00004000
+#define LPM_MEM_IC_IDMAC_1__T1_FLIP_UD         0x1F0408D4,0x00002000
+#define LPM_MEM_IC_IDMAC_1__T1_FLIP_LR         0x1F0408D4,0x00001000
+#define LPM_MEM_IC_IDMAC_1__T1_ROT             0x1F0408D4,0x00000800
+#define LPM_MEM_IC_IDMAC_1__CB7_BURST_16       0x1F0408D4,0x00000080
+#define LPM_MEM_IC_IDMAC_1__CB6_BURST_16       0x1F0408D4,0x00000040
+#define LPM_MEM_IC_IDMAC_1__CB5_BURST_16       0x1F0408D4,0x00000020
+#define LPM_MEM_IC_IDMAC_1__CB4_BURST_16       0x1F0408D4,0x00000010
+#define LPM_MEM_IC_IDMAC_1__CB3_BURST_16       0x1F0408D4,0x00000008
+#define LPM_MEM_IC_IDMAC_1__CB2_BURST_16       0x1F0408D4,0x00000004
+#define LPM_MEM_IC_IDMAC_1__CB1_BURST_16       0x1F0408D4,0x00000002
+#define LPM_MEM_IC_IDMAC_1__CB0_BURST_16       0x1F0408D4,0x00000001
+
+#define LPM_MEM_IC_IDMAC_2__ADDR               0x1F0408D8
+#define LPM_MEM_IC_IDMAC_2__EMPTY              0x1F0408D8,0x00000000
+#define LPM_MEM_IC_IDMAC_2__FULL               0x1F0408D8,0xffffffff
+#define LPM_MEM_IC_IDMAC_2__T3_FR_HEIGHT       0x1F0408D8,0x3FF00000
+#define LPM_MEM_IC_IDMAC_2__T2_FR_HEIGHT       0x1F0408D8,0x000FFC00
+#define LPM_MEM_IC_IDMAC_2__T1_FR_HEIGHT       0x1F0408D8,0x000003FF
+
+#define LPM_MEM_IC_IDMAC_3__ADDR               0x1F0408DC
+#define LPM_MEM_IC_IDMAC_3__EMPTY              0x1F0408DC,0x00000000
+#define LPM_MEM_IC_IDMAC_3__FULL               0x1F0408DC,0xffffffff
+#define LPM_MEM_IC_IDMAC_3__T3_FR_WIDTH                0x1F0408DC,0x3FF00000
+#define LPM_MEM_IC_IDMAC_3__T2_FR_WIDTH                0x1F0408DC,0x000FFC00
+#define LPM_MEM_IC_IDMAC_3__T1_FR_WIDTH                0x1F0408DC,0x000003FF
+
+#define LPM_MEM_IC_IDMAC_4__ADDR                 0x1F0408E0
+#define LPM_MEM_IC_IDMAC_4__EMPTY                0x1F0408E0,0x00000000
+#define LPM_MEM_IC_IDMAC_4__FULL                 0x1F0408E0,0xffffffff
+#define LPM_MEM_IC_IDMAC_4__RM_BRDG_MAX_RQ       0x1F0408E0,0x0000F000
+#define LPM_MEM_IC_IDMAC_4__IBM_BRDG_MAX_RQ      0x1F0408E0,0x00000F00
+#define LPM_MEM_IC_IDMAC_4__MPM_DMFC_BRDG_MAX_RQ  0x1F0408E0,0x000000F0
+#define LPM_MEM_IC_IDMAC_4__MPM_RW_BRDG_MAX_RQ   0x1F0408E0,0x0000000F
+
+#endif
diff --git a/packages/devs/ipu/arm/imx/v1_0/include/rgb2ipt_lut.h b/packages/devs/ipu/arm/imx/v1_0/include/rgb2ipt_lut.h
new file mode 100644 (file)
index 0000000..23a1986
--- /dev/null
@@ -0,0 +1,65545 @@
+#ifndef __RGB2IPT_H__
+#define __RGB2IPT_H__
+
+typedef unsigned char Mrgb2ipt[65536][3];
+
+
+Mrgb2ipt RGB2IPT0 = {
+{80, 104, 119},
+{90, 101, 123},
+{106, 94, 129},
+{124, 87, 135},
+{141, 81, 140},
+{158, 74, 144},
+{175, 68, 149},
+{189, 62, 152},
+{81, 105, 120},
+{91, 101, 124},
+{107, 94, 129},
+{124, 87, 135},
+{141, 81, 140},
+{158, 74, 144},
+{175, 68, 149},
+{189, 62, 152},
+{82, 105, 120},
+{91, 101, 124},
+{107, 95, 129},
+{124, 88, 135},
+{142, 81, 140},
+{159, 74, 145},
+{175, 68, 149},
+{190, 63, 152},
+{83, 106, 120},
+{93, 102, 124},
+{108, 95, 130},
+{125, 88, 135},
+{142, 81, 140},
+{159, 75, 145},
+{176, 68, 149},
+{190, 63, 152},
+{85, 106, 121},
+{94, 102, 124},
+{109, 96, 130},
+{126, 88, 135},
+{143, 82, 140},
+{160, 75, 145},
+{177, 68, 149},
+{191, 63, 152},
+{87, 107, 121},
+{96, 103, 125},
+{111, 96, 130},
+{127, 89, 135},
+{144, 82, 140},
+{161, 75, 145},
+{177, 69, 149},
+{191, 63, 152},
+{89, 108, 122},
+{98, 104, 125},
+{113, 97, 130},
+{129, 90, 135},
+{146, 83, 140},
+{162, 76, 145},
+{178, 69, 149},
+{192, 64, 152},
+{92, 109, 123},
+{100, 105, 126},
+{115, 98, 131},
+{131, 90, 136},
+{147, 83, 140},
+{163, 76, 145},
+{179, 70, 149},
+{193, 64, 152},
+{95, 110, 123},
+{103, 106, 126},
+{117, 99, 131},
+{132, 91, 136},
+{148, 84, 141},
+{165, 77, 145},
+{181, 70, 149},
+{194, 65, 152},
+{98, 111, 124},
+{106, 107, 127},
+{119, 99, 131},
+{134, 92, 136},
+{150, 85, 141},
+{166, 78, 145},
+{182, 71, 149},
+{195, 65, 152},
+{101, 112, 125},
+{109, 107, 127},
+{122, 100, 132},
+{136, 93, 136},
+{152, 85, 141},
+{168, 78, 145},
+{183, 71, 149},
+{197, 66, 152},
+{105, 113, 126},
+{112, 108, 128},
+{124, 101, 132},
+{139, 94, 137},
+{154, 86, 141},
+{170, 79, 145},
+{185, 72, 149},
+{198, 66, 152},
+{108, 114, 126},
+{115, 109, 129},
+{127, 102, 133},
+{141, 94, 137},
+{156, 87, 141},
+{171, 80, 145},
+{187, 73, 149},
+{200, 67, 152},
+{112, 114, 127},
+{118, 110, 129},
+{130, 103, 133},
+{144, 95, 137},
+{158, 88, 141},
+{173, 80, 145},
+{188, 74, 149},
+{201, 68, 152},
+{115, 115, 128},
+{122, 111, 130},
+{133, 104, 133},
+{146, 96, 138},
+{161, 89, 142},
+{175, 81, 146},
+{190, 74, 149},
+{203, 68, 152},
+{119, 116, 128},
+{125, 112, 130},
+{136, 105, 134},
+{149, 97, 138},
+{163, 89, 142},
+{178, 82, 146},
+{192, 75, 149},
+{205, 69, 153},
+{123, 116, 129},
+{129, 112, 131},
+{139, 106, 134},
+{152, 98, 138},
+{166, 90, 142},
+{180, 83, 146},
+{194, 76, 150},
+{207, 70, 153},
+{127, 117, 130},
+{132, 113, 132},
+{142, 106, 135},
+{155, 99, 138},
+{168, 91, 142},
+{182, 84, 146},
+{196, 77, 150},
+{209, 71, 153},
+{131, 118, 130},
+{136, 114, 132},
+{146, 107, 135},
+{158, 100, 139},
+{171, 92, 143},
+{185, 85, 146},
+{199, 77, 150},
+{211, 71, 153},
+{134, 118, 131},
+{140, 114, 133},
+{149, 108, 136},
+{161, 100, 139},
+{174, 93, 143},
+{187, 85, 146},
+{201, 78, 150},
+{213, 72, 153},
+{138, 119, 132},
+{143, 115, 133},
+{153, 109, 136},
+{164, 101, 139},
+{177, 94, 143},
+{190, 86, 147},
+{203, 79, 150},
+{215, 73, 153},
+{142, 119, 132},
+{147, 116, 134},
+{156, 109, 137},
+{167, 102, 140},
+{179, 94, 143},
+{192, 87, 147},
+{206, 80, 150},
+{217, 74, 153},
+{146, 120, 133},
+{151, 116, 134},
+{160, 110, 137},
+{170, 103, 140},
+{182, 95, 143},
+{195, 88, 147},
+{208, 81, 150},
+{220, 75, 153},
+{150, 120, 133},
+{155, 117, 135},
+{163, 111, 137},
+{174, 103, 140},
+{185, 96, 144},
+{198, 89, 147},
+{210, 82, 150},
+{222, 75, 153},
+{154, 121, 134},
+{159, 117, 135},
+{167, 111, 138},
+{177, 104, 141},
+{188, 97, 144},
+{200, 89, 147},
+{213, 82, 151},
+{224, 76, 153},
+{158, 121, 135},
+{162, 118, 136},
+{170, 112, 138},
+{180, 105, 141},
+{191, 98, 144},
+{203, 90, 147},
+{216, 83, 151},
+{227, 77, 153},
+{162, 121, 135},
+{166, 118, 136},
+{174, 112, 139},
+{184, 106, 141},
+{195, 98, 145},
+{206, 91, 148},
+{218, 84, 151},
+{229, 78, 154},
+{166, 122, 136},
+{170, 119, 137},
+{178, 113, 139},
+{187, 106, 142},
+{198, 99, 145},
+{209, 92, 148},
+{221, 85, 151},
+{232, 79, 154},
+{168, 122, 136},
+{172, 119, 137},
+{179, 113, 139},
+{189, 107, 142},
+{199, 99, 145},
+{211, 92, 148},
+{222, 85, 151},
+{233, 79, 154},
+{168, 122, 136},
+{172, 119, 137},
+{179, 113, 139},
+{189, 107, 142},
+{199, 99, 145},
+{211, 92, 148},
+{222, 85, 151},
+{233, 79, 154},
+{168, 122, 136},
+{172, 119, 137},
+{179, 113, 139},
+{189, 107, 142},
+{199, 99, 145},
+{211, 92, 148},
+{222, 85, 151},
+{233, 79, 154},
+{168, 122, 136},
+{172, 119, 137},
+{179, 113, 139},
+{189, 107, 142},
+{199, 99, 145},
+{211, 92, 148},
+{222, 85, 151},
+{233, 79, 154},
+{82, 103, 118},
+{91, 100, 122},
+{107, 94, 128},
+{124, 87, 134},
+{142, 80, 139},
+{159, 74, 144},
+{176, 67, 148},
+{190, 62, 151},
+{82, 104, 118},
+{92, 100, 122},
+{107, 94, 128},
+{125, 87, 134},
+{142, 80, 139},
+{159, 74, 144},
+{176, 68, 148},
+{190, 62, 151},
+{83, 104, 119},
+{92, 100, 123},
+{108, 94, 128},
+{125, 87, 134},
+{142, 81, 139},
+{159, 74, 144},
+{176, 68, 148},
+{190, 62, 151},
+{84, 105, 119},
+{94, 101, 123},
+{109, 94, 128},
+{126, 88, 134},
+{143, 81, 139},
+{160, 74, 144},
+{176, 68, 148},
+{191, 63, 151},
+{86, 105, 120},
+{95, 101, 123},
+{110, 95, 129},
+{127, 88, 134},
+{144, 81, 139},
+{161, 75, 144},
+{177, 68, 148},
+{191, 63, 151},
+{88, 106, 120},
+{97, 102, 124},
+{112, 96, 129},
+{128, 89, 134},
+{145, 82, 139},
+{162, 75, 144},
+{178, 69, 148},
+{192, 63, 151},
+{90, 107, 121},
+{99, 103, 124},
+{113, 96, 129},
+{130, 89, 135},
+{146, 82, 139},
+{163, 75, 144},
+{179, 69, 148},
+{193, 64, 151},
+{93, 108, 121},
+{101, 104, 125},
+{115, 97, 130},
+{131, 90, 135},
+{148, 83, 140},
+{164, 76, 144},
+{180, 70, 148},
+{194, 64, 151},
+{96, 109, 122},
+{104, 105, 125},
+{117, 98, 130},
+{133, 91, 135},
+{149, 84, 140},
+{165, 77, 144},
+{181, 70, 148},
+{195, 64, 152},
+{99, 110, 123},
+{107, 106, 126},
+{120, 99, 130},
+{135, 92, 135},
+{151, 84, 140},
+{167, 77, 144},
+{182, 71, 148},
+{196, 65, 152},
+{102, 111, 124},
+{109, 107, 126},
+{122, 100, 131},
+{137, 92, 135},
+{153, 85, 140},
+{168, 78, 144},
+{184, 71, 148},
+{197, 66, 152},
+{105, 112, 124},
+{113, 108, 127},
+{125, 101, 131},
+{139, 93, 136},
+{155, 86, 140},
+{170, 79, 144},
+{185, 72, 148},
+{199, 66, 152},
+{109, 113, 125},
+{116, 109, 128},
+{128, 102, 132},
+{142, 94, 136},
+{157, 87, 140},
+{172, 79, 145},
+{187, 73, 148},
+{200, 67, 152},
+{112, 114, 126},
+{119, 110, 128},
+{131, 103, 132},
+{144, 95, 136},
+{159, 87, 141},
+{174, 80, 145},
+{189, 73, 149},
+{202, 68, 152},
+{116, 114, 127},
+{122, 110, 129},
+{134, 103, 133},
+{147, 96, 137},
+{161, 88, 141},
+{176, 81, 145},
+{191, 74, 149},
+{203, 68, 152},
+{120, 115, 127},
+{126, 111, 129},
+{137, 104, 133},
+{150, 97, 137},
+{164, 89, 141},
+{178, 82, 145},
+{193, 75, 149},
+{205, 69, 152},
+{124, 116, 128},
+{129, 112, 130},
+{140, 105, 134},
+{152, 98, 137},
+{166, 90, 141},
+{180, 83, 145},
+{195, 76, 149},
+{207, 70, 152},
+{127, 117, 129},
+{133, 113, 131},
+{143, 106, 134},
+{155, 98, 138},
+{169, 91, 142},
+{183, 83, 145},
+{197, 76, 149},
+{209, 70, 152},
+{131, 117, 130},
+{137, 113, 131},
+{146, 107, 134},
+{158, 99, 138},
+{171, 92, 142},
+{185, 84, 146},
+{199, 77, 149},
+{211, 71, 152},
+{135, 118, 130},
+{140, 114, 132},
+{150, 107, 135},
+{161, 100, 138},
+{174, 93, 142},
+{188, 85, 146},
+{201, 78, 149},
+{213, 72, 152},
+{139, 118, 131},
+{144, 115, 132},
+{153, 108, 135},
+{164, 101, 139},
+{177, 93, 142},
+{190, 86, 146},
+{204, 79, 149},
+{215, 73, 152},
+{143, 119, 131},
+{148, 115, 133},
+{157, 109, 136},
+{168, 102, 139},
+{180, 94, 143},
+{193, 87, 146},
+{206, 80, 150},
+{218, 74, 152},
+{147, 119, 132},
+{151, 116, 134},
+{160, 110, 136},
+{171, 102, 139},
+{183, 95, 143},
+{195, 88, 146},
+{208, 80, 150},
+{220, 74, 153},
+{151, 120, 133},
+{155, 116, 134},
+{164, 110, 137},
+{174, 103, 140},
+{186, 96, 143},
+{198, 88, 146},
+{211, 81, 150},
+{222, 75, 153},
+{155, 120, 133},
+{159, 117, 135},
+{167, 111, 137},
+{177, 104, 140},
+{189, 97, 143},
+{201, 89, 147},
+{213, 82, 150},
+{225, 76, 153},
+{159, 121, 134},
+{163, 117, 135},
+{171, 111, 138},
+{181, 105, 141},
+{192, 97, 144},
+{204, 90, 147},
+{216, 83, 150},
+{227, 77, 153},
+{163, 121, 134},
+{167, 118, 136},
+{174, 112, 138},
+{184, 105, 141},
+{195, 98, 144},
+{207, 91, 147},
+{219, 84, 150},
+{230, 78, 153},
+{167, 121, 135},
+{171, 118, 136},
+{178, 113, 138},
+{187, 106, 141},
+{198, 99, 144},
+{210, 92, 147},
+{221, 85, 151},
+{232, 78, 153},
+{169, 121, 135},
+{172, 118, 136},
+{180, 113, 139},
+{189, 106, 141},
+{200, 99, 144},
+{211, 92, 147},
+{223, 85, 151},
+{233, 79, 153},
+{169, 121, 135},
+{172, 118, 136},
+{180, 113, 139},
+{189, 106, 141},
+{200, 99, 144},
+{211, 92, 147},
+{223, 85, 151},
+{233, 79, 153},
+{169, 121, 135},
+{172, 118, 136},
+{180, 113, 139},
+{189, 106, 141},
+{200, 99, 144},
+{211, 92, 147},
+{223, 85, 151},
+{233, 79, 153},
+{169, 121, 135},
+{172, 118, 136},
+{180, 113, 139},
+{189, 106, 141},
+{200, 99, 144},
+{211, 92, 147},
+{223, 85, 151},
+{233, 79, 153},
+{84, 102, 116},
+{93, 98, 120},
+{109, 93, 126},
+{126, 86, 132},
+{143, 80, 137},
+{160, 73, 142},
+{176, 67, 147},
+{190, 62, 150},
+{84, 102, 116},
+{93, 99, 120},
+{109, 93, 126},
+{126, 86, 132},
+{143, 80, 137},
+{160, 73, 142},
+{176, 67, 147},
+{191, 62, 150},
+{85, 102, 117},
+{94, 99, 121},
+{109, 93, 126},
+{126, 87, 132},
+{143, 80, 138},
+{160, 74, 142},
+{177, 67, 147},
+{191, 62, 150},
+{86, 103, 117},
+{95, 99, 121},
+{110, 94, 127},
+{127, 87, 132},
+{144, 80, 138},
+{161, 74, 142},
+{177, 68, 147},
+{191, 62, 150},
+{88, 104, 118},
+{97, 100, 121},
+{112, 94, 127},
+{128, 87, 133},
+{145, 81, 138},
+{162, 74, 142},
+{178, 68, 147},
+{192, 63, 150},
+{90, 105, 118},
+{98, 101, 122},
+{113, 95, 127},
+{129, 88, 133},
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+{162, 75, 142},
+{179, 68, 147},
+{193, 63, 150},
+{92, 106, 119},
+{100, 102, 122},
+{115, 95, 128},
+{131, 89, 133},
+{147, 82, 138},
+{164, 75, 143},
+{180, 69, 147},
+{193, 63, 150},
+{95, 107, 120},
+{103, 103, 123},
+{117, 96, 128},
+{132, 89, 133},
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+{165, 76, 143},
+{181, 69, 147},
+{194, 64, 150},
+{97, 108, 120},
+{105, 104, 123},
+{119, 97, 128},
+{134, 90, 133},
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+{166, 76, 143},
+{182, 70, 147},
+{195, 64, 150},
+{100, 109, 121},
+{108, 105, 124},
+{121, 98, 129},
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+{124, 99, 129},
+{138, 92, 134},
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+{185, 71, 147},
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+{110, 112, 124},
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+{158, 86, 139},
+{173, 79, 143},
+{188, 72, 147},
+{201, 67, 151},
+{114, 113, 124},
+{120, 109, 127},
+{132, 102, 131},
+{145, 94, 135},
+{160, 87, 139},
+{175, 80, 144},
+{190, 73, 147},
+{202, 67, 151},
+{117, 113, 125},
+{124, 109, 127},
+{135, 103, 131},
+{148, 95, 135},
+{162, 88, 140},
+{177, 81, 144},
+{191, 74, 148},
+{204, 68, 151},
+{121, 114, 126},
+{127, 110, 128},
+{138, 103, 132},
+{151, 96, 136},
+{165, 89, 140},
+{179, 81, 144},
+{193, 74, 148},
+{206, 69, 151},
+{125, 115, 127},
+{130, 111, 129},
+{141, 104, 132},
+{153, 97, 136},
+{167, 89, 140},
+{181, 82, 144},
+{195, 75, 148},
+{208, 69, 151},
+{129, 116, 127},
+{134, 112, 129},
+{144, 105, 133},
+{156, 98, 136},
+{170, 90, 140},
+{183, 83, 144},
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+{214, 79, 90},
+{220, 77, 92},
+{227, 74, 96},
+{236, 70, 99},
+{245, 66, 103},
+{255, 61, 108},
+{255, 57, 112},
+{255, 57, 112},
+{214, 79, 90},
+{220, 77, 92},
+{227, 74, 96},
+{236, 70, 99},
+{245, 66, 103},
+{255, 61, 108},
+{255, 57, 112},
+{255, 57, 112},
+{214, 79, 90},
+{220, 77, 92},
+{227, 74, 96},
+{236, 70, 99},
+{245, 66, 103},
+{255, 61, 108},
+{255, 57, 112},
+{255, 57, 112},
+{159, 41, 67},
+{168, 42, 71},
+{179, 43, 77},
+{191, 43, 83},
+{204, 42, 90},
+{217, 40, 96},
+{230, 37, 101},
+{230, 37, 101},
+{159, 41, 67},
+{168, 42, 72},
+{179, 43, 77},
+{191, 43, 84},
+{204, 42, 90},
+{217, 40, 96},
+{230, 37, 101},
+{230, 37, 101},
+{160, 41, 67},
+{168, 43, 72},
+{179, 44, 78},
+{191, 43, 84},
+{204, 42, 90},
+{217, 40, 96},
+{230, 37, 102},
+{230, 37, 102},
+{160, 42, 67},
+{169, 43, 72},
+{180, 44, 78},
+{192, 44, 84},
+{204, 42, 90},
+{217, 40, 96},
+{230, 38, 102},
+{230, 38, 102},
+{161, 43, 68},
+{170, 44, 72},
+{181, 45, 78},
+{192, 44, 84},
+{205, 43, 90},
+{218, 41, 96},
+{231, 38, 102},
+{231, 38, 102},
+{162, 44, 68},
+{171, 45, 73},
+{181, 45, 78},
+{193, 45, 84},
+{206, 43, 90},
+{218, 41, 96},
+{231, 38, 102},
+{231, 38, 102},
+{163, 45, 69},
+{172, 46, 73},
+{182, 46, 79},
+{194, 45, 85},
+{207, 44, 91},
+{219, 42, 97},
+{232, 39, 102},
+{232, 39, 102},
+{165, 46, 69},
+{173, 47, 74},
+{184, 47, 79},
+{195, 46, 85},
+{207, 44, 91},
+{220, 42, 97},
+{233, 39, 102},
+{233, 39, 102},
+{166, 48, 70},
+{174, 48, 74},
+{185, 48, 80},
+{196, 47, 86},
+{208, 45, 91},
+{221, 43, 97},
+{234, 40, 103},
+{234, 40, 103},
+{168, 49, 71},
+{176, 50, 75},
+{186, 49, 80},
+{198, 48, 86},
+{210, 46, 92},
+{222, 43, 97},
+{235, 40, 103},
+{235, 40, 103},
+{170, 51, 72},
+{178, 51, 76},
+{188, 50, 81},
+{199, 49, 87},
+{211, 47, 92},
+{223, 44, 98},
+{236, 41, 103},
+{236, 41, 103},
+{172, 53, 73},
+{179, 53, 77},
+{189, 52, 82},
+{200, 50, 87},
+{212, 48, 93},
+{224, 45, 98},
+{237, 42, 104},
+{237, 42, 104},
+{174, 54, 74},
+{181, 54, 77},
+{191, 53, 82},
+{202, 51, 88},
+{214, 49, 93},
+{226, 46, 99},
+{238, 42, 104},
+{238, 42, 104},
+{176, 56, 74},
+{183, 56, 78},
+{193, 54, 83},
+{204, 52, 88},
+{215, 50, 94},
+{227, 47, 99},
+{239, 43, 104},
+{239, 43, 104},
+{178, 58, 75},
+{185, 57, 79},
+{195, 56, 84},
+{205, 53, 89},
+{217, 51, 94},
+{229, 47, 100},
+{241, 44, 105},
+{241, 44, 105},
+{180, 60, 76},
+{187, 59, 80},
+{197, 57, 85},
+{207, 55, 90},
+{219, 52, 95},
+{230, 48, 100},
+{242, 45, 105},
+{242, 45, 105},
+{183, 61, 78},
+{190, 60, 81},
+{199, 58, 86},
+{209, 56, 90},
+{220, 53, 96},
+{232, 49, 101},
+{244, 46, 106},
+{244, 46, 106},
+{185, 63, 79},
+{192, 62, 82},
+{201, 60, 86},
+{211, 57, 91},
+{222, 54, 96},
+{234, 50, 101},
+{245, 47, 106},
+{245, 47, 106},
+{188, 65, 80},
+{194, 63, 83},
+{203, 61, 87},
+{213, 58, 92},
+{224, 55, 97},
+{235, 51, 102},
+{247, 47, 107},
+{247, 47, 107},
+{190, 67, 81},
+{197, 65, 84},
+{206, 62, 88},
+{215, 59, 93},
+{226, 56, 97},
+{237, 52, 102},
+{249, 48, 107},
+{249, 48, 107},
+{193, 68, 82},
+{199, 66, 85},
+{208, 64, 89},
+{218, 61, 93},
+{228, 57, 98},
+{239, 53, 103},
+{251, 49, 108},
+{251, 49, 108},
+{196, 70, 83},
+{202, 68, 86},
+{210, 65, 90},
+{220, 62, 94},
+{230, 58, 99},
+{241, 54, 103},
+{252, 50, 108},
+{252, 50, 108},
+{198, 71, 84},
+{205, 69, 87},
+{213, 67, 91},
+{222, 63, 95},
+{232, 59, 99},
+{243, 55, 104},
+{254, 51, 109},
+{254, 51, 109},
+{201, 73, 85},
+{207, 71, 88},
+{215, 68, 92},
+{225, 64, 96},
+{235, 61, 100},
+{245, 56, 105},
+{255, 52, 109},
+{255, 52, 109},
+{204, 74, 86},
+{210, 72, 89},
+{218, 69, 93},
+{227, 66, 97},
+{237, 62, 101},
+{247, 58, 105},
+{255, 53, 110},
+{255, 53, 110},
+{207, 76, 87},
+{213, 74, 90},
+{221, 70, 93},
+{230, 67, 97},
+{239, 63, 102},
+{250, 59, 106},
+{255, 54, 110},
+{255, 54, 110},
+{210, 77, 88},
+{216, 75, 91},
+{223, 72, 94},
+{232, 68, 98},
+{242, 64, 102},
+{252, 60, 107},
+{255, 55, 111},
+{255, 55, 111},
+{213, 79, 89},
+{219, 76, 92},
+{226, 73, 95},
+{235, 69, 99},
+{244, 65, 103},
+{254, 61, 107},
+{255, 56, 111},
+{255, 56, 111},
+{214, 79, 90},
+{220, 77, 92},
+{227, 74, 96},
+{236, 70, 99},
+{245, 66, 103},
+{255, 61, 108},
+{255, 57, 112},
+{255, 57, 112},
+{214, 79, 90},
+{220, 77, 92},
+{227, 74, 96},
+{236, 70, 99},
+{245, 66, 103},
+{255, 61, 108},
+{255, 57, 112},
+{255, 57, 112},
+{214, 79, 90},
+{220, 77, 92},
+{227, 74, 96},
+{236, 70, 99},
+{245, 66, 103},
+{255, 61, 108},
+{255, 57, 112},
+{255, 57, 112},
+{214, 79, 90},
+{220, 77, 92},
+{227, 74, 96},
+{236, 70, 99},
+{245, 66, 103},
+{255, 61, 108},
+{255, 57, 112},
+{255, 57, 112},
+};
+#endif 
diff --git a/packages/devs/ipu/arm/imx/v1_0/include/tve_reg_def.h b/packages/devs/ipu/arm/imx/v1_0/include/tve_reg_def.h
new file mode 100644 (file)
index 0000000..03fbc3d
--- /dev/null
@@ -0,0 +1,334 @@
+/***************************************************************************
+*
+*                                                    TVE_REG_DEF.H
+*
+*     registers defination for TVE. 
+*
+***************************************************************************
+*
+* Author(s)            :               Ray Sun-B17777 <Yanfei.Sun@freescale.com> 
+* Create Date  :               2009-01-16
+* Description  :               TV Display Test Case For Elvis TO2 3stack Board.
+*
+***************************************************************************/
+
+#ifndef _TVE_REG_DEF_
+#define _TVE_REG_DEF_
+
+#include <cyg/hal/hal_soc.h>
+
+#define CCM_CDCDR                   (CCM_BASE_ADDR + CCM_CDCDR_OFFSET)
+#define CCM_CDCDR_TVE_CLK_PRED      0x70000000  //the relevant mask for the tve_clk_pred[2:0] field
+
+//#define TVE_BASE_ADDR               0x83FF000
+#define TVE_REG_TVE_EN                                 (TVE_BASE_ADDR + 0x1000),0x00000001
+#define TVE_REG_TVDAC_SAMP_RATE        (TVE_BASE_ADDR + 0x1000),0x00000006
+#define TVE_REG_IPU_CLK_EN                     (TVE_BASE_ADDR + 0x1000),0x00000008
+#define TVE_REG_DATA_SOURCE_SEL        (TVE_BASE_ADDR + 0x1000),0x00000030
+#define TVE_REG_INP_VIDEO_FORM                 (TVE_BASE_ADDR + 0x1000),0x00000040
+#define TVE_REG_P2I_CONV_EN            (TVE_BASE_ADDR + 0x1000),0x00000080
+#define TVE_REG_TV_STAND                       (TVE_BASE_ADDR + 0x1000),0x00000f00
+#define TVE_REG_TV_OUT_MODE            (TVE_BASE_ADDR + 0x1000),0x00007000
+#define TVE_REG_SD_PED_AMP_CONT        (TVE_BASE_ADDR + 0x1000),0x00030000
+#define TVE_REG_SYNC_CH_0_EN           (TVE_BASE_ADDR + 0x1000),0x00100000
+#define TVE_REG_SYNC_CH_1_EN           (TVE_BASE_ADDR + 0x1000),0x00200000
+#define TVE_REG_SYNC_CH_2_EN           (TVE_BASE_ADDR + 0x1000),0x00400000
+#define TVE_REG_ACT_LINE_OFFSET        (TVE_BASE_ADDR + 0x1000),0x07000000
+#define TVE_REG_COM_CONF_REG           (TVE_BASE_ADDR + 0x1000),0x07737fff
+#define TVE_REG_DEFLICK_EN                     (TVE_BASE_ADDR + 0x1004),0x00000001
+#define TVE_REG_DEFLICK_MEAS_WIN       (TVE_BASE_ADDR + 0x1004),0x00000002
+#define TVE_REG_DEFLICK_COEF           (TVE_BASE_ADDR + 0x1004),0x00000070
+#define TVE_REG_DEFLICK_LOW_THRESH     (TVE_BASE_ADDR + 0x1004),0x0000ff00
+#define TVE_REG_DEFLICK_MID_THRESH     (TVE_BASE_ADDR + 0x1004),0x00ff0000
+#define TVE_REG_DEFLICK_HIGH_THRESH (TVE_BASE_ADDR + 0x1004),0xff000000
+#define TVE_REG_LUMA_FILT_CONT_REG_0 (TVE_BASE_ADDR + 0x1004),0xffffff73
+#define TVE_REG_V_SHARP_EN                     (TVE_BASE_ADDR + 0x1008),0x00000001
+#define TVE_REG_V_SHARP_COEF           (TVE_BASE_ADDR + 0x1008),0x00000070
+#define TVE_REG_V_SHARP_LOW_THRESH     (TVE_BASE_ADDR + 0x1008),0x0000ff00
+#define TVE_REG_V_SHARP_HIGH_THRESH (TVE_BASE_ADDR + 0x1008),0xff000000
+#define TVE_REG_LUMA_FILT_CONT_REG_1 (TVE_BASE_ADDR + 0x1008),0xff00ff71
+#define TVE_REG_H_SHARP_EN                     (TVE_BASE_ADDR + 0x100c),0x00000001
+#define TVE_REG_H_SHARP_COEF           (TVE_BASE_ADDR + 0x100c),0x00000070
+#define TVE_REG_H_SHARP_LOW_THRESH     (TVE_BASE_ADDR + 0x100c),0x0000ff00
+#define TVE_REG_H_SHARP_HIGH_THRESH (TVE_BASE_ADDR + 0x100c),0xff000000
+#define TVE_REG_LUMA_FILT_CONT_REG_2 (TVE_BASE_ADDR + 0x100c),0xff00ff71
+#define TVE_REG_DERING_EN                      (TVE_BASE_ADDR + 0x1010),0x00000001
+#define TVE_REG_SUPP_FILTER_TYPE       (TVE_BASE_ADDR + 0x1010),0x00000006
+#define TVE_REG_DERING_COEF            (TVE_BASE_ADDR + 0x1010),0x00000070
+#define TVE_REG_DERING_LOW_THRESH      (TVE_BASE_ADDR + 0x1010),0x0000ff00
+#define TVE_REG_DERING_MID_THRESH      (TVE_BASE_ADDR + 0x1010),0x00ff0000
+#define TVE_REG_DERING_HIGH_THRESH     (TVE_BASE_ADDR + 0x1010),0xff000000
+#define TVE_REG_LUMA_FILT_CONT_REG_3 (TVE_BASE_ADDR + 0x1010),0xffffff77
+#define TVE_REG_LUMA_SA_EN                     (TVE_BASE_ADDR + 0x1014),0x00000001
+#define TVE_REG_SA_H_POINTS_NUM        (TVE_BASE_ADDR + 0x1014),0x00000030
+#define TVE_REG_SA_V_POINTS_NUM        (TVE_BASE_ADDR + 0x1014),0x00000300
+#define TVE_REG_LUMA_SA_CONT_REG_0     (TVE_BASE_ADDR + 0x1014),0x00000331
+#define TVE_REG_SA_WIN_WIDTH           (TVE_BASE_ADDR + 0x1018),0x000000ff
+#define TVE_REG_SA_WIN_HEIGHT  (TVE_BASE_ADDR + 0x1018),0x0000ff00
+#define TVE_REG_SA_WIN_H_OFFSET  (TVE_BASE_ADDR + 0x1018),0x00ff0000
+#define TVE_REG_SA_WIN_V_OFFSET  (TVE_BASE_ADDR + 0x1018),0xff000000
+#define TVE_REG_LUMA_SA_CONT_REG_1 (TVE_BASE_ADDR + 0x1018),0xffffffff
+#define TVE_REG_LPU_DEFLICK_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0x000000ff
+#define TVE_REG_LPU_V_SHARP_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0x0000ff00
+#define TVE_REG_LPU_H_SHARP_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0x00ff0000
+#define TVE_REG_LPU_DERING_MEAS_MEAN (TVE_BASE_ADDR + 0x101c),0xff000000
+#define TVE_REG_LUMA_SA_STAT_REG_0 (TVE_BASE_ADDR + 0x101c),0xffffffff
+#define TVE_REG_LPU_LUMA_MEAN (TVE_BASE_ADDR + 0x1020),0x000000ff
+#define TVE_REG_LUMA_SA_STAT_REG_1 (TVE_BASE_ADDR + 0x1020),0x000000ff
+#define TVE_REG_CHROMA_V_FILT_EN (TVE_BASE_ADDR + 0x1024),0x00000001
+#define TVE_REG_CHROMA_BW (TVE_BASE_ADDR + 0x1024),0x00000070
+#define TVE_REG_SCH_PHASE (TVE_BASE_ADDR + 0x1024),0x0000ff00
+#define TVE_REG_CHROMA_CONT_REG (TVE_BASE_ADDR + 0x1024),0x0000ff71
+#define TVE_REG_TVDAC_0_GAIN (TVE_BASE_ADDR + 0x1028),0x0000003f
+#define TVE_REG_TVDAC_0_OFFSET (TVE_BASE_ADDR + 0x1028),0x0000ff00
+#define TVE_REG_BG_RDY_TIME (TVE_BASE_ADDR + 0x1028),0x00ff0000
+#define TVE_REG_TVDAC_0_CONT_REG (TVE_BASE_ADDR + 0x1028),0x00ffff3f
+#define TVE_REG_TVDAC_1_GAIN (TVE_BASE_ADDR + 0x102c),0x0000003f
+#define TVE_REG_TVDAC_1_OFFSET (TVE_BASE_ADDR + 0x102c),0x0000ff00
+#define TVE_REG_TVDAC_1_CONT_REG (TVE_BASE_ADDR + 0x102c),0x0000ff3f
+#define TVE_REG_TVDAC_2_GAIN (TVE_BASE_ADDR + 0x1030),0x0000003f
+#define TVE_REG_TVDAC_2_OFFSET (TVE_BASE_ADDR + 0x1030),0x0000ff00
+#define TVE_REG_TVDAC_2_CONT_REG (TVE_BASE_ADDR + 0x1030),0x0000ff3f
+#define TVE_REG_CD_EN (TVE_BASE_ADDR + 0x1034),0x00000001
+#define TVE_REG_CD_TRIG_MODE (TVE_BASE_ADDR + 0x1034),0x00000002
+#define TVE_REG_CD_STBY_MON_PER (TVE_BASE_ADDR + 0x1034),0x000000f0
+#define TVE_REG_CD_CH_0_REF_LVL (TVE_BASE_ADDR + 0x1034),0x00000100
+#define TVE_REG_CD_CH_1_REF_LVL (TVE_BASE_ADDR + 0x1034),0x00000200
+#define TVE_REG_CD_CH_2_REF_LVL (TVE_BASE_ADDR + 0x1034),0x00000400
+#define TVE_REG_CD_REF_MODE (TVE_BASE_ADDR + 0x1034),0x00000800
+#define TVE_REG_CD_CH_0_LM_EN (TVE_BASE_ADDR + 0x1034),0x00010000
+#define TVE_REG_CD_CH_1_LM_EN (TVE_BASE_ADDR + 0x1034),0x00020000
+#define TVE_REG_CD_CH_2_LM_EN (TVE_BASE_ADDR + 0x1034),0x00040000
+#define TVE_REG_CD_CH_0_SM_EN (TVE_BASE_ADDR + 0x1034),0x00100000
+#define TVE_REG_CD_CH_1_SM_EN (TVE_BASE_ADDR + 0x1034),0x00200000
+#define TVE_REG_CD_CH_2_SM_EN (TVE_BASE_ADDR + 0x1034),0x00400000
+#define TVE_REG_CD_CONT_REG (TVE_BASE_ADDR + 0x1034),0x00770ff3
+#define TVE_REG_CC_SD_F1_EN (TVE_BASE_ADDR + 0x1038),0x00000001
+#define TVE_REG_CC_SD_F2_EN (TVE_BASE_ADDR + 0x1038),0x00000002
+#define TVE_REG_CC_SD_BOOST_EN (TVE_BASE_ADDR + 0x1038),0x00000004
+#define TVE_REG_CGMS_SD_F1_EN (TVE_BASE_ADDR + 0x1038),0x00000010
+#define TVE_REG_CGMS_SD_F2_EN (TVE_BASE_ADDR + 0x1038),0x00000020
+#define TVE_REG_CGMS_SD_SW_CRC_EN (TVE_BASE_ADDR + 0x1038),0x00000040
+#define TVE_REG_WSS_SD_EN (TVE_BASE_ADDR + 0x1038),0x00000080
+#define TVE_REG_CGMS_HD_A_F1_EN (TVE_BASE_ADDR + 0x1038),0x00000100
+#define TVE_REG_CGMS_HD_A_F2_EN (TVE_BASE_ADDR + 0x1038),0x00000200
+#define TVE_REG_CGMS_HD_A_SW_CRC_EN (TVE_BASE_ADDR + 0x1038),0x00000400
+#define TVE_REG_CGMS_HD_B_F1_EN (TVE_BASE_ADDR + 0x1038),0x00001000
+#define TVE_REG_CGMS_HD_B_F2_EN (TVE_BASE_ADDR + 0x1038),0x00002000
+#define TVE_REG_CGMS_HD_B_SW_CRC_EN (TVE_BASE_ADDR + 0x1038),0x00004000
+#define TVE_REG_CGMS_HD_B_F1_HEADER (TVE_BASE_ADDR + 0x1038),0x003f0000
+#define TVE_REG_CGMS_HD_B_F2_HEADER (TVE_BASE_ADDR + 0x1038),0x3f000000
+#define TVE_REG_VBI_DATA_CONT_REG (TVE_BASE_ADDR + 0x1038),0x3f3f77f7
+#define TVE_REG_CGMS_SD_HD_A_F1_DATA (TVE_BASE_ADDR + 0x103c),0x000fffff
+#define TVE_REG_VBI_DATA_REG_0 (TVE_BASE_ADDR + 0x103c),0x000fffff
+#define TVE_REG_CGMS_SD_HD_A_F2_DATA (TVE_BASE_ADDR + 0x1040),0x000fffff
+#define TVE_REG_VBI_DATA_REG_1 (TVE_BASE_ADDR + 0x1040),0x000fffff
+#define TVE_REG_CC_SD_CGMS_HD_B_F1_DATA_0 (TVE_BASE_ADDR + 0x1044),0xffffffff
+#define TVE_REG_VBI_DATA_REG_2 (TVE_BASE_ADDR + 0x1044),0xffffffff
+#define TVE_REG_WSS_SD_CGMS_HD_B_F1_DATA_1 (TVE_BASE_ADDR + 0x1048),0xffffffff
+#define TVE_REG_VBI_DATA_REG_3 (TVE_BASE_ADDR + 0x1048),0xffffffff
+#define TVE_REG_CGMS_HD_B_F1_DATA_2 (TVE_BASE_ADDR + 0x104c),0xffffffff
+#define TVE_REG_VBI_DATA_REG_4 (TVE_BASE_ADDR + 0x104c),0xffffffff
+#define TVE_REG_CGMS_HD_B_F1_DATA_3 (TVE_BASE_ADDR + 0x1050),0xffffffff
+#define TVE_REG_VBI_DATA_REG_5 (TVE_BASE_ADDR + 0x1050),0xffffffff
+#define TVE_REG_CC_SD_CGMS_HD_B_F2_DATA_0 (TVE_BASE_ADDR + 0x1054),0xffffffff
+#define TVE_REG_VBI_DATA_REG_6 (TVE_BASE_ADDR + 0x1054),0xffffffff
+#define TVE_REG_CGMS_HD_B_F2_DATA_1 (TVE_BASE_ADDR + 0x1058),0xffffffff
+#define TVE_REG_VBI_DATA_REG_7 (TVE_BASE_ADDR + 0x1058),0xffffffff
+#define TVE_REG_CGMS_HD_B_F2_DATA_2 (TVE_BASE_ADDR + 0x105c),0xffffffff
+#define TVE_REG_VBI_DATA_REG_8 (TVE_BASE_ADDR + 0x105c),0xffffffff
+#define TVE_REG_CGMS_HD_B_F2_DATA_3 (TVE_BASE_ADDR + 0x1060),0xffffffff
+#define TVE_REG_VBI_DATA_REG_9 (TVE_BASE_ADDR + 0x1060),0xffffffff
+#define TVE_REG_CD_LM_IEN (TVE_BASE_ADDR + 0x1064),0x00000001
+#define TVE_REG_CD_SM_IEN (TVE_BASE_ADDR + 0x1064),0x00000002
+#define TVE_REG_CD_MON_END_IEN (TVE_BASE_ADDR + 0x1064),0x00000004
+#define TVE_REG_CC_SD_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000008
+#define TVE_REG_CC_SD_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000010
+#define TVE_REG_CGMS_SD_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000020
+#define TVE_REG_CGMS_SD_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000040
+#define TVE_REG_WSS_SD_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000080
+#define TVE_REG_CGMS_HD_A_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000100
+#define TVE_REG_CGMS_HD_A_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000200
+#define TVE_REG_CGMS_HD_B_F1_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000400
+#define TVE_REG_CGMS_HD_B_F2_DONE_IEN (TVE_BASE_ADDR + 0x1064),0x00000800
+#define TVE_REG_TVE_FIELD_END_IEN (TVE_BASE_ADDR + 0x1064),0x00001000
+#define TVE_REG_TVE_FRAME_END_IEN (TVE_BASE_ADDR + 0x1064),0x00002000
+#define TVE_REG_SA_MEAS_END_IEN (TVE_BASE_ADDR + 0x1064),0x00004000
+#define TVE_REG_INT_CONT_REG (TVE_BASE_ADDR + 0x1064),0x00007fff
+#define TVE_REG_CDCU_CD_LM_INT (TVE_BASE_ADDR + 0x1068),0x00000001
+#define TVE_REG_CDCU_CD_SM_INT (TVE_BASE_ADDR + 0x1068),0x00000002
+#define TVE_REG_CDCU_CD_MON_END_INT (TVE_BASE_ADDR + 0x1068),0x00000004
+#define TVE_REG_VDG_CC_SD_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000008
+#define TVE_REG_VDG_CC_SD_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000010
+#define TVE_REG_VDG_CGMS_SD_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000020
+#define TVE_REG_VDG_CGMS_SD_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000040
+#define TVE_REG_VDG_WSS_SD_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000080
+#define TVE_REG_VDG_CGMS_HD_A_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000100
+#define TVE_REG_VDG_CGMS_HD_A_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000200
+#define TVE_REG_VDG_CGMS_HD_B_F1_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000400
+#define TVE_REG_VDG_CGMS_HD_B_F2_DONE_INT (TVE_BASE_ADDR + 0x1068),0x00000800
+#define TVE_REG_TSC_TVE_FIELD_END_INT (TVE_BASE_ADDR + 0x1068),0x00001000
+#define TVE_REG_TSC_TVE_FRAME_END_INT (TVE_BASE_ADDR + 0x1068),0x00002000
+#define TVE_REG_LPU_SA_MEAS_END_INT (TVE_BASE_ADDR + 0x1068),0x00004000
+#define TVE_REG_CD_CH_0_LM_ST (TVE_BASE_ADDR + 0x1068),0x00010000
+#define TVE_REG_CD_CH_1_LM_ST (TVE_BASE_ADDR + 0x1068),0x00020000
+#define TVE_REG_CD_CH_2_LM_ST (TVE_BASE_ADDR + 0x1068),0x00040000
+#define TVE_REG_CD_CH_0_SM_ST (TVE_BASE_ADDR + 0x1068),0x00100000
+#define TVE_REG_CD_CH_1_SM_ST (TVE_BASE_ADDR + 0x1068),0x00200000
+#define TVE_REG_CD_CH_2_SM_ST (TVE_BASE_ADDR + 0x1068),0x00400000
+#define TVE_REG_CD_MAN_TRIG (TVE_BASE_ADDR + 0x1068),0x01000000
+#define TVE_REG_BG_READY (TVE_BASE_ADDR + 0x1068),0x02000000
+#define TVE_REG_STAT_REG (TVE_BASE_ADDR + 0x1068),0x03777fff
+#define TVE_REG_TVDAC_TEST_MODE (TVE_BASE_ADDR + 0x106c),0x00000007
+#define TVE_REG_TVDAC_0_DATA_FORCE (TVE_BASE_ADDR + 0x106c),0x00000010
+#define TVE_REG_TVDAC_1_DATA_FORCE (TVE_BASE_ADDR + 0x106c),0x00000020
+#define TVE_REG_TVDAC_2_DATA_FORCE (TVE_BASE_ADDR + 0x106c),0x00000040
+#define TVE_REG_TVDAC_TEST_SINE_FREQ (TVE_BASE_ADDR + 0x106c),0x00000700
+#define TVE_REG_TVDAC_TEST_SINE_LEVEL (TVE_BASE_ADDR + 0x106c),0x00003000
+#define TVE_REG_COLORBAR_TYPE (TVE_BASE_ADDR + 0x106c),0x00010000
+#define TVE_REG_TST_MODE_REG (TVE_BASE_ADDR + 0x106c),0x00013777
+#define TVE_REG_H_TIMING_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000001
+#define TVE_REG_LUMA_FILT_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000002
+#define TVE_REG_SC_FREQ_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000004
+#define TVE_REG_CSCM_COEF_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000008
+#define TVE_REG_BLANK_LEVEL_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000010
+#define TVE_REG_VBI_DATA_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000020
+#define TVE_REG_TVDAC_DROP_COMP_USR_MODE_EN (TVE_BASE_ADDR + 0x1070),0x00000040
+#define TVE_REG_USER_MODE_CONT_REG (TVE_BASE_ADDR + 0x1070),0x0000007f
+#define TVE_REG_SD_VBI_T0_USR (TVE_BASE_ADDR + 0x1074),0x0000003f
+#define TVE_REG_SD_VBI_T1_USR (TVE_BASE_ADDR + 0x1074),0x0003ff00
+#define TVE_REG_SD_VBI_T2_USR (TVE_BASE_ADDR + 0x1074),0x3ff00000
+#define TVE_REG_SD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1074),0x3ff3ff3f
+#define TVE_REG_SD_ACT_T0_USR (TVE_BASE_ADDR + 0x1078),0x0000007f
+#define TVE_REG_SD_ACT_T1_USR (TVE_BASE_ADDR + 0x1078),0x00001f00
+#define TVE_REG_SD_ACT_T2_USR (TVE_BASE_ADDR + 0x1078),0x007f0000
+#define TVE_REG_SD_ACT_T3_USR (TVE_BASE_ADDR + 0x1078),0x7f000000
+#define TVE_REG_SD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1078),0x7f7f1f7f
+#define TVE_REG_SD_ACT_T4_USR (TVE_BASE_ADDR + 0x107c),0x000007ff
+#define TVE_REG_SD_ACT_T5_USR (TVE_BASE_ADDR + 0x107c),0x003ff000
+#define TVE_REG_SD_ACT_T6_USR (TVE_BASE_ADDR + 0x107c),0x3f000000
+#define TVE_REG_SD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x107c),0x3f3ff7ff
+#define TVE_REG_HD_VBI_ACT_T0_USR (TVE_BASE_ADDR + 0x1080),0x0000007f
+#define TVE_REG_HD_VBI_T1_USR (TVE_BASE_ADDR + 0x1080),0x0001ff00
+#define TVE_REG_HD_VBI_T2_USR (TVE_BASE_ADDR + 0x1080),0x7ff00000
+#define TVE_REG_HD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1080),0x7ff1ff7f
+#define TVE_REG_HD_VBI_T3_USR (TVE_BASE_ADDR + 0x1084),0x00001fff
+#define TVE_REG_HD_ACT_T1_USR (TVE_BASE_ADDR + 0x1084),0x01ff0000
+#define TVE_REG_HD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1084),0x01ff1fff
+#define TVE_REG_HD_ACT_T2_USR (TVE_BASE_ADDR + 0x1088),0x00000fff
+#define TVE_REG_HD_ACT_T3_USR (TVE_BASE_ADDR + 0x1088),0x1fff0000
+#define TVE_REG_HD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1088),0x1fff0fff
+#define TVE_REG_DEFLICK_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x108c),0x00ffffff
+#define TVE_REG_LUMA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x108c),0x00ffffff
+#define TVE_REG_V_SHARP_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x1090),0x00ffffff
+#define TVE_REG_LUMA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1090),0x00ffffff
+#define TVE_REG_H_SHARP_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x1094),0x00ffffff
+#define TVE_REG_LUMA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1094),0x00ffffff
+#define TVE_REG_DERING_MASK_MATRIX_USR (TVE_BASE_ADDR + 0x1098),0x00ffffff
+#define TVE_REG_LUMA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x1098),0x00ffffff
+#define TVE_REG_DATA_CLIP_USR (TVE_BASE_ADDR + 0x109c),0x00000001
+#define TVE_REG_BRIGHT_CORR_USR (TVE_BASE_ADDR + 0x109c),0x00003f00
+#define TVE_REG_CSCM_A_COEF_USR (TVE_BASE_ADDR + 0x109c),0x07ff0000
+#define TVE_REG_CSC_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x109c),0x07ff3f01
+#define TVE_REG_CSCM_B_COEF_USR (TVE_BASE_ADDR + 0x10a0),0x00000fff
+#define TVE_REG_CSCM_C_COEF_USR (TVE_BASE_ADDR + 0x10a0),0x07ff0000
+#define TVE_REG_CSC_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10a0),0x07ff0fff
+#define TVE_REG_CSCM_D_COEF_USR (TVE_BASE_ADDR + 0x10a4),0x00000fff
+#define TVE_REG_CSCM_E_COEF_USR (TVE_BASE_ADDR + 0x10a4),0x1fff0000
+#define TVE_REG_CSC_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10a4),0x1fff0fff
+#define TVE_REG_BLANKING_CH_0_USR (TVE_BASE_ADDR + 0x10a8),0x000003ff
+#define TVE_REG_BLANKING_CH_1_USR (TVE_BASE_ADDR + 0x10a8),0x000ffc00
+#define TVE_REG_BLANKING_CH_2_USR (TVE_BASE_ADDR + 0x10a8),0x3ff00000
+#define TVE_REG_BLANK_USR_CONT_REG (TVE_BASE_ADDR + 0x10a8),0x3fffffff
+#define TVE_REG_SC_FREQ_USR (TVE_BASE_ADDR + 0x10ac),0x3fffffff
+#define TVE_REG_SD_MOD_USR_CONT_REG (TVE_BASE_ADDR + 0x10ac),0x3fffffff
+#define TVE_REG_VBI_DATA_START_TIME_USR (TVE_BASE_ADDR + 0x10b0),0x00000fff
+#define TVE_REG_VBI_DATA_STOP_TIME_USR (TVE_BASE_ADDR + 0x10b0),0x0fff0000
+#define TVE_REG_VBI_DATA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x10b0),0x0fff0fff
+#define TVE_REG_VBI_PACKET_START_TIME_USR (TVE_BASE_ADDR + 0x10b4),0x00000fff
+#define TVE_REG_VBI_DATA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10b4),0x00000fff
+#define TVE_REG_CC_SD_RUNIN_START_TIME_USR (TVE_BASE_ADDR + 0x10b8),0x00000fff
+#define TVE_REG_CC_SD_RUNIN_DIV_NUM_USR (TVE_BASE_ADDR + 0x10b8),0x07ff0000
+#define TVE_REG_VBI_DATA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10b8),0x07ff0fff
+#define TVE_REG_CC_SD_CGMS_HD_B_DIV_NUM_USR (TVE_BASE_ADDR + 0x10bc),0x0000007f
+#define TVE_REG_CC_SD_CGMS_HD_B_DIV_DENOM_USR (TVE_BASE_ADDR + 0x10bc),0x1fff0000
+#define TVE_REG_VBI_DATA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x10bc),0x1fff007f
+#define TVE_REG_WSS_CGMS_SD_CGMS_HD_A_DIV_NUM_USR (TVE_BASE_ADDR + 0x10c0),0x0000007f
+#define TVE_REG_WSS_CGMS_SD_CGMS_HD_A_DIV_DENOM_USR (TVE_BASE_ADDR + 0x10c0),0x1fff0000
+#define TVE_REG_VBI_DATA_USR_CONT_REG_4 (TVE_BASE_ADDR + 0x10c0),0x1fff007f
+#define TVE_REG_TVDAC_0_DROP_COMP (TVE_BASE_ADDR + 0x10c4),0x0000000f
+#define TVE_REG_TVDAC_1_DROP_COMP (TVE_BASE_ADDR + 0x10c4),0x000000f0
+#define TVE_REG_TVDAC_2_DROP_COMP (TVE_BASE_ADDR + 0x10c4),0x00000f00
+#define TVE_REG_DROP_COMP_USR_CONT_REG (TVE_BASE_ADDR + 0x10c4),0x00000fff
+#define TVE_REG_MV_WORD_0 (TVE_BASE_ADDR + 0x10c8),0xffffffff
+#define TVE_REG_MAC_WORD_REG_0 (TVE_BASE_ADDR + 0x10c8),0xffffffff
+#define TVE_REG_MV_WORD_1 (TVE_BASE_ADDR + 0x10cc),0xffffffff
+#define TVE_REG_MAC_WORD_REG_1 (TVE_BASE_ADDR + 0x10cc),0xffffffff
+#define TVE_REG_MV_WORD_2 (TVE_BASE_ADDR + 0x10d0),0xffffffff
+#define TVE_REG_MAC_WORD_REG_2 (TVE_BASE_ADDR + 0x10d0),0xffffffff
+#define TVE_REG_MV_WORD_3 (TVE_BASE_ADDR + 0x10d4),0xffffffff
+#define TVE_REG_MAC_WORD_REG_3 (TVE_BASE_ADDR + 0x10d4),0xffffffff
+#define TVE_REG_MV_WORD_4 (TVE_BASE_ADDR + 0x10d8),0xffffffff
+#define TVE_REG_MAC_WORD_REG_4 (TVE_BASE_ADDR + 0x10d8),0xffffffff
+#define TVE_REG_MV_DATA_READY (TVE_BASE_ADDR + 0x10dc),0x00000001
+#define TVE_REG_MAC_CONT_REG (TVE_BASE_ADDR + 0x10dc),0x00000001
+
+//TVEV2 - registers defines without masking :
+#define TVEV2_REG_COM_CONF_REG (TVE_BASE_ADDR + 0x1000)
+#define TVEV2_REG_LUMA_FILT_CONT_REG_0 (TVE_BASE_ADDR + 0x1004)
+#define TVEV2_REG_LUMA_FILT_CONT_REG_1 (TVE_BASE_ADDR + 0x1008)
+#define TVEV2_REG_LUMA_FILT_CONT_REG_2 (TVE_BASE_ADDR + 0x100c)
+#define TVEV2_REG_LUMA_FILT_CONT_REG_3 (TVE_BASE_ADDR + 0x1010)
+#define TVEV2_REG_LUMA_SA_CONT_REG_0 (TVE_BASE_ADDR + 0x1014)
+#define TVEV2_REG_LUMA_SA_CONT_REG_1 (TVE_BASE_ADDR + 0x1018)
+#define TVEV2_REG_LUMA_SA_STAT_REG_0 (TVE_BASE_ADDR + 0x101c)
+#define TVEV2_REG_LUMA_SA_STAT_REG_1 (TVE_BASE_ADDR + 0x1020)
+#define TVEV2_REG_CHROMA_CONT_REG (TVE_BASE_ADDR + 0x1024)
+#define TVEV2_REG_TVDAC_0_CONT_REG (TVE_BASE_ADDR + 0x1028)
+#define TVEV2_REG_TVDAC_1_CONT_REG (TVE_BASE_ADDR + 0x102c)
+#define TVEV2_REG_TVDAC_2_CONT_REG (TVE_BASE_ADDR + 0x1030)
+#define TVEV2_REG_CD_CONT_REG (TVE_BASE_ADDR + 0x1034)
+#define TVEV2_REG_VBI_DATA_CONT_REG (TVE_BASE_ADDR + 0x1038)
+#define TVEV2_REG_VBI_DATA_REG_0 (TVE_BASE_ADDR + 0x103c)
+#define TVEV2_REG_VBI_DATA_REG_1 (TVE_BASE_ADDR + 0x1040)
+#define TVEV2_REG_VBI_DATA_REG_2 (TVE_BASE_ADDR + 0x1044)
+#define TVEV2_REG_VBI_DATA_REG_3 (TVE_BASE_ADDR + 0x1048)
+#define TVEV2_REG_VBI_DATA_REG_4 (TVE_BASE_ADDR + 0x104c)
+#define TVEV2_REG_VBI_DATA_REG_5 (TVE_BASE_ADDR + 0x1050)
+#define TVEV2_REG_VBI_DATA_REG_6 (TVE_BASE_ADDR + 0x1054)
+#define TVEV2_REG_VBI_DATA_REG_7 (TVE_BASE_ADDR + 0x1058)
+#define TVEV2_REG_VBI_DATA_REG_8 (TVE_BASE_ADDR + 0x105c)
+#define TVEV2_REG_VBI_DATA_REG_9 (TVE_BASE_ADDR + 0x1060)
+#define TVEV2_REG_INT_CONT_REG (TVE_BASE_ADDR + 0x1064)
+#define TVEV2_REG_STAT_REG (TVE_BASE_ADDR + 0x1068)
+#define TVEV2_REG_TST_MODE_REG (TVE_BASE_ADDR + 0x106c)
+#define TVEV2_REG_USER_MODE_CONT_REG (TVE_BASE_ADDR + 0x1070)
+#define TVEV2_REG_SD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1074)
+#define TVEV2_REG_SD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1078)
+#define TVEV2_REG_SD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x107c)
+#define TVEV2_REG_HD_TIMING_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x1080)
+#define TVEV2_REG_HD_TIMING_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1084)
+#define TVEV2_REG_HD_TIMING_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1088)
+#define TVEV2_REG_LUMA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x108c)
+#define TVEV2_REG_LUMA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x1090)
+#define TVEV2_REG_LUMA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x1094)
+#define TVEV2_REG_LUMA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x1098)
+#define TVEV2_REG_CSC_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x109c)
+#define TVEV2_REG_CSC_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10a0)
+#define TVEV2_REG_CSC_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10a4)
+#define TVEV2_REG_BLANK_USR_CONT_REG (TVE_BASE_ADDR + 0x10a8)
+#define TVEV2_REG_SD_MOD_USR_CONT_REG (TVE_BASE_ADDR + 0x10ac)
+#define TVEV2_REG_VBI_DATA_USR_CONT_REG_0 (TVE_BASE_ADDR + 0x10b0)
+#define TVEV2_REG_VBI_DATA_USR_CONT_REG_1 (TVE_BASE_ADDR + 0x10b4)
+#define TVEV2_REG_VBI_DATA_USR_CONT_REG_2 (TVE_BASE_ADDR + 0x10b8)
+#define TVEV2_REG_VBI_DATA_USR_CONT_REG_3 (TVE_BASE_ADDR + 0x10bc)
+#define TVEV2_REG_VBI_DATA_USR_CONT_REG_4 (TVE_BASE_ADDR + 0x10c0)
+#define TVEV2_REG_DROP_COMP_USR_CONT_REG (TVE_BASE_ADDR + 0x10c4)
+#define TVEV2_REG_MAC_WORD_REG_0 (TVE_BASE_ADDR + 0x10c8)
+#define TVEV2_REG_MAC_WORD_REG_1 (TVE_BASE_ADDR + 0x10cc)
+#define TVEV2_REG_MAC_WORD_REG_2 (TVE_BASE_ADDR + 0x10d0)
+#define TVEV2_REG_MAC_WORD_REG_3 (TVE_BASE_ADDR + 0x10d4)
+#define TVEV2_REG_MAC_WORD_REG_4 (TVE_BASE_ADDR + 0x10d8)
+#define TVEV2_REG_MAC_CONT_REG (TVE_BASE_ADDR + 0x10dc)
+
+#endif
diff --git a/packages/devs/ipu/arm/imx/v1_0/include/xec_dls.h b/packages/devs/ipu/arm/imx/v1_0/include/xec_dls.h
new file mode 100644 (file)
index 0000000..99be112
--- /dev/null
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc.
+ *
+ * All modifications are confidential and proprietary information
+ * of Freescale Semiconductor, Inc. ALL RIGHTS RESERVED.
+ *
+ */
+/*!
+ * @file xec_dls.h
+ *
+ * @brief This file contains the XEC_LCD dls part declarations.
+ *
+ */
+#ifndef __XEC_DLS_H__
+#define __XEC_DLS_H__
+
+#define SSIM_XSTEP 4
+#define SSIM_YSTEP 4
+
+/* default configures for xec dls algorithm */
+#define XECDLS_frameStep               6
+#define XECDLS_xStep                           4
+#define XECDLS_yStep                           4
+#define XECDLS_yMaxPrime               235
+#define XECDLS_disTh                           500     /*xxxx = xx.xx */
+#define XECDLS_blDeltaMax              30
+#define XECDLS_alphaMax                138     /* 149 */
+#define XECDLS_yRangeMax               255
+#define XECDLS_yRangeMin               0
+#define XECDLS_FFilter_Step    3
+#define XECDLS_ALPHA_Step      109     /* gamma=2. or 108 if gamma=2.20 */
+#define XECDLS_BLDelay                 20
+#define XECDLS_BLStep                  3
+
+enum XECDLS_FRAME_FORMAT {
+       XECDLS_YV12 = 0,
+       XECDLS_RGB888,
+       XECDLS_YUYV,
+};
+
+struct xecDlsFrameInfo {
+       unsigned char *framePointer;
+       int width;
+       int height;
+       int rectTop;
+       int rectBottom;
+       int rectLeft;
+       int rectRight;
+       int ambientBacklight;
+       enum XECDLS_FRAME_FORMAT frameFormat;
+       int bytesPerPixel;
+       int index;
+};
+
+struct xecDlsConfig {
+       int yMaxPrime;
+       int yRangeMin;
+       int yRangeMax;
+       int xStep;
+       int yStep;
+       int disThreshold;
+       int alphaMax;
+       int blDeltaMax;
+       int frameStep;
+       int blStep;
+       int blDelay;
+};
+
+struct xecDlsOutput {
+       unsigned short pendingAlpha;
+       int pendingBLChange;
+       int pending;
+};
+struct xec_dls_params{
+       int prevCurrent;
+       int curCurrent;
+       int diffCurrent;
+       int prevAlpha;
+       int curAlpha;
+       int diffAlpha;
+       int stepSize;
+       int stepNum;
+       int stepCounter;
+       int lastStep;
+};
+
+typedef struct image_block{
+       unsigned int startAddr;
+       int blockXSize;
+       int blockYSize;
+       int xStride;
+       int yStride;
+}image_block_t;
+
+void xec_dls_core_init(void);
+void xec_dls_core(struct xecDlsFrameInfo g_xecDlsCoreFrameInfo);
+void xec_dls_stream_init(void);
+int xec_dls_perform(unsigned char *frame, int xSize, int ySize,
+                          int pixelformat, int index);
+#endif
+
diff --git a/packages/devs/ipu/arm/imx/v1_0/src/ipu_common.c b/packages/devs/ipu/arm/imx/v1_0/src/ipu_common.c
new file mode 100644 (file)
index 0000000..0f3bde6
--- /dev/null
@@ -0,0 +1,171 @@
+/***************************************************************************
+*
+*                                                    IPU_COMMON.C
+*
+* Copyright 2005-2006 by Freescale Semiconductor, Inc.
+* All modifications are confidential and proprietary information
+* of Freescale Semiconductor, Inc. ALL RIGHTS RESERVED.
+*
+***************************************************************************
+*
+* Author(s)            :               Ray Sun-B17777 <Yanfei.Sun@freescale.com>
+* Create Date  :               2008-11-10
+* Description  :               common functions definition for IPU API.
+*
+***************************************************************************/
+#include <cyg/io/ipu_common.h>
+#ifdef CYGPKG_REDBOOT
+#include <redboot.h>
+#endif
+#include <cyg/io/flash.h>
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+#endif
+#ifdef CYGOPT_REDBOOT_FIS
+#include <fis.h>
+#endif
+
+/*
+* write bit fields of special IPU regs
+*/
+void ipu_write_field(unsigned int id_addr, unsigned int id_mask, unsigned int data)
+{
+       unsigned int rdata;
+
+       id_addr += IPU_CTRL_BASE_ADDR;
+       rdata = readl(id_addr);
+       rdata &= ~id_mask;
+       rdata |= (data * (id_mask & -id_mask)) & id_mask;
+       writel(rdata, id_addr);
+}
+
+/*
+*      enable ipu display
+*/
+void ipu_enable_display(void)
+{
+       //enable DI0 (display interface 1)
+       ipu_write_field(IPU_IPU_CONF__DP_EN, 1);
+       ipu_write_field(IPU_IPU_CONF__DC_EN, 1);
+       ipu_write_field(IPU_IPU_CONF__DMFC_EN, 1);
+       ipu_write_field(IPU_IPU_CONF__DI0_EN, 1);
+       ipu_write_field(IPU_IPU_CONF__DI1_EN, 1);
+#ifdef CYGPKG_HAL_ARM_MX51_3STACK
+       ipu_write_field(IPU_IPU_CONF__CSI1_EN, 1);
+#endif
+}
+
+/*
+*      disable ipu display
+*/
+void ipu_disable_display(void)
+{
+       ipu_write_field(IPU_IPU_CONF__DI0_EN, 0);
+       ipu_write_field(IPU_IPU_CONF__DI1_EN, 0);
+       ipu_write_field(IPU_IPU_CONF__DP_EN, 0);
+       ipu_write_field(IPU_IPU_CONF__DC_EN, 0);
+       ipu_write_field(IPU_IPU_CONF__DMFC_EN, 0);
+       ipu_write_field(IPU_IPU_CONF__IC_EN, 0);
+#ifdef CYGPKG_HAL_ARM_MX51_3STACK
+       ipu_write_field(IPU_IPU_CONF__CSI0_EN, 0);
+       ipu_write_field(IPU_IPU_CONF__CSI1_EN, 0);
+       ipu_write_field(IPU_IPU_CONF__SMFC_EN, 0);
+#endif
+       ipu_write_field(IPU_IC_CONF__PP_EN, 0);
+       ipu_write_field(IPU_IC_CONF__PRPVF_EN, 0);
+       ipu_write_field(IPU_IC_CONF__PRPENC_EN, 0);
+}
+
+#ifdef CYGHWR_MX51_LCD_LOGO
+static display_buffer_info_t display_buffer;
+
+/*!
+* load the logo from nand flash to memory.
+*/
+static bool do_logo_load(void)
+{
+       void *fis_addr;
+       int ret = 0xFF;
+       void *err_addr;
+       unsigned int logo_size;
+       struct fis_image_desc *img;
+
+       /* Read the logo from storage media */
+       if ((img = fis_lookup("logo", NULL)) == NULL) {
+               diag_printf("No logo partition found in the fis table, logo not loaded\n");
+               return false;
+       }
+
+       fis_addr = (void *)img->flash_base;
+       logo_size = img->size;
+       ret = FLASH_READ(fis_addr, DISPLAY_BUFFER_ADDR, logo_size, &err_addr);
+       if (ret != 0) {
+               diag_printf("Loading logo from FLASH to MEMORY failed. error code: %d", ret);
+       }
+       return true;
+}
+
+/*!
+* this function is used to reset ipu by SRC(system reset controller)
+* the return value should be negative if resetting timeout
+*/
+#define IPU_RESET      (1 << 3)
+static int ipu_sw_reset(int timeout)
+{
+       int tmpVal;
+
+       tmpVal = readl(SRC_BASE_ADDR);
+       writel(tmpVal | IPU_RESET, SRC_BASE_ADDR);
+       while (timeout > 0) {
+               if (!(readl(SRC_BASE_ADDR) & IPU_RESET))
+                       return 0;
+               timeout--;
+       }
+       diag_printf("Error: ipu software reset timed out\n");
+       return -1;
+}
+
+static void redboot_fastlogo_display(void)
+{
+       bool fastlogo_feature_enable;
+       int ok;
+
+       ok = CYGACC_CALL_IF_FLASH_CFG_OP(CYGNUM_CALL_IF_FLASH_CFG_GET,
+                                                                       "fastlogo_enable", &fastlogo_feature_enable, CONFIG_BOOL);
+
+       if (ok && fastlogo_feature_enable) {
+               display_buffer.startAddr = (CYG_ADDRESS)DISPLAY_BUFFER_ADDR;
+               display_buffer.width = 640;
+               display_buffer.height = 480;
+               display_buffer.dataFormat = RGB565;
+               display_buffer.bpp = 16; // bit per pixel
+               display_buffer.channel = 28;
+
+               ipu_sw_reset(0x10000);
+               if (!do_logo_load()) {
+                       return;
+               }
+               //mxc_ipu_iomux_config();
+               //lcd_backlit_on();
+               //lcd_config();
+               fastlogo_init(&display_buffer);
+               fastlogo_dma();
+               fastlogo_dmfc();
+               fastlogo_dc();
+               fastlogo_di();
+               ipu_enable_display();
+               ipu_idmac_channel_buf_ready(display_buffer.channel, 0);
+       }
+}
+
+#ifdef CYGPKG_REDBOOT
+RedBoot_init(redboot_fastlogo_display, RedBoot_INIT_SECOND);
+#endif
+
+RedBoot_config_option("Enable fast logo display at boot",
+                                       fastlogo_enable,
+                                       ALWAYS_ENABLED, true,
+                                       CONFIG_BOOL,
+                                       false
+       );
+#endif
diff --git a/packages/devs/ipu/arm/imx/v1_0/src/ipu_display.c b/packages/devs/ipu/arm/imx/v1_0/src/ipu_display.c
new file mode 100644 (file)
index 0000000..57579c3
--- /dev/null
@@ -0,0 +1,145 @@
+//==========================================================================
+//
+//      IPU_DI.c
+//
+//      common functions definitions for IPU modules operation
+//
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       Ray Sun <Yanfei.Sun@freescale.com>
+// Create Date: 2008-07-31
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <cyg/io/ipu_common.h>
+#include <cyg/hal/hal_soc.h>    // Hardware definitions
+
+/*
+* this function is used to config the waveform generator in the DI
+*/
+void ipu_di_sync_config(int di, int pointer, di_sync_wave_gen_t sync_waveform_gen)
+{
+       ipu_write_field(DI_SWGEN0_RUN_VALUE_M1(di, pointer), sync_waveform_gen.runValue);
+       ipu_write_field(DI_SWGEN0_RUN_RESOL(di, pointer), sync_waveform_gen.runResolution);
+       ipu_write_field(DI_SWGEN0_OFFSET_VALUE(di, pointer), sync_waveform_gen.offsetValue);
+       ipu_write_field(DI_SWGEN0_OFFSET_RESOL(di, pointer), sync_waveform_gen.offsetResolution);
+       ipu_write_field(DI_SWGEN1_CNT_POL_GEN_EN(di, pointer), sync_waveform_gen.cntPolarityGenEn);
+       ipu_write_field(DI_SWGEN1_CNT_AUTOLOAD(di, pointer), sync_waveform_gen.cntAutoReload);
+       ipu_write_field(DI_SWGEN1_CNT_CLR_SEL(di, pointer), sync_waveform_gen.cntClrSel);
+       ipu_write_field(DI_SWGEN1_CNT_DOW(di, pointer), sync_waveform_gen.cntDown);
+       ipu_write_field(DI_SWGEN1_CNT_POL_TRIG_SEL(di, pointer), sync_waveform_gen.cntPolarityTrigSel);
+       ipu_write_field(DI_SWGEN1_CNT_POL_CLR_SEL(di, pointer), sync_waveform_gen.cntPolarityClrSel);
+       ipu_write_field(DI_SWGEN1_CNT_CNT_UP(di, pointer), sync_waveform_gen.cntUp);
+       ipu_write_field(DI_STEP_RPT(di, pointer), sync_waveform_gen.stepRepeat);
+
+       return;
+}
+
+void ipu_di_pointer_config(int di, int pointer, int access, int component, int cst, int pt0,
+                                               int pt1, int pt2, int pt3, int pt4, int pt5, int pt6)
+{
+       unsigned int regVal = 0;
+       regVal =
+               (access << 24) | (component << 16) | (cst << 14) | (pt6 << 12) | (pt5 << 10) | (pt4 << 8) |
+               (pt3 << 6) | (pt2 << 4) | (pt1 << 2) | pt0;
+
+       if (di == 0) {
+               writel(regVal, IPU_CTRL_BASE_ADDR + IPU_DI0_DW_GEN_0__ADDR + pointer * 4);
+       } else {
+               writel(regVal, IPU_CTRL_BASE_ADDR + IPU_DI1_DW_GEN_0__ADDR + pointer * 4);
+       }
+       return;
+}
+
+void ipu_di_waveform_config(int di, int pointer, int set, int up, int down)
+{
+       ipu_write_field(DI_WAVESET_UP(di, pointer, set), up);
+       ipu_write_field(DI_WAVESET_DOWN(di, pointer, set), down);
+
+       return;
+}
+
+int ipu_di_bsclk_gen(int di, int division, int up, int down)
+{
+       switch (di) {
+       case 0:
+               ipu_write_field(IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_OFFSET, 0);
+               ipu_write_field(IPU_DI0_BS_CLKGEN0__DI0_DISP_CLK_PERIOD, division);
+               ipu_write_field(IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_DOWN, down);
+               ipu_write_field(IPU_DI0_BS_CLKGEN1__DI0_DISP_CLK_UP, up);
+               break;
+
+       case 1:
+               ipu_write_field(IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_OFFSET, 0);
+               ipu_write_field(IPU_DI1_BS_CLKGEN0__DI1_DISP_CLK_PERIOD, division);
+               ipu_write_field(IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_DOWN, down);
+               ipu_write_field(IPU_DI1_BS_CLKGEN1__DI1_DISP_CLK_UP, up);
+               break;
+
+       default:
+               ERRDP("Wrong di pointer!\n");
+               return -1;
+       }
+       return 0;
+}
+
+int ipu_di_screen_set(int di, int screen_height)
+{
+       switch (di) {
+       case 0:
+               ipu_write_field(IPU_DI0_SCR_CONF__DI0_SCREEN_HEIGHT, screen_height);
+               break;
+
+       case 1:
+               ipu_write_field(IPU_DI1_SCR_CONF__DI1_SCREEN_HEIGHT, screen_height);
+               break;
+
+       default:
+               ERRDP("Wrong di pointer!\n");
+               return -1;
+       }
+       return 0;
+}
+
+int ipu_di_general_set(int di, int line_prediction, int vsync_sel, int hsync_sel, int clk_sel)
+{
+       switch (di) {
+       case 0:
+               ipu_write_field(IPU_DI0_SYNC_AS_GEN__DI0_SYNC_START, line_prediction);
+               ipu_write_field(IPU_DI0_SYNC_AS_GEN__DI0_VSYNC_SEL, vsync_sel);
+               ipu_write_field(IPU_DI0_GENERAL__DI0_CLK_EXT, clk_sel);
+
+               ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_DISP_CLK, 1);
+               ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_3, 0);    //HSYNC polarity, active low
+               ipu_write_field(IPU_DI0_GENERAL__DI0_POLARITY_2, 0);    //VSYNC polarity, active low
+               ipu_write_field(IPU_DI0_POL__DI0_DRDY_POLARITY_15, 1);  //VIDEO_DATA_EN polarity, active hign
+
+               /* release ipu DI0 counter */
+               ipu_write_field(IPU_IPU_DISP_GEN__DI0_COUNTER_RELEASE, 1);
+               break;
+
+       case 1:
+               ipu_write_field(IPU_DI1_SYNC_AS_GEN__DI1_SYNC_START, line_prediction);
+               ipu_write_field(IPU_DI1_SYNC_AS_GEN__DI1_VSYNC_SEL, vsync_sel);
+               ipu_write_field(IPU_DI1_GENERAL__DI1_DISP_Y_SEL, hsync_sel);
+               ipu_write_field(IPU_DI1_GENERAL__DI1_CLK_EXT, clk_sel);
+
+               ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_DISP_CLK, 0);
+               ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_8, 1);
+               ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_5, 1);
+               ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_3, 1);    //HSYNC POLARITY
+               ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_2, 1);    //VSYNC POLARITY
+               ipu_write_field(IPU_DI1_POL__DI1_DRDY_POLARITY_15, 1);
+               /* release ipu DI1 counter */
+               ipu_write_field(IPU_IPU_DISP_GEN__DI1_COUNTER_RELEASE, 1);
+               break;
+
+       default:
+               ERRDP("Wrong di pointer!\n");
+               return -1;
+       }
+       return 0;
+}
diff --git a/packages/devs/ipu/arm/imx/v1_0/src/ipu_dma.c b/packages/devs/ipu/arm/imx/v1_0/src/ipu_dma.c
new file mode 100644 (file)
index 0000000..aa23f85
--- /dev/null
@@ -0,0 +1,224 @@
+//==========================================================================
+//
+//      IPU_COMMON.c
+//
+//      common functions definitions for IPU modules operation
+//
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       Ray Sun <Yanfei.Sun@freescale.com>
+// Create Date: 2008-07-31
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <string.h>
+#include <cyg/io/ipu_common.h>
+
+void ipu_idmac_params_init(ipu_channel_parameter_t *ipu_channel_params_ptr)
+{
+       memset(ipu_channel_params_ptr, 0, sizeof(ipu_channel_parameter_t));
+}
+
+/*
+* config the dma channel to be interleaved mode
+*/
+void ipu_idmac_interleaved_channel_config(ipu_channel_parameter_t ipu_channel_params)
+{
+       int w0_d0 = 0, w0_d1 = 0, w0_d2 = 0, w0_d3 = 0, w0_d4 = 0, w1_d0 = 0, w1_d1 = 0, w1_d2 =
+               0, w1_d3 = 0, w1_d4 = 0;
+
+       w0_d0 = ipu_channel_params.xb << 19 | ipu_channel_params.yv << 10 | ipu_channel_params.xv;
+       w0_d1 =
+               ipu_channel_params.sy << 26 | ipu_channel_params.sx << 14 | ipu_channel_params.
+               cf << 13 | ipu_channel_params.nsb_b << 12 | ipu_channel_params.yb;
+       w0_d2 =
+               ipu_channel_params.sm << 22 | ipu_channel_params.sdx << 15 | ipu_channel_params.
+               ns << 5 | ipu_channel_params.sy >> 6;
+       w0_d3 =
+               ipu_channel_params.fw << 29 | ipu_channel_params.cae << 28 | ipu_channel_params.
+               cap << 27 | ipu_channel_params.the << 26 | ipu_channel_params.vf << 25 | ipu_channel_params.
+               hf << 24 | ipu_channel_params.rot << 23 | ipu_channel_params.bm << 21 | ipu_channel_params.
+               bndm << 18 | ipu_channel_params.so << 17 | ipu_channel_params.
+               dim << 16 | ipu_channel_params.dec_sel << 14 | ipu_channel_params.
+               bpp << 11 | ipu_channel_params.sdry << 10 | ipu_channel_params.
+               sdrx << 9 | ipu_channel_params.sdy << 2 | ipu_channel_params.sce << 1 | ipu_channel_params.
+               scc;
+       w0_d4 = ipu_channel_params.fh << 10 | ipu_channel_params.fw >> 3;
+
+       w1_d0 = ipu_channel_params.eba1 << 29 | ipu_channel_params.eba0;
+       w1_d1 = ipu_channel_params.ilo << 26 | ipu_channel_params.eba1 >> 3;
+       w1_d2 =
+               ipu_channel_params.th << 31 | ipu_channel_params.id << 29 | ipu_channel_params.
+               albm << 26 | ipu_channel_params.alu << 25 | ipu_channel_params.
+               pfs << 21 | ipu_channel_params.npb << 14 | ipu_channel_params.ilo >> 6;
+       w1_d3 =
+               ipu_channel_params.wid3 << 29 | ipu_channel_params.wid2 << 26 | ipu_channel_params.
+               wid1 << 23 | ipu_channel_params.wid0 << 20 | ipu_channel_params.
+               sl << 6 | ipu_channel_params.th >> 1;
+       w1_d4 =
+               ipu_channel_params.ofs3 << 15 | ipu_channel_params.ofs2 << 10 | ipu_channel_params.
+               ofs1 << 5 | ipu_channel_params.ofs0;
+
+       /* config the cpmem */
+       writel(w0_d0,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA0_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w0_d1,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA1_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w0_d2,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA2_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w0_d3,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA3_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w0_d4,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD0_DATA4_INT__ADDR + (ipu_channel_params.channel << 6));
+
+       writel(w1_d0,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA0_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w1_d1,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA1_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w1_d2,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA2_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w1_d3,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA3_INT__ADDR + (ipu_channel_params.channel << 6));
+       writel(w1_d4,
+               IPU_CTRL_BASE_ADDR + CPMEM_WORD1_DATA4_INT__ADDR + (ipu_channel_params.channel << 6));
+}
+
+void ipu_idmac_channel_buf_ready(int channel, int buf)
+{
+       int idx = channel / 32;
+       int offset = channel % 32;
+       if (idx) {
+               if (buf) {
+                       ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF1_RDY1_CLR, 0);
+                       ipu_write_field(IPU_IPU_CH_BUF1_RDY1__ADDR, 1 << offset, 1);
+               } else {
+                       ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF0_RDY1_CLR, 0);
+                       ipu_write_field(IPU_IPU_CH_BUF0_RDY1__ADDR, 1 << offset, 1);
+               }
+       } else {
+               if (buf) {
+                       ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF1_RDY0_CLR, 0);
+                       ipu_write_field(IPU_IPU_CH_BUF1_RDY0__ADDR, 1 << offset, 1);
+               } else {
+                       ipu_write_field(IPU_IPU_GPR__IPU_CH_BUF0_RDY0_CLR, 0);
+                       ipu_write_field(IPU_IPU_CH_BUF0_RDY0__ADDR, 1 << offset, 1);
+               }
+       }
+}
+
+void ipu_idmac_channel_mode_sel(int channel, int double_buf_en)
+{
+       int idx = channel / 32;
+       int offset = channel % 32;
+       ipu_write_field(IPU_IPU_CH_DB_MODE_SEL_0__ADDR + idx * 4, 1 << offset, double_buf_en);
+}
+
+void ipu_idmac_channel_enable(int channel, int enable)
+{
+       int idx = channel / 32;
+       int offset = channel % 32;
+       ipu_write_field(IPU_IDMAC_CH_EN_1__ADDR + idx * 4, 1 << offset, enable);
+}
+
+int ipu_idmac_channel_busy(int channel)
+{
+       int idx, offset;
+       idx = channel / 32;
+       offset = channel % 32;
+       return ((readl(IPU_CTRL_BASE_ADDR + IPU_IDMAC_CH_BUSY_1__ADDR + 4 * idx) & (1 << offset)) >>
+                       offset);
+}
+
+int ipu_idmac_chan_cur_buff(int channel)
+{
+       int idx, offset;
+       idx = channel / 32;
+       offset = channel % 32;
+       return ((readl(IPU_CTRL_BASE_ADDR + IPU_IPU_CUR_BUF_0__ADDR + 4 * idx) & (1 << offset)) >>
+                       offset);
+}
+
+int ipu_idamc_chan_eof_int(int channel)
+{
+       int idx, offset;
+       idx = channel / 32;
+       offset = channel % 32;
+       return ((readl(IPU_CTRL_BASE_ADDR + IPU_IPU_INT_STAT_1__ADDR + 4 * idx) & (1 << offset)) >>
+                       offset);
+}
+
+int ipu_idmac_chan_till_idle(int channel, int timeout)
+{
+       int i = 0;
+       unsigned int chanBusy;
+
+       while (i < timeout) {
+               chanBusy = ipu_idmac_channel_busy(channel);
+               if (!chanBusy) {
+//          diag_printf("\ncount cycles:%d\n",i);
+                       __asm("nop");
+                       return 0;
+               }
+               i++;
+       }
+       ERRDP("can not get channel %d idle state\n", channel);
+       return -1;
+}
+
+/*
+* allocate dmfc fifo for ipu display channel
+*/
+int ipu_dmfc_fifo_allocate(int channel, int fifo_size, int burst_size, int offset_addr)
+{
+
+       if (fifo_size > 7 || fifo_size < 0) {
+               ERRDP("FIFO size is wrong! range from 0 to 7.\n");
+               return -1;
+       }
+       if (burst_size > 3 || burst_size < 0) {
+               ERRDP("Burst size is wrong! range from 0 to 3.\n");
+               return -1;
+       }
+       if (offset_addr < 0 || offset_addr > 7) {
+               ERRDP("Start addr of FIFO is wrong! range from 0 to 7.\n");
+               return -1;
+       }
+       switch (channel) {
+       case 28:
+               ipu_write_field(IPU_DMFC_WR_CHAN__DMFC_FIFO_SIZE_1, fifo_size);
+               ipu_write_field(IPU_DMFC_WR_CHAN__DMFC_BURST_SIZE_1, burst_size);
+               ipu_write_field(IPU_DMFC_WR_CHAN__DMFC_ST_ADDR_1, offset_addr);
+               ipu_write_field(IPU_DMFC_WR_CHAN_DEF__DMFC_WM_CLR_1, 0);
+               ipu_write_field(IPU_DMFC_WR_CHAN_DEF__DMFC_WM_SET_1, 0);
+               ipu_write_field(IPU_DMFC_WR_CHAN_DEF__DMFC_WM_EN_1, 0);
+               ipu_write_field(IPU_DMFC_GENERAL1__WAIT4EOT_1, 0);
+               break;
+
+       case 23:
+               ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5B, fifo_size);
+               ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5B, burst_size);
+               ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5B, offset_addr);
+               ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5B, 0);
+               ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5B, 0);
+               ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5B, 0);
+               ipu_write_field(IPU_DMFC_GENERAL1__WAIT4EOT_5B, 0);
+               break;
+
+       case 27:
+               ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_FIFO_SIZE_5F, fifo_size);
+               ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_BURST_SIZE_5F, burst_size);
+               ipu_write_field(IPU_DMFC_DP_CHAN__DMFC_ST_ADDR_5F, offset_addr);
+               ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_CLR_5F, 0);
+               ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_SET_5F, 0);
+               ipu_write_field(IPU_DMFC_DP_CHAN_DEF__DMFC_WM_EN_5F, 0);
+               ipu_write_field(IPU_DMFC_GENERAL1__WAIT4EOT_5F, 0);
+               break;
+       default:
+               ERRDP("Channel selection error!!\n");
+               return -1;
+       }
+       return 0;
+}
diff --git a/packages/devs/ipu/arm/imx/v1_0/src/ipu_proc.c b/packages/devs/ipu/arm/imx/v1_0/src/ipu_proc.c
new file mode 100644 (file)
index 0000000..294a5bc
--- /dev/null
@@ -0,0 +1,774 @@
+//==========================================================================
+//
+//      IPU_COMMON.c
+//
+//      common functions definitions for IPU modules operation
+//
+//==========================================================================
+//#####DESCRIPTIONBEGIN####
+//
+// Author(s):       Ray Sun <Yanfei.Sun@freescale.com>
+// Create Date: 2008-07-31
+//
+//####DESCRIPTIONEND####
+//
+//==========================================================================
+
+#include <string.h>
+#include <cyg/io/ipu_common.h>
+#include <cyg/io/xec_dls.h>
+
+extern struct xec_dls_params xecDlsParams;
+
+void ipu_ic_enable(int ic_enable, int irt_enable)
+{
+       ipu_write_field(IPU_IPU_CONF__IC_EN, ic_enable);
+       ipu_write_field(IPU_IPU_CONF__IRT_EN, irt_enable);
+}
+
+/*
+* this function is used to config the rotation/resizing task perform by the Image Converter
+*/
+void ipu_ic_task_config(ipu_task_params_t task_params)
+{
+       int resCoff, downsCoff;
+
+       switch (task_params.taskType) {
+       case PrP_ENC_TASK:
+               ipu_write_field(IPU_IC_CONF__PRPENC_EN, 0);
+               ipu_write_field(IPU_IC_CONF__RWS_EN, 1);
+               ipu_write_field(IPU_IPU_FS_PROC_FLOW1__ENC_IN_VALID, 1);
+               ipu_write_field(IPU_IC_IDMAC_1__CB0_BURST_16, 1);   // set to 16bps
+               ipu_write_field(IPU_IC_IDMAC_1__CB6_BURST_16, 1);
+               ipu_write_field(IPU_IC_CONF__PRPENC_EN, 1);
+               ipu_write_field(IPU_IC_CONF__PRPENC_ROT_EN, task_params.rotEnable);
+               /* set rotation task */
+               if (task_params.rotEnable) {
+                       ipu_write_field(IPU_IC_IDMAC_1__T1_FLIP_LR, task_params.rotInfo.HorizFlip);
+                       ipu_write_field(IPU_IC_IDMAC_1__T1_FLIP_UD, task_params.rotInfo.VertFlip);
+                       ipu_write_field(IPU_IC_IDMAC_1__T1_ROT, task_params.rotInfo.rotation);
+               }
+               /* set resizing task */
+               if (task_params.resEnable) {
+                       ipu_write_field(IPU_IC_IDMAC_2__T1_FR_HEIGHT, task_params.resInfo.outHeight - 1);
+                       ipu_write_field(IPU_IC_IDMAC_3__T1_FR_WIDTH, task_params.resInfo.outWidth - 1);
+
+                       ipu_ic_calc_resize_coeffs(task_params.resInfo.inWidth, task_params.resInfo.outWidth,
+                                                                       &resCoff, &downsCoff);
+                       ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_H, downsCoff);
+                       ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_H, resCoff);
+                       ipu_ic_calc_resize_coeffs(task_params.resInfo.inHeight, task_params.resInfo.outHeight,
+                                                                       &resCoff, &downsCoff);
+
+                       ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_DS_R_V, downsCoff);
+                       ipu_write_field(IPU_IC_PRP_ENC_RSC__PRPENC_RS_R_V, resCoff);
+               }
+               ipu_write_field(IPU_IC_CONF__PRPENC_EN, 1);
+               break;
+
+       case PrP_VF_TASK:
+               ipu_write_field(IPU_IC_CONF__PRPVF_EN, 0);
+               ipu_write_field(IPU_IC_CONF__RWS_EN, 1);
+               ipu_write_field(IPU_IPU_FS_PROC_FLOW1__VF_IN_VALID, 1);
+               ipu_write_field(IPU_IC_IDMAC_1__CB1_BURST_16, 1);   // set to 16bps
+               ipu_write_field(IPU_IC_IDMAC_1__CB6_BURST_16, 1);
+               ipu_write_field(IPU_IC_CONF__PRPVF_EN, 1);
+               ipu_write_field(IPU_IC_CONF__PRPVF_ROT_EN, task_params.rotEnable);
+               // set rotation
+               if (task_params.rotEnable) {
+                       ipu_write_field(IPU_IC_IDMAC_1__T2_FLIP_LR, task_params.rotInfo.HorizFlip);
+                       ipu_write_field(IPU_IC_IDMAC_1__T2_FLIP_UD, task_params.rotInfo.VertFlip);
+                       ipu_write_field(IPU_IC_IDMAC_1__T2_ROT, task_params.rotInfo.rotation);
+               }
+               // set resizing
+               if (task_params.resEnable) {
+                       ipu_write_field(IPU_IC_IDMAC_2__T2_FR_HEIGHT, task_params.resInfo.outHeight - 1);
+                       ipu_write_field(IPU_IC_IDMAC_3__T2_FR_WIDTH, task_params.resInfo.outWidth - 1);
+
+                       ipu_ic_calc_resize_coeffs(task_params.resInfo.inWidth, task_params.resInfo.outWidth,
+                                                                       &resCoff, &downsCoff);
+                       ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_DS_R_H, downsCoff);
+                       ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_RS_R_H, resCoff);
+                       ipu_ic_calc_resize_coeffs(task_params.resInfo.inHeight, task_params.resInfo.outHeight,
+                                                                       &resCoff, &downsCoff);
+                       ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_DS_R_V, downsCoff);
+                       ipu_write_field(IPU_IC_PRP_VF_RSC__PRPVF_RS_R_V, resCoff);
+               }
+               ipu_write_field(IPU_IC_CONF__PRPVF_EN, 1);
+               break;
+
+       case PP_TASK:
+               ipu_write_field(IPU_IC_CONF__PP_EN, 0);
+               ipu_write_field(IPU_IC_IDMAC_1__CB2_BURST_16, 1);   // set to 16bps
+               ipu_write_field(IPU_IC_IDMAC_1__CB5_BURST_16, 1);
+               ipu_write_field(IPU_IC_CONF__PP_EN, 1);
+               ipu_write_field(IPU_IC_CONF__PP_ROT_EN, task_params.rotEnable);
+               // set rotation
+               if (task_params.rotEnable) {
+                       ipu_write_field(IPU_IC_IDMAC_1__T3_FLIP_LR, task_params.rotInfo.HorizFlip);
+                       ipu_write_field(IPU_IC_IDMAC_1__T3_FLIP_UD, task_params.rotInfo.VertFlip);
+                       ipu_write_field(IPU_IC_IDMAC_1__T3_ROT, task_params.rotInfo.rotation);
+               }
+               // set resizing
+               if (task_params.resEnable) {
+                       ipu_write_field(IPU_IC_IDMAC_2__T3_FR_HEIGHT, task_params.resInfo.outHeight - 1);
+                       ipu_write_field(IPU_IC_IDMAC_3__T3_FR_WIDTH, task_params.resInfo.outWidth - 1);
+
+                       ipu_ic_calc_resize_coeffs(task_params.resInfo.inWidth, task_params.resInfo.outWidth,
+                                                                       &resCoff, &downsCoff);
+
+                       ipu_write_field(IPU_IC_PP_RSC__PP_DS_R_H, downsCoff);
+                       ipu_write_field(IPU_IC_PP_RSC__PP_RS_R_H, resCoff);
+                       ipu_ic_calc_resize_coeffs(task_params.resInfo.inHeight, task_params.resInfo.outHeight,
+                                                                       &resCoff, &downsCoff);
+
+                       ipu_write_field(IPU_IC_PP_RSC__PP_DS_R_V, downsCoff);
+                       ipu_write_field(IPU_IC_PP_RSC__PP_RS_R_V, resCoff); // FROM (1536/2 -1)->479 *8192 = 13117
+               }
+               ipu_write_field(IPU_IC_CONF__PP_EN, 1);
+               break;
+       default:
+               ERRDP("Task type is wrong, IC task configuration failed\n");
+       }
+}
+
+/*
+* this function is used to calculate the params for resizing
+*/
+void ipu_ic_calc_resize_coeffs(unsigned int in_size, unsigned int out_size,
+                                                       unsigned int *resize_coeff, unsigned int *downsize_coeff)
+{
+       unsigned int tempSize;
+       unsigned int tempDownsize;
+
+       /* Cannot downsize more than 8:1 */
+       if ((out_size << 3) < in_size)
+               return;
+
+       /* compute downsizing coefficient */
+       tempDownsize = 0;
+       tempSize = in_size;
+       while ((tempSize >= out_size * 2) && (tempDownsize < 2)) {
+               tempSize >>= 1;
+               tempDownsize++;
+       }
+       *downsize_coeff = tempDownsize;
+
+       /* compute resizing coefficient using the following equation:
+          resizeCoeff = M*(SI -1)/(SO - 1)
+          where M = 2^13, SI - input size, SO - output size    */
+       *resize_coeff = (8192L * (tempSize - 1)) / (out_size - 1);
+       if (*resize_coeff >= 16384L) {
+               ERRDP("Overflow on resize coeff.\n");
+               *resize_coeff = 0x3FFF;
+       }
+}
+
+/*
+* this function is used to set the resizing parameters
+*/
+int ipu_ic_config_resize_rate(char *task_type, unsigned int res_vert, unsigned int down_vert,
+                                                       unsigned int res_horiz, unsigned int down_horiz)
+{
+       unsigned int val;
+       val = (down_vert << 30) | (res_vert << 16) | (down_horiz << 14) | (res_horiz);
+
+       if (!strcmp(task_type, "PPTASK")) {
+               DP("Post Processing Task!\n");
+               writel(val, IPU_CTRL_BASE_ADDR + IPU_IC_PP_RSC__ADDR);
+       } else if (!strcmp(task_type, "VFTASK")) {
+               DP("View Finder Task!\n");
+               writel(val, IPU_CTRL_BASE_ADDR + IPU_IC_PRP_VF_RSC__ADDR);
+       } else if (!strcmp(task_type, "PrPTASK")) {
+               DP("Pre Processing Task!\n");
+               writel(val, IPU_CTRL_BASE_ADDR + IPU_IC_PRP_ENC_RSC__ADDR);
+       } else {
+               ERRDP("Task type is not defined!\n");
+               return -1;
+       }
+       return 0;
+}
+
+/*
+* this function is used to calculate the output size for IC resizing task
+*/
+void ipu_ic_calc_vout_size(ipu_res_info_t * info, display_device_t disp_device, int rotation,
+                                               int full_screen_enable)
+{
+       float coffHeight, coffWidth;
+
+       /* if rotation is enabled, swap the width and height */
+       if (rotation) {
+               coffWidth = (float)(disp_device.height) / info->inWidth;
+               coffHeight = (float)(disp_device.width) / info->inHeight;
+       } else {
+               coffWidth = (float)(disp_device.width) / info->inWidth;
+               coffHeight = (float)(disp_device.height) / info->inHeight;
+       }
+       /* the resizing ratio should be the same in both width and height */
+       if (coffWidth >= coffHeight) {
+               info->outWidth = info->inWidth * coffHeight;
+               info->outHeight = info->inHeight * coffHeight;
+       } else {
+               info->outWidth = info->inWidth * coffWidth;
+               info->outHeight = info->inHeight * coffWidth;
+       }
+
+       if (full_screen_enable) {
+               if(rotation) {
+                       info->outWidth = disp_device.height;
+                       info->outHeight = disp_device.width;
+               }
+               else {
+                       info->outWidth = disp_device.width;
+                       info->outHeight = disp_device.height;
+               }
+       }
+
+       /* the output of IPU resizing is up to 1024*1024 */
+       info->xSplitParts = info->outWidth / 1024 + 1;
+       info->ySplitParts = info->outHeight / 1024 + 1;
+
+       /* the image in block mode, which is 8*8 size */
+       info->outHeight -= info->outHeight % 8;
+       info->outWidth -= info->outWidth % 8;
+
+}
+
+/*
+* this function is used to config the combination task in the IC
+* local alpha with per-pixel or from separate buffer can be used
+* global alpha can be used also.
+*/
+int ipu_ic_combine_config(ic_comb_params_t comb_params)
+{
+       switch (comb_params.taskType) {
+       case PrP_VF_TASK:
+               ipu_write_field(IPU_IC_IDMAC_1__CB3_BURST_16, 1);   // set to 16bps
+               if (comb_params.alpha < 0) {
+                       ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0);  // local alpha with per-pixel
+               } else if (comb_params.alpha < 0x100) {
+                       ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 1);  // global alpha enabled
+                       ipu_write_field(IPU_IC_CMBP_1__IC_PRPVF_ALPHA_V, comb_params.alpha);    // global alpha value
+               } else {
+                       ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0);  // local alpha from separate buffer
+               }
+               ipu_write_field(IPU_IC_CONF__PRPVF_CMB,
+                                               (comb_params.alpha == 0) ? 0 : 1);
+               ipu_write_field(IPU_IC_CONF__PRPVF_EN, 1);
+               break;
+       case PP_TASK:
+               ipu_write_field(IPU_IC_IDMAC_1__CB4_BURST_16, 1);   // set to 16bps
+               if (comb_params.alpha < 0) {
+                       ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0);  // local alpha with per-pixel
+               } else if (comb_params.alpha < 0x100) {
+                       ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 1);  // global alpha enabled
+                       ipu_write_field(IPU_IC_CMBP_1__IC_PP_ALPHA_V, comb_params.alpha);   // global alpha
+               } else {
+                       ipu_write_field(IPU_IC_CONF__IC_GLB_LOC_A, 0);  // local alpha in sepatate buffer
+               }
+               ipu_write_field(IPU_IC_CONF__PP_CMB,
+                                               (comb_params.alpha == 0) ? 0 : 1);
+               ipu_write_field(IPU_IC_CONF__PP_EN, 1);
+               break;
+       default:
+               ERRDP("Task Type is wrong!!\n");
+               return -1;
+       }
+       return 0;
+}
+
+/*
+* this function is used to config the color space conversion task in the IC
+*/
+extern int xecDlsEnable;
+int ipu_ic_csc_config(int csc_set_index, ic_csc_params_t csc_params)
+{
+       unsigned int param;
+       CYG_ADDRESS tpmBaseAddr = IPU_CTRL_BASE_ADDR + 0x1F060000;
+       CYG_ADDRESS base;
+
+       if (csc_set_index != 1 && csc_set_index != 2) {
+               ERRDP("Wrong index input for IC CSC!!\n");
+               return -1;
+       }
+       /*Y = R *  .299 + G *  .587 + B *  .114;
+         U = R * -.169 + G * -.332 + B *  .500 + 128.;
+         V = R *  .500 + G * -.419 + B * -.0813 + 128.; */
+       unsigned int rgb2ycbcr_coeff[4][3] = {
+               { 0x004D, 0x0096, 0x001D },
+               { 0x01D5, 0x01AB, 0x0080 },
+               { 0x0080, 0x0195, 0x01EB },
+               { 0x0000, 0x0200, 0x0200 },   /* A0, A1, A2 */
+       };
+
+       /* transparent RGB->RGB matrix for combining
+        */
+       unsigned int rgb2rgb_coeff[4][3] = {
+               { 0x0080, 0x0000, 0x0000 },
+               { 0x0000, 0x0080, 0x0000 },
+               { 0x0000, 0x0000, 0x0080 },
+               { 0x0000, 0x0000, 0x0000 },   /* A0, A1, A2 */
+       };
+
+       /*
+         R = (1.164 * (Y - 16)) + (1.596 * (Cr - 128));
+         G = (1.164 * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+         B = (1.164 * (Y - 16)) + (2.017 * (Cb - 128);
+       */
+       unsigned int ycbcr2rgb_coeff[4][3] = {
+               { 0x95, 0x0, 0xCC },
+               { 0x95, 0x1CE, 0x198 },
+               { 0x95, 0xFF, 0x0 },
+               { 0x1E42, 0x10A, 0x1DD6 },    // A0, A1, A2
+       };
+
+       /*
+         R = (1.164 * alpha *  (Y - 16)) + (1.596 * (Cr - 128));
+         G = (1.164 * alpha * (Y - 16)) - (0.392 * (Cb - 128)) - (0.813 * (Cr - 128));
+         B = (1.164 * alpha * (Y - 16)) + (2.017 * (Cb - 128);
+       */
+       if (xecDlsEnable) {
+               /* compensation of y_coeff */
+               ycbcr2rgb_coeff[0][0] = ycbcr2rgb_coeff[0][0] * xecDlsParams.curAlpha/100;
+               ycbcr2rgb_coeff[1][0] = ycbcr2rgb_coeff[1][0] * xecDlsParams.curAlpha/100;
+               ycbcr2rgb_coeff[2][0] = ycbcr2rgb_coeff[2][0] * xecDlsParams.curAlpha/100;
+#if 0
+               /* compensation of constant coeff */
+               ycbcr2rgb_coeff[3][0] -= (1.164 * 16 * 0x2 * (xecDlsParams.curAlpha - 100)/100);
+               ycbcr2rgb_coeff[3][1] -= (1.164 * 16 * 0x2 * (xecDlsParams.curAlpha - 100)/100);
+               ycbcr2rgb_coeff[3][2] -= (1.164 * 16 * 0x2 * (xecDlsParams.curAlpha - 100)/100);
+#endif
+               DP("alpha %d \n",       xecDlsParams.curAlpha);
+       }
+
+       if (csc_set_index == 1) {
+               if (csc_params.taskType == PrP_ENC_TASK) {
+                       base = tpmBaseAddr + 0x2008;
+               } else if (csc_params.taskType == PrP_VF_TASK) {
+                       base = tpmBaseAddr + 0x4028;
+               } else if (csc_params.taskType == PP_TASK) {
+                       base = tpmBaseAddr + 0x6060;
+               } else {
+                       ERRDP("Wrong task type for IC CSC1 input!!\n");
+                       return -1;
+               }
+       } else {
+               if (csc_params.taskType == PrP_VF_TASK) {
+                       base = tpmBaseAddr + 0x4040;
+               } else if (csc_params.taskType == PP_TASK) {
+                       base = tpmBaseAddr + 0x6078;
+               } else {
+                       ERRDP("Wrong task type for IC CSC2 input!!\n");
+                       return -1;
+               }
+       }
+
+       if ((csc_params.inFormat == YCbCr) && (csc_params.outFormat == RGB)) {
+               /* Init CSC (YCbCr->RGB) */
+               param = (ycbcr2rgb_coeff[3][0] << 27) |
+                       (ycbcr2rgb_coeff[0][0] << 18) | (ycbcr2rgb_coeff[1][1] << 9) | ycbcr2rgb_coeff[2][2];
+               writel(param, base++);
+               /* scale = 2, sat = 0 */
+               param = (ycbcr2rgb_coeff[3][0] >> 5) | (2 << (40 - 32));
+               writel(param, base++);
+
+               param = (ycbcr2rgb_coeff[3][1] << 27) |
+                       (ycbcr2rgb_coeff[0][1] << 18) | (ycbcr2rgb_coeff[1][0] << 9) | ycbcr2rgb_coeff[2][0];
+               writel(param, base++);
+               param = (ycbcr2rgb_coeff[3][1] >> 5);
+               writel(param, base++);
+
+               param = (ycbcr2rgb_coeff[3][2] << 27) |
+                       (ycbcr2rgb_coeff[0][2] << 18) | (ycbcr2rgb_coeff[1][2] << 9) | ycbcr2rgb_coeff[2][1];
+               writel(param, base++);
+               param = (ycbcr2rgb_coeff[3][2] >> 5);
+               writel(param, base++);
+       } else if ((csc_params.inFormat == RGB) && (csc_params.outFormat == YCbCr)) {
+               /* Init CSC1 (RGB->YCbCr) */
+               param = (rgb2ycbcr_coeff[3][0] << 27) |
+                       (rgb2ycbcr_coeff[0][0] << 18) | (rgb2ycbcr_coeff[1][1] << 9) | rgb2ycbcr_coeff[2][2];
+               writel(param, base++);
+               /* scale = 1, sat = 0 */
+               param = (rgb2ycbcr_coeff[3][0] >> 5) | (1UL << 8);
+               writel(param, base++);
+
+               param = (rgb2ycbcr_coeff[3][1] << 27) |
+                       (rgb2ycbcr_coeff[0][1] << 18) | (rgb2ycbcr_coeff[1][0] << 9) | rgb2ycbcr_coeff[2][0];
+               writel(param, base++);
+               param = (rgb2ycbcr_coeff[3][1] >> 5);
+               writel(param, base++);
+
+               param = (rgb2ycbcr_coeff[3][2] << 27) |
+                       (rgb2ycbcr_coeff[0][2] << 18) | (rgb2ycbcr_coeff[1][2] << 9) | rgb2ycbcr_coeff[2][1];
+               writel(param, base++);
+               param = (rgb2ycbcr_coeff[3][2] >> 5);
+               writel(param, base++);
+       } else if ((csc_params.inFormat == RGB) && (csc_params.outFormat == RGB)) {
+               /* Init CSC1 */
+               param =
+                       (rgb2rgb_coeff[3][0] << 27) | (rgb2rgb_coeff[0][0] << 18) |
+                       (rgb2rgb_coeff[1][1] << 9) | rgb2rgb_coeff[2][2];
+               writel(param, base++);
+               /* scale = 2, sat = 0 */
+               param = (rgb2rgb_coeff[3][0] >> 5) | (2UL << 8);
+               writel(param, base++);
+
+               param =
+                       (rgb2rgb_coeff[3][1] << 27) | (rgb2rgb_coeff[0][1] << 18) |
+                       (rgb2rgb_coeff[1][0] << 9) | rgb2rgb_coeff[2][0];
+               writel(param, base++);
+               param = (rgb2rgb_coeff[3][1] >> 5);
+               writel(param, base++);
+
+               param =
+                       (rgb2rgb_coeff[3][2] << 27) | (rgb2rgb_coeff[0][2] << 18) |
+                       (rgb2rgb_coeff[1][2] << 9) | rgb2rgb_coeff[2][1];
+               writel(param, base++);
+               param = (rgb2rgb_coeff[3][2] >> 5);
+               writel(param, base++);
+       } else {
+               ERRDP("Unkown color space conversion!!\n");
+               return -1;
+       }
+       if (csc_set_index == 1) {
+               if (csc_params.taskType == PrP_ENC_TASK) {
+                       ipu_write_field(IPU_IC_CONF__PRPENC_CSC1, 1);
+               } else if (csc_params.taskType == PrP_VF_TASK) {
+                       ipu_write_field(IPU_IC_CONF__PRPVF_CSC1, 1);
+               } else if (csc_params.taskType == PP_TASK) {
+                       ipu_write_field(IPU_IC_CONF__PP_CSC1, 1);
+               } else {
+                       ERRDP("Wrong Task input!!\n");
+                       return -1;
+               }
+       } else {
+               if (csc_params.taskType == PrP_VF_TASK) {
+                       ipu_write_field(IPU_IC_CONF__PRPVF_CSC2, 1);
+               } else if (csc_params.taskType == PP_TASK) {
+                       ipu_write_field(IPU_IC_CONF__PP_CSC2, 1);
+               } else {
+                       ERRDP("Wrong Task input!!\n");
+                       return -1;
+               }
+       }
+       return 0;
+}
+
+/*
+* enable ipu tasks, such as preprocessing/post-processing task
+*/
+int ipu_ic_task_enable(int task_type, int task, int enable)
+{
+       switch (task_type) {
+       case PrP_ENC_TASK:
+               if (task == IC_CSC1)
+                       ipu_write_field(IPU_IC_CONF__PRPENC_CSC1, enable);
+               else if (IC_PRPENC)
+                       ipu_write_field(IPU_IC_CONF__PRPENC_EN, enable);
+               else
+                       ERRDP("Task Type is wrong!!\n");
+               break;
+       case PrP_VF_TASK:
+               if (task == IC_CMB)
+                       ipu_write_field(IPU_IC_CONF__PRPVF_CMB, enable);
+               else if (task == IC_CSC1)
+                       ipu_write_field(IPU_IC_CONF__PRPVF_CSC1, enable);
+               else if (task == IC_CSC2)
+                       ipu_write_field(IPU_IC_CONF__PRPVF_CSC2, enable);
+               else if (task == IC_PRPVF)
+                       ipu_write_field(IPU_IC_CONF__PRPVF_EN, enable);
+               else
+                       ERRDP("Task Type is wrong!!\n");
+               break;
+       case PP_TASK:
+               if (task == IC_CMB)
+                       ipu_write_field(IPU_IC_CONF__PP_CMB, enable);
+               else if (task == IC_CSC1)
+                       ipu_write_field(IPU_IC_CONF__PP_CSC1, enable);
+               else if (task == IC_CSC2)
+                       ipu_write_field(IPU_IC_CONF__PP_CSC2, enable);
+               else if (task == IC_PP)
+                       ipu_write_field(IPU_IC_CONF__PP_EN, enable);
+               else
+                       ERRDP("Task Type is wrong!!\n");
+               break;
+       default:
+               ERRDP("Task Type is wrong!!\n");
+               return -1;
+       }
+       return 0;
+}
+
+/*
+* this function is used to config the color space conversion task in the DP
+*/
+void ipu_dp_csc_config(int dp, dp_csc_param_t dp_csc_params, bool srm_mode_update)
+{
+       int **coeff;
+
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_CSC_YUV_SAT_MODE_SYNC, 0); //SAT mode is zero
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_CSC_GAMUT_SAT_EN_SYNC, 0); //GAMUT en (RGB...)
+
+       if (dp_csc_params.mode >= 0) {
+               ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_CSC_DEF_SYNC, dp_csc_params.mode); //disable CSC
+       }
+
+       coeff = dp_csc_params.coeff;
+
+       if (coeff) {
+               writel(GET_LSB(10, coeff[0][0]) | (GET_LSB(10, coeff[0][1]) << 16),
+                       IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_0__ADDR + dp * 4);
+               writel(GET_LSB(10, coeff[0][2]) | (GET_LSB(10, coeff[1][0]) << 16),
+                       IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_1__ADDR + dp * 4);
+               writel(GET_LSB(10, coeff[1][1]) | (GET_LSB(10, coeff[1][2]) << 16),
+                       IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_2__ADDR + dp * 4);
+               writel(GET_LSB(10, coeff[2][0]) | (GET_LSB(10, coeff[2][1]) << 16),
+                       IPU_CTRL_BASE_ADDR + SRM_DP_CSCA_SYNC_3__ADDR + dp * 4);
+               writel(GET_LSB(10, coeff[2][2]) | (GET_LSB(14, coeff[3][0]) << 16) |
+                       (coeff[4][0] << 30), IPU_CTRL_BASE_ADDR + SRM_DP_CSC_SYNC_0__ADDR + dp * 4);
+               writel(GET_LSB(14, coeff[3][1]) | (coeff[4][1] << 14) |
+                       (GET_LSB(14, coeff[3][2]) << 16) | (coeff[4][2] << 30),
+                       IPU_CTRL_BASE_ADDR + SRM_DP_CSC_SYNC_1__ADDR + dp * 4);
+       }
+       if (srm_mode_update) {
+               ipu_write_field(IPU_IPU_SRM_PRI2__DP_S_SRM_MODE, 3);
+               ipu_write_field(IPU_IPU_SRM_PRI2__DP_SRM_PRI, 0x0);
+       }
+}
+
+/*
+* this function is used to config the foreground plane for combination in the DP
+*/
+void ipu_dp_fg_config(dp_fg_param_t foreground_params)
+{
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GAMMA_EN_SYNC, 0);
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GAMMA_YUV_EN_SYNC, 0);
+
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_COC_SYNC, foreground_params.cursorEnable);
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GWCKE_SYNC, foreground_params.colorKeyEnable); //color key
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GWAM_SYNC, foreground_params.alphaMode);   //1=global alpha,0=local alpha
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_GWSEL_SYNC, foreground_params.graphicSelect);  //1=graphic is FG,0=graphic is BG
+       ipu_write_field(SRM_DP_COM_CONF_SYNC__DP_FG_EN_SYNC, foreground_params.fgEnable);   //1=FG channel enabled,0=FG channel disabled
+       ipu_write_field(SRM_DP_FG_POS_SYNC__DP_FGXP_SYNC, foreground_params.offsetHoriz);
+       ipu_write_field(SRM_DP_FG_POS_SYNC__DP_FGYP_SYNC, foreground_params.offsetVert);
+       ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWAV_SYNC, foreground_params.opaque);   // set the FG opaque
+       ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKR_SYNC, 0xFF);
+       ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKG_SYNC, 0xFF);
+       ipu_write_field(SRM_DP_GRAPH_WIND_CTRL_SYNC__DP_GWCKB_SYNC, 0xFF);
+}
+
+/*
+* microcode configuration, refer to ipuv3 spec
+*/
+void ipu_dc_microcode_config(dc_microcode_t microcode)
+{
+       unsigned int LowWord = 0;
+       unsigned int HighWord = 0;
+       unsigned int opcode_fixed;
+
+       if (!strcmp(microcode.opcode, "WROD")) {
+               LowWord = LowWord | microcode.sync;
+               LowWord = LowWord | (microcode.gluelogic << 4);
+               LowWord = LowWord | (microcode.waveform << 11);
+               LowWord = LowWord | (microcode.mapping << 15);
+               LowWord = LowWord | (microcode.operand << 20);
+
+               HighWord = HighWord | (microcode.operand >> 12);
+               opcode_fixed = 0x18 | (microcode.lf << 1);
+               HighWord = HighWord | (opcode_fixed << 4);
+               HighWord = HighWord | (microcode.stop << 9);
+       } else {
+               ERRDP("Microcode type not supported yet!!\n");
+       }
+       writel(LowWord, IPU_CTRL_BASE_ADDR + IPU_MEM_DC_MICROCODE_BASE_ADDR + microcode.addr * 8);
+       writel(HighWord, IPU_CTRL_BASE_ADDR + IPU_MEM_DC_MICROCODE_BASE_ADDR + microcode.addr * 8 + 4);
+}
+
+/*
+* microcode event configuration, to handle different event
+*/
+void ipu_dc_microcode_event(int channel, char event[8], int priority, int address)
+{
+       int channel_offset = (channel >= 5) ? (0x5C + (channel - 5) * 0x1C) : channel * 0x1C;
+
+       if (!strcmp(event, "NL")) {
+               ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NL_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NL_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "NF")) {
+               ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NF_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL0_CH_0__COD_NF_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "NFIELD")) {
+               ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_NFIELD_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_NFIELD_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "EOF")) {
+               ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_EOF_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL1_CH_0__COD_EOF_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "EOFIELD")) {
+               ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOFIELD_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOFIELD_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "EOL")) {
+               ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOL_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL2_CH_0__COD_EOL_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "NEW_CHAN")) {
+               ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_CHAN_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_CHAN_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "NEW_ADDR")) {
+               ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_ADDR_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL3_CH_0__COD_NEW_ADDR_PRIORITY_CHAN_0, priority);
+       } else if (!strcmp(event, "NEW_DATA")) {
+               ipu_write_field(channel_offset + IPU_DC_RL4_CH_0__COD_NEW_DATA_START_CHAN_0, address);
+               ipu_write_field(channel_offset + IPU_DC_RL4_CH_0__COD_NEW_DATA_PRIORITY_CHAN_0, priority);
+       } else {
+               ERRDP("Wrong DC microcode\n");
+       }
+}
+
+/*
+* this function is used to perform pack/unpacking for yuv/rgb data
+*/
+int ipu_dc_map(int map, int format)
+{
+       int offset[3], mask[3];
+
+       if (format == RGB565) {
+               offset[0] = 15;
+               mask[0] = 0xF8;
+               offset[1] = 10;
+               mask[1] = 0xFC;
+               offset[2] = 4;
+               mask[2] = 0xF8;
+       } else if (format == RGB666) {
+               offset[0] = 17;
+               mask[0] = 0xFC;
+               offset[1] = 11;
+               mask[1] = 0xFC;
+               offset[2] = 5;
+               mask[2] = 0xFC;
+       } else if (format == RGB888 || format == YUV888) {
+               offset[0] = 23;
+               mask[0] = 0xFF;
+               offset[1] = 15;
+               mask[1] = 0xFF;
+               offset[2] = 7;
+               mask[2] = 0xFF;
+       } else {
+               ERRDP("Invalid pixel format %d\n", format);
+               return -1;
+       }
+
+       switch (map) {
+       case 0:
+               /* DC_MAP, should be RGB666 mode */
+               ipu_write_field(IPU_DC_MAP_CONF_16__MD_OFFSET_2, offset[0]);
+               ipu_write_field(IPU_DC_MAP_CONF_16__MD_MASK_2, mask[0]);
+               ipu_write_field(IPU_DC_MAP_CONF_15__MD_OFFSET_1, offset[1]);
+               ipu_write_field(IPU_DC_MAP_CONF_15__MD_MASK_1, mask[1]);
+               ipu_write_field(IPU_DC_MAP_CONF_15__MD_OFFSET_0, offset[2]);
+               ipu_write_field(IPU_DC_MAP_CONF_15__MD_MASK_0, mask[2]);
+
+               ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_0, 0);
+               ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_0, 2);
+               ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_0, 1);
+               break;
+
+       case 1:
+               /* DC_MAP */
+               ipu_write_field(IPU_DC_MAP_CONF_18__MD_OFFSET_6, offset[0]);
+               ipu_write_field(IPU_DC_MAP_CONF_18__MD_MASK_6, mask[0]);
+               ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_5, offset[1]);
+               ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_5, mask[1]);
+               ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_4, offset[2]);
+               ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_4, mask[2]);
+               ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE2_1, 6);
+               ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE1_1, 5);
+               ipu_write_field(IPU_DC_MAP_CONF_0__MAPPING_PNTR_BYTE0_1, 4);
+               break;
+
+       default:
+               ERRDP("Invalid map value: %d\n", map);
+               return -1;
+       }
+       return 0;
+}
+
+/*
+*  config the display port in the DC
+*/
+int ipu_dc_display_config(int display_port, int type, int increment, int strideline)
+{
+       switch (display_port) {
+       case 0:
+               ipu_write_field(IPU_DC_DISP_CONF1_0__DISP_TYP_0, type); /* parallel display without byte enable */
+               ipu_write_field(IPU_DC_DISP_CONF1_0__ADDR_INCREMENT_0, increment);
+               ipu_write_field(IPU_DC_DISP_CONF2_0__SL_0, strideline); //stride line
+               break;
+       case 1:
+               ipu_write_field(IPU_DC_DISP_CONF1_1__DISP_TYP_1, type); /* parallel display without byte enable */
+               ipu_write_field(IPU_DC_DISP_CONF1_1__ADDR_INCREMENT_1, increment);
+               ipu_write_field(IPU_DC_DISP_CONF2_1__SL_1, strideline); //stride line
+               break;
+       case 2:
+               ipu_write_field(IPU_DC_DISP_CONF1_2__DISP_TYP_2, type); /* parallel display without byte enable */
+               ipu_write_field(IPU_DC_DISP_CONF1_2__ADDR_INCREMENT_2, increment);
+               ipu_write_field(IPU_DC_DISP_CONF2_2__SL_2, strideline); //stride line
+               break;
+       case 3:
+               ipu_write_field(IPU_DC_DISP_CONF1_3__DISP_TYP_3, type); /* parallel display without byte enable */
+               ipu_write_field(IPU_DC_DISP_CONF1_3__ADDR_INCREMENT_3, increment);
+               ipu_write_field(IPU_DC_DISP_CONF2_3__SL_3, strideline); //stride line
+               break;
+       default:
+               ERRDP("Invalid display port: %d\n", display_port);
+               return -1;
+       }
+       return 0;
+}
+
+/*
+* config the write channel for display.
+* different channels linked to different display port
+*/
+int ipu_dc_write_channel_config(int dma_channel, int disp_port, int link_di_index,
+                                                               int field_mode_enable)
+{
+       switch (dma_channel) {
+       case 23:
+               ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_START_TIME_5, 0);
+               ipu_write_field(IPU_DC_WR_CH_CONF_5__CHAN_MASK_DEFAULT_5, 0);
+               ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_CHAN_TYP_5, 4);   // Normal mode without anti-tearing
+               ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_DISP_ID_5, disp_port);
+               ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5, link_di_index);
+               ipu_write_field(IPU_DC_WR_CH_CONF_5__W_SIZE_5, 2);  // Component size access to DC set to 24bit
+               ipu_write_field(IPU_DC_WR_CH_ADDR_5__ST_ADDR_5, 0);
+               ipu_write_field(IPU_DC_WR_CH_CONF_5__FIELD_MODE_5, field_mode_enable);
+
+               ipu_write_field(IPU_DC_GEN__SYNC_PRIORITY_5, 1);    // sets the priority of channel #5 to high.
+               ipu_write_field(IPU_DC_GEN__MASK4CHAN_5, 0);    // mask channel is associated to the sync flow via DC (without DP)
+               ipu_write_field(IPU_DC_GEN__MASK_EN, 0);    // mask channel is disabled
+               ipu_write_field(IPU_DC_GEN__DC_CH5_TYPE, 0);    // alternate sync or asyn flow
+               break;
+       case 28:
+               ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_START_TIME_1, 0);
+               ipu_write_field(IPU_DC_WR_CH_CONF_1__CHAN_MASK_DEFAULT_1, 0);
+               ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_CHAN_TYP_1, 4);   // Normal mode without anti-tearing
+               ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_DISP_ID_1, disp_port);
+               ipu_write_field(IPU_DC_WR_CH_CONF_1__PROG_DI_ID_1, link_di_index);
+               /* if CH28 is connected to DI0, CH23 must connect to DI1 even if it is not used. */
+               if (link_di_index == 0)
+                       ipu_write_field(IPU_DC_WR_CH_CONF_5__PROG_DI_ID_5, 1);
+
+               ipu_write_field(IPU_DC_WR_CH_CONF_1__W_SIZE_1, 2);  // Component size access to DC set to 24bit
+               ipu_write_field(IPU_DC_WR_CH_ADDR_1__ST_ADDR_1, 0); // START ADDRESS OF CHANNEL
+               ipu_write_field(IPU_DC_WR_CH_CONF_1__FIELD_MODE_1, field_mode_enable);
+
+               ipu_write_field(IPU_DC_GEN__SYNC_PRIORITY_1, 1);    //sets the priority of channel #5 to high.
+               ipu_write_field(IPU_DC_GEN__SYNC_1_6, 2);   // Channel 1 of the DC handles sync flow
+               break;
+       default:
+               ERRDP("Invalid display channel: %d\n", dma_channel);
+               return -1;
+       }
+       return 0;
+}
+