Merge branch 'tx53-bugfix'

diff --git a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
index fed8b8dfad92411c77650be9ebf9193323789144..bbfc79e9e781ffb3ed9728c377fa8243d6b1248e 100644 (file)
--- a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
@@ -488,23 +488,37 @@ GPU Memory                       0xF8020000 0xF805FFFF
 #define MXC_DCD_CMD_FLAG_WRITE         0x0
 #define MXC_DCD_CMD_FLAG_CLR           0x1
 #define MXC_DCD_CMD_FLAG_SET           0x3
-#define MXC_DCD_CMD_FLAG_CHK_ANY       (1 << 0)
-#define MXC_DCD_CMD_FLAG_CHK_SET       (1 << 1)
-#define MXC_DCD_CMD_FLAG_CHK_CLR       (0 << 1)
+#define MXC_DCD_CMD_FLAG_CHK_CLR       ((0 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_SET       ((0 << 0) | (1 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_CLR   ((1 << 0) | (0 << 1))
+#define MXC_DCD_CMD_FLAG_CHK_ANY_SET   ((1 << 0) | (1 << 1))
 
-#define MXC_DCD_CMD_WRT(type, flags, next)                                     \
-       .word   CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type))
+#define MXC_DCD_START                                                  \
+       .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) ; \
+dcd_start:
 
-#define MXC_DCD_CMD_CHK(type, flags, addr, mask)                               \
-       .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\
+       .macro  MXC_DCD_END
+1:
+       .ifgt   . - dcd_start - 1768
+       .error  "DCD too large!"
+       .endif
+dcd_end:
+       .endm
+
+#define MXC_DCD_CMD_WRT(type, flags)                                   \
+1:     .word   CPU_2_BE_32((0xcc << 24) | ((1f - .) << 8) | ((flags) << 3) | (type))
+
+#define MXC_DCD_CMD_CHK(type, flags, addr, mask)                       \
+1:     .word   CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)), \
                CPU_2_BE_32(addr), CPU_2_BE_32(mask)
 
-#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)                    \
-       .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\
+#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count)            \
+1:     .word   CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)), \
                CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count)
 
-#define MXC_DCD_CMD_NOP()                                                      \
-       .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+#define MXC_DCD_CMD_NOP()                              \
+1:     .word   CPU_2_BE_32((0xc0 << 24) | (4 << 8))
+
 
 #define CK_TO_NS(ck)   (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
 #define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)
@@ -779,9 +793,8 @@ ivt_end:
 #define DCD_VERSION    0x40
 
 dcd_hdr:
-       .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
-dcd_start:
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
+       MXC_DCD_START
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 
        MXC_DCD_ITEM(0x53fa8004, 0x00194005)    @ set LDO to 1.3V
 
@@ -886,6 +899,10 @@ dcd_start:
        MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0)
 
        /* MR0..3 - CS0 */
+       MXC_DCD_ITEM(0x63fd901c, 0x00008000) /* CON_REQ */
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, 0x63fd901c, 0x00004000)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
+
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */
@@ -906,52 +923,43 @@ dcd_start:
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */
        MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */
-zq_calib:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
-
-       /* Write Leveling */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val | (1 << 7)) | (1 << 9)) /* MRS: start write leveling */
-       MXC_DCD_ITEM(0x63fd901c, 0x00000000)
-       MXC_DCD_ITEM(0x63fd9048, 0x00000001)
-wl_calib:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd9040, 0x00010000)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 
        /* DQS calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
        MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
-dqs_calib:
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
+
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd907c, 0x90000000)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
 
        /* WR DL calibration */
-       MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+       MXC_DCD_ITEM(0x63fd901c, 0x00008000)
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
        MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
-wr_dl_calib: /* 6c4 */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
+
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a4, 0x00000010)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
 
        /* RD DL calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
        MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
-rd_dl_calib: /* 70c */
-       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
-       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
+
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd90a0, 0x00000010)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
        MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
        MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */
        MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1)
 
+       /* DDR calibration done */
        MXC_DCD_ITEM(0x63fd901c, 0x00000000)
+       MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, 0x63fd901c, 0x00004000)
+       MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE)
 
        /* setup NFC pads */
        /* MUX_SEL */
@@ -986,10 +994,7 @@ rd_dl_calib: /* 70c */
        MXC_DCD_ITEM(0x53fa85a8, 0x000000e4)    @ NANDF_WE_B
        MXC_DCD_ITEM(0x53fa85ac, 0x000000e4)    @ NANDF_RB0
        MXC_DCD_ITEM(0x53fa85b0, 0x00000004)    @ NANDF_CS0
-dcd_end:
-       .ifgt   dcd_end - dcd_start - 1768
-       .error  "DCD too large!"
-       .endif
+       MXC_DCD_END
        .endm
 
 W_CSCMR1_VAL:          .word   0xa6a2a020

diff --git a/packages/hal/arm/mx53/var/v2_0/src/cmds.c b/packages/hal/arm/mx53/var/v2_0/src/cmds.c
index 39cf6476914af5be2d6186afc55ee7993732fc96..fb736b7f3fd2a7ab64e6297b257693ba927dfa53 100644 (file)
--- a/packages/hal/arm/mx53/var/v2_0/src/cmds.c
+++ b/packages/hal/arm/mx53/var/v2_0/src/cmds.c
@@ -98,7 +98,7 @@ struct pll_param {
 };
 
 #define PLL_FREQ_MAX(_ref_clk_)           (4 * _ref_clk_ * PLL_MFI_MAX)
-#define PLL_FREQ_MIN(_ref_clk_)           ((2 * _ref_clk_ * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)
+#define PLL_FREQ_MIN(_ref_clk_)           ((4 * _ref_clk_ * PLL_MFI_MIN) / PLL_PD_MAX)
 #define MAX_DDR_CLK            400000000
 #define AHB_CLK_MAX            133333333
 #define IPG_CLK_MAX            (AHB_CLK_MAX / 2)
@@ -179,16 +179,20 @@ int calc_pll_params(u32 ref, u32 target, struct pll_param *pll)
        // Now got pd and mfi already
        mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
 
-       dbg("%d: ref=%d, target=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+       dbg("%d: ref=%d, target=%d, pd=%d, mfi=%d, mfn=%d, mfd=%d\n",
                __LINE__, ref, target, pd, mfi, mfn, mfd);
 
-       i = 1;
-       if (mfn != 0)
+       if (mfn != 0) {
                i = gcd(mfd, mfn);
+               mfn /= i;
+               mfd /= i;
+       } else {
+               mfd = 1;
+       }
        pll->pd = pd;
        pll->mfi = mfi;
-       pll->mfn = mfn / i;
-       pll->mfd = mfd / i;
+       pll->mfn = mfn;
+       pll->mfd = mfd;
        return 0;
 }
 
@@ -431,8 +435,9 @@ static void clock_setup(int argc,char *argv[])
 
        if (core_clk != 0) {
                if ((core_clk < PLL_FREQ_MIN(PLL_REF_CLK)) || (core_clk > PLL_FREQ_MAX(PLL_REF_CLK))) {
-                       diag_printf("Targeted core clock should be within [%d - %d]\n",
-                                               PLL_FREQ_MIN(PLL_REF_CLK), PLL_FREQ_MAX(PLL_REF_CLK));
+                       diag_printf("Targeted core clock should be within [%d - %d] MHz\n",
+                                               PLL_FREQ_MIN(PLL_REF_CLK) / SZ_DEC_1M,
+                                               PLL_FREQ_MAX(PLL_REF_CLK) / SZ_DEC_1M);
                        return;
                }
        }