Initial revision
authorlothar <lothar>
Fri, 13 Feb 2009 19:33:07 +0000 (19:33 +0000)
committerlothar <lothar>
Fri, 13 Feb 2009 19:33:07 +0000 (19:33 +0000)
156 files changed:
packages/hal/arm/mx25/3stack/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/misc/redboot_ROMRAM_TO1_1.ecm [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx25/3stack/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/cdl/hal_arm_soc.cdl [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/include/hal_cache.h [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/include/hal_diag.h [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/include/hal_mm.h [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/include/hal_soc.h [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/include/hal_var_ints.h [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/include/plf_stub.h [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/include/var_io.h [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/src/cmds.c [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/src/soc_diag.c [new file with mode: 0644]
packages/hal/arm/mx25/var/v2_0/src/soc_misc.c [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx27/3stack/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx31/3stack/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx31/ads/v2_0/misc/redboot_ROMRAM_mmc.ecm [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx35/3stack/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx35/evb/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/cdl/hal_arm_soc.cdl [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/include/hal_cache.h [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/include/hal_diag.h [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/include/hal_mm.h [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/include/hal_soc.h [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/include/hal_var_ints.h [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/include/plf_stub.h [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/include/var_io.h [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/src/cmds.c [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/src/soc_diag.c [new file with mode: 0644]
packages/hal/arm/mx35/var/v2_0/src/soc_misc.c [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx37/3stack/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/cdl/hal_arm_soc.cdl [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/include/hal_cache.h [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/include/hal_diag.h [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/include/hal_mm.h [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/include/hal_soc.h [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/include/hal_var_ints.h [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/include/plf_stub.h [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/include/var_io.h [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/src/cmds.c [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/src/soc_diag.c [new file with mode: 0644]
packages/hal/arm/mx37/var/v2_0/src/soc_misc.c [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/misc/redboot_ROMRAM_TO2.ecm [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx51/babbage/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/cdl/hal_arm_board.cdl [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/include/fsl_board.h [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/include/pkgconf/mlt_arm_board_romram.h [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/include/pkgconf/mlt_arm_board_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/include/pkgconf/mlt_arm_board_romram.mlt [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/src/board_diag.c [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/src/board_misc.c [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/cdl/hal_arm_soc.cdl [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/include/hal_cache.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/include/hal_diag.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/include/hal_mm.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/include/hal_soc.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/include/hal_var_ints.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/include/plf_stub.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/include/var_io.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/src/cmds.c [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/src/soc_diag.c [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/src/soc_misc.c [new file with mode: 0644]
packages/redboot/v2_0/src/imx_usb.c [new file with mode: 0644]

diff --git a/packages/hal/arm/mx25/3stack/v2_0/cdl/hal_arm_board.cdl b/packages/hal/arm/mx25/3stack/v2_0/cdl/hal_arm_board.cdl
new file mode 100644 (file)
index 0000000..577cd6f
--- /dev/null
@@ -0,0 +1,364 @@
+# ====================================================================
+#
+#      hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX25_3STACK {
+    display       "Freescale board"
+    parent        CYGPKG_HAL_ARM_MX25
+    hardware
+    include_dir   cyg/hal
+    define_header hal_arm_board.h
+    description   "
+        This HAL platform package provides generic
+        support for the Freescale i.MX25 3-Stack Board."
+
+    compile       board_misc.c board_diag.c
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+    implements    CYGHWR_HAL_ARM_SOC_UART1
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_arm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_arm_soc.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+       puts $::cdl_header "#define HAL_PLATFORM_CPU    \"i.MX25 \""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"Freescale\""
+        puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE  1771"
+        puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"ROM"}
+        legal_values  {"RAM" "ROM" "ROMRAM"}
+       no_define
+       define -file system.h CYG_HAL_STARTUP
+        description   "
+           When targetting the eval board it is possible to build
+           the system for either RAM bootstrap or ROM bootstrap(s). Select
+           'ram' when building programs to load into RAM using eCos GDB
+           stubs.  Select 'rom' when building a stand-alone application
+           which will be put into ROM, or for the special case of
+           building the eCos GDB stubs themselves. Using ROMRAM will allow
+           the program to exist in ROM, but be copied to RAM during startup."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_DUART_UARTA {
+        display   "ST16552 UARTA available as diagnostic/debug channel"
+        description "
+         The board has a ST16552 DUART chip. This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_DUART_UARTB {
+        display   "ST16552 UARTB available as diagnostic/debug channel"
+        description "
+         The board has a ST16552 DUART chip. This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option selects the baud rate used for the console port.
+            Note: this should match the value chosen for the GDB port if the
+            console and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option selects the baud rate used for the GDB port.
+            Note: this should match the value chosen for the console port if the
+            console and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   5
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The board has three serial ports. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+         display      "Default console channel."
+         flavor       data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         calculated   0
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Console serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+         description      "
+            The board has only three serial ports.  This option
+            chooses which port will be used for console output."
+     }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        description   "
+           Global build options including control over
+           compiler flags, linker flags and choice of toolchain."
+
+
+        parent  CYGPKG_NONE
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-none-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+
+        cdl_option CYGBLD_BUILD_GDB_STUBS {
+            display "Build GDB stub ROM image"
+            default_value 0
+            requires { CYG_HAL_STARTUP == "ROM" }
+            requires CYGSEM_HAL_ROM_MONITOR
+            requires CYGBLD_BUILD_COMMON_GDB_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+            no_define
+            description "
+                This option enables the building of the GDB stubs for the
+                board. The common HAL controls takes care of most of the
+                build process, but the final conversion from ELF image to
+                binary data is handled by the platform CDL, allowing
+                relocation of the data if necessary."
+
+            make -priority 320 {
+                <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+        display "Freescale MXC Board build options"
+        flavor  none
+        no_define
+        description   "
+           Package specific build options including control over
+           compiler flags used only in building this package,
+           and details of which tests are built."
+
+        cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the board HAL. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the board HAL. These flags are removed from
+                the set of global flags if present."
+        }
+
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { (CYG_HAL_STARTUP == "RAM")    ? "arm_board_ram" :
+                     (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+                                                    "arm_board_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { (CYG_HAL_STARTUP == "RAM") ?    "<pkgconf/mlt_arm_board_ram.ldi>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+                                                         "<pkgconf/mlt_arm_board_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { (CYG_HAL_STARTUP == "RAM")    ? "<pkgconf/mlt_arm_board_ram.h>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+                                                         "<pkgconf/mlt_arm_board_rom.h>" }
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+            compile -library=libextras.a redboot_cmds.c
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+        display       "Redboot HAL variant options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+
+        # RedBoot details
+        requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x80008000 }
+        define_proc {
+            puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+        }
+    }
+}
diff --git a/packages/hal/arm/mx25/3stack/v2_0/include/fsl_board.h b/packages/hal/arm/mx25/3stack/v2_0/include/fsl_board.h
new file mode 100644 (file)
index 0000000..7ceec19
--- /dev/null
@@ -0,0 +1,98 @@
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+//      Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h>        // Hardware definitions
+
+#define CPLD_SPI_BASE                  CSPI1_BASE_ADDR
+#define CPLD_SPI_CHIP_SELECT_NO        SPI_CTRL_CS0
+#define CPLD_SPI_CTRL_MODE_MASTER      SPI_CTRL_MODE_MASTER
+
+#define PBC_BASE                    CS5_BASE_ADDR    /* Peripheral Bus Controller */
+#define PBC_LED_CTRL                (PBC_BASE + 0x20000)
+#define PBC_SB_STAT                 (PBC_BASE + 0x20008)
+#define PBC_ID_AAAA                 (PBC_BASE + 0x20040)
+#define PBC_ID_5555                 (PBC_BASE + 0x20048)
+#define PBC_VERSION                 (PBC_BASE + 0x20050)
+#define PBC_ID_CAFE                 (PBC_BASE + 0x20058)
+#define PBC_INT_STAT                (PBC_BASE + 0x20010)
+#define PBC_INT_MASK                (PBC_BASE + 0x20038)
+#define PBC_INT_REST                (PBC_BASE + 0x20020)
+#define PBC_SW_RESET                (PBC_BASE + 0x20060)
+#define BOARD_CS_LAN_BASE           (PBC_BASE + 0x300)
+#define BOARD_CS_UART_BASE          (PBC_BASE + 0x8000)
+
+#define BOARD_FLASH_START           CS0_BASE_ADDR
+#define REDBOOT_IMAGE_SIZE          0x40000
+
+#define SDRAM_BASE_ADDR             CSD0_BASE_ADDR
+#define SDRAM_SIZE                  0x08000000
+#define RAM_BANK0_BASE              CSD0_BASE_ADDR
+#define RAM_BANK1_BASE              CSD1_BASE_ADDR
+
+#ifdef CYGPKG_DEVS_MXC_SPI
+#define LAN92XX_REG_READ(reg_offset) ( \
+               cpld_reg_xfer(reg_offset, 0x0, 1) | \
+               (cpld_reg_xfer(reg_offset + 0x2, 0x0, 1) << 16))
+
+#define LAN92XX_REG_WRITE(reg_offset, val)  do {\
+           cpld_reg_xfer(reg_offset, val, 0); \
+           (cpld_reg_xfer(reg_offset + 0x2, (val >> 16), 0)); } while (0)
+#endif
+
+#define FEC_PHY_ADDR    0x1
+
+#define LED_MAX_NUM    8
+#define LED_IS_ON(n)    ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+#define TURN_LED_ON(n)  writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define BOARD_DEBUG_LED(n)                     \
+    CYG_MACRO_START                            \
+        if (n >= 0 && n < LED_MAX_NUM) {       \
+               if (LED_IS_ON(n))               \
+                       TURN_LED_OFF(n);        \
+               else                            \
+                       TURN_LED_ON(n);         \
+       }                                       \
+    CYG_MACRO_END
+
+#endif /* CYGONCE_FSL_BOARD_H */
diff --git a/packages/hal/arm/mx25/3stack/v2_0/include/hal_platform_setup.h b/packages/hal/arm/mx25/3stack/v2_0/include/hal_platform_setup.h
new file mode 100644 (file)
index 0000000..0ec3099
--- /dev/null
@@ -0,0 +1,863 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+//      hal_platform_setup.h
+//
+//      Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h>             // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H           // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
+#include <cyg/hal/hal_soc.h>            // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h>            // MMU definitions
+#include <cyg/hal/fsl_board.h>          // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#define INTERNAL_BOOT_MODE
+
+#if defined(INTERNAL_BOOT_MODE)
+#define PLATFORM_PREAMBLE setup_flash_header
+#endif
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+#define CYGHWR_HAL_ROM_VADDR        0x0
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+    .macro  _platform_setup1
+FSL_BOARD_SETUP_START:
+    // invalidate I/D cache/TLB and drain write buffer
+    mov r0, #0
+    mcr 15, 0, r0, c7, c7, 0    /* invalidate I cache and D cache */
+    mcr 15, 0, r0, c8, c7, 0    /* invalidate TLBs */
+    mcr 15, 0, r0, c7, c10, 4   /* Drain the write buffer */
+
+#if defined(INTERNAL_BOOT_MODE)
+    // On internal boot mode, check MEM CTRL bits for boot source
+    mov r0, #NAND_FLASH_BOOT
+    ldr r1, CCM_BASE_ADDR_W
+    ldr r1, [r1, #CLKCTL_RCSR]
+    tst r1, #0x80000000
+    movne r0, #MMC_FLASH_BOOT
+    ldr r1, MXCBOOT_FLAG_ADDR_W
+    str r0, [r1]
+#else
+    mov r0, #SDRAM_NON_FLASH_BOOT
+    ldr r1, MXCBOOT_FLAG_ADDR_W
+    str r0, [r1] // for checking boot source from nand, nor or sdram
+#endif
+
+   .globl  init_spba_start, init_aips_start, init_max_start, init_m3if_start
+init_spba_start:
+    init_spba
+init_aips_start:
+    init_aips
+init_max_start:
+    init_max
+init_m3if_start:
+    init_m3if
+
+#ifndef INTERNAL_BOOT_MODE
+    // check if sdram has been setup
+    cmp pc, #SDRAM_BASE_ADDR
+    blo init_clock_start
+    cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+    blo HWInitialise_skip_SDRAM_setup
+
+    // Now we must boot from Flash
+    mov r0, #NOR_FLASH_BOOT
+    ldr r1, MXCBOOT_FLAG_ADDR_W
+    str r0, [r1]
+#endif
+init_clock_start:
+    init_clock
+init_cs5_start:
+#ifndef INTERNAL_BOOT_MODE
+    init_cs5
+
+init_sdram_start:
+    /* Assume DDR memory */
+    setup_sdram
+#endif
+
+HWInitialise_skip_SDRAM_setup:
+    mov r0, #NFC_BASE
+    add r2, r0, #0x1000                // 4K window
+    cmp pc, r0
+    blo Normal_Boot_Continue
+    cmp pc, r2
+    bhi Normal_Boot_Continue
+NAND_Boot_Start:
+    /* Copy image from flash to SDRAM first */
+    ldr r1, MXC_REDBOOT_ROM_START
+
+1:  ldmia r0!, {r3-r10}
+    stmia r1!, {r3-r10}
+    cmp r0, r2
+    blo 1b
+
+    /* Jump to SDRAM */
+    ldr r1, CONST_0x0FFF
+    and r0, pc, r1     /* offset of pc */
+    ldr r1, MXC_REDBOOT_ROM_START
+    add r1, r1, #0x10
+    add pc, r0, r1
+    nop
+    nop
+    nop
+    nop
+NAND_Copy_Main:
+    mov r0, #NAND_FLASH_BOOT
+    ldr r1, MXCBOOT_FLAG_ADDR_W
+    str r0, [r1]
+    mov r0, #MXCFIS_NAND
+    ldr r1, MXCFIS_FLAG_ADDR_W
+    str r0, [r1]
+
+    mov r0, #NFC_BASE;   //r0: nfc base. Reloaded after each page copying
+    add r12, r0, #0x1E00  //r12: NFC register base. Doesn't change
+    ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+    orr r3, r3, #0x1
+
+    /* Setting NFC */
+    ldr r7, CCM_BASE_ADDR_W
+    ldr r1, [r7, #CLKCTL_RCSR]
+    /*BUS WIDTH setting*/
+    tst r1, #0x20000000
+    orrne r1, r1, #0x4000
+    biceq r1, r1, #0x4000
+
+    /*4K PAGE*/
+    tst r1, #0x10000000
+    orrne r1, r1, #0x200
+    bne  1f
+    /*2K PAGE*/
+    bic r1, r1, #0x200
+    tst r1, #0x08000000
+    orrne r1, r1, #0x100 /*2KB page size*/
+    biceq r1, r1, #0x100 /*512B page size*/
+    movne r2, #32 /*64 bytes*/
+    moveq r2, #8  /*16 bytes*/
+    b NAND_setup
+1:
+    tst r1, #0x08000000
+    bicne r3, r3, #1   /*Enable 8bit ECC mode*/
+    movne r2, #109 /*218 bytes*/
+    moveq r2, #64  /*128 bytes*/
+NAND_setup:
+    str r1, [r7, #CLKCTL_RCSR]
+    strh r2, [r12, #ECC_RSLT_SPARE_AREA_REG_OFF]
+    strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+    //unlock internal buffer
+    mov r3, #0x2
+    strh r3, [r12, #NFC_CONFIGURATION_REG_OFF]
+    //unlock nand device
+    mov r3, #0
+    strh r3, [r12, #UNLOCK_START_BLK_ADD_REG_OFF]
+    sub r3, r3, #1
+    strh r3, [r12, #UNLOCK_END_BLK_ADD_REG_OFF]
+    mov r3, #4
+    strh r3, [r12, #NF_WR_PROT_REG_OFF]
+
+    /* r0: NFC base address. RAM buffer base address. [constantly]
+     * r1: starting flash address to be copied. [constantly]
+     * r2: page size. [Doesn't change]
+     * r3: used as argument.
+     * r11: starting SDRAM address for copying. [Updated constantly].
+     * r12: NFC register base address. [constantly].
+     * r13: end of SDRAM address for copying. [Doesn't change].
+     */
+
+    mov r1, #0x1000
+    ldr r3, [r7, #CLKCTL_RCSR]
+    tst r3, #0x200
+    movne r2, #0x1000
+    bne 1f
+    tst r3, #0x100
+    mov r1, #0x800  /*Strang Why is not 4K offset*/
+    movne r2, #0x800
+    moveq r2, #0x200
+1: /*Update the indicator of copy area */
+    ldr r11, MXC_REDBOOT_ROM_START
+    add r13, r11, #REDBOOT_IMAGE_SIZE
+    add r11, r11, r1
+
+Nfc_Read_Page:
+    mov r3, #0x0
+    nfc_cmd_input
+
+    cmp r2, #0x800
+    bhi nfc_addr_ops_4kb
+    beq nfc_addr_ops_2kb
+
+    mov r3, r1
+    do_addr_input       //1st addr cycle
+    mov r3, r1, lsr #9
+    do_addr_input       //2nd addr cycle
+    mov r3, r1, lsr #17
+    do_addr_input       //3rd addr cycle
+    mov r3, r1, lsr #25
+    do_addr_input       //4th addr cycle
+    b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+    mov r3, #0
+    do_addr_input       //1st addr cycle
+    mov r3, #0
+    do_addr_input       //2nd addr cycle
+    mov r3, r1, lsr #11
+    do_addr_input       //3rd addr cycle
+    mov r3, r1, lsr #19
+    do_addr_input       //4th addr cycle
+    mov r3, r1, lsr #27
+    do_addr_input       //5th addr cycle
+
+    mov r3, #0x30
+    nfc_cmd_input
+    b end_of_nfc_addr_ops
+
+nfc_addr_ops_4kb:
+    mov r3, #0
+    do_addr_input       //1st addr cycle
+    mov r3, #0
+    do_addr_input       //2nd addr cycle
+    mov r3, r1, lsr #12
+    do_addr_input       //3rd addr cycle
+    mov r3, r1, lsr #20
+    do_addr_input       //4th addr cycle
+    mov r3, r1, lsr #27
+    do_addr_input       //5th addr cycle
+
+    mov r3, #0x30
+    nfc_cmd_input
+
+end_of_nfc_addr_ops:
+    mov r8, #0
+    bl nfc_data_output
+    bl do_wait_op_done
+    // Check if x16/2kb page
+    cmp r2, #0x800
+    bhi nfc_addr_data_output_done_4k
+    beq nfc_addr_data_output_done_2k
+    beq nfc_addr_data_output_done_512
+
+    // check for bad block
+//    mov r3, r1, lsl #(32-17)    // get rid of block number
+//    cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+    b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_4k:
+//TODO
+    b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_2k:
+// end of 4th
+    // check for bad block
+//TODO    mov r3, r1, lsl #(32-17)    // get rid of block number
+//    cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+    b nfc_addr_data_output_done
+
+nfc_addr_data_output_done_512:
+    // check for bad block
+// TODO   mov r3, r1, lsl #(32-5-9)    // get rid of block number
+// TODO   cmp r3, #(512 << (32-5-9))   // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+#if 0
+    bhi Copy_Good_Blk
+    add r4, r0, #0x1000  //r3 -> spare area buf 0
+    ldrh r4, [r4, #0x4]
+    and r4, r4, #0xFF00
+    cmp r4, #0xFF00
+    beq Copy_Good_Blk
+    // really sucks. Bad block!!!!
+    cmp r3, #0x0
+    beq Skip_bad_block
+    // even suckier since we already read the first page!
+    // Check if x16/2kb page
+    cmp r2, #0x800
+    // for 4k page
+    subhi r11, r11, #0x1000  //rewind 1 page for the sdram pointer
+    subhi r1, r1, #0x1000    //rewind 1 page for the flash pointer
+    // for 2k page
+    subeq r11, r11, #0x800  //rewind 1 page for the sdram pointer
+    subeq r1, r1, #0x800    //rewind 1 page for the flash pointer
+    // for 512 page
+    sublo r11, r11, #512  //rewind 1 page for the sdram pointer
+    sublo r1, r1, #512    //rewind 1 page for the flash pointer
+Skip_bad_block:
+    // Check if x16/2kb page
+    ldr r7, CCM_BASE_ADDR_W
+    ldr r7, [r7, #CLKCTL_RCSR]
+    tst r7, #0x200
+    addne r1, r1, #(128*4096)
+    bne Skip_bad_block_done
+    tst r7, #0x100
+    addeq r1, r1, #(32*512)
+    addne r1, r1, #(64*2048)
+Skip_bad_block_done:
+    b Nfc_Read_Page
+#endif
+Copy_Good_Blk:
+    //copying page
+    add r2, r2, #NFC_BASE
+1:  ldmia r0!, {r3-r10}
+    stmia r11!, {r3-r10}
+    cmp r0, r2
+    blo 1b
+    sub r2, r2, #NFC_BASE
+
+    cmp r11, r13
+    bge NAND_Copy_Main_done
+    // Check if x16/2kb page
+    add r1, r1, r2
+    mov r0, #NFC_BASE
+    b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM    /* enable running from RAM */
+    /* Copy image from flash to SDRAM first */
+    ldr r0, =0xFFFFF000
+    and r0, r0, pc
+    ldr r1, MXC_REDBOOT_ROM_START
+    cmp r0, r1
+    beq HWInitialise_skip_SDRAM_copy
+
+    add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1:  ldmia r0!, {r3-r10}
+    stmia r1!, {r3-r10}
+    cmp r0, r2
+    ble 1b
+
+    /* Jump to SDRAM */
+    ldr r1, =0xFFFF
+    and r0, pc, r1      /* offset of pc */
+    ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+    add pc, r0, r1
+    nop
+    nop
+    nop
+    nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+STACK_Setup:
+    // Set up a stack [for calling C code]
+    ldr r1, =__startup_stack
+    ldr r2, =RAM_BANK0_BASE
+    orr sp, r1, r2
+
+    // Create MMU tables
+    bl hal_mmu_init
+
+    // Enable MMU
+    ldr r2, =10f
+    mrc MMU_CP, 0, r1, MMU_Control, c0      // get c1 value to r1 first
+    orr r1, r1, #7                          // enable MMU bit
+    mcr MMU_CP, 0, r1, MMU_Control, c0
+    mov pc,r2    /* Change address spaces */
+    nop
+    nop
+    nop
+10:
+    // Save shadow copy of BCR, also hardware configuration
+    ldr r1, =_board_BCR
+    str r2,[r1]
+    ldr r1, =_board_CFG
+    str r9,[r1]                // Saved far above...
+
+    .endm                       // _platform_setup1
+
+do_wait_op_done:
+    1:
+        ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+        ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+        beq 1b
+    bx lr     // do_wait_op_done
+
+
+nfc_data_output:
+    ldrh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+    orr r3, r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+    strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+    strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+
+    mov r3, #FDO_PAGE_SPARE_VAL
+    strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+    bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+    /* Do nothing */
+    .macro  init_spba
+    .endm  /* init_spba */
+
+    /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
+    .macro init_aips
+        /*
+         * Set all MPROTx to be non-bufferable, trusted for R/W,
+         * not forced to user-mode.
+         */
+        ldr r0, AIPS1_CTRL_BASE_ADDR_W
+        ldr r1, AIPS1_PARAM_W
+        str r1, [r0, #0x00]
+        str r1, [r0, #0x04]
+        ldr r0, AIPS2_CTRL_BASE_ADDR_W
+        str r1, [r0, #0x00]
+        str r1, [r0, #0x04]
+    .endm /* init_aips */
+
+    /* MAX (Multi-Layer AHB Crossbar Switch) setup */
+    .macro init_max
+        ldr r0, MAX_BASE_ADDR_W
+       /* MPR - priority for MX25 is IAHB>DAHB>USBOTG>RTIC>(SDHC2/SDMA) */
+        ldr r1, MAX_PARAM1
+        str r1, [r0, #0x000]        /* for S0 */
+        str r1, [r0, #0x100]        /* for S1 */
+        str r1, [r0, #0x200]        /* for S2 */
+        str r1, [r0, #0x300]        /* for S3 */
+        str r1, [r0, #0x400]        /* for S4 */
+        /* SGPCR - always park on last master */
+        ldr r1, =0x10
+        str r1, [r0, #0x010]        /* for S0 */
+        str r1, [r0, #0x110]        /* for S1 */
+        str r1, [r0, #0x210]        /* for S2 */
+        str r1, [r0, #0x310]        /* for S3 */
+        str r1, [r0, #0x410]        /* for S4 */
+        /* MGPCR - restore default values */
+        ldr r1, =0x0
+        str r1, [r0, #0x800]        /* for M0 */
+        str r1, [r0, #0x900]        /* for M1 */
+        str r1, [r0, #0xA00]        /* for M2 */
+        str r1, [r0, #0xB00]        /* for M3 */
+        str r1, [r0, #0xC00]        /* for M4 */
+    .endm /* init_max */
+
+    /* Clock setup */
+    .macro    init_clock
+        ldr r0, CCM_BASE_ADDR_W
+
+        /* default CLKO to 1/32 of the ARM core */
+        ldr r1, [r0, #CLKCTL_MCR]
+        bic r1, r1, #0x00F00000
+        bic r1, r1, #0x7F000000
+        mov r2,     #0x5F000000
+        add r2, r2, #0x00200000
+        orr r1, r1, r2
+        str r1, [r0, #CLKCTL_MCR]
+
+       /* enable all the clocks */
+        ldr r2, CCM_CGR0_W
+        str r2, [r0, #CLKCTL_CGR0]
+        ldr r2, CCM_CGR1_W
+        str r2, [r0, #CLKCTL_CGR1]
+        ldr r2, CCM_CGR2_W
+        str r2, [r0, #CLKCTL_CGR2]
+    .endm /* init_clock */
+
+    /* M3IF setup */
+    .macro init_m3if
+        /* Configure M3IF registers */
+        ldr r1, M3IF_BASE_W
+        /*
+        * M3IF Control Register (M3IFCTL) for MX25
+        * MRRP[0] = LCDC           on priority list (1 << 0)  = 0x00000001
+        * MRRP[1] = MAX1       not on priority list (0 << 1)  = 0x00000000
+        * MRRP[2] = MAX0       not on priority list (0 << 2)  = 0x00000000
+        * MRRP[3] = USB HOST   not on priority list (0 << 3)  = 0x00000000
+        * MRRP[4] = SDMA       not on priority list (0 << 4)  = 0x00000000
+        * MRRP[5] = SD/ATA/FEC not on priority list (0 << 5)  = 0x00000000
+        * MRRP[6] = SCMFBC     not on priority list (0 << 6)  = 0x00000000
+        * MRRP[7] = CSI        not on priority list (0 << 7)  = 0x00000000
+        *                                                       ----------
+        *                                                       0x00000001
+        */
+        ldr r0, =0x00000001
+        str r0, [r1]  /* M3IF control reg */
+    .endm /* init_m3if */
+
+     /* CPLD on CS5 setup */
+    .macro init_cs5
+        ldr r0, WEIM_CTRL_CS5_W
+        ldr r1, CS5_CSCRU_0x0000D843
+        str r1, [r0, #CSCRU]
+        ldr r1, CS5_CSCRL_0x22252521
+        str r1, [r0, #CSCRL]
+        ldr r1, CS5_CSCRA_0x22220A00
+        str r1, [r0, #CSCRA]
+    .endm /* init_cs5 */
+
+    .macro setup_sdram
+        ldr r0, ESDCTL_BASE_W
+        mov r3, #0x2000
+        str r3, [r0, #0x0]
+        str r3, [r0, #0x8]
+
+       mov r12, #0x00
+       mov r2, #0x1    /* mDDR */
+       mov r1, #RAM_BANK0_BASE
+       bl setup_sdram_bank
+       cmp r3, #0x0
+       orreq r12, r12, #1
+       eorne r2, r2, #0x1
+       blne setup_sdram_bank
+
+       ldr r3, ESDCTL_DELAY5
+       str r3, [r0, #0x30]
+    .endm
+
+    .macro nfc_cmd_input
+        strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+        mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+        strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+        bl do_wait_op_done
+    .endm   // nfc_cmd_input
+
+    .macro do_addr_input
+        and r3, r3, #0xFF
+        strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+        mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+        strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+        bl do_wait_op_done
+    .endm   // do_addr_input
+
+    /* To support 133MHz DDR */
+    .macro  init_iomuxc
+       mov r0, #0x2
+       ldr r1, IOMUXC_BASE_ADDR_W
+       add r1, r1, #0x368
+       add r2, r1, #0x4C8 - 0x368
+1:      str r0, [r1], #4
+       cmp r1, r2
+       ble 1b
+    .endm /* init_iomuxc */
+
+/*
+ * r0: control base, r1: ram bank base
+ * r2: ddr type(0:DDR2, 1:MDDR) r3, r4: working
+ */
+setup_sdram_bank:
+       mov r3, #0xE /*0xA + 0x4*/
+       tst r2, #0x1
+       orreq r3, r3, #0x300 /*DDR2*/
+       str r3, [r0, #0x10]
+       bic r3, r3, #0x00A
+       str r3, [r0, #0x10]
+       beq 2f
+
+       mov r3, #0x20000
+1:     subs r3, r3, #1
+       bne 1b
+
+2:      adr r4, ESDCTL_CONFIG
+       tst r2, #0x1
+       ldreq r3, [r4, #0x0]
+       ldrne r3, [r4, #0x4]
+       cmp r1, #RAM_BANK1_BASE
+        strlo r3, [r0, #0x4]
+        strhs r3, [r0, #0xC]
+
+        ldr r3, ESDCTL_0x92220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+       mov r3, #0xDA
+        ldr r4, RAM_PARAM1_MDDR
+        strb r3, [r1, r4]
+
+       tst r2, #0x1
+       bne skip_set_mode
+
+       cmp r1, #RAM_BANK1_BASE
+       ldr r3, ESDCTL_0xB2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+       mov r3, #0xDA
+       ldr r4, RAM_PARAM4_MDDR
+        strb r3, [r1, r4]
+        ldr r4, RAM_PARAM5_MDDR
+        strb r3, [r1, r4]
+        ldr r4, RAM_PARAM3_MDDR
+        strb r3, [r1, r4]
+        ldr r4, RAM_PARAM2_MDDR
+        strb r3, [r1, r4]
+
+        ldr r3, ESDCTL_0x92220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+       mov r3, #0xDA
+        ldr r4, RAM_PARAM1_MDDR
+        strb r3, [r1, r4]
+
+skip_set_mode:
+       cmp r1, #RAM_BANK1_BASE
+        ldr r3, ESDCTL_0xA2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+        mov r3, #0xDA
+        strb r3, [r1]
+        strb r3, [r1]
+
+        ldr r3, ESDCTL_0xB2220000
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+       adr r4, RAM_PARAM6_MDDR
+       tst r2, #0x1
+       ldreq r4, [r4, #0x0]
+       ldrne r4, [r4, #0x4]
+        mov r3, #0xDA
+        strb r3, [r1, r4]
+        ldreq r4, RAM_PARAM7_MDDR
+        streqb r3, [r1, r4]
+       adr r4, RAM_PARAM3_MDDR
+       ldreq r4, [r4, #0x0]
+       ldrne r4, [r4, #0x4]
+        strb r3, [r1, r4]
+
+       cmp r1, #RAM_BANK1_BASE
+        ldr r3, ESDCTL_0x82226080
+        strlo r3, [r0, #0x0]
+        strhs r3, [r0, #0x8]
+
+       tst r2, #0x1
+       moveq r4, #0x20000
+       movne r4, #0x200
+1:     subs r4, r4, #1
+       bne 1b
+
+       str r3, [r1, #0x100]
+       ldr r4, [r1, #0x100]
+       cmp r3, r4
+       movne r3, #1
+       moveq r3, #0
+
+       mov pc, lr
+
+#define PLATFORM_VECTORS         _platform_vectors
+    .macro  _platform_vectors
+        .globl  _board_BCR, _board_CFG
+_board_BCR:   .long   0       // Board Control register shadow
+_board_CFG:   .long   0       // Board Configuration (read at RESET)
+    .endm
+
+//Internal Boot, from MMC/SD cards or NAND flash
+#ifdef INTERNAL_BOOT_MODE
+#define DCDGEN(i,type, addr, data) \
+dcd_##i:                         ;\
+    .long type                   ;\
+    .long addr                   ;\
+    .long data
+
+#define FHEADER_OFFSET 0x400
+
+    .macro setup_flash_header
+    b reset_vector
+#if defined(FHEADER_OFFSET)
+    .org FHEADER_OFFSET
+#endif
+app_code_jump_v:       .long reset_vector
+app_code_barker:       .long 0xB1
+app_code_csf:          .long 0
+hwcfg_ptr_ptr:         .long hwcfg_ptr
+super_root_key:                .long 0
+hwcfg_ptr:             .long dcd_data
+app_dest_ptr:          .long SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+dcd_data:              .long 0xB17219E9
+#ifdef MEMORY_MDDR_ENABLE
+                       .long 12*15
+#else
+                       .long 12*24
+#endif
+
+// real dcd data table
+
+// WEIM config-CS5 init -- CPLD
+DCDGEN( 1, 4, 0xB8002050, 0x0000D843)  // CS5_CSCRU
+DCDGEN( 2, 4, 0xB8002054, 0x22252521)  // CS5_CSCRL
+DCDGEN( 3, 4, 0xB8002058, 0x22220A00)  // CS5_CSCRA
+
+#ifdef MEMORY_MDDR_ENABLE
+// MDDR init
+DCDGEN( 4, 4, 0xB8001010, 0x00000004)  // enable mDDR
+DCDGEN( 5, 4, 0xB8001000, 0x92100000)  // precharge command
+DCDGEN( 6, 1, 0x80000400, 0x12344321)  // precharge all dummy write
+DCDGEN( 7, 4, 0xB8001000, 0xA2100000)  // auto-refresh command
+DCDGEN( 8, 4, 0x80000000, 0x12344321)  // dummy write for refresh
+DCDGEN( 9, 4, 0x80000000, 0x12344321)  // dummy write for refresh
+DCDGEN(10, 4, 0xB8001000, 0xB2100000)  // Load Mode Register command - cas=3 bl=8
+DCDGEN(11, 1, 0x80000033, 0xda)                // dummy write -- address has the mode bits
+DCDGEN(12, 1, 0x81000000, 0xff)                // dummy write -- address has the mode bits
+// 
+// For DDR clock speed max = 133 MHz, HYB18M1G320BF-7.5 memory
+// based on data sheet HYx18M1G16x_BF_rev100.pdf.
+// 
+// ESDCTL0=0x82216880:
+//  SDE=1       ESDRAM Controller Enable: Enabled
+//  SMODE=000   SDRAM Controller Operating Mode: Normal Read/Write
+//  SP=0        Supervisor Protect: User mode accesses allowed
+//  ROW=010     Row Address Width: 13 Row Addresses
+//  COL=10      Column Address Width: 10 Column Addresses
+//  DSIZ=01     SDRAM Memory Data Width: 16-bit memory width aligned to D[15:0]
+//  SREFR=011   SDRAM Refresh Rate: 4 rows each refresh clock,
+//                      8192 rows/64 mS @ 32 kHz
+//                      7.81 uS row rate at 32 kHz
+//  PWDT=10     Power Down Timer: 64 clocks (HCLK) after completion of last access
+//                      with Active Power Down (most aggressive)
+//  FP=0        Full Page: Not Full Page
+//  BL=1        Burst Length: 8
+//  PRCT=000000 Precharge Timer: Disabled
+//
+DCDGEN(13, 4, 0xB8001000, 0x82216880)
+//
+// ESDCFG0=0x00295729:
+//   tXP=01     LPDDR exit power down to next valid command delay: 2 clocks
+//   tWTR=0     LPDDR WRITE to READ Command Delay: 1 clock
+//   tRP=10     SDRAM Row Precharge Delay: 3 clocks
+//   tMRD=01    SDRAM Load Mode Register to ACTIVE Command: 2 clocks
+//   tWR=0      SDRAM WRITE to PRECHARGE Command: 2 clocks
+//   tRAS=101   SDRAM ACTIVE to PRECHARGE Command: 6 clocks
+//   tRRD=01    ACTIVE Bank A to ACTIVE Bank B Command: 2 clocks
+//   tCAS=11    SDRAM CAS Latency: 3 clocks
+//   tRCD=010   SDRAM Row to Column Delay: 3 clocks
+//   tRC=1001   SDRAM Row Cycle Delay: 9 clocks
+//
+DCDGEN(14, 4, 0xB8001004, 0x00295729)
+#else
+// DDR2 init
+DCDGEN( 4, 4, 0xB8001004, 0x0076E83A)  // initial value for ESDCFG0
+DCDGEN( 5, 4, 0xB8001010, 0x00000204)  // ESD_MISC
+DCDGEN( 6, 4, 0xB8001000, 0x92210000)  // CS0 precharge command
+DCDGEN( 7, 4, 0x80000f00, 0x12344321)  // precharge all dummy write
+DCDGEN( 8, 4, 0xB8001000, 0xB2210000)  // Load Mode Register command
+DCDGEN( 9, 1, 0x82000000, 0xda)                // dummy write -- Load EMR2
+DCDGEN(10, 1, 0x83000000, 0xda)                // dummy write -- Load EMR3
+DCDGEN(11, 1, 0x81000400, 0xda)                // dummy write -- Load EMR1; enable DLL
+DCDGEN(12, 1, 0x80000333, 0xda)                // dummy write -- Load MR; reset DLL
+
+DCDGEN(13, 4, 0xB8001000, 0x92210000)  // CS0 precharge command
+DCDGEN(14, 1, 0x80000400, 0x12345678)  // precharge all dummy write
+
+DCDGEN(15, 4, 0xB8001000, 0xA2210000)  // select manual refresh mode
+DCDGEN(16, 4, 0x80000000, 0x87654321)  // manual refresh
+DCDGEN(17, 4, 0x80000000, 0x87654321)  // manual refresh twice
+
+DCDGEN(18, 4, 0xB8001000, 0xB2210000)  // Load Mode Register command
+DCDGEN(19, 1, 0x80000233, 0xda)                // -- Load MR; CL=3, BL=8, end DLL reset
+DCDGEN(20, 1, 0x81000780, 0xda)                // -- Load EMR1; OCD default
+DCDGEN(21, 1, 0x81000400, 0xda)                // -- Load EMR1; OCD exit
+
+//  ESD_ESDCTL0  SDE_SMODE_SP_ROW_00_COL_00_DSIZ_SREFR_0_PWDT_0_FP_BL_0__PRCT
+//  ESD_ESDCTL0 32'b1_000__0__010_00__10_00___10___011_0___00_0__0__0_0_000000
+//  @; normal mode row=010//col=10//dzize=10//self ref=011//PWDT =00//BL =0//prct =000000
+DCDGEN(22, 4, 0xB8001000, 0x82216080)
+
+// Init IOMUXC_SW_PAD_CTL_GRP_DDRTYPE_GRP(1-5)
+DCDGEN(23, 4, 0x43FAC454, 0x00001000)
+#endif
+//
+// CLK 
+DCDGEN(99, 4, 0x53F80008, 0x20034000)  // CLKCTL ARM=400 AHB=133
+
+//CARD_FLASH_CFG_PARMS_T---length
+card_cfg:              .long REDBOOT_IMAGE_SIZE
+     .endm
+#endif
+
+AIPS1_CTRL_BASE_ADDR_W:        .word   AIPS1_CTRL_BASE_ADDR
+AIPS2_CTRL_BASE_ADDR_W:        .word   AIPS2_CTRL_BASE_ADDR
+AIPS1_PARAM_W:         .word   0x77777777
+MAX_BASE_ADDR_W:       .word   MAX_BASE_ADDR
+MAX_PARAM1:            .word   0x00043210
+ESDCTL_BASE_W:         .word   ESDCTL_BASE_ADDR
+M3IF_BASE_W:           .word   M3IF_BASE
+RAM_PARAM1_MDDR:       .word   0x00000400
+RAM_PARAM2_MDDR:       .word   0x00000333
+RAM_PARAM3_MDDR:       .word   0x02000400
+                       .word   0x02000000
+RAM_PARAM4_MDDR:       .word   0x04000000
+RAM_PARAM5_MDDR:       .word   0x06000000
+RAM_PARAM6_MDDR:       .word   0x00000233
+                       .word   0x00000033
+RAM_PARAM7_MDDR:       .word   0x02000780
+ESDCTL_0x92220000:     .word   0x92220000
+ESDCTL_0xA2220000:     .word   0xA2220000
+ESDCTL_0xB2220000:     .word   0xB2220000
+ESDCTL_0x82226080:     .word   0x82226080
+ESDCTL_CONFIG:         .word   0x007FFC3F
+                       .word   0x007FFC3F
+ESDCTL_DELAY5:         .word   0x00F49F00
+IOMUXC_BASE_ADDR_W:    .word   IOMUXC_BASE_ADDR
+CCM_CCTL_W:            .word   0x20034000      // ARM clk = 400, AHB clk = 133
+MPCTL_PARAM_399_W:     .word   MPCTL_PARAM_399
+MPCTL_PARAM_532_W:     .word   MPCTL_PARAM_532
+UPCTL_PARAM_W:         .word   UPCTL_PARAM_300
+CCM_CGR0_W:            .word   0x1FFFFFFF
+CCM_CGR1_W:            .word   0xFFFFFFFF
+CCM_CGR2_W:            .word   0x000FDFFF
+MXCBOOT_FLAG_ADDR_W:   .word   MXCBOOT_FLAG_REG
+MXCFIS_FLAG_ADDR_W:    .word   MXCFIS_FLAG_REG
+MXC_REDBOOT_ROM_START: .word   SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0x0FFF:          .word   0x0FFF
+CCM_BASE_ADDR_W:       .word   CCM_BASE_ADDR
+WEIM_CTRL_CS5_W:       .word   WEIM_CTRL_CS5
+WEIM_CTRL_CS0_W:       .word   WEIM_CTRL_CS0
+CS0_CSCRU_0x0000CC03:  .word   0x0000DCF6
+CS0_CSCRL_0xA0330D01:  .word   0x444A4541
+CS0_CSCRA_0x00220800:  .word   0x44443302
+CS5_CSCRU_0x0000D843:  .word   0x0000D843
+CS5_CSCRL_0x22252521:  .word   0x22252521
+CS5_CSCRA_0x22220A00:  .word   0x22220A00
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h                                               */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
diff --git a/packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h b/packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h
new file mode 100644 (file)
index 0000000..0d9ea35
--- /dev/null
@@ -0,0 +1,20 @@
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0x87F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi b/packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi
new file mode 100644 (file)
index 0000000..e9bcdcd
--- /dev/null
@@ -0,0 +1,31 @@
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x7F00000
+    rom : ORIGIN = 0x87F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (rom, 0x87F00000, LMA_EQ_VMA)
+    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+    SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt b/packages/hal/arm/mx25/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt
new file mode 100644 (file)
index 0000000..35b3630
--- /dev/null
@@ -0,0 +1,14 @@
+version 0
+region ram 0 7F00000 0 !
+region rom 87F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 87F00000 87F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
diff --git a/packages/hal/arm/mx25/3stack/v2_0/include/plf_io.h b/packages/hal/arm/mx25/3stack/v2_0/include/plf_io.h
new file mode 100644 (file)
index 0000000..38245c1
--- /dev/null
@@ -0,0 +1,68 @@
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_)                                                           \
+    CYG_MACRO_START                                                                                  \
+    {                                                                                                \
+      extern unsigned int system_rev;                                                                \
+             /* Next ATAG_MEM. */                                                                    \
+         _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long);        \
+         _p_->hdr.tag = ATAG_MEM;                                                                    \
+         /* Round up so there's only one bit set in the memory size.                                 \
+         * Don't double it if it's already a power of two, though.                                   \
+         */                                                                                          \
+         _p_->u.mem.size  = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE);                                 \
+         if (_p_->u.mem.size < (CYGMEM_REGION_ram_SIZE))                                               \
+                 _p_->u.mem.size <<= 1;                                                              \
+         _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram);                              \
+         _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size);                                          \
+         _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long);   \
+         _p_->hdr.tag = ATAG_REVISION;                                                               \
+         _p_->u.revision.rev = system_rev;                                                           \
+     }                                                                                               \
+    CYG_MACRO_END
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
diff --git a/packages/hal/arm/mx25/3stack/v2_0/include/plf_mmap.h b/packages/hal/arm/mx25/3stack/v2_0/include/plf_mmap.h
new file mode 100644 (file)
index 0000000..e81d833
--- /dev/null
@@ -0,0 +1,93 @@
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+//      plf_mmap.h
+//
+//      Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START        \
+        (pagesize) = SZ_1M;                                         \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START           \
+        cyg_uint32 _v_ = (cyg_uint32)(vaddr);                                  \
+        if ( _v_ < 128 * SZ_1M )         /* SDRAM */                           \
+                _v_ += SDRAM_BASE_ADDR;                                             \
+        else                             /* Rest of it */                      \
+                /* no change */ ;                                                  \
+                (paddr) = _v_;                                                         \
+CYG_MACRO_END
+
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+        if(virt < 0x08000000) {
+                return virt|0x80000000;
+        }
+        if((virt & 0xF0000000) == 0x80000000) {
+                return virt&(~0x08000000);
+        }
+        return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+        /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+        if((phy & 0xF0000000) == 0x80000000) {
+                phy |= 0x08000000;
+        }
+        return phy;
+}
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
diff --git a/packages/hal/arm/mx25/3stack/v2_0/misc/redboot_ROMRAM.ecm b/packages/hal/arm/mx25/3stack/v2_0/misc/redboot_ROMRAM.ecm
new file mode 100644 (file)
index 0000000..0d48beb
--- /dev/null
@@ -0,0 +1,158 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    mx25_3stack ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_ARM current ;
+    package -hardware CYGPKG_HAL_ARM_MX25 current ;
+    package -hardware CYGPKG_HAL_ARM_MX25_3STACK current ;
+    package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+    package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+    package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+    package -hardware CYGPKG_DEVS_ETH_FEC current ;
+    package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+    package -hardware CYGPKG_COMPRESS_ZLIB current ;
+    package -hardware CYGPKG_DIAGNOSIS current ;
+    package -hardware CYGPKG_IO_FLASH current ;
+    package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+    package -hardware CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION current ;
+    package -hardware CYGPKG_DEVS_MXC_SPI current ;
+    package -hardware CYGPKG_DEVS_MXC_I2C current ;
+    package -hardware CYGPKG_DEVS_PMIC_ARM_IMX25_3STACK current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_7 {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_PORT {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_ADDR {
+    inferred_value 0x54
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_MX25_MDDR {
+    inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    inferred_value 3
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+    user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+    inferred_value 0x80008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+    user_value 1
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+    inferred_value 1
+};
+
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+    user_value 1 "FSL 200904"
+};
diff --git a/packages/hal/arm/mx25/3stack/v2_0/misc/redboot_ROMRAM_TO1_1.ecm b/packages/hal/arm/mx25/3stack/v2_0/misc/redboot_ROMRAM_TO1_1.ecm
new file mode 100644 (file)
index 0000000..4a10a85
--- /dev/null
@@ -0,0 +1,154 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    mx25_3stack ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_ARM current ;
+    package -hardware CYGPKG_HAL_ARM_MX25 current ;
+    package -hardware CYGPKG_HAL_ARM_MX25_3STACK current ;
+    package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+    package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+    package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+    package -hardware CYGPKG_DEVS_ETH_FEC current ;
+    package -hardware CYGPKG_DEVS_FLASH_AMD_AM29XXXXX current ;
+    package -hardware CYGPKG_COMPRESS_ZLIB current ;
+    package -hardware CYGPKG_DIAGNOSIS current ;
+    package -hardware CYGPKG_IO_FLASH current ;
+    package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+    package -hardware CYGPKG_DEVS_FLASH_IMX_3STACK_SPANSION current ;
+    package -hardware CYGPKG_DEVS_MXC_SPI current ;
+    package -hardware CYGPKG_DEVS_MXC_I2C current ;
+    package -hardware CYGPKG_DEVS_PMIC_ARM_IMX25_3STACK current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_AMD_S29GL512N {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FSL_SPI_VER_0_7 {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_PORT {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_PMIC_I2C_ADDR {
+    inferred_value 0x54
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+    inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    inferred_value 3
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+    user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+    inferred_value 0x80008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+    user_value 1
+};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+    inferred_value 1
+};
+
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+    user_value 1 "FSL 200904"
+};
diff --git a/packages/hal/arm/mx25/3stack/v2_0/src/board_diag.c b/packages/hal/arm/mx25/3stack/v2_0/src/board_diag.c
new file mode 100644 (file)
index 0000000..71b4a88
--- /dev/null
@@ -0,0 +1,639 @@
+/*=============================================================================
+//
+//      board_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // basic machine info
+#include <cyg/hal/hal_intr.h>           // interrupt macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_if.h>             // Calling-if API
+#include <cyg/hal/drv_api.h>            // driver API
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/hal_soc.h>            // Hardware definitions
+#include <cyg/hal/fsl_board.h>          // Platform specifics
+
+static void cyg_hal_plf_duart_init(void);
+extern void cyg_hal_plf_serial_init(void);
+
+void cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+    cyg_hal_plf_duart_init();
+    cyg_hal_plf_serial_init();
+}
+
+//=============================================================================
+// ST16552 DUART driver
+//=============================================================================
+
+//-----------------------------------------------------------------------------
+// Only one external UART.
+#define CYG_DEV_SERIAL_BASE_A    (BOARD_CS_UART_BASE + 0x00)
+
+//-----------------------------------------------------------------------------
+// Based on 3.6864 MHz xtal
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
+#define CYG_DEV_SERIAL_BAUD_MSB        0x00
+#define CYG_DEV_SERIAL_BAUD_LSB        0x18
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
+#define CYG_DEV_SERIAL_BAUD_MSB        0x00
+#define CYG_DEV_SERIAL_BAUD_LSB        0x0C
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
+#define CYG_DEV_SERIAL_BAUD_MSB        0x00
+#define CYG_DEV_SERIAL_BAUD_LSB        0x06
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
+#define CYG_DEV_SERIAL_BAUD_MSB        0x00
+#define CYG_DEV_SERIAL_BAUD_LSB        0x04
+#endif
+#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
+#define CYG_DEV_SERIAL_BAUD_MSB        0x00
+#define CYG_DEV_SERIAL_BAUD_LSB        0x02
+#endif
+
+#ifndef CYG_DEV_SERIAL_BAUD_MSB
+#error Missing/incorrect serial baud rate defined - CDL error?
+#endif
+
+//-----------------------------------------------------------------------------
+// Define the serial registers. The board is equipped with a 16552
+// serial chip.
+
+#if defined (EXT_UART_x16)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
+#define HAL_READ_UINT_UART HAL_READ_UINT16
+typedef cyg_uint16 uart_width;
+#elif defined (EXT_UART_x32)
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT32
+#define HAL_READ_UINT_UART HAL_READ_UINT32
+typedef cyg_uint32 uart_width;
+#else  //_x8
+#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
+#define HAL_READ_UINT_UART HAL_READ_UINT8
+typedef cyg_uint8 uart_width;
+#endif
+
+#define CYG_DEV_SERIAL_RHR   0x00 // receiver buffer register, read, dlab = 0
+#define CYG_DEV_SERIAL_THR   0x00 // transmitter holding register, write, dlab = 0
+#define CYG_DEV_SERIAL_DLL   0x00 // divisor latch (LS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IER   0x01 // interrupt enable register, read/write, dlab = 0
+#define CYG_DEV_SERIAL_DLM   0x01 // divisor latch (MS), read/write, dlab = 1
+#define CYG_DEV_SERIAL_IIR   0x02 // interrupt identification register, read, dlab = 0
+#define CYG_DEV_SERIAL_FCR   0x02 // fifo control register, write, dlab = 0
+#define CYG_DEV_SERIAL_AFR   0x02 // alternate function register, read/write, dlab = 1
+#define CYG_DEV_SERIAL_LCR   0x03 // line control register, read/write
+#define CYG_DEV_SERIAL_MCR   0x04
+#define CYG_DEV_SERIAL_MCR_A 0x04
+#define CYG_DEV_SERIAL_MCR_B 0x04
+#define CYG_DEV_SERIAL_LSR   0x05 // line status register, read
+#define CYG_DEV_SERIAL_MSR   0x06 // modem status register, read
+#define CYG_DEV_SERIAL_SCR   0x07 // scratch pad register
+
+// The interrupt enable register bits.
+#define SIO_IER_ERDAI   0x01            // enable received data available irq
+#define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
+#define SIO_IER_ELSI    0x04            // enable receiver line status irq
+#define SIO_IER_EMSI    0x08            // enable modem status interrupt
+
+// The interrupt identification register bits.
+#define SIO_IIR_IP      0x01            // 0 if interrupt pending
+#define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
+#define ISR_Tx  0x02
+#define ISR_Rx  0x04
+
+// The line status register bits.
+#define SIO_LSR_DR      0x01            // data ready
+#define SIO_LSR_OE      0x02            // overrun error
+#define SIO_LSR_PE      0x04            // parity error
+#define SIO_LSR_FE      0x08            // framing error
+#define SIO_LSR_BI      0x10            // break interrupt
+#define SIO_LSR_THRE    0x20            // transmitter holding register empty
+#define SIO_LSR_TEMT    0x40            // transmitter register empty
+#define SIO_LSR_ERR     0x80            // any error condition
+
+// The modem status register bits.
+#define SIO_MSR_DCTS    0x01            // delta clear to send
+#define SIO_MSR_DDSR    0x02            // delta data set ready
+#define SIO_MSR_TERI    0x04            // trailing edge ring indicator
+#define SIO_MSR_DDCD    0x08            // delta data carrier detect
+#define SIO_MSR_CTS     0x10            // clear to send
+#define SIO_MSR_DSR     0x20            // data set ready
+#define SIO_MSR_RI      0x40            // ring indicator
+#define SIO_MSR_DCD     0x80            // data carrier detect
+
+// The line control register bits.
+#define SIO_LCR_WLS0   0x01             // word length select bit 0
+#define SIO_LCR_WLS1   0x02             // word length select bit 1
+#define SIO_LCR_STB    0x04             // number of stop bits
+#define SIO_LCR_PEN    0x08             // parity enable
+#define SIO_LCR_EPS    0x10             // even parity select
+#define SIO_LCR_SP     0x20             // stick parity
+#define SIO_LCR_SB     0x40             // set break
+#define SIO_LCR_DLAB   0x80             // divisor latch access bit
+
+// The FIFO control register
+#define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
+#define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
+#define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
+
+//-----------------------------------------------------------------------------
+
+typedef struct {
+    uart_width* base;
+    cyg_int32 msec_timeout;
+    int isr_vector;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_DUART_UARTA != 0
+    {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
+#endif
+#if CYGHWR_HAL_ARM_DUART_UARTB != 0
+    {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
+#endif
+};
+
+//-----------------------------------------------------------------------------
+
+static void init_duart_channel(channel_data_t* __ch_data)
+{
+    uart_width* base = __ch_data->base;
+    uart_width lcr;
+
+    // 8-1-no parity.
+    HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
+                        SIO_LCR_WLS0 | SIO_LCR_WLS1);
+
+    HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+    lcr |= SIO_LCR_DLAB;
+    HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+    HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
+    HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
+    lcr &= ~SIO_LCR_DLAB;
+    HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
+    HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07);  // Enable & clear FIFO
+}
+
+//#define x_debug_uart_log_buf
+#ifdef x_debug_uart_log_buf
+#define x_DIAG_BUFSIZE 2048
+static char __x_log_buf[x_DIAG_BUFSIZE];
+static int x_diag_bp = 0;
+#endif
+
+void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
+{
+    uart_width* base = ((channel_data_t*)__ch_data)->base;
+    uart_width lsr;
+
+#ifdef x_debug_uart_log_buf
+    __x_log_buf[x_diag_bp++] = c;
+#endif
+    CYGARC_HAL_SAVE_GP();
+
+    do {
+        HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+    } while ((lsr & SIO_LSR_THRE) == 0);
+
+    HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
+
+    // Hang around until the character has been safely sent.
+    do {
+        HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+    } while ((lsr & SIO_LSR_THRE) == 0);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
+{
+    uart_width* base = ((channel_data_t*)__ch_data)->base;
+    uart_width lsr, ch16;
+
+    HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
+    if ((lsr & SIO_LSR_DR) == 0)
+        return false;
+
+    HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
+
+    *ch = (cyg_uint8) (ch16 & 0x00FF);
+
+    return true;
+}
+
+cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+
+    CYGARC_HAL_SAVE_GP();
+
+    while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
+                                    cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        cyg_hal_plf_duart_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf, 
+                                   cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+    for (;;) {
+        res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int cyg_hal_plf_duart_control(void *__ch_data, 
+                                     __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    uart_width ier;
+    int ret = 0;
+
+    CYGARC_HAL_SAVE_GP();
+
+    switch (__func) {
+    case __COMMCTL_IRQ_ENABLE:
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
+        HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+        ier |= SIO_IER_ERDAI;
+        HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+        irq_state = 1;
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+        ier &= ~SIO_IER_ERDAI;
+        HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        {
+            va_list ap;
+
+            va_start(ap, __func);
+
+            ret = chan->msec_timeout;
+            chan->msec_timeout = va_arg(ap, cyg_uint32);
+
+            va_end(ap);
+        }
+        break;
+    default:
+        break;
+    }
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
+                                 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    uart_width _iir;
+    int res = 0;
+    CYGARC_HAL_SAVE_GP();
+
+    HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
+    _iir &= SIO_IIR_ID_MASK;
+
+    *__ctrlc = 0;
+    if ( ISR_Rx == _iir ) {
+        uart_width c, lsr;
+        cyg_uint8 c8;
+        HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
+        if (lsr & SIO_LSR_DR) {
+
+            HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
+
+            c8 = (cyg_uint8) (c & 0x00FF);
+
+            if (cyg_hal_is_break( &c8 , 1 ))
+                *__ctrlc = 1;
+        }
+
+        // Acknowledge the interrupt
+        HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
+        res = CYG_ISR_HANDLED;
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static void cyg_hal_plf_duart_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+    int i;
+
+    // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+    for (i = 0;  i < NUMOF(channels);  i++) {
+        HAL_INTERRUPT_MASK(channels[i].isr_vector);
+        init_duart_channel(&channels[i]);
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
+        CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
+#define __BASE   CMA101_DUARTA
+#define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_A
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
+#define __BASE   CMA101_DUARTB
+#define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_B
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+    (uart_width*) _BASE, 0, 0
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+    static int init = 0;
+    char *msg = "\n\rARM eCos\n\r";
+    uart_width lcr;
+
+    if (init++) return;
+
+    init_duart_channel(&channel);
+
+    while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define DIAG_BUFSIZE 32
+#else
+#define DIAG_BUFSIZE 2048
+#endif
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void hal_diag_write_char(char c)
+{
+    uart_width lsr;
+
+    hal_diag_init();
+
+    cyg_hal_plf_duart_putc(&channel, c)
+
+#ifdef DEBUG_DIAG
+    diag_buffer[diag_bp++] = c;
+    if (diag_bp == DIAG_BUFSIZE) {
+        while (1) ;
+        diag_bp = 0;
+    }
+#endif
+}
+
+void hal_diag_read_char(char *c)
+{
+    *c = cyg_hal_plf_duart_getc(&channel);
+}
+
+#else // HAL_DIAG relies on GDB
+
+// Initialize diag port - assume GDB channel is already set up
+void hal_diag_init(void)
+{
+    if (0) init_duart_channel(&channel); // avoid warning
+}
+
+// Actually send character down the wire
+static void hal_diag_write_char_serial(char c)
+{
+    cyg_hal_plf_duart_putc(&channel, c);
+}
+
+static bool hal_diag_read_serial(char *c)
+{
+    long timeout = 1000000000;  // A long time...
+
+    while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
+        if (0 == --timeout) return false;
+
+    return true;
+}
+
+void hal_diag_read_char(char *c)
+{
+    while (!hal_diag_read_serial(c)) ;
+}
+
+void hal_diag_write_char(char c)
+{
+    static char line[100];
+    static int pos = 0;
+
+    // No need to send CRs
+    if (c == '\r') return;
+
+    line[pos++] = c;
+
+    if (c == '\n' || pos == sizeof(line)) {
+        CYG_INTERRUPT_STATE old;
+
+        // Disable interrupts. This prevents GDB trying to interrupt us
+        // while we are in the middle of sending a packet. The serial
+        // receive interrupt will be seen when we re-enable interrupts
+        // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+        HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+        while (1) {
+            static char hex[] = "0123456789ABCDEF";
+            cyg_uint8 csum = 0;
+            int i;
+            char c1;
+
+            hal_diag_write_char_serial('$');
+            hal_diag_write_char_serial('O');
+            csum += 'O';
+            for (i = 0; i < pos; i++) {
+                char ch = line[i];
+                char h = hex[(ch>>4)&0xF];
+                char l = hex[ch&0xF];
+                hal_diag_write_char_serial(h);
+                hal_diag_write_char_serial(l);
+                csum += h;
+                csum += l;
+            }
+            hal_diag_write_char_serial('#');
+            hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
+            hal_diag_write_char_serial(hex[csum&0xF]);
+
+            // Wait for the ACK character '+' from GDB here and handle
+            // receiving a ^C instead.  This is the reason for this clause
+            // being a loop.
+            if (!hal_diag_read_serial(&c1))
+                continue;   // No response - try sending packet again
+
+            if ( c1 == '+' )
+                break;          // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
+            if ( c1 == 3 ) {
+                // Ctrl-C: breakpoint.
+                cyg_hal_gdb_interrupt (__builtin_return_address(0));
+                break;
+            }
+#endif
+            // otherwise, loop round again
+        }
+
+        pos = 0;
+
+        // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+        HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+    }
+}
+#endif
+
+#endif // __BASE
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
diff --git a/packages/hal/arm/mx25/3stack/v2_0/src/board_misc.c b/packages/hal/arm/mx25/3stack/v2_0/src/board_misc.c
new file mode 100644 (file)
index 0000000..7dcebf4
--- /dev/null
@@ -0,0 +1,361 @@
+//==========================================================================
+//
+//      board_misc.c
+//
+//      HAL misc board support code for the board
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include <redboot.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // Interrupt names
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_soc.h>         // Hardware definitions
+#include <cyg/hal/fsl_board.h>             // Platform specifics
+
+#include <cyg/infra/diag.h>             // diag_printf
+
+// All the MM table layout is here:
+#include <cyg/hal/hal_mm.h>
+
+externC void* memset(void *, int, size_t);
+static void mxc_fec_setup(void);
+static void mxc_serial_setup(void);
+
+void hal_mmu_init(void)
+{
+    unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
+    unsigned long i;
+
+    /*
+     * Set the TTB register
+     */
+    asm volatile ("mcr  p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
+
+    /*
+     * Set the Domain Access Control Register
+     */
+    i = ARM_ACCESS_DACR_DEFAULT;
+    asm volatile ("mcr  p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
+
+    /*
+     * First clear all TT entries - ie Set them to Faulting
+     */
+    memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
+
+    /*              Actual   Virtual  Size   Attributes                                                    Function  */
+    /*              Base     Base     MB     cached?           buffered?        access permissions                 */
+    /*              xxx00000 xxx00000                                                                                */
+    X_ARM_MMU_SECTION(0x000, 0xF00,   0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
+    X_ARM_MMU_SECTION(0x400, 0x400,   0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
+    X_ARM_MMU_SECTION(0x800, 0x000,   0x080, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+    X_ARM_MMU_SECTION(0x800, 0x800,   0x080, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+    X_ARM_MMU_SECTION(0x800, 0x880,   0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+    X_ARM_MMU_SECTION(0xB00, 0xB00,   0x20,  ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* PSRAM */
+    X_ARM_MMU_SECTION(0xB20, 0xB20,   0x1E0, ARM_UNCACHEABLE, ARM_UNBUFFERABLE,ARM_ACCESS_PERM_RW_RW); /* ESDCTL, WEIM, M3IF, EMI, NFC, External I/O */
+}
+
+//
+// Platform specific initialization
+//
+
+unsigned int g_clock_src;
+
+void plf_hardware_init(void)
+{
+    g_clock_src = FREQ_24MHZ;
+
+    mxc_serial_setup();
+    mxc_fec_setup();
+}
+
+static void mxc_serial_setup(void)
+{
+       // UART1
+       /*RXD1*/
+       writel(0, IOMUXC_BASE_ADDR + 0x170);
+       writel(0x1E0, IOMUXC_BASE_ADDR + 0x368);
+
+       /*TXD1*/
+       writel(0, IOMUXC_BASE_ADDR + 0x174);
+       writel(0x40, IOMUXC_BASE_ADDR + 0x36c);
+
+       /*RTS1*/
+       writel(0, IOMUXC_BASE_ADDR + 0x178);
+       writel(0x1E0, IOMUXC_BASE_ADDR + 0x370);
+
+       /*CTS1*/
+       writel(0, IOMUXC_BASE_ADDR + 0x17c);
+       writel(0x40, IOMUXC_BASE_ADDR + 0x374);
+}
+
+static void mxc_fec_setup(void)
+{
+       unsigned int val;
+
+       /* FEC_TX_CLK */
+       writel(0, IOMUXC_BASE_ADDR + 0x01E8);
+       writel(0x1C0, IOMUXC_BASE_ADDR + 0x03E0);
+
+       /* FEC_RX_DV */
+       writel(0, IOMUXC_BASE_ADDR + 0x01E4);
+       writel(0x1C0, IOMUXC_BASE_ADDR + 0x03DC);
+
+       /* FEC_RDATA0 */
+       writel(0, IOMUXC_BASE_ADDR + 0x01DC);
+       writel(0x1C0, IOMUXC_BASE_ADDR + 0x03D4);
+
+       /* FEC_TDATA0 */
+       writel(0, IOMUXC_BASE_ADDR + 0x01D0);
+       writel(0x40, IOMUXC_BASE_ADDR + 0x03C8);
+
+       /* FEC_TX_EN */
+       writel(0, IOMUXC_BASE_ADDR + 0x01D8);
+       writel(0x40, IOMUXC_BASE_ADDR + 0x03D0);
+
+       /* FEC_MDC */
+       writel(0, IOMUXC_BASE_ADDR + 0x01C8);
+       writel(0x40, IOMUXC_BASE_ADDR + 0x03C0);
+
+       /* FEC_MDIO */
+       writel(0, IOMUXC_BASE_ADDR + 0x01CC);
+       writel(0x1F0, IOMUXC_BASE_ADDR + 0x03C4);
+
+       /* FEC_RDATA1 */
+       writel(0, IOMUXC_BASE_ADDR + 0x01E0);
+       writel(0x1C0, IOMUXC_BASE_ADDR + 0x03D8);
+
+       /* FEC_TDATA1 */
+       writel(0, IOMUXC_BASE_ADDR + 0x01D4);
+       writel(0x40, IOMUXC_BASE_ADDR + 0x03CC);
+
+       /* 
+        * Set up the FEC_RESET_B and FEC_ENABLE GPIO pins.
+        * Assert FEC_RESET_B, then power up the PHY by asserting
+        * FEC_ENABLE, at the same time lifting FEC_RESET_B.
+        *
+        * FEC_RESET_B: gpio2[3] is ALT 5 mode of pin A17
+        * FEC_ENABLE_B: gpio4[8] is ALT 5 mode of pin D12
+        */
+       writel(0x5, IOMUXC_BASE_ADDR + 0x001C);
+       writel(0x5, IOMUXC_BASE_ADDR + 0x0094);
+
+       writel(0x8, IOMUXC_BASE_ADDR + 0x0238); // open drain
+       writel(0x0, IOMUXC_BASE_ADDR + 0x028C); // cmos, no pu/pd
+
+       /* make the pins output */
+       val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_GDIR);
+       writel(val, GPIO2_BASE_ADDR + GPIO_GDIR);
+
+       val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_GDIR);
+       writel(val, GPIO4_BASE_ADDR + GPIO_GDIR);
+
+       /* drop PHY power */
+       val = readl(GPIO2_BASE_ADDR + GPIO_DR) & ~(1 << 3);
+       writel(val, GPIO2_BASE_ADDR + GPIO_DR);
+
+       /* assert reset */
+       val = readl(GPIO4_BASE_ADDR + GPIO_DR) & ~(1 << 8);
+       writel(val, GPIO4_BASE_ADDR + GPIO_DR);
+       hal_delay_us(2);        // spec says 1us min
+
+       /* turn on power & lift reset */
+       val = (1 << 3) | readl(GPIO2_BASE_ADDR + GPIO_DR);
+       writel(val, GPIO2_BASE_ADDR + GPIO_DR);
+       val = (1 << 8) | readl(GPIO4_BASE_ADDR + GPIO_DR);
+       writel(val, GPIO4_BASE_ADDR + GPIO_DR);
+}
+
+static void mxc_cspi_setup(void)
+{
+       /*CSPI1*/
+       /*SCLK*/
+       writel(0, IOMUXC_BASE_ADDR + 0x180);
+       writel(0x1C0, IOMUXC_BASE_ADDR + 0x5c4);
+       /*SPI_RDY*/
+       writel(0, IOMUXC_BASE_ADDR + 0x184);
+       writel(0x1E0, IOMUXC_BASE_ADDR + 0x5c8);
+       /*MOSI*/
+       writel(0, IOMUXC_BASE_ADDR + 0x170);
+       writel(0x1C0, IOMUXC_BASE_ADDR + 0x5b4);
+       /*MISO*/
+       writel(0, IOMUXC_BASE_ADDR + 0x174);
+       writel(0x1C0, IOMUXC_BASE_ADDR + 0x5b8);
+       /*SS1*/
+       writel(0, IOMUXC_BASE_ADDR + 0x17C);
+       writel(0x1E0, IOMUXC_BASE_ADDR + 0x5C0);
+}
+
+void mxc_i2c_init(unsigned int module_base)
+{
+       switch(module_base) {
+       case I2C_BASE_ADDR:
+               /* Pins: SION */
+               writel(0x10, IOMUXC_BASE_ADDR + 0x150);         /* I2C1_CLK */
+               writel(0x10, IOMUXC_BASE_ADDR + 0x154);         /* I2C1_DAT */
+
+               /* Pads: HYS, 100k Pull-up, open drain */
+               writel(0x1E8, IOMUXC_BASE_ADDR + 0x348);        /* I2C1_CLK */
+               writel(0x1E8, IOMUXC_BASE_ADDR + 0x34c);        /* I2C1_DAT */
+               break;
+       case I2C2_BASE_ADDR:
+               /* Pins: ALT1 (of FEC_RDATA1, FEC_RX_DV pins), SION */
+               writel(0x11, IOMUXC_BASE_ADDR + 0x1e0);         /* I2C2_CLK */
+               writel(0x11, IOMUXC_BASE_ADDR + 0x1e4);         /* I2C2_DAT */
+
+               /* Pads: HYS, 100k Pull-up, open drain */
+               writel(0x1E8, IOMUXC_BASE_ADDR + 0x3d8);        /* I2C2_CLK */
+               writel(0x1E8, IOMUXC_BASE_ADDR + 0x3dc);        /* I2C2_DAT */
+               break;
+       case I2C3_BASE_ADDR:
+               /* Pins: ALT2 (of HSYNC, VSYNC pins), SION */
+               writel(0x12, IOMUXC_BASE_ADDR + 0x108);         /* I2C3_CLK */
+               writel(0x12, IOMUXC_BASE_ADDR + 0x10c);         /* I2C3_DAT */
+
+               /* Pads: HYS, 100k Pull-up, open drain */
+               writel(0x1E8, IOMUXC_BASE_ADDR + 0x300);        /* I2C2_CLK */
+               writel(0x1E8, IOMUXC_BASE_ADDR + 0x304);        /* I2C2_DAT */
+               break;
+       default:
+               break;
+       }
+}
+void mxc_mmc_init(base_address)
+{
+       unsigned int val;
+
+       switch(base_address) {
+       case MMC_SDHC1_BASE_ADDR:
+               /* Pins */
+               writel(0x10, IOMUXC_BASE_ADDR + 0x190); /* SD1_CMD */
+               writel(0x10, IOMUXC_BASE_ADDR + 0x194); /* SD1_CLK */
+               writel(0x00, IOMUXC_BASE_ADDR + 0x198); /* SD1_DATA0 */
+               writel(0x00, IOMUXC_BASE_ADDR + 0x19c); /* SD1_DATA1 */
+               writel(0x00, IOMUXC_BASE_ADDR + 0x1a0); /* SD1_DATA2 */
+               writel(0x00, IOMUXC_BASE_ADDR + 0x1a4); /* SD1_DATA3 */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x094); /* D12 (SD1_DATA4) */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x090); /* D13 (SD1_DATA5) */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x08c); /* D14 (SD1_DATA6) */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x088); /* D15 (SD1_DATA7) */
+               writel(0x05, IOMUXC_BASE_ADDR + 0x010); /* A14 (SD1_WP) */
+               writel(0x05, IOMUXC_BASE_ADDR + 0x014); /* A15 (SD1_DET) */
+
+               /* Pads */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x388); /* SD1_CMD */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x38c); /* SD1_CLK */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x390); /* SD1_DATA0 */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x394); /* SD1_DATA1 */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x398); /* SD1_DATA2 */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x39c); /* SD1_DATA3 */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x28c); /* D12 (SD1_DATA4) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x288); /* D13 (SD1_DATA5) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x284); /* D14 (SD1_DATA6) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x280); /* D15 (SD1_DATA7) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x230); /* A14 (SD1_WP) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x234); /* A15 (SD1_DET) */
+
+               /*
+                * Set write protect and card detect gpio as inputs
+                * A14 (SD1_WP) and A15 (SD1_DET)
+                */
+               val = ~(3 << 0) & readl(GPIO1_BASE_ADDR + GPIO_GDIR);
+               writel(val, GPIO1_BASE_ADDR + GPIO_GDIR);
+
+               break;
+       case MMC_SDHC2_BASE_ADDR:
+               /* Pins */
+               writel(0x16, IOMUXC_BASE_ADDR + 0x0e8); /* LD8 (SD1_CMD) */
+               writel(0x16, IOMUXC_BASE_ADDR + 0x0ec); /* LD9 (SD1_CLK) */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x0f0); /* LD10 (SD1_DATA0) */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x0f4); /* LD11 (SD1_DATA1) */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x0f8); /* LD12 (SD1_DATA2) */
+               writel(0x06, IOMUXC_BASE_ADDR + 0x0fc); /* LD13 (SD1_DATA3) */
+               writel(0x02, IOMUXC_BASE_ADDR + 0x120); /* CSI_D2 (SD1_DATA4) */
+               writel(0x02, IOMUXC_BASE_ADDR + 0x124); /* CSI_D3 (SD1_DATA5) */
+               writel(0x02, IOMUXC_BASE_ADDR + 0x128); /* CSI_D4 (SD1_DATA6) */
+               writel(0x02, IOMUXC_BASE_ADDR + 0x12c); /* CSI_D5 (SD1_DATA7) */
+
+               /* Pads */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x2e0); /* LD8 (SD1_CMD) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x2e4); /* LD9 (SD1_CLK) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x2e8); /* LD10 (SD1_DATA0) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x2ec); /* LD11 (SD1_DATA1) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x2f0); /* LD12 (SD1_DATA2) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x2f4); /* LD13 (SD1_DATA3) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x318); /* CSI_D2 (SD1_DATA4) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x31c); /* CSI_D3 (SD1_DATA5) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x320); /* CSI_D4 (SD1_DATA6) */
+               writel(0xD1, IOMUXC_BASE_ADDR + 0x324); /* CSI_D5 (SD1_DATA7) */
+
+       default:
+               break;
+       }
+}
+
+#include CYGHWR_MEMORY_LAYOUT_H
+
+typedef void code_fun(void);
+
+void board_program_new_stack(void *func)
+{
+    register CYG_ADDRESS stack_ptr asm("sp");
+    register CYG_ADDRESS old_stack asm("r4");
+    register code_fun *new_func asm("r0");
+    old_stack = stack_ptr;
+    stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
+    new_func = (code_fun*)func;
+    new_func();
+    stack_ptr = old_stack;
+}
+
+static void display_clock_src(void)
+{
+    diag_printf("\n");
+    diag_printf("Clock input is 24 MHz");
+}
+RedBoot_init(display_clock_src, RedBoot_INIT_LAST);
+
+// ------------------------------------------------------------------------
diff --git a/packages/hal/arm/mx25/3stack/v2_0/src/redboot_cmds.c b/packages/hal/arm/mx25/3stack/v2_0/src/redboot_cmds.c
new file mode 100644 (file)
index 0000000..7ad427a
--- /dev/null
@@ -0,0 +1,277 @@
+//==========================================================================
+//
+//      redboot_cmds.c
+//
+//      Board [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/fsl_board.h>          // Platform specific hardware definitions
+
+#ifdef CYGSEM_REDBOOT_FLASH_CONFIG
+#include <flash_config.h>
+
+#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE)
+#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE
+#endif
+
+RedBoot_config_option("Board specifics",
+                      brd_specs,
+                      ALWAYS_ENABLED,
+                      true,
+                      CONFIG_INT,
+                      0
+                     );
+#endif  //CYGSEM_REDBOOT_FLASH_CONFIG
+
+char HAL_PLATFORM_EXTRA[55] = " PASS 1.0 [x32 DDR]";
+
+static void runImg(int argc, char *argv[]);
+
+RedBoot_cmd("run",
+            "Run an image at a location with MMU off",
+            "[<virtual addr>]",
+            runImg
+           );
+
+void launchRunImg(unsigned long addr)
+{
+    asm volatile ("mov r12, r0;");
+    HAL_MMU_OFF();
+    asm volatile (
+                 "mov r0, #0;"
+                 "mov r1, r12;"
+                 "mov r11, #0;"
+                 "mov r12, #0;"
+                 "mrs r10, cpsr;"
+                 "bic r10, r10, #0xF0000000;"
+                 "msr cpsr_f, r10;"
+                 "mov pc, r1"
+                 );
+}
+
+extern unsigned long entry_address;
+
+static void runImg(int argc,char *argv[])
+{
+    unsigned int virt_addr, phys_addr;
+
+    // Default physical entry point for Symbian
+    if (entry_address == 0xFFFFFFFF)
+        virt_addr = 0x800000;
+    else
+    virt_addr = entry_address;
+
+    if (!scan_opts(argc,argv,1,0,0,(void*)&virt_addr,
+                   OPTION_ARG_TYPE_NUM, "virtual address"))
+        return;
+
+    if (entry_address != 0xFFFFFFFF)
+        diag_printf("load entry_address=0x%lx\n", entry_address);
+    HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr);
+
+    diag_printf("virt_addr=0x%x\n",virt_addr);
+    diag_printf("phys_addr=0x%x\n",phys_addr);
+
+    launchRunImg(phys_addr);
+}
+
+#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM)
+
+RedBoot_cmd("romupdate",
+            "Update Redboot with currently running image",
+            "",
+            romupdate
+           );
+
+extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
+extern int flash_erase(void *addr, int len, void **err_addr);
+extern char *flash_errmsg(int err);
+extern unsigned char *ram_end; //ram end is where the redboot starts FIXME: use PC value
+
+#ifdef CYGPKG_IO_FLASH
+void romupdate(int argc, char *argv[])
+{
+    void *err_addr, *base_addr;
+    int stat;
+
+    if (IS_FIS_FROM_MMC()) {
+        diag_printf("Updating ROM in MMC/SD flash\n");
+        base_addr = (void*)0;
+        /* Read the first 1K from the card */
+        mmc_data_read((cyg_uint32*)ram_end, 0x400, base_addr);
+        diag_printf("Programming Redboot to MMC/SD flash\n");
+        mmc_data_write((cyg_uint32*)ram_end, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, (cyg_uint32)base_addr);
+        return;
+    } else if (IS_FIS_FROM_NAND()) {
+        base_addr = (void*)MXC_NAND_BASE_DUMMY;
+        diag_printf("Updating ROM in NAND flash\n");
+    } else if (IS_FIS_FROM_NOR()) {
+        base_addr = (void*)BOARD_FLASH_START;
+        diag_printf("Updating ROM in NOR flash\n");
+    } else {
+        diag_printf("romupdate not supported\n");
+        diag_printf("Use \"factive [NOR|NAND|MMC]\" to select either NOR, NAND or MMC flash\n");
+        return;
+    }
+
+    // Erase area to be programmed
+    if ((stat = flash_erase((void *)base_addr,
+                            CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+                            (void **)&err_addr)) != 0) {
+        diag_printf("Can't erase region at %p: %s\n",
+                    err_addr, flash_errmsg(stat));
+        return;
+    }
+    // Now program it
+    if ((stat = flash_program((void *)base_addr, (void *)ram_end,
+                              CYGBLD_REDBOOT_MIN_IMAGE_SIZE,
+                              (void **)&err_addr)) != 0) {
+        diag_printf("Can't program region at %p: %s\n",
+                    err_addr, flash_errmsg(stat));
+    }
+}
+
+RedBoot_cmd("factive",
+            "Enable one flash media for Redboot",
+            "[NOR | NAND | MMC]",
+            factive
+           );
+
+void factive(int argc, char *argv[])
+{
+    unsigned long phys_addr;
+
+    if (argc != 2) {
+        diag_printf("Invalid factive cmd\n");
+        return;
+    }
+
+    if (strcasecmp(argv[1], "NOR") == 0) {
+#ifndef MXCFLASH_SELECT_NOR
+        diag_printf("Not supported\n");
+        return;
+#else
+        MXC_ASSERT_NOR_BOOT();
+#endif
+    } else if (strcasecmp(argv[1], "NAND") == 0) {
+#ifndef MXCFLASH_SELECT_NAND
+        diag_printf("Not supported\n");
+        return;
+#else
+        MXC_ASSERT_NAND_BOOT();
+#endif
+    } else if (strcasecmp(argv[1], "MMC") == 0) {
+#ifndef MXCFLASH_SELECT_MMC
+        diag_printf("Not supported\n");
+        return;
+#else
+        MXC_ASSERT_MMC_BOOT();
+#endif
+    } else {
+        diag_printf("Invalid command: %s\n", argv[1]);
+        return;
+    }
+    HAL_VIRT_TO_PHYS_ADDRESS(ram_end, phys_addr);
+
+    launchRunImg(phys_addr);
+}
+#endif //CYGPKG_IO_FLASH
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+static void setcorevol(int argc, char *argv[]);
+
+RedBoot_cmd("setcorevol",
+            "Set the core voltage. Setting is not checked against current core frequency.",
+            "[1.16 | 1.2 | 1.23 | 1.27 | 1.3 | 1.34 | 1.38 | 1.41 | 1.45 | 1.49 | 1.52 | 1.56 | 1.59 | 1.63 | 1.67 | 1.7]",
+            setcorevol
+           );
+
+static void setcorevol(int argc, char *argv[])
+{
+    unsigned int coreVol;
+
+    /* check if the number of args is OK. 1 arg expected. argc = 2 */
+    if(argc != 2) {
+        diag_printf("Invalid argument. Need to specify a voltage\n");
+        return;
+    }
+
+    /* check if the argument is valid. */
+    if (strcasecmp(argv[1], "1.16") == 0) {    /* -20% */
+        coreVol = 0x8;
+    } else if (strcasecmp(argv[1], "1.2") == 0) {
+        coreVol = 0x9;
+    } else if (strcasecmp(argv[1], "1.23") == 0) {
+        coreVol = 0xA;
+    } else if (strcasecmp(argv[1], "1.27") == 0) {
+        coreVol = 0xB;
+    } else if (strcasecmp(argv[1], "1.3") == 0) {
+        coreVol = 0xC;
+    } else if (strcasecmp(argv[1], "1.34") == 0) {
+        coreVol = 0xD;
+    } else if (strcasecmp(argv[1], "1.38") == 0) {
+        coreVol = 0xE;
+    } else if (strcasecmp(argv[1], "1.41") == 0) {
+        coreVol = 0xF;
+    } else if (strcasecmp(argv[1], "1.45") == 0) {     /* 0% */
+        coreVol = 0x0;
+    } else if (strcasecmp(argv[1], "1.49") == 0) {
+        coreVol = 0x1;
+    } else if (strcasecmp(argv[1], "1.52") == 0) {
+        coreVol = 0x2;
+    } else if (strcasecmp(argv[1], "1.56") == 0) {
+        coreVol = 0x3;
+    } else if (strcasecmp(argv[1], "1.59") == 0) {
+        coreVol = 0x4;
+    } else if (strcasecmp(argv[1], "1.63") == 0) {
+        coreVol = 0x5;
+    } else if (strcasecmp(argv[1], "1.67") == 0) {
+        coreVol = 0x6;
+    } else if (strcasecmp(argv[1], "1.7") == 0) {      /* +17.5% */
+        coreVol = 0x7;
+    } else {
+        diag_printf("Invalid argument. Type \"help setcorevol\" for valid settings\n");
+        return;
+    }
+
+    pmic_reg(0x08, coreVol << 1, 1);
+
+    return;
+}
diff --git a/packages/hal/arm/mx25/var/v2_0/cdl/hal_arm_soc.cdl b/packages/hal/arm/mx25/var/v2_0/cdl/hal_arm_soc.cdl
new file mode 100644 (file)
index 0000000..9a20820
--- /dev/null
@@ -0,0 +1,180 @@
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+# ====================================================================
+######DESCRIPTIONBEGIN####
+#
+# Author(s):      gthomas
+# Original data:  gthomas
+# Contributors:
+# Date:           2000-05-08
+#
+#####DESCRIPTIONEND####
+#
+# ====================================================================
+cdl_package CYGPKG_HAL_ARM_MX25 {
+    display       "Freescale SoC architecture"
+    parent        CYGPKG_HAL_ARM
+    hardware
+    include_dir   cyg/hal
+    define_header hal_arm_soc.h
+    description   "
+        This HAL variant package provides generic
+        support for the Freescale SoC. It is also
+        necessary to select a specific target platform HAL
+        package."
+
+    implements    CYGINT_HAL_ARM_ARCH_ARM9
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT
+
+    # Let the architectural HAL see this variant's interrupts file -
+    # the SoC has no variation between targets here.
+    define_proc {
+        puts $::cdl_header "#define CYGBLD_HAL_VAR_INTS_H <cyg/hal/hal_var_ints.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_ARM_VAR_IO_H"
+
+        puts $::cdl_header "#define CYGPRI_KERNEL_TESTS_DHRYSTONE_PASSES 1000000"
+    }
+
+    compile       soc_diag.c soc_misc.c
+    compile -library=libextras.a cmds.c
+
+    cdl_option CYGHWR_MX25_MDDR {
+        display       "mDDR/DDR2 support"
+        default_value 0
+        description   "
+           When this option is enabled, it indicates support
+           for Mobile DDR on the MX25 3stack CPU board.  mDDR
+           was used on TO1.0 boards.  Subsequent boards use
+           DDR2 memory."
+        define_proc {
+           puts $::cdl_system_header "#define MEMORY_MDDR_ENABLE"
+        }
+    }
+
+    cdl_option CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK {
+        display       "Processor clock rate"
+        active_if     { CYG_HAL_STARTUP == "ROM" }
+        flavor        data
+        legal_values  150000 200000
+        default_value { CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT ?
+                        CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK_OVERRIDE_DEFAULT : 150000}
+        description   "
+           The processor can run at various frequencies.
+           These values are expressed in KHz.  Note that there are
+           several steppings of the rated to run at different
+           maximum frequencies.  Check the specs to make sure that your
+           particular processor can run at the rate you select here."
+    }
+
+    # Real-time clock/counter specifics
+    cdl_component CYGNUM_HAL_RTC_CONSTANTS {
+        display       "Real-time clock constants"
+        flavor        none
+        no_define
+
+        cdl_option CYGNUM_HAL_RTC_NUMERATOR {
+            display       "Real-time clock numerator"
+            flavor        data
+            calculated    1000000000
+        }
+        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
+            display       "Real-time clock denominator"
+            flavor        data
+            default_value 100
+            description   "
+              This option selects the heartbeat rate for the real-time clock.
+              The rate is specified in ticks per second.  Change this value
+              with caution - too high and your system will become saturated
+              just handling clock interrupts, too low and some operations
+              such as thread scheduling may become sluggish."
+        }
+        cdl_option CYGNUM_HAL_RTC_PERIOD {
+            display       "Real-time clock period"
+            flavor        data
+            calculated    (3686400/CYGNUM_HAL_RTC_DENOMINATOR)        ;# Clock for OS Timer is 3.6864MHz
+        }
+    }
+
+    # Control over hardware layout.
+    cdl_interface     CYGHWR_HAL_ARM_SOC_UART1 {
+        display   "UART1 available as diagnostic/debug channel"
+        description "
+         The chip has multiple serial channels which may be
+          used for different things on different platforms.  This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_SOC_UART2 {
+        display   "UART2 available as diagnostic/debug channel"
+        description "
+         The chip has multiple serial channels which may be
+          used for different things on different platforms.  This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_SOC_UART3 {
+        display   "UART3 available as diagnostic/debug channel"
+        description "
+         The chip has multiple serial channels which may be
+          used for different things on different platforms.  This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_SOC_UART4 {
+        display   "UART4 available as diagnostic/debug channel"
+        description "
+         The chip has multiple serial channels which may be
+          used for different things on different platforms.  This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_SOC_UART5 {
+        display   "UART5 available as diagnostic/debug channel"
+        description "
+         The chip has multiple serial channels which may be
+          used for different things on different platforms.  This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_interface CYGINT_DEVS_ETH_FEC_REQUIRED {
+        display   "FEC ethernet driver required"
+    }
+
+    implements CYGINT_DEVS_ETH_FEC_REQUIRED
+}
diff --git a/packages/hal/arm/mx25/var/v2_0/include/hal_cache.h b/packages/hal/arm/mx25/var/v2_0/include/hal_cache.h
new file mode 100644 (file)
index 0000000..6d579ba
--- /dev/null
@@ -0,0 +1,376 @@
+#ifndef CYGONCE_HAL_CACHE_H
+#define CYGONCE_HAL_CACHE_H
+
+//=============================================================================
+//
+//      hal_cache.h
+//
+//      HAL cache control API
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/infra/cyg_type.h>
+#include <cyg/hal/hal_soc.h>         // Variant specific hardware definitions
+
+//-----------------------------------------------------------------------------
+// Cache dimensions
+
+// Data cache
+#define HAL_DCACHE_SIZE                 0x4000    // 16KB Size of data cache in bytes
+#define HAL_DCACHE_LINE_SIZE            32    // Size of a data cache line
+#define HAL_DCACHE_WAYS                 64    // Associativity of the cache
+
+// Instruction cache
+#define HAL_ICACHE_SIZE                 0x4000    // Size of cache in bytes
+#define HAL_ICACHE_LINE_SIZE            32    // Size of a cache line
+#define HAL_ICACHE_WAYS                 64    // Associativity of the cache
+
+#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
+#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
+
+# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
+# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
+# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
+//-----------------------------------------------------------------------------
+// Global control of data cache
+
+// Enable the data cache
+#define HAL_DCACHE_ENABLE()                                             \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mrc  p15,0,r1,c1,c0,0;"                                        \
+        "orr  r1,r1,#0x0007;" /* enable DCache (also ensures    */      \
+                              /* the MMU, alignment faults, and */      \
+        "mcr  p15,0,r1,c1,c0,0"                                         \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Disable the data cache
+#define HAL_DCACHE_DISABLE()    \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mov    r1,#0;"                                                 \
+        "mcr  p15,0,r1,c7,c6,0;" /* clear data cache */                  \
+        "mrc  p15,0,r1,c1,c0,0;"                                        \
+        "bic  r1,r1,#0x0004;" /* disable DCache  */                     \
+                              /* but not MMU and alignment faults */    \
+        "mcr  p15,0,r1,c1,c0,0"                                        \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Sync  data cache in range
+#define HAL_DCACHE_SYNC_RANGE(start, end)                               \
+CYG_MACRO_START                                                         \
+        asm volatile (                                                  \
+                "nop;"                                                  \
+                "nop;"                                                  \
+                "nop;"                                                  \
+                "nop;"                                                  \
+                "nop;"                                                  \
+                "nop;"                                                  \
+                "       bic %0, %0, %3;"                                \
+                "       add %1, %1, %3;"                                \
+                "       bic %1, %1, %3;"                                \
+                "1:     cmp %1, %0;"                                    \
+                "       mcrhi p15, 0, %0, c7, c14, 1;"                  \
+                "       addhi %0, %0, %2;"                              \
+                "       bhi     1b;"                                    \
+                "       mov %0, #0;"                                    \
+                "       mcr p15, 0, %0, c7, c10, 4"                     \
+                :                                                       \
+                :"r"(start), "r"(end),                          \
+                        "I"(HAL_DCACHE_LINE_SIZE),                      \
+                        "I"(HAL_DCACHE_LINE_SIZE-1)                     \
+        );                                                              \
+CYG_MACRO_END
+
+// Invalidate data cache in range
+#define HAL_DCACHE_INVALID_RANGE(start, end)                            \
+CYG_MACRO_START                                                         \
+        asm volatile (                                                  \
+                "       bic %0, %0, %3;"                                \
+                "       add %1, %1, %3;"                                \
+                "       bic %1, %1, %3;"                                \
+                "1:     mcr p15, 0, %0, c7, c6, 1;"                     \
+                "       add %0, %0, %2;"                                \
+                "       cmp %0, %1;"                                    \
+                "       blo 1b"                 \
+                :                                                       \
+                :"r"(start), "r"(end),                                  \
+                        "I"(HAL_DCACHE_LINE_SIZE),                      \
+                        "I"(HAL_DCACHE_LINE_SIZE-1)                     \
+        );                                                              \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_DCACHE_INVALIDATE_ALL()                                     \
+CYG_MACRO_START  /* this macro can discard dirty cache lines. */        \
+    asm volatile (                                                      \
+       "mov    r0,#0;"                                                 \
+        "mcr    p15,0,r0,c7,c6,0;" /* flush d-cache */                  \
+        "mcr    p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */                 \
+        :                                                               \
+        :                                                               \
+        : "r0","memory" /* clobber list */);                            \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// using ARM9's defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
+#if 1
+#define HAL_DCACHE_SYNC()                                               \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "nop; "                                                \
+        "nop; "                                                \
+        "nop; "                                                \
+        "nop; "                                                \
+        "nop; "                                                \
+        "nop; "                                                \
+        "1: "                                                \
+        "mrc p15, 0, r15, c7, c14, 3;"                                                \
+        "bne 1b;"                                                           \
+        "mov    r0, #0x0;"                                                    \
+        "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
+        :                                                               \
+        :                                                               \
+        : "r0" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+#else
+#define HAL_DCACHE_SYNC()                                               \
+CYG_MACRO_START                                                         \
+    cyg_uint32 _tmp1, _tmp2;                                            \
+    asm volatile (                                                      \
+        "mov    %0, #0;"                                                \
+        "1: "                                                           \
+        "mov    %1, #0;"                                                \
+        "2: "                                                           \
+        "orr    r0,%0,%1;"                                              \
+        "mcr    p15,0,r0,c7,c14,2;"  /* clean index in DCache */        \
+        "add    %1,%1,%2;"                                              \
+        "cmp    %1,%3;"                                                 \
+        "bne    2b;"                                                    \
+        "add    %0,%0,#0x04000000;"  /* get to next index */            \
+        "cmp    %0,#0;"                                                 \
+        "bne    1b;"                                                    \
+        "mov    r0, #0x0;"                                                    \
+        "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
+        : "=r" (_tmp1), "=r" (_tmp2)                                    \
+        : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP),            \
+          "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT)            \
+        : "r0" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+#endif
+
+// Query the state of the data cache
+#define HAL_DCACHE_IS_ENABLED(_state_)                                   \
+CYG_MACRO_START                                                          \
+    register int reg;                                                    \
+    asm volatile (  \
+        "nop; "                                                \
+        "nop; "                                                \
+        "nop; "                                                \
+        "nop; "                                                \
+        "nop; "                                                \
+        "mrc  p15,0,%0,c1,c0,0;"                               \
+                  : "=r"(reg)                                            \
+                  :                                                      \
+        );                                                               \
+    (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */           \
+CYG_MACRO_END
+
+// Purge contents of data cache
+//#define HAL_DCACHE_PURGE_ALL() -- not used
+
+// Set the data cache refill burst size
+//#define HAL_DCACHE_BURST_SIZE(_size_)
+
+// Set the data cache write mode
+//#define HAL_DCACHE_WRITE_MODE( _mode_ )
+
+//#define HAL_DCACHE_WRITETHRU_MODE       0
+//#define HAL_DCACHE_WRITEBACK_MODE       1
+
+// Load the contents of the given address range into the data cache
+// and then lock the cache so that it stays there.
+//#define HAL_DCACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_DCACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_DCACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Data cache line control
+
+// Allocate cache lines for the given address range without reading its
+// contents from memory.
+//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory and invalidate the cache entries
+// for the given address range.
+//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
+
+// Write dirty cache lines to memory for the given address range.
+//#define HAL_DCACHE_STORE( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of reading
+// from it later.
+//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
+
+// Preread the given range into the cache with the intention of writing
+// to it later.
+//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
+
+// Allocate and zero the cache lines associated with the given range.
+//#define HAL_DCACHE_ZERO( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+// Global control of Instruction cache
+
+// Enable the instruction cache
+#define HAL_ICACHE_ENABLE()                                             \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mrc  p15,0,r1,c1,c0,0;"                                        \
+        "orr  r1,r1,#0x1000;"                                           \
+        "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */       \
+                              /* that MMU and alignment faults */       \
+                              /* are enabled)                  */       \
+        "mcr  p15,0,r1,c1,c0,0"                                         \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Query the state of the instruction cache
+#define HAL_ICACHE_IS_ENABLED(_state_)                                   \
+CYG_MACRO_START                                                          \
+    register cyg_uint32 reg;                                             \
+    asm volatile ("mrc  p15,0,%0,c1,c0,0"                                \
+                  : "=r"(reg)                                            \
+                  :                                                      \
+        );                                                               \
+    (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */     \
+CYG_MACRO_END
+
+// Disable the instruction cache
+#define HAL_ICACHE_DISABLE()                                            \
+CYG_MACRO_START                                                         \
+    asm volatile (                                                      \
+        "mrc    p15,0,r1,c1,c0,0;"                                      \
+        "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
+        "mcr    p15,0,r1,c1,c0,0;"                                      \
+        "mov    r1,#0;"                                                 \
+        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
+        "nop;" /* next few instructions may be via cache    */          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop"                                                           \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Invalidate the entire cache
+#define HAL_ICACHE_INVALIDATE_ALL()                                     \
+CYG_MACRO_START                                                         \
+    /* this macro can discard dirty cache lines (N/A for ICache) */     \
+    asm volatile (                                                      \
+        "mov    r1,#0;"                                                 \
+        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
+        "mcr    p15,0,r1,c8,c5,0;"  /* flush ITLB only */               \
+        "nop;" /* next few instructions may be via cache    */          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        "nop;"                                                          \
+        :                                                               \
+        :                                                               \
+        : "r1" /* Clobber list */                                       \
+        );                                                              \
+CYG_MACRO_END
+
+// Synchronize the contents of the cache with memory.
+// (which includes flushing out pending writes)
+#define HAL_ICACHE_SYNC()                                       \
+CYG_MACRO_START                                                 \
+    HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
+    HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
+CYG_MACRO_END
+
+#else
+
+
+// Set the instruction cache refill burst size
+//#define HAL_ICACHE_BURST_SIZE(_size_)
+
+// Load the contents of the given address range into the instruction cache
+// and then lock the cache so that it stays there.
+//#define HAL_ICACHE_LOCK(_base_, _size_)
+
+// Undo a previous lock operation
+//#define HAL_ICACHE_UNLOCK(_base_, _size_)
+
+// Unlock entire cache
+//#define HAL_ICACHE_UNLOCK_ALL()
+
+//-----------------------------------------------------------------------------
+// Instruction cache line control
+
+// Invalidate cache lines in the given range without writing to memory.
+//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
+
+//-----------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_CACHE_H
+// End of hal_cache.h
diff --git a/packages/hal/arm/mx25/var/v2_0/include/hal_diag.h b/packages/hal/arm/mx25/var/v2_0/include/hal_diag.h
new file mode 100644 (file)
index 0000000..e491908
--- /dev/null
@@ -0,0 +1,83 @@
+#ifndef CYGONCE_HAL_DIAG_H
+#define CYGONCE_HAL_DIAG_H
+
+/*=============================================================================
+//
+//      hal_diag.h
+//
+//      HAL Support for Kernel Diagnostic Routines
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+
+#include <cyg/infra/cyg_type.h>
+
+#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
+
+#include <cyg/hal/hal_if.h>
+
+#define HAL_DIAG_INIT() hal_if_diag_init()
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
+#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
+
+#else // everything by steam
+
+/*---------------------------------------------------------------------------*/
+/* functions implemented in hal_diag.c                                       */
+
+externC void hal_diag_init(void);
+externC void hal_diag_write_char(char c);
+externC void hal_diag_read_char(char *c);
+
+/*---------------------------------------------------------------------------*/
+
+#define HAL_DIAG_INIT() hal_diag_init()
+
+#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
+
+#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
+
+#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+// LED
+
+externC void hal_diag_led(int n);
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_diag.h                                                         */
+#endif /* CYGONCE_HAL_DIAG_H */
diff --git a/packages/hal/arm/mx25/var/v2_0/include/hal_mm.h b/packages/hal/arm/mx25/var/v2_0/include/hal_mm.h
new file mode 100644 (file)
index 0000000..1970034
--- /dev/null
@@ -0,0 +1,176 @@
+#ifndef CYGONCE_HAL_MM_H
+#define CYGONCE_HAL_MM_H
+
+//=============================================================================
+//
+//      hal_mm.h
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+// -------------------------------------------------------------------------
+// MMU initialization:
+//
+// These structures are laid down in memory to define the translation
+// table.
+//
+
+/*
+ * Translation Table Base Bit Masks
+ */
+#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
+
+/*
+ * Domain Access Control Bit Masks
+ */
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
+
+struct ARM_MMU_FIRST_LEVEL_FAULT {
+        unsigned int id : 2;
+        unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
+
+struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
+        unsigned int id : 2;
+        unsigned int imp : 2;
+        unsigned int domain : 4;
+        unsigned int sbz : 1;
+        unsigned int base_address : 23;
+};
+
+#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
+
+struct ARM_MMU_FIRST_LEVEL_SECTION {
+        unsigned int id : 2;
+        unsigned int b : 1;
+        unsigned int c : 1;
+        unsigned int imp : 1;
+        unsigned int domain : 4;
+        unsigned int sbz0 : 1;
+        unsigned int ap : 2;
+        unsigned int sbz1 : 8;
+        unsigned int base_address : 12;
+};
+
+#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
+
+struct ARM_MMU_FIRST_LEVEL_RESERVED {
+        unsigned int id : 2;
+        unsigned int sbz : 30;
+};
+
+#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
+
+#define ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, table_index) \
+        (unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
+
+#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
+
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,              \
+                        cacheable, bufferable, perm)                      \
+    CYG_MACRO_START                                                       \
+        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;               \
+                                                                          \
+        desc.word = 0;                                                    \
+        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                 \
+        desc.section.domain = 0;                                          \
+        desc.section.c = (cacheable);                                     \
+        desc.section.b = (bufferable);                                    \
+        desc.section.ap = (perm);                                         \
+        desc.section.base_address = (actual_base);                        \
+        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+                            = desc.word;                                  \
+    CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access)                 \
+      {                                                            \
+        int i; int j = abase; int k = vbase;                              \
+        for (i = size; i > 0 ; i--,j++,k++) {                             \
+        ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);      \
+      }                                                            \
+    }
+
+union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
+        unsigned long word;
+        struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+        struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+        struct ARM_MMU_FIRST_LEVEL_SECTION section;
+        struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+};
+
+#define ARM_UNCACHEABLE                         0
+#define ARM_CACHEABLE                           1
+#define ARM_UNBUFFERABLE                        0
+#define ARM_BUFFERABLE                          1
+
+#define ARM_ACCESS_PERM_NONE_NONE               0
+#define ARM_ACCESS_PERM_RO_NONE                 0
+#define ARM_ACCESS_PERM_RO_RO                   0
+#define ARM_ACCESS_PERM_RW_NONE                 1
+#define ARM_ACCESS_PERM_RW_RO                   2
+#define ARM_ACCESS_PERM_RW_RW                   3
+
+/*
+ * Initialization for the Domain Access Control Register
+ */
+#define ARM_ACCESS_DACR_DEFAULT      (          \
+        ARM_ACCESS_TYPE_MANAGER(0)    |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(1)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(2)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(3)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(4)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(5)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(6)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(7)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(8)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(9)  |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(10) |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(11) |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(12) |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(13) |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(14) |         \
+        ARM_ACCESS_TYPE_NO_ACCESS(15) )
+
+// ------------------------------------------------------------------------
+#endif // ifndef CYGONCE_HAL_MM_H
+// End of hal_mm.h
+
+
+
+
+
diff --git a/packages/hal/arm/mx25/var/v2_0/include/hal_soc.h b/packages/hal/arm/mx25/var/v2_0/include/hal_soc.h
new file mode 100644 (file)
index 0000000..cc95a95
--- /dev/null
@@ -0,0 +1,514 @@
+//==========================================================================
+//
+//      hal_soc.h
+//
+//      SoC chip definitions
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+// Copyright (C) 2002 Gary Thomas
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#ifndef __HAL_SOC_H__
+#define __HAL_SOC_H__
+
+#ifdef __ASSEMBLER__
+
+#define REG8_VAL(a)          (a)
+#define REG16_VAL(a)         (a)
+#define REG32_VAL(a)         (a)
+
+#define REG8_PTR(a)          (a)
+#define REG16_PTR(a)         (a)
+#define REG32_PTR(a)         (a)
+
+#else /* __ASSEMBLER__ */
+
+extern char HAL_PLATFORM_EXTRA[];
+#define REG8_VAL(a)          ((unsigned char)(a))
+#define REG16_VAL(a)         ((unsigned short)(a))
+#define REG32_VAL(a)         ((unsigned int)(a))
+
+#define REG8_PTR(a)          ((volatile unsigned char *)(a))
+#define REG16_PTR(a)         ((volatile unsigned short *)(a))
+#define REG32_PTR(a)         ((volatile unsigned int *)(a))
+#define readb(a)             (*(volatile unsigned char *)(a))
+#define readw(a)             (*(volatile unsigned short *)(a))
+#define readl(a)             (*(volatile unsigned int *)(a))
+#define writeb(v,a)          (*(volatile unsigned char *)(a) = (v))
+#define writew(v,a)          (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a)          (*(volatile unsigned int *)(a) = (v))
+
+#endif /* __ASSEMBLER__ */
+
+/*
+ * Default Memory Layout Definitions
+ */
+
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_CTRL_BASE_ADDR    AIPS1_BASE_ADDR
+#define MAX_BASE_ADDR           0x43F04000
+#define CLKCTL_BASE_ADDR        0x43F08000
+#define ETB_SLOT4_BASE_ADDR     0x43F0C000
+#define ETB_SLOT5_BASE_ADDR     0x43F1000l
+#define ECT_CTIO_BASE_ADDR      0x43F18000
+#define I2C_BASE_ADDR           0x43F80000
+#define I2C3_BASE_ADDR          0x43F84000
+#define CAN1_BASE_ADDR          0x43F88000
+#define CAN2_BASE_ADDR          0x43F8C000
+#define UART1_BASE_ADDR         0x43F90000
+#define UART2_BASE_ADDR         0x43F94000
+#define I2C2_BASE_ADDR          0x43F98000
+#define OWIRE_BASE_ADDR         0x43F9C000
+#define CSPI1_BASE_ADDR         0x43FA4000
+#define KPP_BASE_ADDR           0x43FA8000
+#define IOMUXC_BASE_ADDR        0x43FAC000
+#define AUDMUX_BASE_ADDR        0x43FB0000
+#define ECT_IP1_BASE_ADDR       0x43FB8000
+#define ECT_IP2_BASE_ADDR       0x43FBC000
+
+/*
+ * SPBA
+ */
+#define SPBA_BASE_ADDR          0x50000000
+#define CSPI3_BASE_ADDR         0x50040000
+#define UART4_BASE_ADDR         0x50008000
+#define UART3_BASE_ADDR         0x5000C000
+#define CSPI2_BASE_ADDR         0x50010000
+#define SSI2_BASE_ADDR          0x50014000
+#define ESAI_BASE_ADDR          0x50018000
+#define ATA_DMA_BASE_ADDR       0x50020000
+#define SIM1_BASE_ADDR          0x50024000
+#define SIM2_BASE_ADDR          0x50028000
+#define UART5_BASE_ADDR         0x5002C000
+#define TSC_BASE_ADDR           0x50030000
+#define SSI1_BASE_ADDR          0x50034000
+#define FEC_BASE_ADDR          0x50038000
+#define SOC_FEC_BASE           FEC_BASE_ADDR
+#define SPBA_CTRL_BASE_ADDR     0x5003C000
+
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_CTRL_BASE_ADDR    AIPS2_BASE_ADDR
+#define CCM_BASE_ADDR           0x53F80000
+#define GPT4_BASE_ADDR          0x53F84000
+#define GPT3_BASE_ADDR          0x53F88000
+#define GPT2_BASE_ADDR          0x53F8C000
+#define GPT1_BASE_ADDR          0x53F90000
+#define EPIT1_BASE_ADDR         0x53F94000
+#define EPIT2_BASE_ADDR         0x53F98000
+#define GPIO4_BASE_ADDR         0x53F9C000
+#define PWM2_BASE_ADDR          0x53FA0000
+#define GPIO3_BASE_ADDR         0x53FA4000
+#define PWM3_BASE_ADDR          0x53FA8000
+#define SCC_BASE_ADDR           0x53FAC000
+#define SCM_BASE_ADDR           0x53FAE000
+#define SMN_BASE_ADDR           0x53FAF000
+#define RNGD_BASE_ADDR          0x53FB0000
+#define MMC_SDHC1_BASE_ADDR     0x53FB4000
+#define MMC_SDHC2_BASE_ADDR     0x53FB8000
+#define ESDHC1_REG_BASE         MMC_SDHC1_BASE_ADDR
+#define LCDC_BASE_ADDR          0x53FBC000
+#define SLCDC_BASE_ADDR         0x53FC0000
+#define PWM4_BASE_ADDR          0x53FC8000
+#define GPIO1_BASE_ADDR         0x53FCC000
+#define GPIO2_BASE_ADDR         0x53FD0000
+#define SDMA_BASE_ADDR          0x53FD4000
+#define WDOG_BASE_ADDR          0x53FDC000
+#define PWM1_BASE_ADDR          0x53FE0000
+#define RTIC_BASE_ADDR          0x53FEC000
+#define IIM_BASE_ADDR           0x53FF0000
+#define USB_BASE_ADDR           0x53FF4000
+#define CSI_BASE_ADDR           0x53FF8000
+#define DRYICE_BASE_ADDR        0x53FFC000
+
+/*
+ * ROMPATCH and AVIC
+ */
+#define ROMPATCH_BASE_ADDR      0x60000000
+#define ASIC_BASE_ADDR          0x68000000
+
+#define RAM_BASE_ADDR           0x78000000
+
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define EXT_MEM_CTRL_BASE       0xB8000000
+#define ESDCTL_BASE_ADDR        0xB8001000
+#define WEIM_BASE_ADDR          0xB8002000
+#define WEIM_CTRL_CS0           WEIM_BASE_ADDR
+#define WEIM_CTRL_CS1           (WEIM_BASE_ADDR + 0x10)
+#define WEIM_CTRL_CS2           (WEIM_BASE_ADDR + 0x20)
+#define WEIM_CTRL_CS3           (WEIM_BASE_ADDR + 0x30)
+#define WEIM_CTRL_CS4           (WEIM_BASE_ADDR + 0x40)
+#define WEIM_CTRL_CS5           (WEIM_BASE_ADDR + 0x50)
+#define M3IF_BASE               0xB8003000
+#define EMI_BASE               0xB8004000
+
+#define NFC_BASE                0xBB000000
+/*
+ * Memory regions and CS
+ */
+#define CSD0_BASE_ADDR          0x80000000
+#define CSD1_BASE_ADDR          0x90000000
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+#define CS4_BASE_ADDR           0xB4000000
+#define CS5_BASE_ADDR           0xB6000000
+
+/*
+ * IRQ Controller Register Definitions.
+ */
+#define ASIC_NIMASK                     REG32_PTR(ASIC_BASE_ADDR + (0x04))
+#define ASIC_INTTYPEH                   REG32_PTR(ASIC_BASE_ADDR + (0x18))
+#define ASIC_INTTYPEL                   REG32_PTR(ASIC_BASE_ADDR + (0x1C))
+
+/* CCM */
+#define CLKCTL_MPCTL                    0x00
+#define CLKCTL_UPCTL                    0x04
+#define CLKCTL_CCTL                     0x08
+#define CLKCTL_CGR0                     0x0C
+#define CLKCTL_CGR1                     0x10
+#define CLKCTL_CGR2                     0x14
+#define CLKCTL_PCDR0                    0x18
+#define CLKCTL_PCDR1                    0x1C
+#define CLKCTL_PCDR2                    0x20
+#define CLKCTL_PCDR3                    0x24
+#define CLKCTL_RCSR                     0x28
+#define CLKCTL_CRDR                     0x2C
+#define CLKCTL_DCVR0                    0x30
+#define CLKCTL_DCVR1                    0x34
+#define CLKCTL_DCVR2                    0x38
+#define CLKCTL_DCVR3                    0x3C
+#define CLKCTL_LTR0                     0x40
+#define CLKCTL_LTR1                     0x44
+#define CLKCTL_LTR2                     0x48
+#define CLKCTL_LTR3                     0x4C
+#define CLKCTL_LTBR0                    0x50
+#define CLKCTL_LTBR1                    0x54
+#define CLKCTL_PCMR0                    0x58
+#define CLKCTL_PCMR1                    0x5C
+#define CLKCTL_PCMR2                    0x60
+#define CLKCTL_MCR                      0x64
+#define CLKCTL_LPIMR0                   0x68
+#define CLKCTL_LPIMR1                   0x6C
+
+#define CRM_CCTL_ARM_SRC               (1 << 14)
+#define CRM_CCTL_AHB_OFFSET            28
+
+
+#define FREQ_24MHZ                      24000000
+#define PLL_REF_CLK                     FREQ_24MHZ
+
+/*
+ * FIXME-DALE - Constants verified up to this point.
+ *              Offsets and derived constants below should be confirmed.
+ */
+
+#define CLKMODE_AUTO           0
+#define CLKMODE_CONSUMER       1
+
+/* WEIM - CS0 */
+#define CSCRU                           0x00
+#define CSCRL                           0x04
+#define CSCRA                           0x08
+
+#define CHIP_REV_1_0            0x0      /* PASS 1.0 */
+#define CHIP_REV_1_1            0x1      /* PASS 1.1 */
+#define CHIP_REV_2_0            0x2      /* PASS 2.0 */
+#define CHIP_LATEST             CHIP_REV_1_1
+
+#define IIM_STAT_OFF            0x00
+#define IIM_STAT_BUSY           (1 << 7)
+#define IIM_STAT_PRGD           (1 << 1)
+#define IIM_STAT_SNSD           (1 << 0)
+#define IIM_STATM_OFF           0x04
+#define IIM_ERR_OFF             0x08
+#define IIM_ERR_PRGE            (1 << 7)
+#define IIM_ERR_WPE             (1 << 6)
+#define IIM_ERR_OPE             (1 << 5)
+#define IIM_ERR_RPE             (1 << 4)
+#define IIM_ERR_WLRE            (1 << 3)
+#define IIM_ERR_SNSE            (1 << 2)
+#define IIM_ERR_PARITYE         (1 << 1)
+#define IIM_EMASK_OFF           0x0C
+#define IIM_FCTL_OFF            0x10
+#define IIM_UA_OFF              0x14
+#define IIM_LA_OFF              0x18
+#define IIM_SDAT_OFF            0x1C
+#define IIM_PREV_OFF            0x20
+#define IIM_SREV_OFF            0x24
+#define IIM_PREG_P_OFF          0x28
+#define IIM_SCS0_OFF            0x2C
+#define IIM_SCS1_OFF            0x30
+#define IIM_SCS2_OFF            0x34
+#define IIM_SCS3_OFF            0x38
+
+#define EPIT_BASE_ADDR          EPIT1_BASE_ADDR
+#define EPITCR                  0x00
+#define EPITSR                  0x04
+#define EPITLR                  0x08
+#define EPITCMPR                0x0C
+#define EPITCNR                 0x10
+
+#define GPT_BASE_ADDR           GPT1_BASE_ADDR
+#define GPTCR                   0x00
+#define GPTPR                   0x04
+#define GPTSR                   0x08
+#define GPTIR                   0x0C
+#define GPTOCR1                 0x10
+#define GPTOCR2                 0x14
+#define GPTOCR3                 0x18
+#define GPTICR1                 0x1C
+#define GPTICR2                 0x20
+#define GPTCNT                  0x24
+
+/* ESDCTL */
+#define ESDCTL_ESDCTL0                  0x00
+#define ESDCTL_ESDCFG0                  0x04
+#define ESDCTL_ESDCTL1                  0x08
+#define ESDCTL_ESDCFG1                  0x0C
+#define ESDCTL_ESDMISC                  0x10
+
+/* DRYICE */
+#define DRYICE_DTCMR           0x00
+#define DRYICE_DTCLR           0x04
+#define DRYICE_DCAMR           0x08
+#define DRYICE_DCALR           0x0C
+#define DRYICE_DCR             0x10
+#define DRYICE_DSR             0x14
+#define DRYICE_DIER            0x18
+#define DRYICE_DMCR            0x1C
+#define DRYICE_DKSR            0x20
+#define DRYICE_DKCR            0x24
+#define DRYICE_DTCR            0x28
+#define DRYICE_DACR            0x2C
+#define DRYICE_DGPR            0x3C
+#define DRYICE_DPKR0           0x40
+#define DRYICE_DPKR1           0x44
+#define DRYICE_DPKR2           0x48
+#define DRYICE_DPKR3           0x4C
+#define DRYICE_DPKR4           0x50
+#define DRYICE_DPKR5           0x54
+#define DRYICE_DPKR6           0x58
+#define DRYICE_DPKR7           0x5C
+#define DRYICE_DRKR0           0x60
+#define DRYICE_DRKR1           0x64
+#define DRYICE_DRKR2           0x68
+#define DRYICE_DRKR3           0x6C
+#define DRYICE_DRKR4           0x70
+#define DRYICE_DRKR5           0x74
+#define DRYICE_DRKR6           0x78
+#define DRYICE_DRKR7           0x7C
+
+/* GPIO */
+#define GPIO_DR                 0x00
+#define GPIO_GDIR               0x04
+#define GPIO_PSR0               0x08
+#define GPIO_ICR1               0x0C
+#define GPIO_ICR2               0x10
+#define GPIO_IMR                0x14
+#define GPIO_ISR                0x18
+#define GPIO_EDGE_SEL           0x1C
+
+
+#if (PLL_REF_CLK != 24000000)
+#error Wrong PLL reference clock! The following macros will not work.
+#endif
+
+/* Assuming 24MHz input clock */
+/*                            PD             MFD              MFI          MFN */
+#define MPCTL_PARAM_399     (((1-1) << 26) + ((16-1) << 16) + (8  << 10) + (5 << 0))
+#define MPCTL_PARAM_532     ((1 << 31) + ((1-1) << 26) + ((12-1) << 16) + (11  << 10) + (1 << 0))
+#define MPCTL_PARAM_665     (((1-1) << 26) + ((48-1) << 16) + (13  << 10) + (41 << 0))
+
+/* UPCTL                      PD             MFD              MFI          MFN */
+#define UPCTL_PARAM_300     (((1-1) << 26) + ((4-1) << 16) + (6  << 10) + (1  << 0))
+
+#define NFC_V1_1
+
+#define NAND_REG_BASE                   (NFC_BASE + 0x1E00)
+#define NFC_BUFSIZE_REG_OFF             (0 + 0x00)
+#define RAM_BUFFER_ADDRESS_REG_OFF      (0 + 0x04)
+#define NAND_FLASH_ADD_REG_OFF          (0 + 0x06)
+#define NAND_FLASH_CMD_REG_OFF          (0 + 0x08)
+#define NFC_CONFIGURATION_REG_OFF       (0 + 0x0A)
+#define ECC_STATUS_RESULT_REG_OFF       (0 + 0x0C)
+#define ECC_RSLT_MAIN_AREA_REG_OFF      (0 + 0x0E)
+#define ECC_RSLT_SPARE_AREA_REG_OFF     (0 + 0x10)
+#define NF_WR_PROT_REG_OFF              (0 + 0x12)
+#define NAND_FLASH_WR_PR_ST_REG_OFF     (0 + 0x18)
+#define NAND_FLASH_CONFIG1_REG_OFF      (0 + 0x1A)
+#define NAND_FLASH_CONFIG2_REG_OFF      (0 + 0x1C)
+#define UNLOCK_START_BLK_ADD_REG_OFF    (0 + 0x20)
+#define UNLOCK_END_BLK_ADD_REG_OFF      (0 + 0x22)
+#define RAM_BUFFER_ADDRESS_RBA_3        0x3
+#define NFC_BUFSIZE_1KB                 0x0
+#define NFC_BUFSIZE_2KB                 0x1
+#define NFC_CONFIGURATION_UNLOCKED      0x2
+#define ECC_STATUS_RESULT_NO_ERR        0x0
+#define ECC_STATUS_RESULT_1BIT_ERR      0x1
+#define ECC_STATUS_RESULT_2BIT_ERR      0x2
+#define NF_WR_PROT_UNLOCK               0x4
+#define NAND_FLASH_CONFIG1_FORCE_CE     (1 << 7)
+#define NAND_FLASH_CONFIG1_RST          (1 << 6)
+#define NAND_FLASH_CONFIG1_BIG          (1 << 5)
+#define NAND_FLASH_CONFIG1_INT_MSK      (1 << 4)
+#define NAND_FLASH_CONFIG1_ECC_EN       (1 << 3)
+#define NAND_FLASH_CONFIG1_SP_EN        (1 << 2)
+#define NAND_FLASH_CONFIG2_INT_DONE     (1 << 15)
+#define NAND_FLASH_CONFIG2_FDO_PAGE     (0 << 3)
+#define NAND_FLASH_CONFIG2_FDO_ID       (2 << 3)
+#define NAND_FLASH_CONFIG2_FDO_STATUS   (4 << 3)
+#define NAND_FLASH_CONFIG2_FDI_EN       (1 << 2)
+#define NAND_FLASH_CONFIG2_FADD_EN      (1 << 1)
+#define NAND_FLASH_CONFIG2_FCMD_EN      (1 << 0)
+#define FDO_PAGE_SPARE_VAL              0x8
+#define NAND_BUF_NUM   8
+
+#define MXC_NAND_BASE_DUMMY             0x00000000
+#define MXC_MMC_BASE_DUMMY              0x00000000
+#define NOR_FLASH_BOOT                  0
+#define NAND_FLASH_BOOT                 0x10000000
+#define SDRAM_NON_FLASH_BOOT            0x20000000
+#define MMC_FLASH_BOOT                  0x40000000
+#define MXCBOOT_FLAG_REG                (CSI_BASE_ADDR + 0x28) // use CSIDMASA-FB1
+#define MXCFIS_NOTHING                  0x00000000
+#define MXCFIS_NAND                     0x10000000
+#define MXCFIS_NOR                      0x20000000
+#define MXCFIS_MMC                      0x40000000
+#define MXCFIS_FLAG_REG                 (CSI_BASE_ADDR + 0x2C) // use CSIDMASA-FB2
+
+#define IS_BOOTING_FROM_NAND()          (readl(MXCBOOT_FLAG_REG) == NAND_FLASH_BOOT)
+#define IS_BOOTING_FROM_NOR()           (readl(MXCBOOT_FLAG_REG) == NOR_FLASH_BOOT)
+#define IS_BOOTING_FROM_SDRAM()         (readl(MXCBOOT_FLAG_REG) == SDRAM_NON_FLASH_BOOT)
+#define IS_BOOTING_FROM_MMC()           (readl(MXCBOOT_FLAG_REG) == MMC_FLASH_BOOT)
+
+#ifndef MXCFLASH_SELECT_NAND
+#define IS_FIS_FROM_NAND()              0
+#else
+#define IS_FIS_FROM_NAND()              (readl(MXCFIS_FLAG_REG) == MXCFIS_NAND)
+#endif
+
+#ifndef MXCFLASH_SELECT_MMC
+#define IS_FIS_FROM_MMC()               0
+#else
+#define IS_FIS_FROM_MMC()               (readl(MXCFIS_FLAG_REG) == MXCFIS_MMC)
+#endif
+
+#ifndef MXCFLASH_SELECT_NOR
+#define IS_FIS_FROM_NOR()               0
+#else
+#define IS_FIS_FROM_NOR()               (readl(MXCFIS_FLAG_REG) == MXCFIS_NOR)
+#endif
+
+#define MXC_ASSERT_NOR_BOOT()           writel(MXCFIS_NOR, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_NAND_BOOT()          writel(MXCFIS_NAND, MXCFIS_FLAG_REG)
+#define MXC_ASSERT_MMC_BOOT()           writel(MXCFIS_MMC, MXCFIS_FLAG_REG)
+
+/*
+ * This macro is used to get certain bit field from a number
+ */
+#define MXC_GET_FIELD(val, len, sh)          ((val >> sh) & ((1 << len) - 1))
+
+/*
+ * This macro is used to set certain bit field inside a number
+ */
+#define MXC_SET_FIELD(val, len, sh, nval)    ((val & ~(((1 << len) - 1) << sh)) | (nval << sh))
+
+#define UART_WIDTH_32         /* internal UART is 32bit access only */
+
+#if !defined(__ASSEMBLER__)
+void cyg_hal_plf_serial_init(void);
+void cyg_hal_plf_serial_stop(void);
+void hal_delay_us(unsigned int usecs);
+#define HAL_DELAY_US(n)     hal_delay_us(n)
+
+enum plls {
+        MCU_PLL = CCM_BASE_ADDR + CLKCTL_MPCTL,
+        USB_PLL = CCM_BASE_ADDR + CLKCTL_UPCTL,
+};
+
+enum main_clocks {
+        CPU_CLK,
+        AHB_CLK,
+        IPG_CLK,
+        IPG_PER_CLK, // not there on MX25 but simulated for compatibility
+};
+
+enum peri_clocks {
+        PER_UART_CLK,
+        SPI1_CLK = CSPI1_BASE_ADDR,
+        SPI2_CLK = CSPI2_BASE_ADDR,
+};
+
+unsigned int pll_clock(enum plls pll);
+
+unsigned int get_main_clock(enum main_clocks clk);
+
+unsigned int get_peri_clock(enum peri_clocks clk);
+
+typedef unsigned int nfc_setup_func_t(unsigned int, unsigned int, unsigned int, unsigned int);
+
+#endif //#if !defined(__ASSEMBLER__)
+
+#define HAL_MMU_OFF()                                               \
+CYG_MACRO_START                                                     \
+    asm volatile (                                                  \
+        "1: "                                                       \
+        "mrc p15, 0, r15, c7, c14, 3;"   /*test clean and inval*/   \
+        "bne 1b;"                                                   \
+        "mov r0, #0;"                                               \
+        "mcr p15,0,r0,c7,c10,4;"   /*drain write buffer*/           \
+        "mcr p15,0,r0,c7,c5,0;" /* invalidate I cache */            \
+        "mrc p15,0,r0,c1,c0,0;" /* read c1 */                       \
+        "bic r0,r0,#0x7;" /* disable DCache and MMU */              \
+        "bic r0,r0,#0x1000;" /* disable ICache */                   \
+        "mcr p15,0,r0,c1,c0,0;" /*  */                              \
+        "nop;" /* flush i+d-TLBs */                                 \
+        "nop;" /* flush i+d-TLBs */                                 \
+        "nop;" /* flush i+d-TLBs */                                 \
+        :                                                           \
+        :                                                           \
+        : "r0","memory" /* clobber list */);                        \
+CYG_MACRO_END
+
+#endif /* __HAL_SOC_H__ */
diff --git a/packages/hal/arm/mx25/var/v2_0/include/hal_var_ints.h b/packages/hal/arm/mx25/var/v2_0/include/hal_var_ints.h
new file mode 100644 (file)
index 0000000..98bbe3b
--- /dev/null
@@ -0,0 +1,127 @@
+#ifndef CYGONCE_HAL_VAR_INTS_H
+#define CYGONCE_HAL_VAR_INTS_H
+//==========================================================================
+//
+//      hal_var_ints.h
+//
+//      HAL Interrupt and clock support
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/hal/hal_soc.h>         // registers
+
+#define CYGNUM_HAL_INTERRUPT_GPIO0   0
+#define CYGNUM_HAL_INTERRUPT_GPIO1   1
+#define CYGNUM_HAL_INTERRUPT_GPIO2   2
+#define CYGNUM_HAL_INTERRUPT_GPIO3   3
+#define CYGNUM_HAL_INTERRUPT_GPIO4   4
+#define CYGNUM_HAL_INTERRUPT_GPIO5   5
+#define CYGNUM_HAL_INTERRUPT_GPIO6   6
+#define CYGNUM_HAL_INTERRUPT_GPIO7   7
+#define CYGNUM_HAL_INTERRUPT_GPIO8   8
+#define CYGNUM_HAL_INTERRUPT_GPIO9   9
+#define CYGNUM_HAL_INTERRUPT_GPIO10  10
+#define CYGNUM_HAL_INTERRUPT_GPIO    11  // Don't use directly!
+#define CYGNUM_HAL_INTERRUPT_LCD     12
+#define CYGNUM_HAL_INTERRUPT_UDC     13
+#define CYGNUM_HAL_INTERRUPT_UART1   15
+#define CYGNUM_HAL_INTERRUPT_UART2   16
+#define CYGNUM_HAL_INTERRUPT_UART3   17
+#define CYGNUM_HAL_INTERRUPT_UART4   17
+#define CYGNUM_HAL_INTERRUPT_MCP     18
+#define CYGNUM_HAL_INTERRUPT_SSP     19
+#define CYGNUM_HAL_INTERRUPT_TIMER0  26
+#define CYGNUM_HAL_INTERRUPT_TIMER1  27
+#define CYGNUM_HAL_INTERRUPT_TIMER2  28
+#define CYGNUM_HAL_INTERRUPT_TIMER3  29
+#define CYGNUM_HAL_INTERRUPT_HZ      30
+#define CYGNUM_HAL_INTERRUPT_ALARM   31
+
+// GPIO bits 31..11 can generate interrupts as well, but they all
+// end up clumped into interrupt signal #11.  Using the symbols
+// below allow for detection of these separately.
+
+#define CYGNUM_HAL_INTERRUPT_GPIO11  (32+11)
+#define CYGNUM_HAL_INTERRUPT_GPIO12  (32+12)
+#define CYGNUM_HAL_INTERRUPT_GPIO13  (32+13)
+#define CYGNUM_HAL_INTERRUPT_GPIO14  (32+14)
+#define CYGNUM_HAL_INTERRUPT_GPIO15  (32+15)
+#define CYGNUM_HAL_INTERRUPT_GPIO16  (32+16)
+#define CYGNUM_HAL_INTERRUPT_GPIO17  (32+17)
+#define CYGNUM_HAL_INTERRUPT_GPIO18  (32+18)
+#define CYGNUM_HAL_INTERRUPT_GPIO19  (32+19)
+#define CYGNUM_HAL_INTERRUPT_GPIO20  (32+20)
+#define CYGNUM_HAL_INTERRUPT_GPIO21  (32+21)
+#define CYGNUM_HAL_INTERRUPT_GPIO22  (32+22)
+#define CYGNUM_HAL_INTERRUPT_GPIO23  (32+23)
+#define CYGNUM_HAL_INTERRUPT_GPIO24  (32+24)
+#define CYGNUM_HAL_INTERRUPT_GPIO25  (32+25)
+#define CYGNUM_HAL_INTERRUPT_GPIO26  (32+26)
+#define CYGNUM_HAL_INTERRUPT_GPIO27  (32+27)
+
+#define CYGNUM_HAL_INTERRUPT_NONE    -1
+
+#define CYGNUM_HAL_ISR_MIN            0
+#define CYGNUM_HAL_ISR_MAX           (27+32)
+
+#define CYGNUM_HAL_ISR_COUNT         (CYGNUM_HAL_ISR_MAX+1)
+
+// The vector used by the Real time clock
+#define CYGNUM_HAL_INTERRUPT_RTC     CYGNUM_HAL_INTERRUPT_TIMER0
+
+// The vector used by the Ethernet
+#define CYGNUM_HAL_INTERRUPT_ETH     CYGNUM_HAL_INTERRUPT_GPIO0
+
+// method for reading clock interrupt latency
+#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
+externC void hal_clock_latency(cyg_uint32 *);
+# define HAL_CLOCK_LATENCY( _pvalue_ ) \
+         hal_clock_latency( (cyg_uint32 *)(_pvalue_) )
+#endif
+
+//----------------------------------------------------------------------------
+// Reset.
+#define HAL_PLATFORM_RESET()                                        \
+        CYG_MACRO_START                                             \
+                *(volatile unsigned short *)WDOG_BASE_ADDR |= 0x4;  \
+                /* hang here forever if reset fails */              \
+                while (1){}                                         \
+        CYG_MACRO_END
+
+// Fallback (never really used)
+#define HAL_PLATFORM_RESET_ENTRY 0x00000000
+
+#endif // CYGONCE_HAL_VAR_INTS_H
diff --git a/packages/hal/arm/mx25/var/v2_0/include/plf_stub.h b/packages/hal/arm/mx25/var/v2_0/include/plf_stub.h
new file mode 100644 (file)
index 0000000..248631a
--- /dev/null
@@ -0,0 +1,72 @@
+#ifndef CYGONCE_HAL_PLF_STUB_H
+#define CYGONCE_HAL_PLF_STUB_H
+
+//=============================================================================
+//
+//      plf_stub.h
+//
+//      Platform header for GDB stub support.
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <pkgconf/hal.h>
+#include <cyg/infra/cyg_type.h>         // CYG_UNUSED_PARAM
+
+#include <cyg/hal/hal_soc.h>         // registers
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_intr.h>           // Interrupt macros
+#include <cyg/hal/arm_stub.h>           // architecture stub support
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//----------------------------------------------------------------------------
+// Define some platform specific communication details. This is mostly
+// handled by hal_if now, but we need to make sure the comms tables are
+// properly initialized.
+
+externC void cyg_hal_plf_comms_init(void);
+
+#define HAL_STUB_PLATFORM_INIT_SERIAL()         cyg_hal_plf_comms_init()
+#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud)   CYG_UNUSED_PARAM(int, (baud))
+#define HAL_STUB_PLATFORM_INTERRUPTIBLE         0
+
+//----------------------------------------------------------------------------
+// Stub initializer.
+#define HAL_STUB_PLATFORM_INIT()                CYG_EMPTY_STATEMENT
+
+#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+//-----------------------------------------------------------------------------
+#endif // CYGONCE_HAL_PLF_STUB_H
+// End of plf_stub.h
diff --git a/packages/hal/arm/mx25/var/v2_0/include/var_io.h b/packages/hal/arm/mx25/var/v2_0/include/var_io.h
new file mode 100644 (file)
index 0000000..192d501
--- /dev/null
@@ -0,0 +1,81 @@
+#ifndef CYGONCE_VAR_IO_H
+#define CYGONCE_VAR_IO_H
+
+//=============================================================================
+//
+//      var_io.h
+//
+//      Variant specific IO support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/plf_io.h>             // Platform specifics
+
+//-----------------------------------------------------------------------------
+
+// Memory mapping details
+#ifndef CYGARC_PHYSICAL_ADDRESS
+#ifdef SRAM_BASE_ADDR
+#if (SDRAM_BASE_ADDR==SRAM_BASE_ADDR)
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+       (((unsigned long)(x) & 0x00FFFFFF) + SRAM_BASE_ADDR)
+/*#elif (SDRAM_BASE_ADDR == RAM_BANK0_BASE)
+       #define CYGARC_PHYSICAL_ADDRESS(x) \
+         (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE)*/
+#else
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+       ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+         (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE): \
+         (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE))
+#endif
+#else //SRAM_BASE_ADDR
+#if (SDRAM_BASE_ADDR == RAM_BANK0_BASE) 
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+       ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+         (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE): \
+         (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE))   
+#else
+#define CYGARC_PHYSICAL_ADDRESS(x) \
+       ((((unsigned long)x & 0x1FFFFFFF) > 0x0FFFFFFF)? \
+         (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK0_BASE): \
+         (((unsigned long)x & 0x0FFFFFFF) + RAM_BANK1_BASE))   
+#endif
+#endif //SRAM_BASE_ADDr
+#endif
+
+//-----------------------------------------------------------------------------
+// end of var_io.h
+#endif // CYGONCE_VAR_IO_H
diff --git a/packages/hal/arm/mx25/var/v2_0/src/cmds.c b/packages/hal/arm/mx25/var/v2_0/src/cmds.c
new file mode 100644 (file)
index 0000000..95fcc0d
--- /dev/null
@@ -0,0 +1,487 @@
+//==========================================================================
+//
+//      cmds.c
+//
+//      SoC [platform] specific RedBoot commands
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+#include <redboot.h>
+#include <cyg/hal/hal_intr.h>
+#include <cyg/hal/plf_mmap.h>
+#include <cyg/hal/hal_soc.h>         // Hardware definitions
+#include <cyg/hal/hal_cache.h>
+
+#define IIM_FUSE_DEBUG
+
+typedef unsigned long long  u64;
+typedef unsigned int        u32;
+typedef unsigned short      u16;
+typedef unsigned char       u8;
+
+u32 pll_clock(enum plls pll);
+u32 get_main_clock(enum main_clocks clk);
+u32 get_peri_clock(enum peri_clocks clk);
+
+static void clock_setup(int argc, char *argv[]);
+
+RedBoot_cmd("clock",
+            "Setup/Display clock\nSyntax:",
+            "[<ARM core clock in MHz> [:<ARM-AHB clock divider>]\n\
+If a selection is zero or no divider is specified, the optimal divider values\n\
+will be chosen. Examples:\n\
+   [clock]         -> Show various clocks\n\
+   [clock 399]     -> Core=399   AHB=133           IPG=66.5(AHB/2)\n\
+   [clock 532:4]   -> Core=532   AHB=133(Core/4)   IPG=66.5(AHB/2)\n\
+   [clock 399:4]   -> Core=399   AHB=99.75(Core/4) IPG=49.875(AHB/2)\n\
+   [clock 199:3]   -> Core=199.5 AHB=66.5(Core/3)  IPG=33.25(AHB/2)\n\
+   [clock 133:2]   -> Core=133   AHB=66.5(Core/2)  IPG=33.25(AHB/2)\n\
+                      Core range: 532-133, AHB range: 133-66.5, IPG is always AHB/2\n",
+            clock_setup
+           );
+
+void clock_spi_enable(unsigned int spi_clk)
+{
+    diag_printf("%s: stubbed\n", __func__);
+}
+
+static void clock_setup(int argc,char *argv[])
+{
+    u32 i, data[2], temp, core_clk, ahb_div, cctl, arm_src, arm_div;
+
+    if (argc == 1)
+        goto print_clock;
+
+    for (i = 0;  i < 2;  i++) {
+        if (!parse_num(*(&argv[1]), (unsigned long *)&temp, &argv[1], ":")) {
+            diag_printf("Error: Invalid parameter\n");
+            return;
+        }
+        data[i] = temp;
+    }
+
+    core_clk = data[0];
+    ahb_div = data[1] - 1;
+
+    if (core_clk / (ahb_div + 1) > 133 ||
+       core_clk / (ahb_div + 1) < 66) {
+       diag_printf("Illegal AHB divider value specified\n");
+       return;
+    }
+
+    switch (core_clk) {
+    case 532:
+       arm_src = 0;
+       arm_div = 1 - 1;
+       break;
+    case 399:
+       arm_src = 1;
+       arm_div = 1 - 1;
+       break;
+    case 199:
+    case 200:
+       arm_src = 1;
+       arm_div = 2 - 1;
+       break;
+    case 133:
+       arm_src = 1;
+       arm_div = 3 - 1;
+       break;
+    default:
+       diag_printf("Illegal core clock value specified\n");
+       return;
+    }
+
+    cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
+    cctl &= ~0xF0004000;
+    cctl |= arm_div << 30;
+    cctl |= ahb_div << 28;
+    cctl |= arm_src << 14;
+    writel(cctl, CCM_BASE_ADDR + CLKCTL_CCTL);
+
+    diag_printf("\n<<<New clock settings>>>\n");
+
+    // Now printing clocks
+print_clock:
+    diag_printf("\nMPLL\t\tUPLL\n");
+    diag_printf("=========================\n");
+    diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(USB_PLL));
+    diag_printf("CPU\t\tAHB\t\tIPG\n");
+    diag_printf("========================================\n");
+    diag_printf("%-16d%-16d%-16d\n\n",
+                get_main_clock(CPU_CLK),
+                get_main_clock(AHB_CLK),
+                get_main_clock(IPG_CLK));
+
+    diag_printf("UART\n");
+    diag_printf("========\n");
+    diag_printf("%-16d\n\n",
+                get_peri_clock(PER_UART_CLK));
+
+    diag_printf("SPI\n");
+    diag_printf("========\n");
+    diag_printf("%-16d\n\n",
+                get_peri_clock(SPI1_CLK));
+}
+
+/*!
+ * This function returns the PLL output value in Hz based on pll.
+ */
+u32 pll_clock(enum plls pll)
+{
+    u64 mfi, mfn, mfd, pdf, ref_clk, pll_out;
+    u64 reg = readl(pll);
+
+    pdf = (reg >> 26) & 0xF;
+    mfd = (reg >> 16) & 0x3FF;
+    mfi = (reg >> 10) & 0xF;
+    mfi = (mfi <= 5) ? 5: mfi;
+    mfn = reg & 0x3FF;
+
+    ref_clk = PLL_REF_CLK;
+
+    pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
+              (pdf + 1);
+
+    return (u32)pll_out;
+}
+
+/*!
+ * This function returns the main clock value in Hz.
+ */
+u32 get_main_clock(enum main_clocks clk)
+{
+    u32 cctl = readl(CCM_BASE_ADDR + CLKCTL_CCTL);
+    u32 ahb_div;
+    u32 ret_val = 0;
+
+    switch (clk) {
+    case CPU_CLK:
+        ret_val = pll_clock(MCU_PLL);
+        if (cctl & CRM_CCTL_ARM_SRC) {
+                ret_val *= 3;
+                ret_val /= 4;
+        }
+        break;
+    case AHB_CLK:
+        ahb_div = ((cctl >> CRM_CCTL_AHB_OFFSET) & 3) + 1;
+        ret_val = get_main_clock(CPU_CLK) / ahb_div;
+        break;
+    case IPG_CLK:
+    case IPG_PER_CLK:
+        ret_val = get_main_clock(AHB_CLK) / 2;
+        break;
+    default:
+        diag_printf("Unknown clock: %d\n", clk);
+        break;
+    }
+
+    return ret_val;
+}
+
+/*!
+ * This function returns the peripheral clock value in Hz.
+ */
+u32 get_peri_clock(enum peri_clocks clk)
+{
+    u32 ret_val = 0;
+    u32 pcdr, div;
+
+    switch (clk) {
+    case PER_UART_CLK:
+        pcdr = readl(CCM_BASE_ADDR + CLKCTL_PCDR3);
+        div = (pcdr >> 24) + 1;
+        ret_val = get_main_clock(AHB_CLK) / div;
+        break;
+    case SPI1_CLK:
+    case SPI2_CLK:
+        ret_val = get_main_clock(IPG_CLK);
+        break;
+    default:
+        diag_printf("%s(): This clock: %d not supported yet \n",
+                    __FUNCTION__, clk);
+        break;
+    }
+    return ret_val;
+}
+
+
+#define IIM_ERR_SHIFT       8
+#define POLL_FUSE_PRGD      (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD      (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+
+static void fuse_op_start(void)
+{
+    /* Do not generate interrupt */
+    writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+    // clear the status bits and error bits
+    writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+    writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+}
+
+/*
+ * The action should be either:
+ *          POLL_FUSE_PRGD
+ * or:
+ *          POLL_FUSE_SNSD
+ */
+static int poll_fuse_op_done(int action)
+{
+
+    u32 status, error;
+
+    if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+        diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+        return -1;
+    }
+
+    /* Poll busy bit till it is NOT set */
+    while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+    }
+
+    /* Test for successful write */
+    status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+    error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+
+    if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+        if (error) {
+            diag_printf("Even though the operation seems successful...\n");
+            diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+                        (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+        }
+        return 0;
+    }
+    diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+    diag_printf("status address=0x%x, value=0x%x\n",
+                (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+    diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
+                (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+    return -1;
+}
+
+static void sense_fuse(int bank, int row, int bit)
+{
+    int addr, addr_l, addr_h, reg_addr;
+
+    fuse_op_start();
+
+    addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+    /* Set IIM Program Upper Address */
+    addr_h = (addr >> 8) & 0x000000FF;
+    /* Set IIM Program Lower Address */
+    addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+    diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+                __FUNCTION__, addr_h, addr_l);
+#endif
+    writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+    writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+    /* Start sensing */
+    writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+    if (poll_fuse_op_done(POLL_FUSE_SNSD) != 0) {
+        diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+                    __FUNCTION__, bank, row, bit);
+    }
+    reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+    diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
+}
+
+void do_fuse_read(int argc, char *argv[])
+{
+    int bank, row;
+
+    if (argc == 1) {
+        diag_printf("Useage: fuse_read <bank> <row>\n");
+        return;
+    } else if (argc == 3) {
+        if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+                diag_printf("Error: Invalid parameter\n");
+            return;
+        }
+        if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+                diag_printf("Error: Invalid parameter\n");
+                return;
+            }
+
+        diag_printf("Read fuse at bank:%d row:%d\n", bank, row);
+        sense_fuse(bank, row, 0);
+
+    } else {
+        diag_printf("Passing in wrong arguments: %d\n", argc);
+        diag_printf("Useage: fuse_read <bank> <row>\n");
+    }
+}
+
+/* Blow fuses based on the bank, row and bit positions (all 0-based)
+*/
+static int fuse_blow(int bank,int row,int bit)
+{
+    int addr, addr_l, addr_h, ret = -1;
+
+    fuse_op_start();
+
+    /* Disable IIM Program Protect */
+    writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+
+    addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+    /* Set IIM Program Upper Address */
+    addr_h = (addr >> 8) & 0x000000FF;
+    /* Set IIM Program Lower Address */
+    addr_l = (addr & 0x000000FF);
+
+#ifdef IIM_FUSE_DEBUG
+    diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+#endif
+
+    writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+    writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+    /* Start Programming */
+    writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
+    if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+        ret = 0;
+    }
+
+    /* Enable IIM Program Protect */
+    writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+    return ret;
+}
+
+/*
+ * This command is added for burning IIM fuses
+ */
+RedBoot_cmd("fuse_read",
+            "read some fuses",
+            "<bank> <row>",
+            do_fuse_read
+           );
+
+RedBoot_cmd("fuse_blow",
+            "blow some fuses",
+            "<bank> <row> <value>",
+            do_fuse_blow
+           );
+
+#define         INIT_STRING              "12345678"
+static char ready_to_blow[] = INIT_STRING;
+
+void quick_itoa(u32 num, char *a)
+{
+    int i, j, k;
+    for (i = 0; i <= 7; i++) {
+        j = (num >> (4 * i)) & 0xF;
+        k = (j < 10) ? '0' : ('a' - 0xa);
+        a[i] = j + k;
+    }
+}
+
+void do_fuse_blow(int argc, char *argv[])
+{
+    int bank, row, value, i;
+
+    if (argc == 1) {
+        diag_printf("It is too dangeous for you to use this command.\n");
+        return;
+    } else if (argc == 2) {
+        if (strcasecmp(argv[1], "nandboot") == 0) {
+            quick_itoa(readl(EPIT_BASE_ADDR + EPITCNR), ready_to_blow);
+            diag_printf("%s\n", ready_to_blow);
+        }
+        return;
+    } else if (argc == 3) {
+        if (strcasecmp(argv[1], "nandboot") == 0 &&
+            strcasecmp(argv[2], ready_to_blow) == 0) {
+#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31) ||defined(CYGPKG_HAL_ARM_MX35) || defined(CYGPKG_HAL_ARM_MX25)
+            diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+#else
+#error "Are you sure you want this?"
+            diag_printf("Ready to burn NAND boot fuses\n");
+            if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+                diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+            } else {
+                diag_printf("NAND BOOT fuse blown successfully ...\n");
+            }
+        } else {
+            diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+#endif
+        }
+    } else if (argc == 4) {
+        if (!parse_num(*(&argv[1]), (unsigned long *)&bank, &argv[1], " ")) {
+                diag_printf("Error: Invalid parameter\n");
+                return;
+        }
+        if (!parse_num(*(&argv[2]), (unsigned long *)&row, &argv[2], " ")) {
+                diag_printf("Error: Invalid parameter\n");
+                return;
+        }
+        if (!parse_num(*(&argv[3]), (unsigned long *)&value, &argv[3], " ")) {
+                diag_printf("Error: Invalid parameter\n");
+                return;
+        }
+
+        diag_printf("Blowing fuse at bank:%d row:%d value:%d\n",
+                    bank, row, value);
+        for (i = 0; i < 8; i++) {
+            if (((value >> i) & 0x1) == 0) {
+                continue;
+            }
+            if (fuse_blow(bank, row, i) != 0) {
+                diag_printf("fuse_blow(bank: %d, row: %d, bit: %d failed\n",
+                            bank, row, i);
+            } else {
+                diag_printf("fuse_blow(bank: %d, row: %d, bit: %d successful\n",
+                            bank, row, i);
+            }
+        }
+        sense_fuse(bank, row, 0);
+
+    } else {
+        diag_printf("Passing in wrong arguments: %d\n", argc);
+    }
+    /* Reset to default string */
+    strcpy(ready_to_blow, INIT_STRING);;
+}
+
+/* precondition: m>0 and n>0.  Let g=gcd(m,n). */
+int gcd(int m, int n)
+{
+    int t;
+    while(m > 0) {
+        if(n > m) {t = m; m = n; n = t;} /* swap */
+        m -= n;
+    }
+    return n;
+}
+
diff --git a/packages/hal/arm/mx25/var/v2_0/src/soc_diag.c b/packages/hal/arm/mx25/var/v2_0/src/soc_diag.c
new file mode 100644 (file)
index 0000000..aef5714
--- /dev/null
@@ -0,0 +1,743 @@
+/*=============================================================================
+//
+//      hal_diag.c
+//
+//      HAL diagnostic output code
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================*/
+
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_arch.h>           // basic machine info
+#include <cyg/hal/hal_intr.h>           // interrupt macros
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_if.h>             // Calling interface definitions
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/drv_api.h>            // cyg_drv_interrupt_acknowledge
+#include <cyg/hal/hal_misc.h>           // Helper functions
+#include <cyg/hal/hal_soc.h>         // Hardware definitions
+
+/*
+ * UART Control Register 0 Bit Fields.
+ */
+#define EUartUCR1_ADEN      (1 << 15)           // Auto dectect interrupt
+#define EUartUCR1_ADBR      (1 << 14)           // Auto detect baud rate
+#define EUartUCR1_TRDYEN    (1 << 13)           // Transmitter ready interrupt enable
+#define EUartUCR1_IDEN      (1 << 12)           // Idle condition interrupt
+#define EUartUCR1_RRDYEN    (1 << 9)            // Recv ready interrupt enable
+#define EUartUCR1_RDMAEN    (1 << 8)            // Recv ready DMA enable
+#define EUartUCR1_IREN      (1 << 7)            // Infrared interface enable
+#define EUartUCR1_TXMPTYEN  (1 << 6)            // Transimitter empty interrupt enable
+#define EUartUCR1_RTSDEN    (1 << 5)            // RTS delta interrupt enable
+#define EUartUCR1_SNDBRK    (1 << 4)            // Send break
+#define EUartUCR1_TDMAEN    (1 << 3)            // Transmitter ready DMA enable
+#define EUartUCR1_DOZE      (1 << 1)            // Doze
+#define EUartUCR1_UARTEN    (1 << 0)            // UART enabled
+#define EUartUCR2_ESCI      (1 << 15)           // Escape seq interrupt enable
+#define EUartUCR2_IRTS      (1 << 14)           // Ignore RTS pin
+#define EUartUCR2_CTSC      (1 << 13)           // CTS pin control
+#define EUartUCR2_CTS       (1 << 12)           // Clear to send
+#define EUartUCR2_ESCEN     (1 << 11)           // Escape enable
+#define EUartUCR2_PREN      (1 << 8)            // Parity enable
+#define EUartUCR2_PROE      (1 << 7)            // Parity odd/even
+#define EUartUCR2_STPB      (1 << 6)            // Stop
+#define EUartUCR2_WS        (1 << 5)            // Word size
+#define EUartUCR2_RTSEN     (1 << 4)            // Request to send interrupt enable
+#define EUartUCR2_ATEN      (1 << 3)            // Aging timer enable
+#define EUartUCR2_TXEN      (1 << 2)            // Transmitter enabled
+#define EUartUCR2_RXEN      (1 << 1)            // Receiver enabled
+#define EUartUCR2_SRST_     (1 << 0)            // SW reset
+#define EUartUCR3_PARERREN  (1 << 12)           // Parity enable
+#define EUartUCR3_FRAERREN  (1 << 11)           // Frame error interrupt enable
+#define EUartUCR3_ADNIMP    (1 << 7)            // Autobaud detection not improved
+#define EUartUCR3_RXDSEN    (1 << 6)            // Receive status interrupt enable
+#define EUartUCR3_AIRINTEN  (1 << 5)            // Async IR wake interrupt enable
+#define EUartUCR3_AWAKEN    (1 << 4)            // Async wake interrupt enable
+#define EUartUCR3_RXDMUXSEL (1 << 2)            // RXD muxed input selected
+#define EUartUCR3_INVT      (1 << 1)            // Inverted Infrared transmission
+#define EUartUCR3_ACIEN     (1 << 0)            // Autobaud counter interrupt enable
+#define EUartUCR4_CTSTL_32  (32 << 10)          // CTS trigger level (32 chars)
+#define EUartUCR4_INVR      (1 << 9)            // Inverted infrared reception
+#define EUartUCR4_ENIRI     (1 << 8)            // Serial infrared interrupt enable
+#define EUartUCR4_WKEN      (1 << 7)            // Wake interrupt enable
+#define EUartUCR4_IRSC      (1 << 5)            // IR special case
+#define EUartUCR4_LPBYP     (1 << 4)            // Low power bypass
+#define EUartUCR4_TCEN      (1 << 3)            // Transmit complete interrupt enable
+#define EUartUCR4_BKEN      (1 << 2)            // Break condition interrupt enable
+#define EUartUCR4_OREN      (1 << 1)            // Receiver overrun interrupt enable
+#define EUartUCR4_DREN      (1 << 0)            // Recv data ready interrupt enable
+#define EUartUFCR_RXTL_SHF  0                   // Receiver trigger level shift
+#define EUartUFCR_RFDIV_1   (5 << 7)            // Reference freq divider (div 1)
+#define EUartUFCR_RFDIV_2   (4 << 7)            // Reference freq divider (div 2)
+#define EUartUFCR_RFDIV_3   (3 << 7)            // Reference freq divider (div 3)
+#define EUartUFCR_RFDIV_4   (2 << 7)            // Reference freq divider (div 4)
+#define EUartUFCR_RFDIV_5   (1 << 7)            // Reference freq divider (div 5)
+#define EUartUFCR_RFDIV_6   (0 << 7)            // Reference freq divider (div 6)
+#define EUartUFCR_RFDIV_7   (6 << 7)            // Reference freq divider (div 7)
+#define EUartUFCR_TXTL_SHF  10                  // Transmitter trigger level shift
+#define EUartUSR1_PARITYERR (1 << 15)           // Parity error interrupt flag
+#define EUartUSR1_RTSS      (1 << 14)           // RTS pin status
+#define EUartUSR1_TRDY      (1 << 13)           // Transmitter ready interrupt/dma flag
+#define EUartUSR1_RTSD      (1 << 12)           // RTS delta
+#define EUartUSR1_ESCF      (1 << 11)           // Escape seq interrupt flag
+#define EUartUSR1_FRAMERR   (1 << 10)           // Frame error interrupt flag
+#define EUartUSR1_RRDY      (1 << 9)            // Receiver ready interrupt/dma flag
+#define EUartUSR1_AGTIM     (1 << 8)            // Aging timeout interrupt status
+#define EUartUSR1_RXDS      (1 << 6)            // Receiver idle interrupt flag
+#define EUartUSR1_AIRINT    (1 << 5)            // Async IR wake interrupt flag
+#define EUartUSR1_AWAKE     (1 << 4)            // Aysnc wake interrupt flag
+#define EUartUSR2_ADET      (1 << 15)           // Auto baud rate detect complete
+#define EUartUSR2_TXFE      (1 << 14)           // Transmit buffer FIFO empty
+#define EUartUSR2_IDLE      (1 << 12)           // Idle condition
+#define EUartUSR2_ACST      (1 << 11)           // Autobaud counter stopped
+#define EUartUSR2_IRINT     (1 << 8)            // Serial infrared interrupt flag
+#define EUartUSR2_WAKE      (1 << 7)            // Wake
+#define EUartUSR2_RTSF      (1 << 4)            // RTS edge interrupt flag
+#define EUartUSR2_TXDC      (1 << 3)            // Transmitter complete
+#define EUartUSR2_BRCD      (1 << 2)            // Break condition
+#define EUartUSR2_ORE       (1 << 1)            // Overrun error
+#define EUartUSR2_RDR       (1 << 0)            // Recv data ready
+#define EUartUTS_FRCPERR    (1 << 13)           // Force parity error
+#define EUartUTS_LOOP       (1 << 12)           // Loop tx and rx
+#define EUartUTS_TXEMPTY    (1 << 6)            // TxFIFO empty
+#define EUartUTS_RXEMPTY    (1 << 5)            // RxFIFO empty
+#define EUartUTS_TXFULL     (1 << 4)            // TxFIFO full
+#define EUartUTS_RXFULL     (1 << 3)            // RxFIFO full
+#define EUartUTS_SOFTRST    (1 << 0)            // Software reset
+
+#define EUartUFCR_RFDIV                        EUartUFCR_RFDIV_1
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_1)
+#define MXC_UART_REFFREQ                        (get_peri_clock(PER_UART_CLK) / 1)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_2)
+#define MXC_UART_REFFREQ                        (get_peri_clock(PER_UART_CLK) / 2)
+#endif
+
+#if (EUartUFCR_RFDIV==EUartUFCR_RFDIV_4)
+#define MXC_UART_REFFREQ                        (get_peri_clock(PER_UART_CLK) / 4)
+#endif
+
+#if 0
+void
+cyg_hal_plf_comms_init(void)
+{
+    static int initialized = 0;
+
+    if (initialized)
+        return;
+
+    initialized = 1;
+
+    cyg_hal_plf_serial_init();
+}
+#endif
+
+//=============================================================================
+// MXC Serial Port (UARTx) for Debug
+//=============================================================================
+#ifdef UART_WIDTH_32
+struct mxc_serial {
+    volatile cyg_uint32 urxd[16];
+    volatile cyg_uint32 utxd[16];
+    volatile cyg_uint32 ucr1;
+    volatile cyg_uint32 ucr2;
+    volatile cyg_uint32 ucr3;
+    volatile cyg_uint32 ucr4;
+    volatile cyg_uint32 ufcr;
+    volatile cyg_uint32 usr1;
+    volatile cyg_uint32 usr2;
+    volatile cyg_uint32 uesc;
+    volatile cyg_uint32 utim;
+    volatile cyg_uint32 ubir;
+    volatile cyg_uint32 ubmr;
+    volatile cyg_uint32 ubrc;
+    volatile cyg_uint32 onems;
+    volatile cyg_uint32 uts;
+};
+#else
+struct mxc_serial {
+    volatile cyg_uint16 urxd[1];
+    volatile cyg_uint16 resv0[31];
+
+    volatile cyg_uint16 utxd[1];
+    volatile cyg_uint16 resv1[31];
+    volatile cyg_uint16 ucr1;
+    volatile cyg_uint16 resv2;
+    volatile cyg_uint16 ucr2;
+    volatile cyg_uint16 resv3;
+    volatile cyg_uint16 ucr3;
+    volatile cyg_uint16 resv4;
+    volatile cyg_uint16 ucr4;
+    volatile cyg_uint16 resv5;
+    volatile cyg_uint16 ufcr;
+    volatile cyg_uint16 resv6;
+    volatile cyg_uint16 usr1;
+    volatile cyg_uint16 resv7;
+    volatile cyg_uint16 usr2;
+    volatile cyg_uint16 resv8;
+    volatile cyg_uint16 uesc;
+    volatile cyg_uint16 resv9;
+    volatile cyg_uint16 utim;
+    volatile cyg_uint16 resv10;
+    volatile cyg_uint16 ubir;
+    volatile cyg_uint16 resv11;
+    volatile cyg_uint16 ubmr;
+    volatile cyg_uint16 resv12;
+    volatile cyg_uint16 ubrc;
+    volatile cyg_uint16 resv13;
+    volatile cyg_uint16 onems;
+    volatile cyg_uint16 resv14;
+    volatile cyg_uint16 uts;
+    volatile cyg_uint16 resv15;
+};
+#endif
+
+typedef struct {
+    volatile struct mxc_serial* base;
+    cyg_int32 msec_timeout;
+    int isr_vector;
+    int baud_rate;
+} channel_data_t;
+
+static channel_data_t channels[] = {
+#if CYGHWR_HAL_ARM_SOC_UART1 != 0
+    {(volatile struct mxc_serial*)UART1_BASE_ADDR, 1000,
+      CYGNUM_HAL_INTERRUPT_UART1, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART2 != 0
+    {(volatile struct mxc_serial*)UART2_BASE_ADDR, 1000,
+     CYGNUM_HAL_INTERRUPT_UART2, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+#if CYGHWR_HAL_ARM_SOC_UART3 != 0
+    {(volatile struct mxc_serial*)UART3_BASE_ADDR, 1000,
+     CYGNUM_HAL_INTERRUPT_UART3, CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD},
+#endif
+};
+
+/*---------------------------------------------------------------------------*/
+
+static void init_serial_channel(channel_data_t* __ch_data)
+{
+    volatile struct mxc_serial* base = __ch_data->base;
+
+    /* Wait for UART to finish transmitting */
+    while (!(base->uts & EUartUTS_TXEMPTY));
+
+    /* Disable UART */
+    base->ucr1 &= ~EUartUCR1_UARTEN;
+
+    /* Set to default POR state */
+    base->ucr1 = 0x00000000;
+    base->ucr2 = 0x00000000;
+
+    while (!(base->ucr2 & EUartUCR2_SRST_));
+
+    base->ucr3 = 0x00000704;
+    base->ucr4 = 0x00008000;
+    base->ufcr = 0x00000801;
+    base->uesc = 0x0000002B;
+    base->utim = 0x00000000;
+    base->ubir = 0x00000000;
+    base->ubmr = 0x00000000;
+    base->onems = 0x00000000;
+    base->uts  = 0x00000000;
+
+    /* Configure FIFOs */
+    base->ufcr = (1 << EUartUFCR_RXTL_SHF) | EUartUFCR_RFDIV
+                 | (2 << EUartUFCR_TXTL_SHF);
+
+    /* Setup One MS timer */
+    base->onems  = (MXC_UART_REFFREQ / 1000);
+
+    /* Set to 8N1 */
+    base->ucr2 &= ~EUartUCR2_PREN;
+    base->ucr2 |= EUartUCR2_WS;
+    base->ucr2 &= ~EUartUCR2_STPB;
+
+    /* Ignore RTS */
+    base->ucr2 |= EUartUCR2_IRTS;
+
+    /* Enable UART */
+    base->ucr1 |= EUartUCR1_UARTEN;
+
+    /* Enable FIFOs */
+    base->ucr2 |= EUartUCR2_SRST_ | EUartUCR2_RXEN | EUartUCR2_TXEN;
+
+    /* Clear status flags */
+    base->usr2 |= EUartUSR2_ADET  |
+                  EUartUSR2_IDLE  |
+                  EUartUSR2_IRINT |
+                  EUartUSR2_WAKE  |
+                  EUartUSR2_RTSF  |
+                  EUartUSR2_BRCD  |
+                  EUartUSR2_ORE   |
+                  EUartUSR2_RDR;
+
+    /* Clear status flags */
+    base->usr1 |= EUartUSR1_PARITYERR |
+                  EUartUSR1_RTSD      |
+                  EUartUSR1_ESCF      |
+                  EUartUSR1_FRAMERR   |
+                  EUartUSR1_AIRINT    |
+                  EUartUSR1_AWAKE;
+
+    /* Set the numerator value minus one of the BRM ratio */
+    base->ubir = (__ch_data->baud_rate / 100) - 1;
+
+    /* Set the denominator value minus one of the BRM ratio    */
+    base->ubmr = ((MXC_UART_REFFREQ / 1600) - 1);
+
+}
+
+static void stop_serial_channel(channel_data_t* __ch_data)
+{
+    volatile struct mxc_serial* base = __ch_data->base;
+
+    /* Wait for UART to finish transmitting */
+    while (!(base->uts & EUartUTS_TXEMPTY));
+
+    /* Disable UART */
+    base->ucr1 &= ~EUartUCR1_UARTEN;
+}
+
+//#define debug_uart_log_buf
+#ifdef debug_uart_log_buf
+#define DIAG_BUFSIZE 2048
+static char __log_buf[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+
+void cyg_hal_plf_serial_putc(void *__ch_data, char c)
+{
+    volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+#ifdef debug_uart_log_buf
+    __log_buf[diag_bp++] = c;
+#endif
+
+    CYGARC_HAL_SAVE_GP();
+
+    // Wait for Tx FIFO not full
+    while (base->uts & EUartUTS_TXFULL)
+        ;
+    base->utxd[0] = c;
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static cyg_bool cyg_hal_plf_serial_getc_nonblock(void* __ch_data,
+                                                 cyg_uint8* ch)
+{
+    volatile struct mxc_serial* base = ((channel_data_t*)__ch_data)->base;
+
+    // If receive fifo is empty, return false
+    if (base->uts & EUartUTS_RXEMPTY)
+        return false;
+
+    *ch = (char)base->urxd[0];
+
+    return true;
+}
+
+cyg_uint8 cyg_hal_plf_serial_getc(void* __ch_data)
+{
+    cyg_uint8 ch;
+    CYGARC_HAL_SAVE_GP();
+
+    while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
+
+    CYGARC_HAL_RESTORE_GP();
+    return ch;
+}
+
+static void cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
+                         cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while(__len-- > 0)
+        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+static void cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf,
+                                    cyg_uint32 __len)
+{
+    CYGARC_HAL_SAVE_GP();
+
+    while (__len-- > 0)
+        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
+
+    CYGARC_HAL_RESTORE_GP();
+}
+
+cyg_bool cyg_hal_plf_serial_getc_timeout(void* __ch_data,
+                                         cyg_uint8* ch)
+{
+    int delay_count;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    cyg_bool res;
+    CYGARC_HAL_SAVE_GP();
+
+    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
+
+    for(;;) {
+        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
+        if (res || 0 == delay_count--)
+            break;
+
+        CYGACC_CALL_IF_DELAY_US(100);
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+static int cyg_hal_plf_serial_control(void *__ch_data,
+                                      __comm_control_cmd_t __func, ...)
+{
+    static int irq_state = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    int ret = -1;
+    va_list ap;
+
+    CYGARC_HAL_SAVE_GP();
+    va_start(ap, __func);
+
+    switch (__func) {
+    case __COMMCTL_GETBAUD:
+        ret = chan->baud_rate;
+        break;
+    case __COMMCTL_SETBAUD:
+        chan->baud_rate = va_arg(ap, cyg_int32);
+        // Should we verify this value here?
+        init_serial_channel(chan);
+        ret = 0;
+        break;
+    case __COMMCTL_IRQ_ENABLE:
+        irq_state = 1;
+
+        chan->base->ucr1 |= EUartUCR1_RRDYEN;
+
+        HAL_INTERRUPT_UNMASK(chan->isr_vector);
+        break;
+    case __COMMCTL_IRQ_DISABLE:
+        ret = irq_state;
+        irq_state = 0;
+
+        chan->base->ucr1 &= ~EUartUCR1_RRDYEN;
+
+        HAL_INTERRUPT_MASK(chan->isr_vector);
+        break;
+    case __COMMCTL_DBG_ISR_VECTOR:
+        ret = chan->isr_vector;
+        break;
+    case __COMMCTL_SET_TIMEOUT:
+        ret = chan->msec_timeout;
+        chan->msec_timeout = va_arg(ap, cyg_uint32);
+        break;
+    default:
+        break;
+    }
+    va_end(ap);
+    CYGARC_HAL_RESTORE_GP();
+    return ret;
+}
+
+static int cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
+                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
+{
+    int res = 0;
+    channel_data_t* chan = (channel_data_t*)__ch_data;
+    char c;
+
+    CYGARC_HAL_SAVE_GP();
+
+    cyg_drv_interrupt_acknowledge(chan->isr_vector);
+
+    *__ctrlc = 0;
+    if (!(chan->base->uts & EUartUTS_RXEMPTY)) {
+       c = (char)chan->base->urxd[0];
+
+        if (cyg_hal_is_break( &c , 1 ))
+            *__ctrlc = 1;
+
+        res = CYG_ISR_HANDLED;
+    }
+
+    CYGARC_HAL_RESTORE_GP();
+    return res;
+}
+
+void cyg_hal_plf_serial_init(void)
+{
+    hal_virtual_comm_table_t* comm;
+    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
+    int i;
+    static int jjj = 0;
+
+    // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+    for (i = 0;  i < NUMOF(channels);  i++) {
+        init_serial_channel(&channels[i]);
+        CYGACC_CALL_IF_SET_CONSOLE_COMM(i+2);
+        comm = CYGACC_CALL_IF_CONSOLE_PROCS();
+        CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
+        CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
+        CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
+        CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
+        CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
+        CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
+        CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
+        CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
+        if (jjj == 0) {
+            cyg_hal_plf_serial_putc(&channels[i], '+');
+            jjj++;
+        }
+        cyg_hal_plf_serial_putc(&channels[i], '+');
+    }
+
+    // Restore original console
+    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
+}
+
+void cyg_hal_plf_serial_stop(void)
+{
+        int i;
+
+        // Init channels
+#define NUMOF(x) (sizeof(x)/sizeof(x[0]))
+        for (i = 0;  i < NUMOF(channels);  i++) {
+                stop_serial_channel(&channels[i]);
+        }
+}
+
+//=============================================================================
+// Compatibility with older stubs
+//=============================================================================
+
+#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
+
+#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 2)
+#define __BASE ((void*)UART1_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART1
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 3)
+#define __BASE ((void*)UART2_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART2
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 4)
+#define __BASE ((void*)UART3_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART3
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 5)
+#define __BASE ((void*)UART4_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART4
+#elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 6)
+#define __BASE ((void*)UART5_BASE_ADDR)
+#define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_UART5
+#endif
+
+#ifdef __BASE
+
+#ifdef CYGSEM_HAL_ROM_MONITOR
+#define CYG_HAL_STARTUP_ROM
+#define CYG_HAL_STARTUP_ROMRAM
+#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+#endif
+
+#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
+#define HAL_DIAG_USES_HARDWARE
+#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
+#define HAL_DIAG_USES_HARDWARE
+#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
+#define HAL_DIAG_USES_HARDWARE
+#endif
+
+static channel_data_t channel = {
+    (volatile struct mxc_serial*)__BASE, 0, CYGHWR_HAL_GDB_PORT_VECTOR
+};
+
+#ifdef HAL_DIAG_USES_HARDWARE
+
+void hal_diag_init(void)
+{
+    static int init = 0;
+    char *msg = "\n\rARM eCos\n\r";
+    cyg_uint8 lcr;
+
+    if (init++) return;
+
+    init_serial_channel(&channel);
+
+    while (*msg) hal_diag_write_char(*msg++);
+}
+
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+#define DIAG_BUFSIZE 2048
+static char diag_buffer[DIAG_BUFSIZE];
+static int diag_bp = 0;
+#endif
+#endif
+
+void hal_diag_write_char(char c)
+{
+#ifdef DEBUG_DIAG
+#ifndef CYG_HAL_STARTUP_ROM
+    diag_buffer[diag_bp++] = c;
+    if (diag_bp == sizeof(diag_buffer)) diag_bp = 0;
+#endif
+#endif
+    cyg_hal_plf_serial_putc(&channel, c);
+}
+
+void hal_diag_read_char(char *c)
+{
+    *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+#else // not HAL_DIAG_USES_HARDWARE - it uses GDB protocol
+
+void hal_diag_read_char(char *c)
+{
+    *c = cyg_hal_plf_serial_getc(&channel);
+}
+
+void hal_diag_write_char(char c)
+{
+    static char line[100];
+    static int pos = 0;
+
+    // FIXME: Some LED blinking might be nice right here.
+
+    // No need to send CRs
+    if( c == '\r' ) return;
+
+    line[pos++] = c;
+
+        if (c == '\n' || pos == sizeof(line)) {
+        CYG_INTERRUPT_STATE old;
+
+        // Disable interrupts. This prevents GDB trying to interrupt us
+        // while we are in the middle of sending a packet. The serial
+        // receive interrupt will be seen when we re-enable interrupts
+        // later.
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
+#else
+        HAL_DISABLE_INTERRUPTS(old);
+#endif
+
+        while (1) {
+            static char hex[] = "0123456789ABCDEF";
+            cyg_uint8 csum = 0;
+            int i;
+#ifndef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+            char c1;
+#endif
+            cyg_hal_plf_serial_putc(&channel, '$');
+            cyg_hal_plf_serial_putc(&channel, 'O');
+            csum += 'O';
+            for(i = 0; i < pos; i++) {
+                char ch = line[i];
+                char h = hex[(ch>>4)&0xF];
+                char l = hex[ch&0xF];
+                cyg_hal_plf_serial_putc(&channel, h);
+                cyg_hal_plf_serial_putc(&channel, l);
+                csum += h;
+                csum += l;
+            }
+            cyg_hal_plf_serial_putc(&channel, '#');
+            cyg_hal_plf_serial_putc(&channel, hex[(csum>>4)&0xF]);
+            cyg_hal_plf_serial_putc(&channel, hex[csum&0xF]);
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+
+            break; // regardless
+
+#else // not CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT Ie. usually...
+
+            // Wait for the ACK character '+' from GDB here and handle
+            // receiving a ^C instead.  This is the reason for this clause
+            // being a loop.
+            c1 = cyg_hal_plf_serial_getc(&channel);
+
+            if( c1 == '+' )
+                break;              // a good acknowledge
+
+#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            cyg_drv_interrupt_acknowledge(CYGHWR_HAL_GDB_PORT_VECTOR);
+            if( c1 == 3 ) {
+                // Ctrl-C: breakpoint.
+                cyg_hal_gdb_interrupt(
+                    (target_register_t)__builtin_return_address(0) );
+                break;
+            }
+#endif // CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+
+#endif // ! CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT
+            // otherwise, loop round again
+        }
+
+        pos = 0;
+
+        // And re-enable interrupts
+#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+        CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
+#else
+        HAL_RESTORE_INTERRUPTS(old);
+#endif
+
+    }
+}
+#endif
+
+#endif // __BASE
+
+#endif // !CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
+
+/*---------------------------------------------------------------------------*/
+/* End of hal_diag.c */
diff --git a/packages/hal/arm/mx25/var/v2_0/src/soc_misc.c b/packages/hal/arm/mx25/var/v2_0/src/soc_misc.c
new file mode 100644 (file)
index 0000000..1387a10
--- /dev/null
@@ -0,0 +1,396 @@
+//==========================================================================
+//
+//      soc_misc.c
+//
+//      HAL misc board support code
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//========================================================================*/
+
+#include <redboot.h>
+#include <pkgconf/hal.h>
+#include <pkgconf/system.h>
+#include CYGBLD_HAL_PLATFORM_H
+
+#include <cyg/infra/cyg_type.h>         // base types
+#include <cyg/infra/cyg_trac.h>         // tracing macros
+#include <cyg/infra/cyg_ass.h>          // assertion macros
+
+#include <cyg/hal/hal_misc.h>           // Size constants
+#include <cyg/hal/hal_io.h>             // IO macros
+#include <cyg/hal/hal_arch.h>           // Register state info
+#include <cyg/hal/hal_diag.h>
+#include <cyg/hal/hal_intr.h>           // Interrupt names
+#include <cyg/hal/hal_cache.h>          // Cache control
+#include <cyg/hal/hal_soc.h>            // Hardware definitions
+#include <cyg/hal/hal_mm.h>             // MMap table definitions
+
+#include <cyg/infra/diag.h>             // diag_printf
+
+// Most initialization has already been done before we get here.
+// All we do here is set up the interrupt environment.
+// FIXME: some of the stuff in hal_platform_setup could be moved here.
+
+externC void plf_hardware_init(void);
+
+#define IIM_PROD_REV_SH         3
+#define IIM_PROD_REV_LEN        5
+#define IIM_SREV_REV_SH         4
+#define IIM_SREV_REV_LEN        4
+
+#define PROD_SIGNATURE_MX25     0x1
+
+#define PROD_SIGNATURE_SUPPORTED_1  PROD_SIGNATURE_MX25
+
+#define CHIP_VERSION_NONE           0xFFFFFFFF      // invalid product ID
+#define CHIP_VERSION_UNKNOWN        0xDEADBEEF      // invalid chip rev
+
+#define PART_NUMBER_OFFSET          (12)
+#define MAJOR_NUMBER_OFFSET         (4)
+#define MINOR_NUMBER_OFFSET         (0)
+
+/*
+ * System_rev will have the following format
+ * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, 0x35, etc)
+ * 11-8 = unused
+ * 7-4 = major (1.y)
+ * 3-0 = minor (x.0)
+ */
+unsigned int system_rev = CHIP_REV_1_0;
+static int find_correct_chip;
+extern char HAL_PLATFORM_EXTRA[55];
+
+/*
+ * This functions reads the IIM module and returns the system revision number.
+ * It returns the IIM silicon revision reg value if valid product rev is found.
+ . Otherwise, it returns -1.
+ */
+static int read_system_rev(void)
+{
+    int val;
+
+    val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
+
+    system_rev = 0x25 << PART_NUMBER_OFFSET; /* For MX25 Platform*/
+    /* If the IIM doesn't contain valid product signature, return
+     * the lowest revision number */
+    if ((MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) !=
+                       PROD_SIGNATURE_SUPPORTED_1)) {
+        return CHIP_VERSION_NONE;
+    }
+
+    /* Now trying to retrieve the silicon rev from IIM's SREV register */
+    return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
+}
+
+extern nfc_setup_func_t *nfc_setup;
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
+                                      unsigned int is_mlc, unsigned int num_of_chips);
+void hal_hardware_init(void)
+{
+    int ver;
+
+    ver = read_system_rev();
+    find_correct_chip = ver;
+
+    // Mask all interrupts
+    writel(0xFFFFFFFF, ASIC_NIMASK);
+
+    // Make all interrupts do IRQ and not FIQ
+    // FIXME: Change this if you use FIQs.
+    writel(0, ASIC_INTTYPEH);
+    writel(0, ASIC_INTTYPEL);
+
+    // Enable caches
+    HAL_ICACHE_ENABLE();
+    HAL_DCACHE_ENABLE();
+
+    // enable EPIT and start it with 32KHz input clock
+    writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
+
+    // make sure reset is complete
+    while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
+    }
+
+    writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
+    writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
+
+    writel(0, EPIT_BASE_ADDR + EPITCMPR);  // always compare with 0
+
+    if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+        // increase the WDOG timeout value to the max
+        writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
+    }
+
+    // Perform any platform specific initializations
+    plf_hardware_init();
+
+    // Set up eCos/ROM interfaces
+    hal_if_init();
+
+    nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
+}
+
+// -------------------------------------------------------------------------
+void hal_clock_initialize(cyg_uint32 period)
+{
+}
+
+// This routine is called during a clock interrupt.
+
+// Define this if you want to ensure that the clock is perfect (i.e. does
+// not drift).  One reason to leave it turned off is that it costs some
+// us per system clock interrupt for this maintenance.
+#undef COMPENSATE_FOR_CLOCK_DRIFT
+
+void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
+{
+}
+
+// Read the current value of the clock, returning the number of hardware
+// "ticks" that have occurred (i.e. how far away the current value is from
+// the start)
+
+// Note: The "contract" for this function is that the value is the number
+// of hardware clocks that have happened since the last interrupt (i.e.
+// when it was reset).  This value is used to measure interrupt latencies.
+// However, since the hardware counter runs freely, this routine computes
+// the difference between the current clock period and the number of hardware
+// ticks left before the next timer interrupt.
+void hal_clock_read(cyg_uint32 *pvalue)
+{
+}
+
+// This is to cope with the test read used by tm_basic with
+// CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP
+// in the ISR, *before* resetting the clock.  Which returns 1tick +
+// latency if we just use plain hal_clock_read().
+void hal_clock_latency(cyg_uint32 *pvalue)
+{
+}
+
+unsigned int hal_timer_count(void)
+{
+    return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
+}
+
+#define WDT_MAGIC_1             0x5555
+#define WDT_MAGIC_2             0xAAAA
+#define MXC_WDT_WSR             0x2
+
+unsigned int i2c_base_addr[] = {
+    I2C_BASE_ADDR,
+    I2C2_BASE_ADDR,
+    I2C3_BASE_ADDR
+};
+unsigned int i2c_num = 3;
+
+static unsigned int led_on = 0;
+//
+// Delay for some number of micro-seconds
+//
+void hal_delay_us(unsigned int usecs)
+{
+    /*
+     * This causes overflow.
+     * unsigned int delayCount = (usecs * 32000) / 1000000;
+     * So use the following one instead
+     */
+    unsigned int delayCount = (usecs*4 + 124) / 125;
+
+    if (delayCount == 0) {
+        return;
+    }
+
+    // issue the service sequence instructions
+    if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
+        writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
+        writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
+    }
+
+    writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
+
+    writel(delayCount, EPIT_BASE_ADDR + EPITLR);
+
+    while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+    if ((++led_on % 2000) == 0)
+        BOARD_DEBUG_LED(0);
+}
+
+// -------------------------------------------------------------------------
+
+// This routine is called to respond to a hardware interrupt (IRQ).  It
+// should interrogate the hardware and return the IRQ vector number.
+int hal_IRQ_handler(void)
+{
+#ifdef HAL_EXTENDED_IRQ_HANDLER
+    cyg_uint32 index;
+
+    // Use platform specific IRQ handler, if defined
+    // Note: this macro should do a 'return' with the appropriate
+    // interrupt number if such an extended interrupt exists.  The
+    // assumption is that the line after the macro starts 'normal' processing.
+    HAL_EXTENDED_IRQ_HANDLER(index);
+#endif
+
+    return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
+}
+
+//
+// Interrupt control
+//
+
+void hal_interrupt_mask(int vector)
+{
+//    diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_MASK
+    // Use platform specific handling, if defined
+    // Note: this macro should do a 'return' for "extended" values of 'vector'
+    // Normal vectors are handled by code subsequent to the macro call.
+    HAL_EXTENDED_INTERRUPT_MASK(vector);
+#endif
+}
+
+void hal_interrupt_unmask(int vector)
+{
+//    diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
+
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+    // Use platform specific handling, if defined
+    // Note: this macro should do a 'return' for "extended" values of 'vector'
+    // Normal vectors are handled by code subsequent to the macro call.
+    HAL_EXTENDED_INTERRUPT_UNMASK(vector);
+#endif
+}
+
+void hal_interrupt_acknowledge(int vector)
+{
+
+//    diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
+#ifdef HAL_EXTENDED_INTERRUPT_UNMASK
+    // Use platform specific handling, if defined
+    // Note: this macro should do a 'return' for "extended" values of 'vector'
+    // Normal vectors are handled by code subsequent to the macro call.
+    HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
+#endif
+}
+
+void hal_interrupt_configure(int vector, int level, int up)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
+    // Use platform specific handling, if defined
+    // Note: this macro should do a 'return' for "extended" values of 'vector'
+    // Normal vectors are handled by code subsequent to the macro call.
+    HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
+#endif
+}
+
+void hal_interrupt_set_level(int vector, int level)
+{
+
+#ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
+    // Use platform specific handling, if defined
+    // Note: this macro should do a 'return' for "extended" values of 'vector'
+    // Normal vectors are handled by code subsequent to the macro call.
+    HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
+#endif
+
+    // Interrupt priorities are not configurable.
+}
+
+unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc, unsigned int num_of_chips)
+{
+    unsigned int tmp ;
+    if (is_mlc) {
+        tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) | (1 << 8);
+    } else {
+        tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & (~(1 << 8));
+    }
+
+    writew(tmp, NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF);
+    tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR);
+    if (io_sz == 16) {
+        tmp |= (1 << 14);
+    } else {
+        tmp &= (~(1 << 14));
+    }
+
+    tmp &= ~(3<<8);
+    switch(pg_sz = 2048){
+    case 2048:
+       tmp |= (1<<8);
+       break;
+    case 4096:
+       tmp |= (1<<9);
+       break;
+    }
+
+    writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
+    diag_printf("NAND: RCSR=%x\n", tmp);
+    return 0x10;
+}
+
+static void check_reset_source(void)
+{
+       unsigned int rest = readl(CCM_BASE_ADDR + CLKCTL_RCSR) & 0xF;
+
+       if (rest == 0)
+               diag_printf("hardware reset by POR\n");
+       else if (rest == 1)
+               diag_printf("hardware reset by Board reset signal\n");
+       else if ((rest & 2) == 2)
+               diag_printf("hardware reset by WDOG\n");
+       else if ((rest & 4) == 4)
+               diag_printf("hardware reset by SOFT RESET\n");
+       else if ((rest & 8) == 8)
+               diag_printf("hardware reset by JTAG SW RESET\n");
+       else
+               diag_printf("hardware reset by unknown source (REST=%x)\n", rest);
+}
+
+RedBoot_init(check_reset_source, RedBoot_INIT_LAST);
+
+static void check_correct_chip(void)
+{
+    if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
+        diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
+        diag_printf("Assuming chip version=0x%x\n", system_rev);
+    } else if (find_correct_chip == CHIP_VERSION_NONE) {
+        diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
+    }
+}
+
+RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);
diff --git a/packages/hal/arm/mx27/3stack/v2_0/cdl/hal_arm_board.cdl b/packages/hal/arm/mx27/3stack/v2_0/cdl/hal_arm_board.cdl
new file mode 100644 (file)
index 0000000..7fd8411
--- /dev/null
@@ -0,0 +1,366 @@
+# ====================================================================
+#
+#      hal_arm_board.cdl
+#
+# ====================================================================
+#####ECOSGPLCOPYRIGHTBEGIN####
+## -------------------------------------------
+## This file is part of eCos, the Embedded Configurable Operating System.
+## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+##
+## eCos is free software; you can redistribute it and/or modify it under
+## the terms of the GNU General Public License as published by the Free
+## Software Foundation; either version 2 or (at your option) any later version.
+##
+## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+## WARRANTY; without even the implied warranty of MERCHANTABILITY or
+## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+## for more details.
+##
+## You should have received a copy of the GNU General Public License along
+## with eCos; if not, write to the Free Software Foundation, Inc.,
+## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+##
+## As a special exception, if other files instantiate templates or use macros
+## or inline functions from this file, or you compile this file and link it
+## with other works to produce a work based on this file, this file does not
+## by itself cause the resulting work to be covered by the GNU General Public
+## License. However the source code for this file must still be made available
+## in accordance with section (3) of the GNU General Public License.
+##
+## This exception does not invalidate any other reasons why a work based on
+## this file might be covered by the GNU General Public License.
+##
+## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+## at http://sources.redhat.com/ecos/ecos-license/
+## -------------------------------------------
+#####ECOSGPLCOPYRIGHTEND####
+
+cdl_package CYGPKG_HAL_ARM_MX27_3STACK {
+    display       "Freescale board"
+    parent        CYGPKG_HAL_ARM_MX27
+    hardware
+    include_dir   cyg/hal
+    define_header hal_arm_board.h
+    description   "
+        This HAL platform package provides generic
+        support for the Freescale 3-Stack Board."
+
+    compile       board_misc.c board_diag.c
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS
+    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
+    implements    CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
+
+    implements    CYGHWR_HAL_ARM_DUART_UARTA
+    implements    CYGHWR_HAL_ARM_SOC_UART1
+    implements    CYGHWR_DEVS_FLASH_MXC_NAND_RESET_WORKAROUND
+
+    define_proc {
+        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_arm.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_arm_soc.h>"
+        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_board.h>"
+       puts $::cdl_header "#define HAL_PLATFORM_CPU    \"Freescale i.MX27 based\""
+        puts $::cdl_header "#define HAL_PLATFORM_BOARD  \"MX27 3-Stack\""
+        puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE  1430"
+        puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack"
+    }
+
+    cdl_component CYG_HAL_STARTUP {
+        display       "Startup type"
+        flavor        data
+        default_value {"ROM"}
+        legal_values  {"RAM" "ROM" "ROMRAM"}
+       no_define
+       define -file system.h CYG_HAL_STARTUP
+        description   "
+           When targetting the eval board it is possible to build
+           the system for either RAM bootstrap or ROM bootstrap(s). Select
+           'ram' when building programs to load into RAM using eCos GDB
+           stubs.  Select 'rom' when building a stand-alone application
+           which will be put into ROM, or for the special case of
+           building the eCos GDB stubs themselves. Using ROMRAM will allow
+           the program to exist in ROM, but be copied to RAM during startup."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_DUART_UARTA {
+        display   "ST16552 UARTA available as diagnostic/debug channel"
+        description "
+         The board has a ST16552 DUART chip. This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_interface     CYGHWR_HAL_ARM_DUART_UARTB {
+        display   "ST16552 UARTB available as diagnostic/debug channel"
+        description "
+         The board has a ST16552 DUART chip. This
+          interface allows a platform to indicate that the specified
+          serial port can be used as a diagnostic and/or debug channel."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
+        display       "Diagnostic serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option selects the baud rate used for the console port.
+            Note: this should match the value chosen for the GDB port if the
+            console and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD {
+        display       "GDB serial port baud rate"
+        flavor        data
+        legal_values  9600 19200 38400 57600 115200
+        default_value 115200
+        description   "
+            This option selects the baud rate used for the GDB port.
+            Note: this should match the value chosen for the console port if the
+            console and GDB port are the same."
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
+        display      "Number of communication channels on the board"
+        flavor       data
+        calculated   6
+    }
+
+    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
+        display          "Debug serial port"
+        active_if        CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE
+        flavor data
+        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+        default_value    0
+        description      "
+            The board has three serial ports. This option
+            chooses which port will be used to connect to a host
+            running GDB."
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT {
+         display      "Default console channel."
+         flavor       data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         calculated   0
+     }
+
+     cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL {
+         display          "Console serial port"
+         active_if        CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE
+         flavor data
+         legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
+         default_value    CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT
+         description      "
+            The board has only three serial ports.  This option
+            chooses which port will be used for console output."
+     }
+
+    cdl_component CYGBLD_GLOBAL_OPTIONS {
+        display "Global build options"
+        flavor  none
+        no_define
+        description   "
+           Global build options including control over
+           compiler flags, linker flags and choice of toolchain."
+
+
+        parent  CYGPKG_NONE
+
+        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
+            display "Global command prefix"
+            flavor  data
+            no_define
+            default_value { "arm-none-eabi" }
+            description "
+                This option specifies the command prefix used when
+                invoking the build tools."
+        }
+
+        cdl_option CYGBLD_GLOBAL_CFLAGS {
+            display "Global compiler flags"
+            flavor  data
+            no_define
+            default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            description   "
+                This option controls the global compiler flags which are used to
+                compile all packages by default. Individual packages may define
+                options which override these global flags."
+        }
+
+        cdl_option CYGBLD_GLOBAL_LDFLAGS {
+            display "Global linker flags"
+            flavor  data
+            no_define
+            default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" }
+            description   "
+                This option controls the global linker flags. Individual
+                packages may define options which override these global flags."
+        }
+
+        cdl_option CYGBLD_BUILD_GDB_STUBS {
+            display "Build GDB stub ROM image"
+            default_value 0
+            requires { CYG_HAL_STARTUP == "ROM" }
+            requires CYGSEM_HAL_ROM_MONITOR
+            requires CYGBLD_BUILD_COMMON_GDB_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
+            requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
+            requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
+            requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
+            requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
+            no_define
+            description "
+                This option enables the building of the GDB stubs for the
+                board. The common HAL controls takes care of most of the
+                build process, but the final conversion from ELF image to
+                binary data is handled by the platform CDL, allowing
+                relocation of the data if necessary."
+
+            make -priority 320 {
+                <PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
+                $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS {
+        display "Freescale MXC Board build options"
+        flavor  none
+        no_define
+        description   "
+           Package specific build options including control over
+           compiler flags used only in building this package,
+           and details of which tests are built."
+
+        cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD {
+            display "Additional compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the board HAL. These flags are used in addition
+                to the set of global flags."
+        }
+
+        cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE {
+            display "Suppressed compiler flags"
+            flavor  data
+            no_define
+            default_value { "" }
+            description   "
+                This option modifies the set of compiler flags for
+                building the board HAL. These flags are removed from
+                the set of global flags if present."
+        }
+
+    }
+
+    cdl_component CYGHWR_MEMORY_LAYOUT {
+        display "Memory layout"
+        flavor data
+        no_define
+        calculated { (CYG_HAL_STARTUP == "RAM")    ? "arm_board_ram" :
+                     (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" :
+                                                    "arm_board_rom" }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
+            display "Memory layout linker script fragment"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
+            calculated { (CYG_HAL_STARTUP == "RAM") ?    "<pkgconf/mlt_arm_board_ram.ldi>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.ldi>" :
+                                                         "<pkgconf/mlt_arm_board_rom.ldi>" }
+        }
+
+        cdl_option CYGHWR_MEMORY_LAYOUT_H {
+            display "Memory layout header file"
+            flavor data
+            no_define
+            define -file system.h CYGHWR_MEMORY_LAYOUT_H
+            calculated { (CYG_HAL_STARTUP == "RAM")    ? "<pkgconf/mlt_arm_board_ram.h>" :
+                         (CYG_HAL_STARTUP == "ROMRAM") ? "<pkgconf/mlt_arm_board_romram.h>" :
+                                                         "<pkgconf/mlt_arm_board_rom.h>" }
+        }
+    }
+
+    cdl_option CYGSEM_HAL_ROM_MONITOR {
+        display       "Behave as a ROM monitor"
+        flavor        bool
+        default_value 0
+        parent        CYGPKG_HAL_ROM_MONITOR
+        requires      { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" }
+        description   "
+            Enable this option if this program is to be used as a ROM monitor,
+            i.e. applications will be loaded into RAM on the board, and this
+            ROM monitor may process exceptions or interrupts generated from the
+            application. This enables features such as utilizing a separate
+            interrupt stack when exceptions are generated."
+    }
+
+    cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
+         display       "Work with a ROM monitor"
+         flavor        booldata
+         legal_values  { "Generic" "GDB_stubs" }
+         default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
+         parent        CYGPKG_HAL_ROM_MONITOR
+         requires      { CYG_HAL_STARTUP == "RAM" }
+         description   "
+             Support can be enabled for different varieties of ROM monitor.
+             This support changes various eCos semantics such as the encoding
+             of diagnostic output, or the overriding of hardware interrupt
+             vectors.
+             Firstly there is \"Generic\" support which prevents the HAL
+             from overriding the hardware vectors that it does not use, to
+             instead allow an installed ROM monitor to handle them. This is
+             the most basic support which is likely to be common to most
+             implementations of ROM monitor.
+             \"GDB_stubs\" provides support when GDB stubs are included in
+             the ROM monitor or boot ROM."
+     }
+
+    cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
+        display       "Redboot HAL options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+        description   "
+            This option lists the target's requirements for a valid Redboot
+            configuration."
+
+            compile -library=libextras.a redboot_cmds.c
+
+        cdl_option CYGBLD_BUILD_REDBOOT_BIN {
+            display       "Build Redboot ROM binary image"
+            active_if     CYGBLD_BUILD_REDBOOT
+            default_value 1
+            no_define
+            description "This option enables the conversion of the Redboot ELF
+                         image to a binary image suitable for ROM programming."
+
+            make -priority 325 {
+                <PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
+                $(OBJCOPY) --strip-debug $< $(@:.bin=.img)
+                $(OBJCOPY) -O srec $< $(@:.bin=.srec)
+                $(OBJCOPY) -O binary $< $@
+            }
+        }
+    }
+
+    cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS {
+        display       "Redboot HAL variant options"
+        flavor        none
+        no_define
+        parent        CYGPKG_REDBOOT
+        active_if     CYGPKG_REDBOOT
+
+        # RedBoot details
+        requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0xA0008000 }
+        define_proc {
+            puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00"
+        }
+    }
+}
diff --git a/packages/hal/arm/mx27/3stack/v2_0/include/fsl_board.h b/packages/hal/arm/mx27/3stack/v2_0/include/fsl_board.h
new file mode 100644 (file)
index 0000000..e46bf97
--- /dev/null
@@ -0,0 +1,99 @@
+#ifndef CYGONCE_FSL_BOARD_H
+#define CYGONCE_FSL_BOARD_H
+
+//=============================================================================
+//
+//      Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_soc.h>     // Hardware definitions
+
+#define PMIC_SPI_BASE            CSPI2_BASE_ADDR
+#define PMIC_SPI_CHIP_SELECT_NO  SPI_CTRL_CS0
+
+#define PBC_BASE                 SOC_CS5_BASE    /* Peripheral Bus Controller */
+#define PBC_LED_CTRL            (PBC_BASE + 0x20000)
+#define PBC_SB_STAT             (PBC_BASE + 0x20008)
+#define PBC_ID_AAAA             (PBC_BASE + 0x20040)
+#define PBC_ID_5555             (PBC_BASE + 0x20048)
+#define PBC_VERSION             (PBC_BASE + 0x20050)
+#define PBC_ID_CAFE             (PBC_BASE + 0x20058)
+#define PBC_INT_STAT            (PBC_BASE + 0x20068)
+#define PBC_INT_MASK            (PBC_BASE + 0x20010)
+#define PBC_INT_REST            (PBC_BASE + 0x20020)
+#define PBC_SW_RESET            (PBC_BASE + 0x20060)
+
+#define BOARD_CS_LAN_BASE        (SOC_CS5_BASE + 0x00000)
+#define BOARD_CS_UART_BASE       (SOC_CS5_BASE + 0x08000)
+
+#define BOARD_FLASH_START       SOC_CS0_BASE
+#define REDBOOT_IMAGE_SIZE       0x40000
+
+#define RAM_BANK0_BASE           SOC_CSD0_BASE
+
+#define SDRAM_BASE_ADDR          SOC_CSD0_BASE
+#define SDRAM_SIZE               0x08000000
+
+#define EXT_UART_x16
+//#define EXT_UART_x32
+#define LED_MAX_NUM    8
+#define LED_IS_ON(n)    ((readw(PBC_LED_CTRL) & (1<<(n))) != 0)
+#define TURN_LED_ON(n)  writew((readw(PBC_LED_CTRL)|(1<<(n))), PBC_LED_CTRL)
+#define TURN_LED_OFF(n) writew((readw(PBC_LED_CTRL)&(~(1<<(n)))), PBC_LED_CTRL)
+
+#define FEC_PHY_ADDR    0x1F
+
+#define BOARD_DEBUG_LED(n)                     \
+    CYG_MACRO_START                            \
+        if (n >= 0 && n < LED_MAX_NUM) {       \
+               if (LED_IS_ON(n))               \
+                       TURN_LED_OFF(n);        \
+               else                            \
+                       TURN_LED_ON(n);         \
+       }                                       \
+    CYG_MACRO_END
+
+#define BOARD_PBC_VERSION       (*(volatile unsigned short*)(PBC_VERSION))
+
+#if !defined(__ASSEMBLER__)
+enum {
+    BOARD_TYPE_UNKNOWN,
+    BOARD_TYPE_3STACK,
+};
+#endif
+
+#endif /* CYGONCE_FSL_BOARD_H */
diff --git a/packages/hal/arm/mx27/3stack/v2_0/include/hal_platform_setup.h b/packages/hal/arm/mx27/3stack/v2_0/include/hal_platform_setup.h
new file mode 100644 (file)
index 0000000..e588fcb
--- /dev/null
@@ -0,0 +1,673 @@
+#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
+#define CYGONCE_HAL_PLATFORM_SETUP_H
+
+//=============================================================================
+//
+//      hal_platform_setup.h
+//
+//      Platform specific support for HAL (assembly code)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <pkgconf/system.h>             // System-wide configuration info
+#include CYGBLD_HAL_VARIANT_H           // Variant specific configuration
+#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
+#include <cyg/hal/hal_soc.h>            // Variant specific hardware definitions
+#include <cyg/hal/hal_mmu.h>            // MMU definitions
+#include <cyg/hal/fsl_board.h>          // Platform specific hardware definitions
+
+#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1 _platform_setup1
+#define CYGHWR_HAL_ARM_HAS_MMU
+
+#ifdef CYG_HAL_STARTUP_ROMRAM
+#define CYGSEM_HAL_ROM_RESET_USES_JUMP
+#endif
+
+#define CYGHWR_HAL_ROM_VADDR        0x0
+
+// This macro represents the initial startup code for the platform
+// r11 is reserved to contain chip rev info in this file
+    .macro  _platform_setup1
+FSL_BOARD_SETUP_START:
+    // invalidate I/D cache/TLB and drain write buffer
+    mov r0, #0
+    mcr 15, 0, r0, c7, c7, 0    /* invalidate I cache and D cache */
+    mcr 15, 0, r0, c8, c7, 0    /* invalidate TLBs */
+    mcr 15, 0, r0, c7, c10, 4   /* Drain the write buffer */
+
+init_aipi_start:
+    init_aipi
+
+    mov r0, #SDRAM_NON_FLASH_BOOT
+    ldr r1, AVIC_VECTOR0_ADDR_W
+    str r0, [r1] // for checking boot source from nand, nor or sdram
+
+    // setup System Controls
+    ldr r0, SOC_SYSCTRL_BASE_W
+    mov r1, #0x03
+    str r1, [r0, #(SOC_SYSCTRL_PCSR - SOC_SYSCTRL_BASE)]
+    ldr r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
+    and r1, r1, #0xFFFFFFF0
+    orr r1, r1, #9
+    str r1, [r0, #(SOC_SYSCTRL_FMCR - SOC_SYSCTRL_BASE)]
+
+init_max_start:
+    init_max
+init_drive_strength_start:
+    init_drive_strength
+init_cs5_start:
+    init_cs5
+
+    // check if sdram has been setup
+    cmp pc, #SDRAM_BASE_ADDR
+    blo init_clock_start
+    cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
+    blo HWInitialise_skip_SDRAM_setup
+init_clock_start:
+    init_clock
+
+    // Now we must boot from Flash
+    mov r0, #NOR_FLASH_BOOT
+    ldr r1, AVIC_VECTOR0_ADDR_W
+    str r0, [r1]
+
+init_sdram_start:
+    setup_sdram_ddr
+
+HWInitialise_skip_SDRAM_setup:
+    ldr r0, NFC_BASE_W
+    add r2, r0, #0x800      // 2K window
+    cmp pc, r0
+    blo Normal_Boot_Continue
+    cmp pc, r2
+    bhi Normal_Boot_Continue
+NAND_Boot_Start:
+    /* Copy image from flash to SDRAM first */
+    ldr r1, MXC_REDBOOT_ROM_START
+
+1:  ldmia r0!, {r3-r10}
+    stmia r1!, {r3-r10}
+    cmp r0, r2
+    blo 1b
+
+    /* Jump to SDRAM */
+    ldr r1, CONST_0xFFF
+    and r0, pc, r1     /* offset of pc */
+    ldr r1, MXC_REDBOOT_ROM_START
+    add r1, r1, #0x10
+    add pc, r0, r1
+    nop
+    nop
+    nop
+    nop
+
+NAND_Copy_Main:
+    // Check if x16/2kb page
+    ldr r7, SOC_SYSCTRL_BASE_W
+    ldr r7, [r7, #0x14]
+    ands r7, r7, #(1 << 5)
+
+    mov r0, #NAND_FLASH_BOOT
+    ldr r1, AVIC_VECTOR0_ADDR_W
+    str r0, [r1]
+    mov r0, #MXCFIS_NAND
+    ldr r1, AVIC_VECTOR1_ADDR_W
+    str r0, [r1]
+
+    ldr r0, NFC_BASE_W   //r0: nfc base. Reloaded after each page copying
+    mov r1, #0x800       //r1: starting flash addr to be copied. Updated constantly
+    add r2, r0, #0x800     //2K Page:: r2: end of 1st RAM buf. Doesn't change
+    addeq r2, r0, #0x200   //512 Page:: r2: end of 1st RAM buf. Doesn't change
+    add r12, r0, #0xE00  //r12: NFC register base. Doesn't change
+    ldr r11, MXC_REDBOOT_ROM_START
+    add r13, r11, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
+    add r11, r11, r1     //r11: starting SDRAM address for copying. Updated constantly
+
+    //unlock internal buffer
+    mov r3, #0x2
+    strh r3, [r12, #0xA]
+
+Nfc_Read_Page:
+//  NFC_CMD_INPUT(FLASH_Read_Mode1);
+    mov r3, #0x0
+    nfc_cmd_input
+
+    // Check if x16/2kb page
+    ldr r7, SOC_SYSCTRL_BASE_W
+    ldr r7, [r7, #0x14]
+    ands r7, r7, #(1 << 5)
+
+    bne nfc_addr_ops_2kb
+//    start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+    mov r3, r1
+    do_addr_input       //1st addr cycle
+    mov r3, r1, lsr #9
+    do_addr_input       //2nd addr cycle
+    mov r3, r1, lsr #17
+    do_addr_input       //3rd addr cycle
+    mov r3, r1, lsr #25
+    do_addr_input       //4th addr cycle
+    b end_of_nfc_addr_ops
+
+nfc_addr_ops_2kb:
+//    start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
+    mov r3, #0
+    do_addr_input       //1st addr cycle
+    mov r3, #0
+    do_addr_input       //2nd addr cycle
+    mov r3, r1, lsr #11
+    do_addr_input       //3rd addr cycle
+    mov r3, r1, lsr #19
+    do_addr_input       //4th addr cycle
+    mov r3, r1, lsr #27
+    do_addr_input       //4th addr cycle
+
+//    NFC_CMD_INPUT(FLASH_Read_Mode1_2K);
+    mov r3, #0x30
+    nfc_cmd_input
+
+end_of_nfc_addr_ops:
+//    NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
+//        writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
+//               NAND_FLASH_CONFIG1_REG);
+    mov r8, #0
+    bl nfc_data_output
+    bl do_wait_op_done
+    // Check if x16/2kb page
+    ldr r7, SOC_SYSCTRL_BASE_W
+    ldr r7, [r7, #0x14]
+    ands r7, r7, #(1 << 5)
+
+    beq nfc_addr_data_output_done_512
+
+// For 2K page - 2nd 512
+    mov r8, #1
+    bl nfc_data_output
+    bl do_wait_op_done
+
+// 3rd 512
+    mov r8, #2
+    bl nfc_data_output
+    bl do_wait_op_done
+
+// 4th 512
+    mov r8, #3
+    bl nfc_data_output
+    bl do_wait_op_done
+// end of 4th
+
+    // check for bad block
+    mov r3, r1, lsl #(32-17)    // get rid of block number
+    cmp r3, #(0x800 << (32-17)) // check if not page 0 or 1
+    b nfc_addr_data_output_done
+nfc_addr_data_output_done_512:
+    // check for bad block
+    mov r3, r1, lsl #(32-5-9)    // get rid of block number
+    cmp r3, #(512 << (32-5-9))   // check if not page 0 or 1
+
+nfc_addr_data_output_done:
+    bhi Copy_Good_Blk
+    add r4, r0, #0x800  //r3 -> spare area buf 0
+    ldrh r4, [r4, #0x4]
+    and r4, r4, #0xFF00
+    cmp r4, #0xFF00
+    beq Copy_Good_Blk
+    // really sucks. Bad block!!!!
+    cmp r3, #0x0
+    beq Skip_bad_block
+    // even suckier since we already read the first page!
+
+    // Check if x16/2kb page
+    ldr r7, SOC_SYSCTRL_BASE_W
+    ldr r7, [r7, #0x14]
+    ands r7, r7, #(1 << 5)
+
+    subeq r11, r11, #512  //rewind 1 page for the sdram pointer
+    subeq r1, r1, #512    //rewind 1 page for the flash pointer
+
+    // for 2k page
+    subne r11, r11, #0x800  //rewind 1 page for the sdram pointer
+    subne r1, r1, #0x800    //rewind 1 page for the flash pointer
+
+Skip_bad_block:
+    // Check if x16/2kb page
+    ldr r7, SOC_SYSCTRL_BASE_W
+    ldr r7, [r7, #0x14]
+    ands r7, r7, #(1 << 5)
+
+    addeq r1, r1, #(32*512)
+    addne r1, r1, #(64*2048)
+
+    b Nfc_Read_Page
+Copy_Good_Blk:
+    //copying page
+1:  ldmia r0!, {r3-r10}
+    stmia r11!, {r3-r10}
+    cmp r0, r2
+    blo 1b
+    cmp r11, r13
+    bge NAND_Copy_Main_done
+    // Check if x16/2kb page
+    ldr r7, SOC_SYSCTRL_BASE_W
+    ldr r7, [r7, #0x14]
+    ands r7, r7, #(1 << 5)
+
+    addeq r1, r1, #0x200
+    addne r1, r1, #0x800
+    mov r0, #NFC_BASE
+    b Nfc_Read_Page
+
+NAND_Copy_Main_done:
+
+Normal_Boot_Continue:
+
+#ifdef CYG_HAL_STARTUP_ROMRAM    /* enable running from RAM */
+    /* Copy image from flash to SDRAM first */
+    ldr r0, =0xFFFFF000
+    and r0, r0, pc
+    ldr r1, MXC_REDBOOT_ROM_START
+    cmp r0, r1
+    beq HWInitialise_skip_SDRAM_copy
+
+    add r2, r0, #REDBOOT_IMAGE_SIZE
+
+1:  ldmia r0!, {r3-r10}
+    stmia r1!, {r3-r10}
+    cmp r0, r2
+    ble 1b
+
+    /* Jump to SDRAM */
+    ldr r1, =0xFFFF
+    and r0, pc, r1      /* offset of pc */
+    ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
+    add pc, r0, r1
+    nop
+    nop
+    nop
+    nop
+#endif /* CYG_HAL_STARTUP_ROMRAM */
+
+HWInitialise_skip_SDRAM_copy:
+
+//trace
+init_cs0_sync_start:
+    init_cs0_sync
+
+NAND_ClockSetup:
+    ldr r1, =(SOC_CRM_BASE)
+    ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+/*Get chip ID://eq:i.MX27 TO1; neq:i.MX27 TO2*/
+    ldr r1, =SOC_SI_ID_REG
+    ldr r1, [r1]
+    ands r1, r1, #0xF0000000
+
+    orreq r2, r2, #0xF000
+    orrne r2, r2, #0x01C0
+
+    ldr r1, =(SOC_CRM_BASE)
+    str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+
+/* end of NAND clock divider setup */
+
+    // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR
+    ldr r1, =(SOC_SYSCTRL_GPCR)
+    ldr r2, [r1]
+    orr r2, r2, #0x700
+    str r2, [r1]
+
+    // Set up a stack [for calling C code]
+    ldr r1, =__startup_stack
+    ldr r2, =RAM_BANK0_BASE
+    orr sp, r1, r2
+
+    // Create MMU tables
+    bl hal_mmu_init
+
+    // Enable MMU
+    ldr r2, =10f
+    mrc MMU_CP, 0, r1, MMU_Control, c0      // get c1 value to r1 first
+    orr r1, r1, #7                          // enable MMU bit
+    mcr MMU_CP, 0, r1, MMU_Control, c0
+    mov pc,r2    /* Change address spaces */
+    nop
+    nop
+    nop
+10:
+    // Save shadow copy of BCR, also hardware configuration
+    ldr r1, =_board_BCR
+    str r2,[r1]
+    ldr r1, =_board_CFG
+    str r9,[r1]                // Saved far above...
+
+    .endm                       // _platform_setup1
+
+do_wait_op_done:
+    1:
+        ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+        ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
+        beq 1b
+    bx lr     // do_wait_op_done
+
+nfc_data_output:
+    mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
+    strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
+
+    // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
+    strh r8, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
+    // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
+    mov r3, #FDO_PAGE_SPARE_VAL
+    strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+    bx lr
+
+#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
+#define PLATFORM_SETUP1
+#endif
+
+    .macro init_clock
+        ldr r0, SOC_CRM_BASE_W
+        // disable MPLL/SPLL first
+        ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+        bic r1, r1, #0x3
+        str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+        /* Get the chip version and configure PLLs*/
+        ldr r1, SOC_SI_ID_REG_W
+        ldr r1, [r1]
+        ands r1, r1, #0xF0000000
+
+       ldreq r1, CRM_MPCTL0_VAL_W
+       ldrne r1, CRM_MPCTL0_VAL2_W
+        str r1, [r0, #(SOC_CRM_MPCTL0 - SOC_CRM_BASE)]
+
+        ldreq r1, CRM_SPCTL0_VAL_W
+        ldrne r1, CRM_SPCTL0_VAL2_W
+        str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)]
+
+        // enable/restart SPLL/MPLL
+        ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+#ifdef PLL_REF_CLK_32768HZ
+        // Make sure to use CKIL
+        bic r1, r1, #(3 << 16)
+#else
+        orr r1, r1, #(3 << 16)      // select 26MHz
+#endif
+        orr r1, r1, #0x000C0000
+        orr r1, r1, #0x00000003
+        str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+        // add some delay here
+        mov r1, #0x1000
+    1:  subs r1, r1, #0x1
+        bne 1b
+
+        //Check The chip version TO1 or TO2
+        ldr r1, SOC_SI_ID_REG_W
+        ldr r1, [r1]
+        ands r1, r1, #0xF0000000
+
+        ldreq r2, SOC_CRM_CSCR_W
+        ldrne r2, SOC_CRM_CSCR2_W
+        str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+
+        //for i.MX27 TO2, Set divider of H264_CLK to zero, NFC to 3.
+        ldrne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+        bicne r2, r2, #0x0000FC00
+        strne r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+
+        /* Configure PCDR */
+        /* Configure PCDR1 */
+        ldr r1, SOC_CRM_PCDR1_W
+        str r1, [r0, #(SOC_CRM_PCDR1 - SOC_CRM_BASE)]
+
+        // Configure PCCR0 and PCCR1
+        ldr r1, SOC_CRM_PCCR0_W
+        str r1, [r0, #(SOC_CRM_PCCR0 - SOC_CRM_BASE)]
+
+        ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
+        orr r1, r1, #0x0780
+        str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)]
+        // make default CLKO to be FCLK
+        ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
+        and r1, r1, #0xFFFFFFE0
+        orr r1, r1, #0x7
+        str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)]
+    .endm //init_clock
+
+    /* CS0 sync mode setup */
+    .macro init_cs0_sync
+        /*
+         * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
+         */
+        /* Flash reset command */
+        ldr     r0, CS0_BASE_ADDR_W
+        mov     r1, #0x00F0
+        strh    r1, [r0]
+        /* 1st command */
+        ldr     r2, CS0_CMD_0xAAA
+        add     r2, r2, r0
+        mov     r1, #0x00AA
+        strh    r1, [r2]
+        /* 2nd command */
+        ldr     r2, CS0_CMD_0x554
+        add     r2, r2, r0
+        mov     r1, #0x0055
+        strh    r1, [r2]
+        /* 3rd command */
+        ldr     r2, CS0_CMD_0xAAA
+        add     r2, r2, r0
+        mov     r1, #0x00D0
+        strh    r1, [r2]
+        /* Write flash config register */
+        ldr     r1, CS0_CFG_0x66CA
+        strh    r1, [r2]
+        /* Flash reset command */
+        mov     r1, #0x00F0
+        strh    r1, [r0]
+
+        ldr r0, =SOC_CS0_CTL_BASE
+        ldr r1, CS0_0x23524E80
+        str r1, [r0, #CSCRU_OFFSET]
+        ldr r1, CS0_0x10000D03
+        str r1, [r0, #CSCRL_OFFSET]
+        ldr r1, CS0_0x00720900
+        str r1, [r0, #CSCRA_OFFSET]
+    .endm /* init_cs0_sync */
+
+    .macro init_cs5 /* 3-Stack board expanded IOs */
+        ldr r1, SOC_CS5_CTL_BASE_W
+        ldr r2, CS5_CSCRU_0x0000DCF6
+        str r2, [r1, #CSCRU_OFFSET]
+        ldr r2, CS5_CSCRL_0x444A4541
+        str r2, [r1, #CSCRL_OFFSET]
+        ldr r2, CS5_CSCRA_0x44443302
+        str r2, [r1, #CSCRA_OFFSET]
+    .endm   /* init_cs5 */
+
+    .macro init_aipi
+        // setup AIPI1 and AIPI2
+        mov r0, #SOC_AIPI1_BASE
+        ldr r1, AIPI1_0x20040304
+        str r1, [r0]  /* PSR0 */
+        ldr r2, AIPI1_0xDFFBFCFB
+        str r2, [r0, #4]  /* PSR1 */
+        // set r0 = AIPI2 base
+        add r0, r0, #0x20000
+        mov r1, #0x0
+        str r1, [r0]  /* PSR0 */
+        mov r2, #0xFFFFFFFF
+        str r2, [r0, #4]  /* PSR1 */
+    .endm // init_aipi
+
+    .macro init_max
+        ldr r0, SOC_MAX_BASE_W
+        add r1, r0, #MAX_SLAVE_PORT1_OFFSET
+        add r2, r0, #MAX_SLAVE_PORT2_OFFSET
+        add r0, r0, #MAX_SLAVE_PORT0_OFFSET
+
+        /* MPR and AMPR */
+        ldr r6, SOC_MAX_0x00302145         /* Priority SLCD>EMMA>DMA>Codec>DAHB>IAHB */
+        str r6, [r0, #MAX_SLAVE_MPR_OFFSET]   /* same for all slave ports */
+        str r6, [r0, #MAX_SLAVE_AMPR_OFFSET]
+        str r6, [r1, #MAX_SLAVE_MPR_OFFSET]
+        str r6, [r1, #MAX_SLAVE_AMPR_OFFSET]
+        str r6, [r2, #MAX_SLAVE_MPR_OFFSET]
+        str r6, [r2, #MAX_SLAVE_AMPR_OFFSET]
+    .endm //init_max
+
+   .macro init_drive_strength
+        ldr r0, SOC_SYSCTRL_BASE_W
+        ldr r1, DS_0x55555555
+        str r1, [r0, #(SOC_SYSCTRL_DSCR3 - SOC_SYSCTRL_BASE)]
+        str r1, [r0, #(SOC_SYSCTRL_DSCR5 - SOC_SYSCTRL_BASE)]
+        str r1, [r0, #(SOC_SYSCTRL_DSCR6 - SOC_SYSCTRL_BASE)]
+        ldr r1, DS_0x00005005
+        str r1, [r0, #(SOC_SYSCTRL_DSCR7 - SOC_SYSCTRL_BASE)]
+        ldr r1, DS_0x15555555
+        str r1, [r0, #(SOC_SYSCTRL_DSCR8 - SOC_SYSCTRL_BASE)]
+    .endm       // init_drive_strength
+
+    .macro setup_sdram_ddr
+        ldr r0, SOC_ESDCTL_BASE_W
+        mov r2, #SOC_CSD0_BASE
+        mov r1, #0x8        // initial reset
+        str r1, [r0, #0x10]
+        // Hold for more than 200ns
+        ldr r1, =0x10000
+    1:
+        subs r1, r1, #0x1
+        bne 1b
+
+        mov r1, #0x4
+        str r1, [r0, #0x10]
+
+        //Check The chip version TO1 or TO2
+        ldr r1, SOC_SI_ID_REG_W
+        ldr r1, [r1]
+        ands r1, r1, #0xF0000000
+        // add Latency on CAS only for TO2
+        ldreq r1, SDRAM_0x00795729
+        ldrne r1, SDRAM_0x00795429
+
+        str r1, [r0, #0x4]
+        ldr r1, SDRAM_0x92200000
+        str r1, [r0, #0x0]
+        ldr r1, [r2, #0xF00]
+        ldr r1, SDRAM_0xA2200000
+        str r1, [r0, #0x0]
+        ldr r1, [r2, #0xF00]
+        ldr r1, [r2, #0xF00]
+        ldr r1, SDRAM_0xB2200000
+        str r1, [r0, #0x0]
+        ldrb r1, [r2, #0x33]
+        add r3, r2, #0x1000000
+        ldrb r1, [r3]
+        ldr r1, SDRAM_0x82228485
+        str r1, [r0, #0x0]
+    .endm   // setup_sdram_ddr
+
+   .macro nfc_cmd_input
+        strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
+        mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
+        strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+        bl do_wait_op_done
+    .endm   // nfc_cmd_input
+
+    .macro do_addr_input
+        and r3, r3, #0xFF
+        strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
+        mov r3, #NAND_FLASH_CONFIG2_FADD_EN
+        strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
+        bl do_wait_op_done
+    .endm   // do_addr_input
+
+#define PLATFORM_VECTORS         _platform_vectors
+    .macro  _platform_vectors
+        .globl  _board_BCR, _board_CFG
+_board_BCR:   .long   0       // Board Control register shadow
+_board_CFG:   .long   0       // Board Configuration (read at RESET)
+    .endm
+
+MXC_REDBOOT_ROM_START:      .word   SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
+CONST_0xFFF:                .word   0xFFF
+AVIC_VECTOR0_ADDR_W:        .word   MXCBOOT_FLAG_REG
+AVIC_VECTOR1_ADDR_W:        .word   MXCFIS_FLAG_REG
+SOC_SYSCTRL_BASE_W:         .word   SOC_SYSCTRL_BASE
+SOC_MAX_BASE_W:             .word   SOC_MAX_BASE
+SOC_MAX_0x00302145:         .word   0x00302145
+SOC_CRM_BASE_W:             .word   SOC_CRM_BASE
+CRM_MPCTL0_VAL_W:           .word   CRM_MPCTL0_VAL
+CRM_SPCTL0_VAL_W:           .word   CRM_SPCTL0_VAL
+SOC_CRM_CSCR_W:             .word   CRM_CSCR_VAL
+CRM_MPCTL0_VAL2_W:           .word   CRM_MPCTL0_VAL2
+CRM_SPCTL0_VAL2_W:           .word   CRM_SPCTL0_VAL2
+SOC_CRM_CSCR2_W:             .word   CRM_CSCR_VAL2
+SOC_CRM_PCDR1_W:            .word   0x09030913   // p1=20 p2=10 p3=4 p4=10
+SOC_CRM_PCCR0_W:            .word   0x3108480F
+SOC_CS5_CTL_BASE_W:         .word   SOC_CS5_CTL_BASE
+CS5_CSCRU_0x0000DCF6:       .word   0x0000DCF6
+CS5_CSCRL_0x444A4541:       .word   0x444A4541
+CS5_CSCRA_0x44443302:       .word   0x44443302
+NFC_BASE_W:                 .word   NFC_BASE
+SOC_ESDCTL_BASE_W:          .word   SOC_ESDCTL_BASE
+SDRAM_0x00795429:           .word   0x00795429
+SDRAM_0x00795729:           .word   0x00795729
+SDRAM_0x92200000:           .word   0x92200000
+SDRAM_0xA2200000:           .word   0xA2200000
+SDRAM_0xB2200000:           .word   0xB2200000
+SDRAM_0x82228485:           .word   0x82228485
+CS0_0x0000CC03:             .word   0x0000CC03
+CS0_0xA0330D01:             .word   0xA0330D01
+CS0_0x00220800:             .word   0x00220800
+CS0_0x23524E80:             .word   0x23524E80
+CS0_0x10000D03:             .word   0x10000D03
+CS0_0x00720900:             .word   0x00720900
+CS0_CMD_0xAAA:              .word   0x0AAA
+CS0_CMD_0x554:              .word   0x0554
+CS0_CFG_0x66CA:                    .word   0x66CA
+CS0_BASE_ADDR_W:            .word   CS0_BASE_ADDR
+SOC_CS0_CTL_BASE_W:         .word   SOC_CS0_CTL_BASE
+DS_0x55555555:              .word   0x55555555
+DS_0x00005005:              .word   0x00005005
+DS_0x15555555:              .word   0x15555555
+AIPI1_0x20040304:           .word   0x20040304
+AIPI1_0xDFFBFCFB:           .word   0xDFFBFCFB
+PBC_BASE_W:                 .word   PBC_BASE
+SOC_SI_ID_REG_W:            .word   SOC_SI_ID_REG
+
+/*---------------------------------------------------------------------------*/
+/* end of hal_platform_setup.h                                               */
+#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
diff --git a/packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h b/packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.h
new file mode 100644 (file)
index 0000000..f203560
--- /dev/null
@@ -0,0 +1,20 @@
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#ifndef __ASSEMBLER__
+#include <cyg/infra/cyg_type.h>
+#include <stddef.h>
+
+#endif
+#define CYGMEM_REGION_ram (0x00000000)
+#define CYGMEM_REGION_ram_SIZE (0x7F00000)
+#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
+#define CYGMEM_REGION_rom (0xA7F00000)
+#define CYGMEM_REGION_rom_SIZE (0x100000)
+#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
+#ifndef __ASSEMBLER__
+extern char CYG_LABEL_NAME (__heap1) [];
+#endif
+#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
+#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_ram_SIZE - (size_t) CYG_LABEL_NAME (__heap1))
diff --git a/packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi b/packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.ldi
new file mode 100644 (file)
index 0000000..8f763de
--- /dev/null
@@ -0,0 +1,31 @@
+// eCos memory layout - Fri Oct 20 05:56:55 2000
+
+// This is a generated file - do not edit
+
+#include <cyg/infra/cyg_type.inc>
+
+MEMORY
+{
+    ram : ORIGIN = 0, LENGTH = 0x7F00000
+    rom : ORIGIN = 0xA7F00000, LENGTH = 0x100000
+}
+
+SECTIONS
+{
+    SECTIONS_BEGIN
+    SECTION_rom_vectors (rom, 0xA7F00000, LMA_EQ_VMA)
+    SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA)
+    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
+    SECTION_data (ram, 0x8000, FOLLOWING (.gcc_except_table))
+    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
+    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
+    SECTIONS_END
+}
diff --git a/packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt b/packages/hal/arm/mx27/3stack/v2_0/include/pkgconf/mlt_arm_board_romram.mlt
new file mode 100644 (file)
index 0000000..de6d40d
--- /dev/null
@@ -0,0 +1,14 @@
+version 0
+region ram 0 7F00000 0 !
+region rom A7F00000 100000 1 !
+section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
+section data 0 1 1 1 1 1 0 0 8000 bss !
+section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
+section heap1 0 8 0 0 0 0 0 0 !
+section rom_vectors 0 1 0 1 1 1 1 1 A7F00000 A7F00000 text text !
+section text 0 4 0 1 0 1 0 1 fini fini !
+section fini 0 4 0 1 0 1 0 1 rodata rodata !
+section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
+section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
+section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
+section gcc_except_table 0 4 0 1 0 0 0 1 data !
diff --git a/packages/hal/arm/mx27/3stack/v2_0/include/plf_io.h b/packages/hal/arm/mx27/3stack/v2_0/include/plf_io.h
new file mode 100644 (file)
index 0000000..e1004c7
--- /dev/null
@@ -0,0 +1,69 @@
+#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H
+
+//=============================================================================
+//
+//      plf_io.h
+//
+//      Platform specific support (register layout, etc)
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//=============================================================================
+
+#include <cyg/hal/fsl_board.h>
+#include <cyg/hal/hal_soc.h>
+
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_)                                                           \
+    CYG_MACRO_START                                                                                  \
+    {                                                                                                \
+      extern unsigned int system_rev;                                                                \
+             /* Next ATAG_MEM. */                                                                    \
+         _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long);        \
+         _p_->hdr.tag = ATAG_MEM;                                                                    \
+         /* Round up so there's only one bit set in the memory size.                                 \
+         * Don't double it if it's already a power of two, though.                                   \
+         */                                                                                          \
+         _p_->u.mem.size  = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE);                                 \
+         if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE)                                               \
+                 _p_->u.mem.size <<= 1;                                                              \
+         _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram);                              \
+         _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size);                                          \
+         _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long);   \
+         _p_->hdr.tag = ATAG_REVISION;                                                               \
+         _p_->u.revision.rev = system_rev;                                                           \
+    }                                                                                               \
+    CYG_MACRO_END
+
+#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
diff --git a/packages/hal/arm/mx27/3stack/v2_0/include/plf_mmap.h b/packages/hal/arm/mx27/3stack/v2_0/include/plf_mmap.h
new file mode 100644 (file)
index 0000000..e66a2fb
--- /dev/null
@@ -0,0 +1,69 @@
+#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
+//=============================================================================
+//
+//      plf_mmap.h
+//
+//      Platform specific memory map support
+//
+//=============================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//===========================================================================
+
+#include <cyg/hal/hal_misc.h>
+
+// Get the pagesize for a particular virtual address:
+
+// This does not depend on the vaddr.
+#define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START      \
+    (pagesize) = SZ_1M;                                         \
+CYG_MACRO_END
+
+// Get the physical address from a virtual address:
+
+#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START           \
+    cyg_uint32 _v_ = (cyg_uint32)(vaddr);                                  \
+    if ( _v_ < 128 * SZ_1M )          /* SDRAM */                           \
+        _v_ += 0xA00u * SZ_1M;                                             \
+    else if ( _v_ < 0xF00u * SZ_1M )                                       \
+        /* no change */ ;                                                  \
+    else if ( _v_ < 0xF01u * SZ_1M ) /* Boot ROM */                        \
+        _v_ -= 0xF00u * SZ_1M;                                             \
+    else                             /* Rest of it */                      \
+        /* no change */ ;                                                  \
+    (paddr) = _v_;                                                         \
+CYG_MACRO_END
+
+//---------------------------------------------------------------------------
+#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
diff --git a/packages/hal/arm/mx27/3stack/v2_0/misc/redboot_ROMRAM.ecm b/packages/hal/arm/mx27/3stack/v2_0/misc/redboot_ROMRAM.ecm
new file mode 100644 (file)
index 0000000..b24970f
--- /dev/null
@@ -0,0 +1,120 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    mx27_3stack ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_ARM current ;
+    package -hardware CYGPKG_HAL_ARM_MX27 current ;
+    package -hardware CYGPKG_HAL_ARM_MX27_3STACK current ;
+    package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+    package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+    package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+    package -hardware CYGPKG_DEVS_ETH_FEC current ;
+    package -hardware CYGPKG_COMPRESS_ZLIB current ;
+    package -hardware CYGPKG_IO_FLASH current ;
+    package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+    package -hardware CYGPKG_DEVS_MXC_SPI current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+    inferred_value 1