TX51 RedBoot Release 2011-12-23

diff --git a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
index ca4d18b9929bacf76c1910c238a3e31987defed3..39b7b61be6d062e3e1b7bbe6953ffa5d046f5141 100644 (file)
--- a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h
@@ -101,8 +101,9 @@
        // GPIO_DR
        mov     r9, \val
        cmp     r9, #0
-       movne   r9, #(1 << DEBUG_LED_BIT)       @ LED ON
-       moveq   r9, #0                          @ LED OFF
+       ldr     r9, [r10, #GPIO_DR]
+       orrne   r9, #(1 << DEBUG_LED_BIT)       @ LED ON
+       biceq   r9, #(1 << DEBUG_LED_BIT)       @ LED OFF
        str     r9, [r10, #GPIO_DR]
        .endm
 
@@ -124,6 +125,10 @@
        .macro  LED_INIT
        // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
        ldr     r10, =LED_GPIO_BASE
+       // GPIO_DR
+       ldr     r9, [r10, #GPIO_DR]
+       bic     r9, #(1 << DEBUG_LED_BIT)
+       str     r9, [r10, #GPIO_DR]
        // GPIO_GDIR
        ldr     r9, [r10, #GPIO_GDIR]
        orr     r9, r9, #(1 << DEBUG_LED_BIT)
@@ -132,9 +137,6 @@
        ldr     r10, =IOMUXC_BASE_ADDR
        mov     r9, #LED_MUX_MODE
        str     r9, [r10, #LED_MUX_OFFSET]
-       // GPIO_DR
-       mov     r9, #(1 << DEBUG_LED_BIT)       @ LED ON
-       str     r9, [r10, #GPIO_DR]
        .endm
 
 #define DCDGEN(type, addr, data)  .long        type, addr, data
@@ -332,7 +334,7 @@ osc_ok:
        ldr     r1, PLATFORM_CLOCK_DIV
        str     r1, [r2, #PLATFORM_ICGC]
 
-        /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+       /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
        cmp     r11, #0x10
        movls   r1, #1
        movhi   r1, #0
@@ -363,7 +365,7 @@ osc_ok:
        ldr     r1, CCM_CSCDR1_VAL
        str     r1, [r0, #CLKCTL_CSCDR1]
 
-       /* make sure divider effective */
+       /* make sure divider is in effect */
 1:
        ldr     r1, [r0, #CLKCTL_CDHIPR]
        cmp     r1, #0x0
@@ -372,23 +374,62 @@ osc_ok:
        mov     r1, #0x00000
        str     r1, [r0, #CLKCTL_CCDR]
 
-       @ for cko - for ARM div by 8
-       mov     r1, #0x000A0000
-       orr     r1, r1, #0x00000F0
-       str     r1, [r0, #CLKCTL_CCOSR]
-
        ldr     r1, [r0, #CLKCTL_CCR]
        bic     r1, #(1 << 8)           /* switch off FPM */
        str     r1, [r0, #CLKCTL_CCR]
-end_clk_init:
        .endm   @ init_clock
 
        .macro  setup_pll pll_nr, mhz
        ldr     r2, BASE_ADDR_\pll_nr
-       ldr     r1, PLL_VAL_0x1232
-       str     r1, [r2, #PLL_DP_CTL]           @ Set DPLL ON (set UPEN bit); BRMO=1
-       mov     r1, #0x2
-       str     r1, [r2, #PLL_DP_CONFIG]        @ Enable auto-restart AREN bit
+       .ifge   \mhz - 800
+       /* implement workaround for ENGcm12051 */
+       mov     r1, #0                          @ Disable auto-restart (AREN)
+       str     r1, [r2, #PLL_DP_CONFIG]
+
+       ldr     r1, =DP_OP_864
+       str     r1, [r2, #PLL_DP_OP]
+       str     r1, [r2, #PLL_DP_HFS_OP]
+
+       ldr     r1, =DP_MFD_864
+       str     r1, [r2, #PLL_DP_MFD]
+       str     r1, [r2, #PLL_DP_HFS_MFD]
+
+       ldr     r1, =DP_MFN_864
+       str     r1, [r2, #PLL_DP_MFN]
+       str     r1, [r2, #PLL_DP_HFS_MFN]
+
+       ldr     r1, =((1 << 2) | 0x1232)        @ Set DPLL ON; UPEN=1 BRMO=1 PLM=1
+       str     r1, [r2, #PLL_DP_CTL]
+100:
+       ldr     r1, [r2, #PLL_DP_CTL]           @ Poll LRF
+       tst     r1, #(1 << 0)
+       beq     100b
+
+       ldr     r1, =60
+       str     r1, [r2, #PLL_DP_MFN]
+       str     r1, [r2, #PLL_DP_HFS_MFN]
+
+       mov     r1, #(1 << 0)
+       str     r1, [r2, #PLL_DP_CONFIG]        @ Assert LDREQ
+101:
+       ldr     r1, [r2, #PLL_DP_CONFIG]        @ Poll LDREQ
+       tst     r1, #(1 << 0)
+       bne     101b
+
+       mov     r1, #4
+       /*
+        * delay for 4 µs
+        * since cache is disabled, this loop is more than enough
+        */
+102:
+       subs    r1, r1, #1
+       bne     102b
+       .else
+       ldr     r1, =0x1232                     @ Set DPLL ON (set UPEN bit); BRMO=1
+       str     r1, [r2, #PLL_DP_CTL]
+
+       mov     r1, #(1 << 1)                   @ Enable auto-restart (AREN)
+       str     r1, [r2, #PLL_DP_CONFIG]
 
        ldr     r1, W_DP_OP_\mhz
        str     r1, [r2, #PLL_DP_OP]
@@ -402,19 +443,20 @@ end_clk_init:
        str     r1, [r2, #PLL_DP_MFN]
        str     r1, [r2, #PLL_DP_HFS_MFN]
 
-       mov     r1, #0x3
-       str     r1, [r2, #PLL_DP_CONFIG]        @ Assert LDREQ
+       mov     r1, #((1 << 0) | (1 << 1))
+       str     r1, [r2, #PLL_DP_CONFIG]        @ Assert LDREQ + AREN
 
        @ Now restart PLL
-       ldr     r1, PLL_VAL_0x1232
+       ldr     r1, =0x1232
        str     r1, [r2, #PLL_DP_CTL]
-101:
+103:
        ldr     r1, [r2, #PLL_DP_CTL]
        ands    r1, r1, #0x1
-       beq     101b
+       beq     103b
+       .endif
        .endm
 
-       /* M3IF setup */
+       /* M4IF setup */
        .macro  init_m4if
        ldr     r1, =M4IF_BASE_ADDR
        ldr     r0, M4IF_M4IF4_VAL
@@ -646,7 +688,6 @@ CCM_CSCDR1_VAL:             .word   0x00C30321
 BASE_ADDR_PLL1:                .long   PLL1_BASE_ADDR
 BASE_ADDR_PLL2:                .long   PLL2_BASE_ADDR
 BASE_ADDR_PLL3:                .long   PLL3_BASE_ADDR
-PLL_VAL_0x1232:                .word   0x1232
 W_DP_OP_800:           .word   DP_OP_800
 W_DP_MFD_800:          .word   DP_MFD_800
 W_DP_MFN_800:          .word   DP_MFN_800

diff --git a/packages/hal/arm/mx51/var/v2_0/include/hal_soc.h b/packages/hal/arm/mx51/var/v2_0/include/hal_soc.h
index e710a2bd21eb9a082289f7be76c5a2f1f1311813..6ba27303a96cc4e0b91a71ca8d178f343ab77c1d 100644 (file)
--- a/packages/hal/arm/mx51/var/v2_0/include/hal_soc.h
+++ b/packages/hal/arm/mx51/var/v2_0/include/hal_soc.h
@@ -573,6 +573,10 @@ externC void plf_hardware_init(void);
 
 /* Assuming 24MHz input clock with doubler ON */
 /*                                                                       MFI             PDF */
+#define DP_OP_864                                      ((8 << 4) + ((1 - 1)  << 0))
+#define DP_MFD_864                                     (180 - 1)
+#define DP_MFN_864                                     180
+
 #define DP_OP_850                                      ((8 << 4) + ((1 - 1)  << 0))
 #define DP_MFD_850                                     (48 - 1)
 #define DP_MFN_850                                     41

diff --git a/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c b/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c
index 723810bf29b41b90d546b039ed1f7c1a7242d050..11b00b55f711cc894a49bc0be9c015c75665ccf0 100644 (file)
--- a/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c
+++ b/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c
@@ -373,7 +373,7 @@ void hal_delay_us(unsigned int usecs)
 
        writel(delayCount, EPIT_BASE_ADDR + EPITLR);
 
-       while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
+       while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // wait until compare bit is set
        if ((++led_on % 3000) == 0)
                BOARD_DEBUG_LED(0);
 }