TX53:

  - updated SDRAM initialization to work with NT5CB128M16 mask
    revision 'F' (see: TX53-PCN-2013-08.pdf)

diff --git a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
index 738b3fe6fbf57b26cbf972f5cb09272e8a0a6d9b..de331e089b410264982ea1c06dcd4c0ba06737a8 100644 (file)
--- a/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
+++ b/packages/hal/arm/mx53/karo/v1_0/include/hal_platform_setup.h
@@ -54,10 +54,10 @@
 
 #define SDRAM_CLK                      400
 
 
 #define SDRAM_CLK                      400
 

-#define DEBUG_LED_BIT                  20
-#define LED_GPIO_BASE                  GPIO2_BASE_ADDR
-#define LED_MUX_OFFSET                 0x174
-#define LED_MUX_MODE                   0x11
+#define DEBUG_LED_BIT          20
+#define LED_GPIO_BASE          GPIO2_BASE_ADDR
+#define LED_MUX_OFFSET         0x174
+#define LED_MUX_MODE           0x11

 
 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
 #define LED_ON                         bl      led_on
 
 #ifdef CYGOPT_HAL_ARM_TX53_DEBUG
 #define LED_ON                         bl      led_on


@@ -444,8 +444,43 @@ _KARO_CECFG_END:
        (((l) >> 8) & 0x0000FF00) |     \
        (((l) >> 24) & 0x000000FF))
 
        (((l) >> 8) & 0x0000FF00) |     \
        (((l) >> 24) & 0x000000FF))
 

-#define MXC_DCD_ITEM(addr, val)                \
-       .word   CPU_2_BE_32(addr), CPU_2_BE_32(val)
+/*
+CCM register set                 0x53FD4000 0x53FD7FFF
+EIM register set                 0x63FDA000 0x63FDAFFF
+NANDFC register set              0xF7FF0000 0xF7FFFFFF
+IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF
+DPLLC1 register                  0x63F80000 0x63F83FFF
+DPLLC2 register                  0x63F84000 0x63F87FFF
+DPLLC3 register                  0x63F88000 0x63F8BFFF
+DPLLC4 register                  0x63F8C000 0x63F8FFFF
+ESD RAM controller register      0x63FD9000 0x63FD9FFF
+M4IF register                    0x63FD8000 0x63FD8FFF
+DDR                              0x70000000 0xEFFFFFFF
+EIM                              0xF0000000 0xF7FEFFFF
+NANDFC Buffers                   0xF7FF0000 0xF7FFFFFF
+IRAM Free Space                  0xF8006000 0xF8017FF0
+GPU Memory                       0xF8020000 0xF805FFFF
+*/
+#define CHECK_DCD_ADDR(a)      (                                       \
+       ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ ||           \
+       ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ ||     \
+       ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ ||        \
+       ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ ||             \
+       ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \
+       ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ ||         \
+       ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \
+       ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \
+       ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */)
+
+       .macro  mxc_dcd_item    addr, val
+       .ifne   CHECK_DCD_ADDR(\addr)
+       .word   CPU_2_BE_32(\addr), CPU_2_BE_32(\val)
+       .else
+       .error  "Address \addr not accessible from DCD"
+       .endif
+       .endm
+
+#define MXC_DCD_ITEM(addr, val)                mxc_dcd_item    addr, val

 
 #define MXC_DCD_CMD_SZ_BYTE            1
 #define MXC_DCD_CMD_SZ_SHORT           2
 
 #define MXC_DCD_CMD_SZ_BYTE            1
 #define MXC_DCD_CMD_SZ_SHORT           2


@@ -473,6 +508,7 @@ _KARO_CECFG_END:
 
 #define CK_TO_NS(ck)   (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
 #define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)
 
 #define CK_TO_NS(ck)   (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK)
 #define NS_TO_CK(ns)   (((ns) * SDRAM_CLK + 999) / 1000)

+#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10)

 
        .macro          CK_VAL, name, clks, offs, max
        .iflt           \clks - \offs
 
        .macro          CK_VAL, name, clks, offs, max
        .iflt           \clks - \offs


@@ -480,6 +516,8 @@ _KARO_CECFG_END:
        .else
        .ifle           \clks - \offs - \max
        .set            \name, \clks - \offs
        .else
        .ifle           \clks - \offs - \max
        .set            \name, \clks - \offs

+       .else
+       .error          "Value \clks out of range for parameter \name"

        .endif
        .endif
        .endm
        .endif
        .endif
        .endm


@@ -517,70 +555,139 @@ _KARO_CECFG_END:
 #endif
 #define SDRAM_BURST_LENGTH             8
 #define RALAT                          5
 #endif
 #define SDRAM_BURST_LENGTH             8
 #define RALAT                          5

-#define WALAT                          1
+#define WALAT                          0
+#define BI_ON                          0

 #define ADDR_MIRROR                    0
 #define DDR_TYPE                       ESDMISC_DDR_TYPE_DDR3
 
 #define ADDR_MIRROR                    0
 #define DDR_TYPE                       ESDMISC_DDR_TYPE_DDR3
 

-/* 512/1024MiB SDRAM: NT5CB128M16P-CG */
+/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */
+#if SDRAM_CLK > 666 && SDRAM_CLK <= 800
+#define CL_VAL 11
+#define CWL_VAL        8
+#elif SDRAM_CLK > 533 && SDRAM_CLK <= 666
+#define CL_VAL 9 // or 10
+#define CWL_VAL        7
+#elif SDRAM_CLK > 400 && SDRAM_CLK <= 533
+#define CL_VAL 7 // or 8
+#define CWL_VAL        6
+#elif SDRAM_CLK > 333 && SDRAM_CLK <= 400
+#define CL_VAL 6
+#define CWL_VAL        5
+#elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333
+#define CL_VAL 5
+#define CWL_VAL        5
+#else
+#error SDRAM clock out of range: 303 .. 800
+#endif
+

 /* ESDCFG0 0x0c */
 NS_VAL tRFC,   160, 1, 255             /* clks - 1 (0..255) */
 /* ESDCFG0 0x0c */
 NS_VAL tRFC,   160, 1, 255             /* clks - 1 (0..255) */

-CK_MAX tXS,    tRFC + 1 + NS_TO_CK(10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
-CK_MAX tXP,    3, NS_TO_CK(6), 1, 7    /* clks - 1 (0..7) */ /* max(6ns, 3*CK) */
+CK_MAX tXS,    NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */
+CK_MAX tXP,    NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */

 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */
 CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15  /* clks - 1 (0..15) */

-NS_VAL tFAW,   45, 1, 31               /* clks - 1 (0..31) */
-CK_VAL tCL,    9, 3, 8                 /* clks - 3 (0..8) CAS Latency */
+NS_VAL tFAW,   50, 1, 31               /* clks - 1 (0..31) */
+CK_VAL tCL,    CL_VAL, 3, 8            /* clks - 3 (0..8) CAS Latency */

 
 /* ESDCFG1 0x10 */
 
 /* ESDCFG1 0x10 */

-NS_VAL tRCD,   14, 1, 7                /* clks - 1 (0..7) */
-NS_VAL tRP,    14, 1, 7                /* clks - 1 (0..7) */
+CK_VAL tRCD,   NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */
+CK_VAL tRP,    NS_TO_CK10(125), 1, 7   /* clks - 1 (0..7) */ /* 12.5 */

 NS_VAL tRC,    50, 1, 31               /* clks - 1 (0..31) */
 NS_VAL tRC,    50, 1, 31               /* clks - 1 (0..31) */

-NS_VAL tRAS,   36, 1, 31               /* clks - 1 (0..31) */
-CK_VAL tRPA,   0, 0, 1                 /* clks     (0..1) */
+CK_VAL tRAS,   NS_TO_CK10(375), 1, 31  /* clks - 1 (0..31) */ /* 37.5 */
+CK_VAL tRPA,   1, 0, 1                 /* clks     (0..1) */

 NS_VAL tWR,    15, 1, 15               /* clks - 1 (0..15) */
 CK_VAL tMRD,   4, 1, 15                /* clks - 1 (0..15) */
 NS_VAL tWR,    15, 1, 15               /* clks - 1 (0..15) */
 CK_VAL tMRD,   4, 1, 15                /* clks - 1 (0..15) */

-CK_VAL tCWL,   5, 2, 6                 /* clks - 2 (0..6) */
+CK_VAL tCWL,   CWL_VAL, 2, 6           /* clks - 2 (0..6) */

 
 /* ESDCFG2 0x14 */
 CK_VAL tDLLK,  512, 1, 511             /* clks - 1 (0..511) */
 
 /* ESDCFG2 0x14 */
 CK_VAL tDLLK,  512, 1, 511             /* clks - 1 (0..511) */

-CK_MAX tRTP,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
-CK_MAX tWTR,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
-CK_MAX tRRD,   4, NS_TO_CK(8), 1, 7    /* clks - 1 (0..7) */
+CK_MAX tRTP,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tWTR,   NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */
+CK_MAX tRRD,   NS_TO_CK(10), 4, 1, 7   /* clks - 1 (0..7) */

 
 /* ESDOR 0x30 */
 CK_MAX tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */
 
 /* ESDOR 0x30 */
 CK_MAX tXPR,   NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */

-
-/* ESDOTC 0x08 */
-NS_VAL tAOFPD, 9, 1, 7                 /* clks - 1 (0..7) */
-NS_VAL tAONPD, 9, 1, 7                 /* clks - 1 (0..7) */
-CK_VAL tANPD,  tCWL, 1, 15             /* clks - 1 (0..15) */
-CK_VAL tAXPD,  tCWL, 1, 15             /* clks - 1 (0..15) */
-CK_VAL tODTLon tCWL - 1, 1, 7          /* clks - 1 (0..7) */
-CK_VAL tODTLoff tCWL - 1, 1, 31        /* clks - 1 (0..31) */
-

 #define tSDE_RST                       (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)
 #define tSDE_RST                       (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1)

-

                                        /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
                                         * erroneous Erratum Engcm12377
                                         */
 #define tRST_CKE                       (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
 
                                        /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to
                                         * erroneous Erratum Engcm12377
                                         */
 #define tRST_CKE                       (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1)
 

+
+/* ESDOTC 0x08 */
+CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
+CK_VAL tAONPD, NS_TO_CK10(85), 1, 7    /* clks - 1 (0..7) */ /* 8.5ns */
+CK_VAL tANPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
+CK_VAL tAXPD,  tCWL + 1, 1, 15         /* clks - 1 (0..15) */
+CK_VAL tODTLon tCWL, 0, 7              /* clks - 1 (0..7) */ /* CWL+AL-2 */
+CK_VAL tODTLoff tCWL, 0, 31            /* clks - 1 (0..31) */ /* CWL+AL-2 */
+
+/* ESDPDC 0x04 */
+CK_MAX tCKE,   NS_TO_CK(5), 3, 1, 7
+CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7
+CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7
+
+#define PRCT           0
+#define PWDT           5
+#define SLOW_PD                0
+#define BOTH_CS_PD     1
+
+#define ESDPDC_VAL_0   (       \
+       (PRCT << 28) |          \
+       (PRCT << 24) |          \
+       (tCKE << 16) |          \
+       (SLOW_PD << 7) |        \
+       (BOTH_CS_PD << 6) |     \
+       (tCKSRX << 3) |         \
+       (tCKSRE << 0)           \
+       )
+
+#define ESDPDC_VAL_1   (ESDPDC_VAL_0 |         \
+       (PWDT << 12) |                          \
+       (PWDT << 8)                             \
+       )
+

 #define ROW_ADDR_BITS                  14
 #define COL_ADDR_BITS                  10
 
 #define ROW_ADDR_BITS                  14
 #define COL_ADDR_BITS                  10
 

+#define Rtt_Nom                                1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */
+#define Rtt_WR                         0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */
+#define DLL_DISABLE                    0
+

        .iflt   tWR - 7
        .iflt   tWR - 7

-       .set    mrs_val, (0x8080 | \
-                       (3 << 4) /* MRS command */ | \
-                       ((1 << 8) /* DLL Reset */ | \
-                       ((tWR + 1 - 4) << 9) | \
-                       (((tCL + 3) - 4) << 4)) << 16)
+       .set    mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ |    \
+                       (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
+                       ((tWR + 1 - 4) << 9) |                          \
+                       ((((tCL + 3) - 4) & 0x7) << 4) |                \
+                       ((((tCL + 3) - 4) & 0x8) >> 1))

        .else
        .else

-       .set    mrs_val, (0x8080 | \
-                       (3 << 4) /* MRS command */ | \
-                       ((1 << 8) /* DLL Reset */ | \
-                       (((tWR + 1) / 2) << 9) | \
-                       (((tCL + 3) - 4) << 4)) << 16)
+       .set    mr0_val, ((1 << 8) /* DLL Reset */ |                    \
+                       (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\
+                       (((tWR + 1) / 2) << 9) |        \
+                       ((((tCL + 3) - 4) & 0x7) << 4) | \
+                       ((((tCL + 3) - 4) & 0x8) >> 1))

        .endif
        .endif

-#define ESDSCR_MRS_VAL(cs)     (mrs_val | ((cs) << 3))
+
+#define mr1_val                                (                                       \
+                                        ((Rtt_Nom & 1) << 2) |                 \
+                                        (((Rtt_Nom >> 1) & 1) << 6) |          \
+                                        (((Rtt_Nom >> 2) & 1) << 9) |          \
+                                        (DLL_DISABLE << 0) |                   \
+                                       0)
+#define mr2_val                                (                                       \
+                                        (Rtt_WR << 9) /* dynamic ODT */ |      \
+                                        (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \
+                                        (1 << 6) | /* ASR: Automatic Self Refresh */\
+                                        (((tCWL + 2) - 5) << 3) |              \
+                                       0)
+#define mr3_val                                0
+
+#define ESDSCR_MRS_VAL(cs, mr, val)    (((val) << 16) |                        \
+                                       (1 << 15) /* CON_REQ */ |               \
+                                       0x80 |                                  \
+                                       (3 << 4) /* MRS command */ |            \
+                                       ((cs) << 3) |                           \
+                                       ((mr) << 0) |                           \
+                                       0)

 
 #define ESDCFG0_VAL    (               \
        (tRFC << 24) |                  \
 
 #define ESDCFG0_VAL    (               \
        (tRFC << 24) |                  \


@@ -675,6 +782,9 @@ dcd_hdr:
        .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
 dcd_start:
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)
        .word   CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION)
 dcd_start:
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib)

+
+       MXC_DCD_ITEM(0x53fa8004, 0x00194005)    @ set LDO to 1.3V
+

        /* disable all irrelevant clocks */
        MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc0fff)
        MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3)
        /* disable all irrelevant clocks */
        MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR0, 0xffcc0fff)
        MXC_DCD_ITEM(CCM_BASE_ADDR + CLKCTL_CCGR1, 0x000fffc3)


@@ -773,22 +883,22 @@ dcd_start:
        MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
        MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
        MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)
        MXC_DCD_ITEM(0x63fd902c, 0x000026d2)
        MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL)
        MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL)

-       MXC_DCD_ITEM(0x63fd9004, 0x00030012)
-
-       /* MR0 - CS0 */
-       MXC_DCD_ITEM(0x63fd901c, 0x00008032) /* MRS: MR2 */
-       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: MR3 */
-       MXC_DCD_ITEM(0x63fd901c, 0x00408031) /* MRS: MR1 */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0)) /* MRS: MR0 */
-       /* MR0 - CS1 */
+       MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0)
+
+       /* MR0..3 - CS0 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 0, mr0_val)) /* MRS: MR0 */

 #if BANK_ADDR_BITS > 1
 #if BANK_ADDR_BITS > 1

-       MXC_DCD_ITEM(0x63fd901c, 0x0000803a) /* MRS: MR2 */
-       MXC_DCD_ITEM(0x63fd901c, 0x0000803b) /* MRS: MR3 */
-       MXC_DCD_ITEM(0x63fd901c, 0x00408039) /* MRS: MR1 */
-       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1)) /* MRS: MR0 */
+       /* MR0..3 - CS1 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 2, 0x0000)) /* MRS: MR2 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 3, 0x0000)) /* MRS: MR3 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 1, 0x0040)) /* MRS: MR1 */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 0, mr0_val)) /* MRS: MR0 */

 #endif
 #endif

-       MXC_DCD_ITEM(0x63fd9020, 0x00005800) /* refresh interval */
-       MXC_DCD_ITEM(0x63fd9058, 0x00011112)
+       MXC_DCD_ITEM(0x63fd9020, 3 << 14) /* disable refresh during calibration */
+       MXC_DCD_ITEM(0x63fd9058, 0x00022222)

 
        MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
 
 
        MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */
 


@@ -801,48 +911,48 @@ zq_calib:
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
 
        /* Write Leveling */
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib)
 
        /* Write Leveling */

-       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
-       MXC_DCD_ITEM(0x63fd901c, 0x00848231) /* MRS: start write leveling */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val | (1 << 7)) | (1 << 9)) /* MRS: start write leveling */

        MXC_DCD_ITEM(0x63fd901c, 0x00000000)
        MXC_DCD_ITEM(0x63fd9048, 0x00000001)
 wl_calib:
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)
        MXC_DCD_ITEM(0x63fd901c, 0x00000000)
        MXC_DCD_ITEM(0x63fd9048, 0x00000001)
 wl_calib:
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib)

-       MXC_DCD_ITEM(0x63fd901c, 0x00048031) /* MRS: end write leveling */
-       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */

 
        /* DQS calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
 
        /* DQS calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */

-       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */

        MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
 dqs_calib:
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)
        MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */
 dqs_calib:
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib)

-       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */

 
        /* WR DL calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x00000000)
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
 
        /* WR DL calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x00000000)
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */

-       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */

        MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
 wr_dl_calib: /* 6c4 */
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)
        MXC_DCD_ITEM(0x63fd90a4, 0x00000010)
 wr_dl_calib: /* 6c4 */
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib)

-       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */

 
        /* RD DL calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */
 
        /* RD DL calibration */
        MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */

-       MXC_DCD_ITEM(0x63fd901c, 0x00048033) /* MRS: select MPR */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */

        MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
 rd_dl_calib: /* 70c */
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)
        MXC_DCD_ITEM(0x63fd90a0, 0x00000010)
 rd_dl_calib: /* 70c */
        MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010)
        MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end)

-       MXC_DCD_ITEM(0x63fd901c, 0x00008033) /* MRS: select normal data path */
+       MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */
+       MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */
+       MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1)

 
        MXC_DCD_ITEM(0x63fd901c, 0x00000000)
 
 
        MXC_DCD_ITEM(0x63fd901c, 0x00000000)
 

-       MXC_DCD_ITEM(0x53fa8004, 0x00194005)    @ set LDO to 1.3V
-

        /* setup NFC pads */
        /* MUX_SEL */
        MXC_DCD_ITEM(0x53fa819c, 0x00000000)    @ EIM_DA0
        /* setup NFC pads */
        /* MUX_SEL */
        MXC_DCD_ITEM(0x53fa819c, 0x00000000)    @ EIM_DA0


@@ -878,7 +988,7 @@ rd_dl_calib: /* 70c */
        MXC_DCD_ITEM(0x53fa85b0, 0x00000004)    @ NANDF_CS0
 dcd_end:
        .ifgt   dcd_end - dcd_start - 1768
        MXC_DCD_ITEM(0x53fa85b0, 0x00000004)    @ NANDF_CS0
 dcd_end:
        .ifgt   dcd_end - dcd_start - 1768

-       DCD too large!
+       .error  "DCD too large!"

        .endif
        .endm
 
        .endif
        .endm