TX51 pre-release
authorlothar <lothar>
Thu, 14 Jan 2010 17:13:27 +0000 (17:13 +0000)
committerlothar <lothar>
Thu, 14 Jan 2010 17:13:27 +0000 (17:13 +0000)
47 files changed:
packages/hal/arm/arch/v2_0/src/hal_misc.c
packages/hal/arm/arch/v2_0/src/redboot_linux_exec.c
packages/hal/arm/arm9/var/v2_0/include/hal_cache.h
packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h
packages/hal/arm/mx27/karo/v1_0/include/plf_mmap.h
packages/hal/arm/mx27/karo/v1_0/src/tx27_misc.c
packages/hal/arm/mx27/var/v2_0/include/hal_mm.h
packages/hal/arm/mx27/var/v2_0/include/hal_soc.h
packages/hal/arm/mx27/var/v2_0/src/cmds.c
packages/hal/arm/mx51/3stack/v2_0/cdl/hal_arm_board.cdl
packages/hal/arm/mx51/3stack/v2_0/include/fsl_board.h
packages/hal/arm/mx51/3stack/v2_0/include/hal_platform_setup.h
packages/hal/arm/mx51/3stack/v2_0/include/plf_io.h
packages/hal/arm/mx51/3stack/v2_0/misc/redboot_ROMRAM.ecm
packages/hal/arm/mx51/3stack/v2_0/misc/redboot_ROMRAM_mddr.ecm [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/src/board_misc.c
packages/hal/arm/mx51/3stack/v2_0/src/epson_lcd.c [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/src/mx51_fastlogo.c [new file with mode: 0644]
packages/hal/arm/mx51/3stack/v2_0/src/redboot_cmds.c
packages/hal/arm/mx51/babbage/v2_0/cdl/hal_arm_board.cdl
packages/hal/arm/mx51/babbage/v2_0/include/hal_platform_setup.h
packages/hal/arm/mx51/babbage/v2_0/include/plf_mmap.h
packages/hal/arm/mx51/babbage/v2_0/misc/redboot_ROMRAM.ecm
packages/hal/arm/mx51/babbage/v2_0/src/board_misc.c
packages/hal/arm/mx51/babbage/v2_0/src/redboot_cmds.c
packages/hal/arm/mx51/karo/v1_0/cdl/hal_arm_tx51.cdl [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/include/karo_tx51.h [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/include/pkgconf/mlt_arm_tx51_romram.h [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/include/pkgconf/mlt_arm_tx51_romram.ldi [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/include/plf_io.h [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/include/plf_mmap.h [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/misc/redboot_ROMRAM.ecm [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/src/mx51_fastlogo.c [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/src/redboot_cmds.c [new file with mode: 0644]
packages/hal/arm/mx51/karo/v1_0/src/tx51_misc.c [new file with mode: 0644]
packages/hal/arm/mx51/rocky/v2_0/cdl/hal_arm_board.cdl
packages/hal/arm/mx51/var/v2_0/cdl/hal_arm_soc.cdl
packages/hal/arm/mx51/var/v2_0/include/hal_cache.h
packages/hal/arm/mx51/var/v2_0/include/hal_mm.h
packages/hal/arm/mx51/var/v2_0/include/hal_soc.h
packages/hal/arm/mx51/var/v2_0/include/hal_var_ints.h
packages/hal/arm/mx51/var/v2_0/include/mx51_iomux.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/src/cmds.c
packages/hal/arm/mx51/var/v2_0/src/hab_super_root.h [new file with mode: 0644]
packages/hal/arm/mx51/var/v2_0/src/soc_diag.c
packages/hal/arm/mx51/var/v2_0/src/soc_misc.c

index ba13034..0de2752 100644 (file)
 #endif
 
 #include <cyg/infra/cyg_type.h>
-#include <cyg/infra/cyg_trac.h>         // tracing macros
-#include <cyg/infra/cyg_ass.h>          // assertion macros
+#include <cyg/infra/cyg_trac.h>                        // tracing macros
+#include <cyg/infra/cyg_ass.h>                 // assertion macros
 
-#include <cyg/hal/hal_arch.h>           // HAL header
-#include <cyg/hal/hal_intr.h>           // HAL header
+#include <cyg/hal/hal_arch.h>                  // HAL header
+#include <cyg/hal/hal_intr.h>                  // HAL header
 
 #include <cyg/infra/diag.h>
 
 /*------------------------------------------------------------------------*/
-/* First level C exception handler.                                       */
+/* First level C exception handler.                                                                              */
 
 externC void __handle_exception (void);
 
@@ -102,17 +102,17 @@ static int exception_level;
 static void
 __take_over_debug_traps(void)
 {
-    hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
-    hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
-    hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
-    hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
+       hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
+       hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
+       hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
+       hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
 }
 
 static void
 __restore_debug_traps(void)
 {
-    hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
-    hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
+       hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_PREFETCH];
+       hardware_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA] = hold_vectors[CYGNUM_HAL_VECTOR_ABORT_DATA];
 }
 #endif // !CYGPKG_CYGMON
 #endif
@@ -120,43 +120,43 @@ __restore_debug_traps(void)
 void
 exception_handler(HAL_SavedRegisters *regs)
 {
-    // Special case handler for code which has chosen to take care
-    // of data exceptions (i.e. code which expects them to happen)
-    // This is common in discovery code, e.g. checking for a particular
-    // device which may generate an exception when probing if the
-    // device is not present
+       // Special case handler for code which has chosen to take care
+       // of data exceptions (i.e. code which expects them to happen)
+       // This is common in discovery code, e.g. checking for a particular
+       // device which may generate an exception when probing if the
+       // device is not present
 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
-    if (__mem_fault_handler && 
-        regs->vector == CYGNUM_HAL_EXCEPTION_DATA_ACCESS) {
-        regs->pc = (unsigned long)__mem_fault_handler;
-        return; // Caught an exception inside stubs        
-    }
+       if (__mem_fault_handler &&
+               regs->vector == CYGNUM_HAL_EXCEPTION_DATA_ACCESS) {
+               regs->pc = (unsigned long)__mem_fault_handler;
+               return; // Caught an exception inside stubs
+       }
 #endif
 
 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) && !defined(CYGPKG_CYGMON)
-    if (++exception_level == 1) __take_over_debug_traps();
+       if (++exception_level == 1) __take_over_debug_traps();
 
-    _hal_registers = regs;
-    __handle_exception();
+       _hal_registers = regs;
+       __handle_exception();
 
-    if (--exception_level == 0) __restore_debug_traps();
+       if (--exception_level == 0) __restore_debug_traps();
 
 #elif defined(CYGPKG_KERNEL_EXCEPTIONS)
 
-    // We should decode the vector and pass a more appropriate
-    // value as the second argument. For now we simply pass a
-    // pointer to the saved registers. We should also divert
-    // breakpoint and other debug vectors into the debug stubs.
+       // We should decode the vector and pass a more appropriate
+       // value as the second argument. For now we simply pass a
+       // pointer to the saved registers. We should also divert
+       // breakpoint and other debug vectors into the debug stubs.
 
-    cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
+       cyg_hal_deliver_exception( regs->vector, (CYG_ADDRWORD)regs );
 
 #else
 
-    CYG_FAIL("Exception!!!");
-    
-#endif    
-    
-    return;
+       CYG_FAIL("Exception!!!");
+
+#endif
+
+       return;
 }
 
 void hal_spurious_IRQ(HAL_SavedRegisters *regs) CYGBLD_ATTRIB_WEAK;
@@ -164,10 +164,10 @@ void
 hal_spurious_IRQ(HAL_SavedRegisters *regs)
 {
 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
-    exception_handler(regs);
+       exception_handler(regs);
 #else
-    CYG_FAIL("Spurious interrupt!!");
-#endif    
+       CYG_FAIL("Spurious interrupt!!");
+#endif
 }
 
 /*------------------------------------------------------------------------*/
@@ -185,21 +185,21 @@ void
 cyg_hal_invoke_constructors (void)
 {
 #ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
-    static pfunc *p = &__CTOR_END__[-1];
-    
-    cyg_hal_stop_constructors = 0;
-    for (; p >= __CTOR_LIST__; p--) {
-        (*p) ();
-        if (cyg_hal_stop_constructors) {
-            p--;
-            break;
-        }
-    }
+       static pfunc *p = &__CTOR_END__[-1];
+
+       cyg_hal_stop_constructors = 0;
+       for (; p >= __CTOR_LIST__; p--) {
+               (*p) ();
+               if (cyg_hal_stop_constructors) {
+                       p--;
+                       break;
+               }
+       }
 #else
-    pfunc *p;
+       pfunc *p;
 
-    for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
-        (*p) ();
+       for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
+               (*p) ();
 #endif
 }
 
@@ -209,10 +209,10 @@ cyg_hal_invoke_constructors (void)
 externC cyg_uint32
 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
 {
-    CYG_TRACE1(true, "Interrupt: %d", vector);
+       CYG_TRACE1(true, "Interrupt: %d", vector);
 
-    CYG_FAIL("Spurious Interrupt!!!");
-    return 0;
+       CYG_FAIL("Spurious Interrupt!!!");
+       return 0;
 }
 
 /*-------------------------------------------------------------------------*/
@@ -227,7 +227,7 @@ hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
 void
 breakpoint(void)
 {
-    HAL_BREAKPOINT(_breakinst);
+       HAL_BREAKPOINT(_breakinst);
 }
 
 
@@ -236,45 +236,45 @@ breakpoint(void)
 unsigned long
 __break_opcode (void)
 {
-    return HAL_BREAKINST;
+       return HAL_BREAKINST;
 }
 #endif
 
 int
 hal_lsbindex(int mask)
 {
-    int i;
-    for (i = 0;  i < 32;  i++) {
-      if (mask & (1<<i)) return (i);
-    }
-    return (-1);
+       int i;
+       for (i = 0;  i < 32;  i++) {
+               if (mask & (1<<i)) return (i);
+       }
+       return (-1);
 }
 
 int
 hal_msbindex(int mask)
 {
-    int i;
-    for (i = 31;  i >= 0;  i--) {
-      if (mask & (1<<i)) return (i);
-    }
-    return (-1);
+       int i;
+       for (i = 31;  i >= 0;  i--) {
+               if (mask & (1<<i)) return (i);
+       }
+       return (-1);
 }
 
 #ifdef  CYGHWR_HAL_ARM_DUMP_EXCEPTIONS
 void
 dump_frame(unsigned char *frame)
 {
-    HAL_SavedRegisters *rp = (HAL_SavedRegisters *)frame;
-    int i;
-    diag_dump_buf(frame, 128);
-    diag_printf("Registers:\n");
-    for (i = 0;  i <= 10;  i++) {
-        if ((i == 0) || (i == 6)) diag_printf("R%d: ", i);
-        diag_printf("%08X ", rp->d[i]);
-        if ((i == 5) || (i == 10)) diag_printf("\n");
-    }
-    diag_printf("FP: %08X, SP: %08X, LR: %08X, PC: %08X, PSR: %08X\n",
-                rp->fp, rp->sp, rp->lr, rp->pc, rp->cpsr);
+       HAL_SavedRegisters *rp = (HAL_SavedRegisters *)frame;
+       int i;
+       diag_dump_buf(frame, 128);
+       diag_printf("Registers:\n");
+       for (i = 0;  i <= 10;  i++) {
+               if ((i == 0) || (i == 6)) diag_printf("R%d: ", i);
+               diag_printf("%08X ", rp->d[i]);
+               if ((i == 5) || (i == 10)) diag_printf("\n");
+       }
+       diag_printf("FP: %08X, SP: %08X, LR: %08X, PC: %08X, PSR: %08X\n",
+                               rp->fp, rp->sp, rp->lr, rp->pc, rp->cpsr);
 }
 #endif
 
@@ -282,21 +282,21 @@ dump_frame(unsigned char *frame)
 void
 show_frame_in(HAL_SavedRegisters *frame)
 {
-    int old;
-    HAL_DISABLE_INTERRUPTS(old);
-    diag_printf("[IN] IRQ Frame:\n");
-    dump_frame((unsigned char *)frame);
-    HAL_RESTORE_INTERRUPTS(old);
+       int old;
+       HAL_DISABLE_INTERRUPTS(old);
+       diag_printf("[IN] IRQ Frame:\n");
+       dump_frame((unsigned char *)frame);
+       HAL_RESTORE_INTERRUPTS(old);
 }
 
 void
 show_frame_out(HAL_SavedRegisters *frame)
 {
-    int old;
-    HAL_DISABLE_INTERRUPTS(old);
-    diag_printf("[OUT] IRQ Frame:\n");
-    dump_frame((unsigned char *)frame);
-    HAL_RESTORE_INTERRUPTS(old);
+       int old;
+       HAL_DISABLE_INTERRUPTS(old);
+       diag_printf("[OUT] IRQ Frame:\n");
+       dump_frame((unsigned char *)frame);
+       HAL_RESTORE_INTERRUPTS(old);
 }
 #endif
 
@@ -304,47 +304,47 @@ show_frame_out(HAL_SavedRegisters *frame)
 // Debug routines
 void cyg_hal_report_undefined_instruction(HAL_SavedRegisters *frame)
 {
-    int old;
-    HAL_DISABLE_INTERRUPTS(old);
-    diag_printf("[UNDEFINED INSTRUCTION] Frame:\n");
-    dump_frame((unsigned char *)frame);
-    HAL_RESTORE_INTERRUPTS(old);
+       int old;
+       HAL_DISABLE_INTERRUPTS(old);
+       diag_printf("[UNDEFINED INSTRUCTION] Frame:\n");
+       dump_frame((unsigned char *)frame);
+       HAL_RESTORE_INTERRUPTS(old);
 }
 
 void cyg_hal_report_software_interrupt(HAL_SavedRegisters *frame)
 {
-    int old;
-    HAL_DISABLE_INTERRUPTS(old);
-    diag_printf("[SOFTWARE INTERRUPT] Frame:\n");
-    dump_frame((unsigned char *)frame);
-    HAL_RESTORE_INTERRUPTS(old);
+       int old;
+       HAL_DISABLE_INTERRUPTS(old);
+       diag_printf("[SOFTWARE INTERRUPT] Frame:\n");
+       dump_frame((unsigned char *)frame);
+       HAL_RESTORE_INTERRUPTS(old);
 }
 
 void cyg_hal_report_abort_prefetch(HAL_SavedRegisters *frame)
 {
-    int old;
-    HAL_DISABLE_INTERRUPTS(old);
-    diag_printf("[ABORT PREFETCH] Frame:\n");
-    dump_frame((unsigned char *)frame);    
-    HAL_RESTORE_INTERRUPTS(old);
+       int old;
+       HAL_DISABLE_INTERRUPTS(old);
+       diag_printf("[ABORT PREFETCH] Frame:\n");
+       dump_frame((unsigned char *)frame);
+       HAL_RESTORE_INTERRUPTS(old);
 }
 
 void cyg_hal_report_abort_data(HAL_SavedRegisters *frame)
 {
-    int old;
-    HAL_DISABLE_INTERRUPTS(old);
-    diag_printf("[ABORT DATA] Frame:\n");
-    dump_frame((unsigned char *)frame);
-    HAL_RESTORE_INTERRUPTS(old);
+       int old;
+       HAL_DISABLE_INTERRUPTS(old);
+       diag_printf("[ABORT DATA] Frame:\n");
+       dump_frame((unsigned char *)frame);
+       HAL_RESTORE_INTERRUPTS(old);
 }
 
 void cyg_hal_report_exception_handler_returned(HAL_SavedRegisters *frame)
-{    
-    int old;
-    HAL_DISABLE_INTERRUPTS(old);
-    diag_printf("Exception handler returned!\n");
-    dump_frame((unsigned char *)frame);
-    HAL_RESTORE_INTERRUPTS(old);
+{
+       int old;
+       HAL_DISABLE_INTERRUPTS(old);
+       diag_printf("Exception handler returned!\n");
+       dump_frame((unsigned char *)frame);
+       HAL_RESTORE_INTERRUPTS(old);
 }
 #endif
 
index ac7c7f1..81c1bec 100644 (file)
@@ -54,9 +54,9 @@
 // Contributors: gthomas, jskov,
 //                              Russell King <rmk@arm.linux.org.uk>
 // Date:                2001-02-20
-// Purpose:             
-// Description:         
-//                             
+// Purpose:
+// Description:
+//
 // This code is part of RedBoot (tm).
 //
 //####DESCRIPTIONEND####
@@ -88,8 +88,8 @@
 
 // Exported CLI function(s)
 static void do_exec(int argc, char *argv[]);
-RedBoot_cmd("exec", 
-                       "Execute an image - with MMU off", 
+RedBoot_cmd("exec",
+                       "Execute an image - with MMU off",
                        "[-w timeout] [-b <load addr> [-l <length>]]\n"
                        "                [-r <ramdisk addr> [-s <ramdisk length>]]\n"
                        "                [-c \"kernel command line\"] [-t <target> ] [<entry_point>]",
@@ -287,18 +287,18 @@ struct tag {
 // Default memory layout - can be overridden by platform, typically in
 // <cyg/hal/plf_io.h>
 #ifndef CYGHWR_REDBOOT_LINUX_ATAG_MEM
-#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_)                                                                                                             \
-       CYG_MACRO_START                                                                                                                                                         \
-       /* Next ATAG_MEM. */                                                                                                                                            \
-       _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long);            \
-       _p_->hdr.tag = ATAG_MEM;                                                                                                                                        \
-       /* Round up so there's only one bit set in the memory size.                                                                     \
-        * Don't double it if it's already a power of two, though.                                                                      \
-        */                                                                                                                                                                                     \
-       _p_->u.mem.size  = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE);                                                                     \
-       if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE)                                                                                           \
-               _p_->u.mem.size <<= 1;                                                                                                                          \
-       _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram);                                                          \
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_)                                                             \
+       CYG_MACRO_START                                                                                                         \
+       /* Next ATAG_MEM. */                                                                                            \
+       _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \
+       _p_->hdr.tag = ATAG_MEM;                                                                                        \
+       /* Round up so there's only one bit set in the memory size.                     \
+        * Don't double it if it's already a power of two, though.                      \
+        */                                                                                                                                     \
+       _p_->u.mem.size  = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE);                     \
+       if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE)                                           \
+               _p_->u.mem.size <<= 1;                                                                                  \
+       _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram);          \
        CYG_MACRO_END
 #endif
 
@@ -306,7 +306,7 @@ struct tag {
 // Round up a quantity to a longword (32 bit) length
 #define ROUNDUP(n) (((n) + 3) & ~3)
 
-static void 
+static void
 do_exec(int argc, char *argv[])
 {
        unsigned long entry;
@@ -328,38 +328,33 @@ do_exec(int argc, char *argv[])
 #endif
        extern char __tramp_start__[], __tramp_end__[];
 
-#if 1
        target = load_address;
        entry = entry_address;
-#else
-       // Default physical entry point for Linux is kernel base.
-       entry = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
-       target = (unsigned long)CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS;
-#endif
+
        base_addr = load_address;
        length = load_address_end - load_address;
        // Round length up to the next quad word
        length = (length + 3) & ~0x3;
 
        ramdisk_size = 4096*1024;
-       init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM, 
-                         &wait_time, &wait_time_set, "wait timeout");
-       init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM, 
-                         &base_addr, &base_addr_set, "base address");
-       init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM, 
-                         &length, &length_set, "length");
-       init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_STR, 
-                         &cmd_line, &cmd_line_set, "kernel command line");
-       init_opts(&opts[4], 'r', true, OPTION_ARG_TYPE_NUM, 
-                         &ramdisk_addr, &ramdisk_addr_set, "ramdisk_addr");
-       init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM, 
-                         &ramdisk_size, &ramdisk_size_set, "ramdisk_size");
+       init_opts(&opts[0], 'w', true, OPTION_ARG_TYPE_NUM,
+                       &wait_time, &wait_time_set, "wait timeout");
+       init_opts(&opts[1], 'b', true, OPTION_ARG_TYPE_NUM,
+                       &base_addr, &base_addr_set, "base address");
+       init_opts(&opts[2], 'l', true, OPTION_ARG_TYPE_NUM,
+                       &length, &length_set, "length");
+       init_opts(&opts[3], 'c', true, OPTION_ARG_TYPE_STR,
+                       &cmd_line, &cmd_line_set, "kernel command line");
+       init_opts(&opts[4], 'r', true, OPTION_ARG_TYPE_NUM,
+                       &ramdisk_addr, &ramdisk_addr_set, "ramdisk_addr");
+       init_opts(&opts[5], 's', true, OPTION_ARG_TYPE_NUM,
+                       &ramdisk_size, &ramdisk_size_set, "ramdisk_size");
        init_opts(&opts[6], 't', true, OPTION_ARG_TYPE_NUM,
-                         &target, 0, "[physical] target address");
+                       &target, 0, "[physical] target address");
        num_opts = 7;
 #ifdef CYGHWR_REDBOOT_LINUX_EXEC_X_SWITCH
-       init_opts(&opts[num_opts], 'x', false, OPTION_ARG_TYPE_FLG, 
-                         &swap_endian, 0, "swap endianness");
+       init_opts(&opts[num_opts], 'x', false, OPTION_ARG_TYPE_FLG,
+                       &swap_endian, 0, "swap endianness");
        ++num_opts;
 #endif
        if (!scan_opts(argc, argv, 1, opts, num_opts, &entry,
@@ -376,7 +371,7 @@ do_exec(int argc, char *argv[])
        // Set up parameters to pass to kernel
 
        // CORE tag must be present & first
-       params->hdr.size = (sizeof(struct tag_core) + sizeof(struct tag_header))/sizeof(long);
+       params->hdr.size = (sizeof(struct tag_core) + sizeof(struct tag_header)) / sizeof(long);
        params->hdr.tag = ATAG_CORE;
        params->u.core.flags = 0;
        params->u.core.pagesize = 0;
@@ -388,7 +383,7 @@ do_exec(int argc, char *argv[])
 
        params = (struct tag *)((long *)params + params->hdr.size);
        if (ramdisk_addr_set) {
-               params->hdr.size = (sizeof(struct tag_initrd) + sizeof(struct tag_header))/sizeof(long);
+               params->hdr.size = (sizeof(struct tag_initrd) + sizeof(struct tag_header)) / sizeof(long);
                params->hdr.tag = ATAG_INITRD2;
                params->u.initrd.start = CYGARC_PHYSICAL_ADDRESS(ramdisk_addr);
                params->u.initrd.size = ramdisk_size;
@@ -452,7 +447,7 @@ do_exec(int argc, char *argv[])
        // memory map possibly convoluted from 1-1.      The trampoline code
        // between labels __tramp_start__ and __tramp_end__ must be copied
        // to RAM and then executed at the non-mapped address.
-       // 
+       //
        // This magic was created in order to be able to execute standard
        // Linux kernels with as little change/perturberance as possible.
 
@@ -485,7 +480,7 @@ do_exec(int argc, char *argv[])
                                          " mov r2,%6;\n"                 // Kernel parameters
                                          " mov pc,%0;\n"                 // Jump to kernel
                                          "__xtramp_end__:\n"
-                                         : : 
+                                         : :
                                          "r"(entry),
                                          "r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
                                          "r"(length),
@@ -522,7 +517,7 @@ do_exec(int argc, char *argv[])
                                  " mov r2,%6;\n"               // Kernel parameters
                                  " mov pc,%0;\n"               // Jump to kernel
                                  "__tramp_end__:\n"
-                                 : : 
+                                 : :
                                  "r"(entry),
                                  "r"(CYGARC_PHYSICAL_ADDRESS(base_addr)),
                                  "r"(length),
@@ -533,7 +528,7 @@ do_exec(int argc, char *argv[])
                                  : "r0", "r1"
                                  );
 }
-         
+
 #endif // HAL_PLATFORM_MACHINE_TYPE - otherwise we do not support this stuff...
 
 // EOF redboot_linux_exec.c
index f5cd738..7d0a34d 100644 (file)
@@ -54,7 +54,7 @@
 // Usage:
 //              #include <cyg/hal/hal_cache.h>
 //              ...
-//              
+//
 //
 //####DESCRIPTIONEND####
 //
 // Cache dimensions
 
 #if defined(CYGPKG_HAL_ARM_ARM9_ARM920T)
-# define HAL_ICACHE_SIZE                 0x4000
-# define HAL_ICACHE_LINE_SIZE            32
-# define HAL_ICACHE_WAYS                 64
+# define HAL_ICACHE_SIZE                                0x4000
+# define HAL_ICACHE_LINE_SIZE                   32
+# define HAL_ICACHE_WAYS                                64
 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
-# define HAL_DCACHE_SIZE                 0x4000
-# define HAL_DCACHE_LINE_SIZE            32
-# define HAL_DCACHE_WAYS                 64
+# define HAL_DCACHE_SIZE                                0x4000
+# define HAL_DCACHE_LINE_SIZE                   32
+# define HAL_DCACHE_WAYS                                64
 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 
-# define HAL_WRITE_BUFFER                64
+# define HAL_WRITE_BUFFER                               64
 
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
 
 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM922T)
-# define HAL_ICACHE_SIZE                 0x2000
-# define HAL_ICACHE_LINE_SIZE            32
-# define HAL_ICACHE_WAYS                 64
+# define HAL_ICACHE_SIZE                                0x2000
+# define HAL_ICACHE_LINE_SIZE                   32
+# define HAL_ICACHE_WAYS                                64
 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
-# define HAL_DCACHE_SIZE                 0x2000
-# define HAL_DCACHE_LINE_SIZE            32
-# define HAL_DCACHE_WAYS                 64
+# define HAL_DCACHE_SIZE                                0x2000
+# define HAL_DCACHE_LINE_SIZE                   32
+# define HAL_DCACHE_WAYS                                64
 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 
-# define HAL_WRITE_BUFFER                64
+# define HAL_WRITE_BUFFER                               64
 
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x20
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x80
 
 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM925T)
-# define HAL_ICACHE_SIZE                 0x4000
-# define HAL_ICACHE_LINE_SIZE            16
-# define HAL_ICACHE_WAYS                 2
+# define HAL_ICACHE_SIZE                                0x4000
+# define HAL_ICACHE_LINE_SIZE                   16
+# define HAL_ICACHE_WAYS                                2
 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
-# define HAL_DCACHE_SIZE                 0x2000
-# define HAL_DCACHE_LINE_SIZE            16
-# define HAL_DCACHE_WAYS                 2
+# define HAL_DCACHE_SIZE                                0x2000
+# define HAL_DCACHE_LINE_SIZE                   16
+# define HAL_DCACHE_WAYS                                2
 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 
-# define HAL_WRITE_BUFFER                64
+# define HAL_WRITE_BUFFER                               64
 // must flush everything manually
-# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE 
+# define CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE
 
 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM926EJ)
-# define HAL_ICACHE_SIZE                 0x4000
-# define HAL_ICACHE_LINE_SIZE            32
-# define HAL_ICACHE_WAYS                 4
+# define HAL_ICACHE_SIZE                                0x4000
+# define HAL_ICACHE_LINE_SIZE                   32
+# define HAL_ICACHE_WAYS                                4
 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
-# define HAL_DCACHE_SIZE                 0x2000
-# define HAL_DCACHE_LINE_SIZE            32
-# define HAL_DCACHE_WAYS                 4
+# define HAL_DCACHE_SIZE                                0x2000
+# define HAL_DCACHE_LINE_SIZE                   32
+# define HAL_DCACHE_WAYS                                4
 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 
-# define HAL_WRITE_BUFFER                64
+# define HAL_WRITE_BUFFER                               64
 
 #define CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE //has instruction to clean D-cache
 
 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
-# define HAL_ICACHE_SIZE                 0x1000
-# define HAL_ICACHE_LINE_SIZE            16
-# define HAL_ICACHE_WAYS                 4
+# define HAL_ICACHE_SIZE                                0x1000
+# define HAL_ICACHE_LINE_SIZE                   16
+# define HAL_ICACHE_WAYS                                4
 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
-# define HAL_DCACHE_SIZE                 0x1000
-# define HAL_DCACHE_LINE_SIZE            16
-# define HAL_DCACHE_WAYS                 4
+# define HAL_DCACHE_SIZE                                0x1000
+# define HAL_DCACHE_LINE_SIZE                   16
+# define HAL_DCACHE_WAYS                                4
 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 
-# define HAL_WRITE_BUFFER                32
+# define HAL_WRITE_BUFFER                               32
 
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0x10
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x40
 
 #elif defined(CYGPKG_HAL_ARM_ARM9_ARM966E)
-# define HAL_ICACHE_SIZE                 0
-# define HAL_ICACHE_LINE_SIZE            0
-# define HAL_ICACHE_WAYS                 0
+# define HAL_ICACHE_SIZE                                0
+# define HAL_ICACHE_LINE_SIZE                   0
+# define HAL_ICACHE_WAYS                                0
 # define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
-# define HAL_DCACHE_SIZE                 0
-# define HAL_DCACHE_LINE_SIZE            0
-# define HAL_DCACHE_WAYS                 0
+# define HAL_DCACHE_SIZE                                0
+# define HAL_DCACHE_LINE_SIZE                   0
+# define HAL_DCACHE_WAYS                                0
 # define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 
-# define HAL_WRITE_BUFFER                32
+# define HAL_WRITE_BUFFER                               32
 
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
 # define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP  0
 // FIXME: disable/enable instruction streaming?
 
 // Enable the instruction cache
-#define HAL_ICACHE_ENABLE()                                             \
-CYG_MACRO_START                                                         \
-    asm volatile (                                                      \
-        "mrc  p15,0,r1,c1,c0,0;"                                        \
-        "orr  r1,r1,#0x1000;"                                           \
-        "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */       \
-                              /* that MMU and alignment faults */       \
-                              /* are enabled)                  */       \
-        "mcr  p15,0,r1,c1,c0,0"                                         \
-        :                                                               \
-        :                                                               \
-        : "r1" /* Clobber list */                                       \
-        );                                                              \
+#define HAL_ICACHE_ENABLE()                                                                                            \
+CYG_MACRO_START                                                                                                                        \
+       asm volatile (                                                                                                          \
+               "mrc  p15,0,r1,c1,c0,0;"                                                                                \
+               "orr  r1,r1,#0x1000;"                                                                                   \
+               "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */               \
+                                                         /* that MMU and alignment faults */           \
+                                                         /* are enabled)                                  */           \
+               "mcr  p15,0,r1,c1,c0,0"                                                                                 \
+               :                                                                                                                               \
+               :                                                                                                                               \
+               : "r1" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 
 // Disable the instruction cache (and invalidate it, required semanitcs)
-#define HAL_ICACHE_DISABLE()                                            \
-CYG_MACRO_START                                                         \
-    asm volatile (                                                      \
-        "mrc    p15,0,r1,c1,c0,0;"                                      \
-        "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
-        "mcr    p15,0,r1,c1,c0,0;"                                      \
-        "mov    r1,#0;"                                                 \
-        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
-        "nop;" /* next few instructions may be via cache    */          \
-        "nop;"                                                          \
-        "nop;"                                                          \
-        "nop;"                                                          \
-        "nop;"                                                          \
-        "nop"                                                           \
-        :                                                               \
-        :                                                               \
-        : "r1" /* Clobber list */                                       \
-        );                                                              \
+#define HAL_ICACHE_DISABLE()                                                                                   \
+CYG_MACRO_START                                                                                                                        \
+       asm volatile (                                                                                                          \
+               "mrc    p15,0,r1,c1,c0,0;"                                                                              \
+               "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
+               "mcr    p15,0,r1,c1,c0,0;"                                                                              \
+               "mov    r1,#0;"                                                                                                 \
+               "mcr    p15,0,r1,c7,c5,0;"      /* flush ICache */                                      \
+               "nop;" /* next few instructions may be via cache        */                      \
+               "nop;"                                                                                                                  \
+               "nop;"                                                                                                                  \
+               "nop;"                                                                                                                  \
+               "nop;"                                                                                                                  \
+               "nop"                                                                                                                   \
+               :                                                                                                                               \
+               :                                                                                                                               \
+               : "r1" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 
 // Query the state of the instruction cache
-#define HAL_ICACHE_IS_ENABLED(_state_)                                   \
-CYG_MACRO_START                                                          \
-    register cyg_uint32 reg;                                             \
-    asm volatile ("mrc  p15,0,%0,c1,c0,0"                                \
-                  : "=r"(reg)                                            \
-                  :                                                      \
-        );                                                               \
-    (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */     \
+#define HAL_ICACHE_IS_ENABLED(_state_)                                                                  \
+CYG_MACRO_START                                                                                                                         \
+       register cyg_uint32 reg;                                                                                         \
+       asm volatile ("mrc      p15,0,%0,c1,c0,0"                                                                \
+                                 : "=r"(reg)                                                                                    \
+                                 :                                                                                                              \
+               );                                                                                                                               \
+       (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */         \
 CYG_MACRO_END
 
 // Invalidate the entire cache
-#define HAL_ICACHE_INVALIDATE_ALL()                                     \
-CYG_MACRO_START                                                         \
-    /* this macro can discard dirty cache lines (N/A for ICache) */     \
-    asm volatile (                                                      \
-        "mov    r1,#0;"                                                 \
-        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
-        "mcr    p15,0,r1,c8,c5,0;"  /* flush ITLB only */               \
-        "nop;" /* next few instructions may be via cache    */          \
-        "nop;"                                                          \
-        "nop;"                                                          \
-        "nop;"                                                          \
-        "nop;"                                                          \
-        "nop;"                                                          \
-        :                                                               \
-        :                                                               \
-        : "r1" /* Clobber list */                                       \
-        );                                                              \
+#define HAL_ICACHE_INVALIDATE_ALL()                                                                            \
+CYG_MACRO_START                                                                                                                        \
+       /* this macro can discard dirty cache lines (N/A for ICache) */         \
+       asm volatile (                                                                                                          \
+               "mov    r1,#0;"                                                                                                 \
+               "mcr    p15,0,r1,c7,c5,0;"      /* flush ICache */                                      \
+               "mcr    p15,0,r1,c8,c5,0;"      /* flush ITLB only */                           \
+               "nop;" /* next few instructions may be via cache        */                      \
+               "nop;"                                                                                                                  \
+               "nop;"                                                                                                                  \
+               "nop;"                                                                                                                  \
+               "nop;"                                                                                                                  \
+               "nop;"                                                                                                                  \
+               :                                                                                                                               \
+               :                                                                                                                               \
+               : "r1" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 
 // Synchronize the contents of the cache with memory.
 // (which includes flushing out pending writes)
-#define HAL_ICACHE_SYNC()                                       \
-CYG_MACRO_START                                                 \
-    HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
-    HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
+#define HAL_ICACHE_SYNC()                                                                              \
+CYG_MACRO_START                                                                                                        \
+       HAL_DCACHE_SYNC(); /* ensure data gets to RAM */                        \
+       HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */           \
 CYG_MACRO_END
 
 #else
@@ -290,134 +290,134 @@ CYG_MACRO_END
 #if HAL_DCACHE_SIZE != 0
 
 // Enable the data cache
-#define HAL_DCACHE_ENABLE()                                             \
-CYG_MACRO_START                                                         \
-    asm volatile (                                                      \
-        "mrc  p15,0,r1,c1,c0,0;"                                        \
-        "orr  r1,r1,#0x000F;" /* enable DCache (also ensures    */      \
-                              /* the MMU, alignment faults, and */      \
-                              /* write buffer are enabled)      */      \
-        "mcr  p15,0,r1,c1,c0,0"                                         \
-        :                                                               \
-        :                                                               \
-        : "r1" /* Clobber list */                                       \
-        );                                                              \
+#define HAL_DCACHE_ENABLE()                                                                                            \
+CYG_MACRO_START                                                                                                                        \
+       asm volatile (                                                                                                          \
+               "mrc  p15,0,r1,c1,c0,0;"                                                                                \
+               "orr  r1,r1,#0x000F;" /* enable DCache (also ensures    */              \
+                                                         /* the MMU, alignment faults, and */          \
+                                                         /* write buffer are enabled)          */              \
+               "mcr  p15,0,r1,c1,c0,0"                                                                                 \
+               :                                                                                                                               \
+               :                                                                                                                               \
+               : "r1" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 
 // Disable the data cache (and invalidate it, required semanitcs)
-#define HAL_DCACHE_DISABLE()                                            \
-CYG_MACRO_START                                                         \
-    asm volatile (                                                      \
-        "mrc  p15,0,r1,c1,c0,0;"                                        \
-        "bic  r1,r1,#0x000C;" /* disable DCache AND write buffer  */    \
-                              /* but not MMU and alignment faults */    \
-        "mcr  p15,0,r1,c1,c0,0;"                                        \
-        "mov    r1,#0;"                                                 \
-        "mcr  p15,0,r1,c7,c6,0" /* clear data cache */                  \
-        :                                                               \
-        :                                                               \
-        : "r1" /* Clobber list */                                       \
-        );                                                              \
+#define HAL_DCACHE_DISABLE()                                                                                   \
+CYG_MACRO_START                                                                                                                        \
+       asm volatile (                                                                                                          \
+               "mrc  p15,0,r1,c1,c0,0;"                                                                                \
+               "bic  r1,r1,#0x000C;" /* disable DCache AND write buffer  */    \
+                                                         /* but not MMU and alignment faults */        \
+               "mcr  p15,0,r1,c1,c0,0;"                                                                                \
+               "mov    r1,#0;"                                                                                                 \
+               "mcr  p15,0,r1,c7,c6,0" /* clear data cache */                                  \
+               :                                                                                                                               \
+               :                                                                                                                               \
+               : "r1" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 
 // Query the state of the data cache
-#define HAL_DCACHE_IS_ENABLED(_state_)                                   \
-CYG_MACRO_START                                                          \
-    register int reg;                                                    \
-    asm volatile ("mrc  p15,0,%0,c1,c0,0;"                               \
-                  : "=r"(reg)                                            \
-                  :                                                      \
-        );                                                               \
-    (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */           \
+#define HAL_DCACHE_IS_ENABLED(_state_)                                                                  \
+CYG_MACRO_START                                                                                                                         \
+       register int reg;                                                                                                        \
+       asm volatile ("mrc      p15,0,%0,c1,c0,0;"                                                               \
+                                 : "=r"(reg)                                                                                    \
+                                 :                                                                                                              \
+               );                                                                                                                               \
+       (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */                       \
 CYG_MACRO_END
 
 // Flush the entire dcache (and then both TLBs, just in case)
-#define HAL_DCACHE_INVALIDATE_ALL()                                     \
-CYG_MACRO_START  /* this macro can discard dirty cache lines. */        \
-    asm volatile (                                                      \
-       "mov    r0,#0;"                                                 \
-        "mcr    p15,0,r0,c7,c6,0;" /* flush d-cache */                  \
-        "mcr    p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */                 \
-        :                                                               \
-        :                                                               \
-        : "r0","memory" /* clobber list */);                            \
+#define HAL_DCACHE_INVALIDATE_ALL()                                                                            \
+CYG_MACRO_START         /* this macro can discard dirty cache lines. */                \
+       asm volatile (                                                                                                          \
+       "mov    r0,#0;"                                                                                                 \
+               "mcr    p15,0,r0,c7,c6,0;" /* flush d-cache */                                  \
+               "mcr    p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */                                 \
+               :                                                                                                                               \
+               :                                                                                                                               \
+               : "r0","memory" /* clobber list */);                                                    \
 CYG_MACRO_END
 
 // Synchronize the contents of the cache with memory.
 #ifdef CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE
-#define HAL_DCACHE_SYNC()                                               \
-CYG_MACRO_START                                                         \
-    asm volatile (                                                      \
-        "mov    r0, #0;"                                                \
-        "mcr    p15,0,r0,c7,c10,0;"  /* clean DCache */                 \
-        "1: mrc p15,0,r0,c15,c4,0;"  /* wait for dirty flag to clear */ \
-        "ands   r0,r0,#0x80000000;"                                     \
-        "bne    1b;"                                                    \
-        "mov    r0,#0;"                                                 \
-        "mcr    p15,0,r0,c7,c6,0;"  /* flush DCache */                  \
-        "mcr    p15,0,r0,c7,c10,4;" /* and drain the write buffer */    \
-        :                                                               \
-        :                                                               \
-        : "r0" /* Clobber list */                                       \
-        );                                                              \
+#define HAL_DCACHE_SYNC()                                                                                              \
+CYG_MACRO_START                                                                                                                        \
+       asm volatile (                                                                                                          \
+               "mov    r0, #0;"                                                                                                \
+               "mcr    p15,0,r0,c7,c10,0;"      /* clean DCache */                                     \
+               "1: mrc p15,0,r0,c15,c4,0;"      /* wait for dirty flag to clear */ \
+               "ands   r0,r0,#0x80000000;"                                                                             \
+               "bne    1b;"                                                                                                    \
+               "mov    r0,#0;"                                                                                                 \
+               "mcr    p15,0,r0,c7,c6,0;"      /* flush DCache */                                      \
+               "mcr    p15,0,r0,c7,c10,4;" /* and drain the write buffer */    \
+               :                                                                                                                               \
+               :                                                                                                                               \
+               : "r0" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 #elif defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
-#define HAL_DCACHE_SYNC()                                               \
-CYG_MACRO_START                                                         \
-    cyg_uint32 _tmp1, _tmp2;                                            \
-    asm volatile (                                                      \
-        "mov    %0, #0;"                                                \
-        "1: "                                                           \
-        "mov    %1, #0;"                                                \
-        "2: "                                                           \
-        "orr    r0,%0,%1;"                                              \
-        "mcr    p15,0,r0,c7,c14,2;"  /* clean index in DCache */        \
-        "add    %1,%1,%2;"                                              \
-        "cmp    %1,%3;"                                                 \
-        "bne    2b;"                                                    \
-        "add    %0,%0,#0x04000000;"  /* get to next index */            \
-        "cmp    %0,#0;"                                                 \
-        "bne    1b;"                                                    \
-        "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
-        : "=r" (_tmp1), "=r" (_tmp2)                                    \
-        : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP),            \
-          "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT)            \
-        : "r0" /* Clobber list */                                       \
-        );                                                              \
+#define HAL_DCACHE_SYNC()                                                                                              \
+CYG_MACRO_START                                                                                                                        \
+       cyg_uint32 _tmp1, _tmp2;                                                                                        \
+       asm volatile (                                                                                                          \
+               "mov    %0, #0;"                                                                                                \
+               "1: "                                                                                                                   \
+               "mov    %1, #0;"                                                                                                \
+               "2: "                                                                                                                   \
+               "orr    r0,%0,%1;"                                                                                              \
+               "mcr    p15,0,r0,c7,c14,2;"      /* clean index in DCache */            \
+               "add    %1,%1,%2;"                                                                                              \
+               "cmp    %1,%3;"                                                                                                 \
+               "bne    2b;"                                                                                                    \
+               "add    %0,%0,#0x04000000;"      /* get to next index */                        \
+               "cmp    %0,#0;"                                                                                                 \
+               "bne    1b;"                                                                                                    \
+               "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */                \
+               : "=r" (_tmp1), "=r" (_tmp2)                                                                    \
+               : "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP),                    \
+                 "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT)                    \
+               : "r0" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 #elif defined(CYGHWR_HAL_ARM_ARM9_ALT_CLEAN_DCACHE)
 /*
  * 'Clean & Invalidate whole DCache'
   */
-#define HAL_DCACHE_SYNC()                                               \
-CYG_MACRO_START                                                         \
-    asm volatile (                                                      \
+#define HAL_DCACHE_SYNC()                                                                                              \
+CYG_MACRO_START                                                                                                                        \
+       asm volatile (                                                                                                          \
        "mov    r0, #255 << 4;" /* 256 entries/set */ \
-        "2: "                    \
+               "2: "                                    \
        "mcr    p15, 0, r0, c7, c14, 2;" \
        "subs   r0, r0, #1 << 4;" \
        "bcs    2b;"            /* entries 255 to 0 */ \
-        "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
-        : \
-        : \
-        : "r0" /* Clobber list */                                       \
-        );                                                              \
+               "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */                \
+               : \
+               : \
+               : "r0" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 #elif defined(CYGHWR_HAL_ARM_ARM926EJ_CLEAN_DCACHE)
 /*
  * 'Clean & Invalidate whole DCache'
  */
-#define HAL_DCACHE_SYNC()                                               \
-CYG_MACRO_START                                                         \
-    asm volatile (                                                      \
-        "1: "                   /* clean & invalidate D index */ \
+#define HAL_DCACHE_SYNC()                                                                                              \
+CYG_MACRO_START                                                                                                                        \
+       asm volatile (                                                                                                          \
+               "1: "                                   /* clean & invalidate D index */ \
        "mrc    p15, 0, r15, c7, c14, 3;" \
-       "bne    1b;" \
-        "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */        \
-        : \
-        : \
-        : "r0" /* Clobber list */                                       \
-        );                                                              \
+       "bne    1b;" \
+               "mcr    p15,0,r0,c7,c10,4;" /* drain the write buffer */                \
+               : \
+               : \
+               : "r0" /* Clobber list */                                                                               \
+               );                                                                                                                              \
 CYG_MACRO_END
 #else
 # error "Don't know how to sync Dcache"
@@ -440,12 +440,12 @@ CYG_MACRO_END
 // Set the data cache write mode
 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
-#define HAL_DCACHE_WRITETHRU_MODE       0
-#define HAL_DCACHE_WRITEBACK_MODE       1
+#define HAL_DCACHE_WRITETHRU_MODE              0
+#define HAL_DCACHE_WRITEBACK_MODE              1
 
 // Get the current writeback mode - or only writeback mode if fixed
-#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START           \
-    _mode_ = HAL_DCACHE_WRITEBACK_MODE;                                 \
+#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START                  \
+       _mode_ = HAL_DCACHE_WRITEBACK_MODE;                                                                     \
 CYG_MACRO_END
 
 // Load the contents of the given address range into the data cache
@@ -470,45 +470,45 @@ CYG_MACRO_END
 // ---- this seems not to work despite the documentation ---
 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 //CYG_MACRO_START
-//    HAL_DCACHE_STORE( _base_ , _size_ );
-//    HAL_DCACHE_INVALIDATE( _base_ , _size_ );
+//       HAL_DCACHE_STORE( _base_ , _size_ );
+//       HAL_DCACHE_INVALIDATE( _base_ , _size_ );
 //CYG_MACRO_END
 
 // Invalidate cache lines in the given range without writing to memory.
 // ---- this seems not to work despite the documentation ---
 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 //CYG_MACRO_START
-//    register int addr, enda;
-//    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
-//              enda = (int)(_base_) + (_size_);
-//          addr < enda ;
-//          addr += HAL_DCACHE_LINE_SIZE )
-//    {
-//        asm volatile (
-//                      "mcr  p15,0,%0,c7,c6,1;" /* flush entry away */
-//                      :
-//                      : "r"(addr)
-//                      : "memory"
-//            );
-//    }
+//       register int addr, enda;
+//       for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
+//                             enda = (int)(_base_) + (_size_);
+//                     addr < enda ;
+//                     addr += HAL_DCACHE_LINE_SIZE )
+//       {
+//               asm volatile (
+//                                             "mcr  p15,0,%0,c7,c6,1;" /* flush entry away */
+//                                             :
+//                                             : "r"(addr)
+//                                             : "memory"
+//                       );
+//       }
 //CYG_MACRO_END
-                          
+
 // Write dirty cache lines to memory for the given address range.
 // ---- this seems not to work despite the documentation ---
 //#define HAL_DCACHE_STORE( _base_ , _size_ )
 //CYG_MACRO_START
-//    register int addr, enda;
-//    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
-//              enda = (int)(_base_) + (_size_);
-//          addr < enda ;
-//          addr += HAL_DCACHE_LINE_SIZE )
-//    {
-//        asm volatile ("mcr  p15,0,%0,c7,c10,1;" /* push entry to RAM */
-//                      :
-//                      : "r"(addr)
-//                      : "memory"
-//            );
-//    }
+//       register int addr, enda;
+//       for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
+//                             enda = (int)(_base_) + (_size_);
+//                     addr < enda ;
+//                     addr += HAL_DCACHE_LINE_SIZE )
+//       {
+//               asm volatile ("mcr  p15,0,%0,c7,c10,1;" /* push entry to RAM */
+//                                             :
+//                                             : "r"(addr)
+//                                             : "memory"
+//                       );
+//       }
 //CYG_MACRO_END
 
 // Preread the given range into the cache with the intention of reading
@@ -526,22 +526,22 @@ CYG_MACRO_END
 // Cache controls for safely disabling/reenabling caches around execution
 // of relocated code.
 
-#define HAL_FLASH_CACHES_OFF(_d_, _i_)          \
-    CYG_MACRO_START                             \
-    HAL_ICACHE_IS_ENABLED(_i_);                 \
-    HAL_DCACHE_IS_ENABLED(_d_);                 \
-    HAL_ICACHE_INVALIDATE_ALL();                \
-    HAL_ICACHE_DISABLE();                       \
-    HAL_DCACHE_SYNC();                          \
-    HAL_DCACHE_INVALIDATE_ALL();                \
-    HAL_DCACHE_DISABLE();                       \
-    CYG_MACRO_END
-
-#define HAL_FLASH_CACHES_ON(_d_, _i_)           \
-    CYG_MACRO_START                             \
-    if (_d_) HAL_DCACHE_ENABLE();               \
-    if (_i_) HAL_ICACHE_ENABLE();               \
-    CYG_MACRO_END
+#define HAL_FLASH_CACHES_OFF(_d_, _i_)                 \
+       CYG_MACRO_START                                                         \
+       HAL_ICACHE_IS_ENABLED(_i_);                                     \
+       HAL_DCACHE_IS_ENABLED(_d_);                                     \
+       HAL_ICACHE_INVALIDATE_ALL();                            \
+       HAL_ICACHE_DISABLE();                                           \
+       HAL_DCACHE_SYNC();                                                      \
+       HAL_DCACHE_INVALIDATE_ALL();                            \
+       HAL_DCACHE_DISABLE();                                           \
+       CYG_MACRO_END
+
+#define HAL_FLASH_CACHES_ON(_d_, _i_)                  \
+       CYG_MACRO_START                                                         \
+       if (_d_) HAL_DCACHE_ENABLE();                           \
+       if (_i_) HAL_ICACHE_ENABLE();                           \
+       CYG_MACRO_END
 
 //-----------------------------------------------------------------------------
 // Virtual<->Physical translations
index d35d587..d7659d6 100644 (file)
@@ -318,11 +318,8 @@ Copy_Good_Blk:
 NAND_Copy_Main_done:
 
 Normal_Boot_Continue:
-       bl      jump_to_sdram
+//     bl      jump_to_sdram
 // Code and all data used up to here must fit within the first 2KiB of FLASH ROM!
-Now_in_SDRAM:
-       LED_BLINK #3
-
 #ifdef CYG_HAL_STARTUP_ROMRAM  /* enable running from RAM */
        /* Copy image from flash to SDRAM first */
        ldr     r0, =0xFFFFF000
@@ -339,6 +336,8 @@ Now_in_SDRAM:
        ble     1b
 
        bl      jump_to_sdram
+Now_in_SDRAM:
+       LED_BLINK #3
 #endif /* CYG_HAL_STARTUP_ROMRAM */
 
 HWInitialise_skip_SDRAM_copy:
index 95001ff..4be393a 100644 (file)
 // Get the pagesize for a particular virtual address:
 
 // This does not depend on the vaddr.
-#define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START      \
-    (pagesize) = SZ_1M;                                         \
+#define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START     \
+       (pagesize) = SZ_1M;                                                                             \
 CYG_MACRO_END
 
 // Get the physical address from a virtual address:
 
 #define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START       \
-    cyg_uint32 _v_ = (cyg_uint32)(vaddr);                              \
-    if ( _v_ < 128 * SZ_1M )          /* SDRAM */                      \
-        _v_ += 0xA00u * SZ_1M;                                         \
-    else                             /* Rest of it */                  \
-        /* no change */ ;                                              \
-    (paddr) = _v_;                                                     \
+       cyg_uint32 _v_ = (cyg_uint32)(vaddr);                                                   \
+       if ( _v_ < 128 * SZ_1M )                  /* SDRAM */                                   \
+               _v_ += 0xA00u * SZ_1M;                                                                          \
+       else                                                     /* Rest of it */                               \
+               /* no change */ ;                                                                                       \
+       (paddr) = _v_;                                                                                                  \
 CYG_MACRO_END
 
+/*
+ * translate the virtual address of ram space to physical address
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
+{
+               if(virt < 0x08000000) {
+                               return virt|0xA0000000;
+               }
+               if((virt & 0xF0000000) == 0xA0000000) {
+                               return virt&(~0x08000000);
+               }
+               return virt;
+}
+
+/*
+ * remap the physical address of ram space to uncacheable virtual address space
+ * It is dependent on the implementation of hal_mmu_init
+ */
+static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
+{
+               /* 0xA8000000~0xA8FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+               if((phy & 0xF0000000) == 0xA0000000) {
+                               phy |= 0x08000000;
+               }
+               return phy;
+}
+
 //---------------------------------------------------------------------------
 #endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
index 6446d77..e37aaa8 100644 (file)
@@ -90,9 +90,9 @@ void hal_mmu_init(void)
        X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
        X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* Internal Registers */
        X_ARM_MMU_SECTION(0x800, 0x800, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* CSI/ATA Registers */
-       X_ARM_MMU_SECTION(0xA00, 0x000, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
-       X_ARM_MMU_SECTION(0xA00, 0xA00, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
-       X_ARM_MMU_SECTION(0xA00, 0xA80, TX27_SDRAM_SIZE >> 20,  ARM_UNCACHEABLE,  ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* SDRAM */
+       X_ARM_MMU_SECTION(0xA00, 0x000, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+       X_ARM_MMU_SECTION(0xA00, 0xA00, TX27_SDRAM_SIZE >> 20,  ARM_CACHEABLE,    ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+       X_ARM_MMU_SECTION(0xA00, 0xA80, TX27_SDRAM_SIZE >> 20,  ARM_UNCACHEABLE,  ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* SDRAM */
 //     X_ARM_MMU_SECTION(0xC00, 0xC00, 0x020, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* Flash */
        X_ARM_MMU_SECTION(0xD40, 0xD40, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW);   /* CS4 for External I/O */
        X_ARM_MMU_SECTION(0xD60, 0xD60, 0x020, ARM_CACHEABLE,   ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* CS5 PSRAM */
@@ -115,7 +115,7 @@ static void fec_gpio_init(void)
 {
        /* GPIOs to set up for TX27/Starterkit-5:
           Function       GPIO  Dir  act.  FCT
-                                     Lvl   
+                                     Lvl
           FEC_RESET      PB30  OUT  LOW   GPIO
           FEC_ENABLE     PB27  OUT  HIGH  GPIO
           OSCM26_ENABLE  PB22  OUT  HIGH  GPIO
@@ -184,28 +184,28 @@ extern int fuse_blow(int bank, int row, int bit);
 #define SOC_I2C2_BASE          UL(0x1001D000)
 
 /* Address offsets of the I2C registers */
-#define MXC_IADR                0x00   /* Address Register */
-#define MXC_IFDR                0x04   /* Freq div register */
-#define MXC_I2CR                0x08   /* Control regsiter */
-#define MXC_I2SR                0x0C   /* Status register */
-#define MXC_I2DR                0x10   /* Data I/O register */
+#define MXC_IADR                               0x00    /* Address Register */
+#define MXC_IFDR                               0x04    /* Freq div register */
+#define MXC_I2CR                               0x08    /* Control regsiter */
+#define MXC_I2SR                               0x0C    /* Status register */
+#define MXC_I2DR                               0x10    /* Data I/O register */
 
 /* Bit definitions of I2CR */
-#define MXC_I2CR_IEN            0x0080
-#define MXC_I2CR_IIEN           0x0040
-#define MXC_I2CR_MSTA           0x0020
-#define MXC_I2CR_MTX            0x0010
-#define MXC_I2CR_TXAK           0x0008
-#define MXC_I2CR_RSTA           0x0004
+#define MXC_I2CR_IEN                   0x0080
+#define MXC_I2CR_IIEN                  0x0040
+#define MXC_I2CR_MSTA                  0x0020
+#define MXC_I2CR_MTX                   0x0010
+#define MXC_I2CR_TXAK                  0x0008
+#define MXC_I2CR_RSTA                  0x0004
 
 /* Bit definitions of I2SR */
-#define MXC_I2SR_ICF            0x0080
-#define MXC_I2SR_IAAS           0x0040
-#define MXC_I2SR_IBB            0x0020
-#define MXC_I2SR_IAL            0x0010
-#define MXC_I2SR_SRW            0x0004
-#define MXC_I2SR_IIF            0x0002
-#define MXC_I2SR_RXAK           0x0001
+#define MXC_I2SR_ICF                   0x0080
+#define MXC_I2SR_IAAS                  0x0040
+#define MXC_I2SR_IBB                   0x0020
+#define MXC_I2SR_IAL                   0x0010
+#define MXC_I2SR_SRW                   0x0004
+#define MXC_I2SR_IIF                   0x0002
+#define MXC_I2SR_RXAK                  0x0001
 
 #define LP3972_SLAVE_ADDR      0x34
 
@@ -433,7 +433,7 @@ int tx27_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
 
                if ((fuse | mac_addr[i]) != mac_addr[i]) {
                        diag_printf("MAC address fuse cannot be programmed: fuse[%d]=0x%02x -> 0x%02x\n",
-                                   i, fuse, mac_addr[i]);
+                                               i, fuse, mac_addr[i]);
                        return -1;
                }
                if (fuse != mac_addr[i]) {
@@ -465,7 +465,7 @@ int tx27_mac_addr_program(unsigned char mac_addr[ETHER_ADDR_LEN])
                        }
                        if (fuse_blow(0, i + 5, bit)) {
                                diag_printf("Failed to blow fuse bank 0 row %d bit %d\n",
-                                           i, bit);
+                                                       i, bit);
                                ret = -1;
                                goto out;
                        }
index d08712e..b67a210 100644 (file)
 /*
  * Translation Table Base Bit Masks
  */
-#define ARM_TRANSLATION_TABLE_MASK               0xFFFFC000
+#define ARM_TRANSLATION_TABLE_MASK                              0xFFFFC000
 
 /*
  * Domain Access Control Bit Masks
  */
-#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)    (0x0 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_CLIENT(domain_num)       (0x1 << (domain_num)*2)
-#define ARM_ACCESS_TYPE_MANAGER(domain_num)      (0x3 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_NO_ACCESS(domain_num)   (0x0 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_CLIENT(domain_num)              (0x1 << (domain_num)*2)
+#define ARM_ACCESS_TYPE_MANAGER(domain_num)             (0x3 << (domain_num)*2)
 
 struct ARM_MMU_FIRST_LEVEL_FAULT {
-    unsigned int id : 2;
-    unsigned int sbz : 30;
+       unsigned int id : 2;
+       unsigned int sbz : 30;
 };
 
 #define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
 
 struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE {
-    unsigned int id : 2;
-    unsigned int imp : 2;
-    unsigned int domain : 4;
-    unsigned int sbz : 1;
-    unsigned int base_address : 23;
+       unsigned int id : 2;
+       unsigned int imp : 2;
+       unsigned int domain : 4;
+       unsigned int sbz : 1;
+       unsigned int base_address : 23;
 };
 
 #define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
 
 struct ARM_MMU_FIRST_LEVEL_SECTION {
-    unsigned int id : 2;
-    unsigned int b : 1;
-    unsigned int c : 1;
-    unsigned int imp : 1;
-    unsigned int domain : 4;
-    unsigned int sbz0 : 1;
-    unsigned int ap : 2;
-    unsigned int sbz1 : 8;
-    unsigned int base_address : 12;
+       unsigned int id : 2;
+       unsigned int b : 1;
+       unsigned int c : 1;
+       unsigned int imp : 1;
+       unsigned int domain : 4;
+       unsigned int sbz0 : 1;
+       unsigned int ap : 2;
+       unsigned int sbz1 : 8;
+       unsigned int base_address : 12;
 };
 
 #define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
 
 struct ARM_MMU_FIRST_LEVEL_RESERVED {
-    unsigned int id : 2;
-    unsigned int sbz : 30;
+       unsigned int id : 2;
+       unsigned int sbz : 30;
 };
 
 #define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
@@ -101,83 +101,84 @@ struct ARM_MMU_FIRST_LEVEL_RESERVED {
 
 #define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
 
-#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,              \
-                        cacheable, bufferable, perm)                      \
-    CYG_MACRO_START                                                       \
-        register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;               \
-                                                                          \
-        desc.word = 0;                                                    \
-        desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                 \
-        desc.section.domain = 0;                                          \
-        desc.section.c = (cacheable);                                     \
-        desc.section.b = (bufferable);                                    \
-        desc.section.ap = (perm);                                         \
-        desc.section.base_address = (actual_base);                        \
-        *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
-                            = desc.word;                                  \
-    CYG_MACRO_END
-
-#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access)      \
-    { int i; int j = abase; int k = vbase;                         \
-      for (i = size; i > 0 ; i--,j++,k++)                          \
-      {                                                            \
-        ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);      \
-      }                                                            \
-    }
+#define ARM_MMU_SECTION(ttb_base, actual_base, virtual_base,                     \
+                                               cacheable, bufferable, perm)                                      \
+       CYG_MACRO_START                                                                                                           \
+               register union ARM_MMU_FIRST_LEVEL_DESCRIPTOR desc;                               \
+                                                                                                                                                 \
+               desc.word = 0;                                                                                                    \
+               desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;                                 \
+               desc.section.domain = 0;                                                                                  \
+               desc.section.c = (cacheable);                                                                     \
+               desc.section.b = (bufferable);                                                                    \
+               desc.section.ap = (perm);                                                                                 \
+               desc.section.base_address = (actual_base);                                                \
+               *ARM_MMU_FIRST_LEVEL_DESCRIPTOR_ADDRESS(ttb_base, (virtual_base)) \
+                                                       = desc.word;                                                              \
+       CYG_MACRO_END
+
+#define X_ARM_MMU_SECTION(abase,vbase,size,cache,buff,access)     \
+       { int i; int j = abase; int k = vbase;                                             \
+         for (i = size; i > 0 ; i--,j++,k++)                                              \
+         {                                                                                                                        \
+               ARM_MMU_SECTION(ttb_base, j, k, cache, buff, access);      \
+         }                                                                                                                        \
+       }
 
 union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
-    unsigned long word;
-    struct ARM_MMU_FIRST_LEVEL_FAULT fault;
-    struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
-    struct ARM_MMU_FIRST_LEVEL_SECTION section;
-    struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
+       unsigned long word;
+       struct ARM_MMU_FIRST_LEVEL_FAULT fault;
+       struct ARM_MMU_FIRST_LEVEL_PAGE_TABLE page_table;
+       struct ARM_MMU_FIRST_LEVEL_SECTION section;
+       struct ARM_MMU_FIRST_LEVEL_RESERVED reserved;
 };
 
-#define ARM_UNCACHEABLE                         0
-#define ARM_CACHEABLE                           1
-#define ARM_UNBUFFERABLE                        0
-#define ARM_BUFFERABLE                          1
+#define ARM_UNCACHEABLE                                                        0
+#define ARM_CACHEABLE                                                  1
+#define ARM_UNBUFFERABLE                                               0
+#define ARM_BUFFERABLE                                                 1
 
-#define ARM_ACCESS_PERM_NONE_NONE               0
-#define ARM_ACCESS_PERM_RO_NONE                 0
-#define ARM_ACCESS_PERM_RO_RO                   0
-#define ARM_ACCESS_PERM_RW_NONE                 1
-#define ARM_ACCESS_PERM_RW_RO                   2
-#define ARM_ACCESS_PERM_RW_RW                   3
+#define ARM_ACCESS_PERM_NONE_NONE                              0
+#define ARM_ACCESS_PERM_RO_NONE                                        0
+#define ARM_ACCESS_PERM_RO_RO                                  0
+#define ARM_ACCESS_PERM_RW_NONE                                        1
+#define ARM_ACCESS_PERM_RW_RO                                  2
+#define ARM_ACCESS_PERM_RW_RW                                  3
 
 /*
  * Initialization for the Domain Access Control Register
  */
-#define ARM_ACCESS_DACR_DEFAULT      (          \
-        ARM_ACCESS_TYPE_MANAGER(0)    |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(1)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(2)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(3)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(4)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(5)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(6)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(7)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(8)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(9)  |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(10) |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(11) |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(12) |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(13) |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(14) |         \
-        ARM_ACCESS_TYPE_NO_ACCESS(15)  )
+#define ARM_ACCESS_DACR_DEFAULT                 (                      \
+               ARM_ACCESS_TYPE_MANAGER(0)        |                     \
+               ARM_ACCESS_TYPE_NO_ACCESS(1)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(2)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(3)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(4)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(5)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(6)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(7)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(8)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(9)  |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(10) |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(11) |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(12) |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(13) |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(14) |                 \
+               ARM_ACCESS_TYPE_NO_ACCESS(15)  )
+#if 0
 /*
  * translate the virtual address of ram space to physical address
  * It is dependent on the implementation of hal_mmu_init
  */
 static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
 {
-        if(virt < 0x08000000) {
-                return virt|0xA0000000;
-        }
-        if((virt & 0xF0000000) == 0xA0000000) {
-                return virt&(~0x08000000);
-        }
-        return virt;
+               if(virt < 0x08000000) {
+                               return virt|0xA0000000;
+               }
+               if((virt & 0xF0000000) == 0xA0000000) {
+                               return virt&(~0x08000000);
+               }
+               return virt;
 }
 
 /*
@@ -186,12 +187,13 @@ static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
  */
 static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
 {
-        /* 0xA8000000~0xA8FFFFFF is uncacheable meory space which is mapped to SDRAM*/
-        if((phy & 0xF0000000) == 0xA0000000) {
-                phy |= 0x08000000;
-        }
-        return phy;
+               /* 0xA8000000~0xA8FFFFFF is uncacheable meory space which is mapped to SDRAM*/
+               if((phy & 0xF0000000) == 0xA0000000) {
+                               phy |= 0x08000000;
+               }
+               return phy;
 }
+#endif
 
 // ------------------------------------------------------------------------
 #endif // ifndef CYGONCE_HAL_MM_H
index 770c8a6..c6b6745 100644 (file)
@@ -59,7 +59,7 @@
 
 #define UL(a)           (a##UL)
 
-extern char HAL_PLATFORM_EXTRA[];
+extern char HAL_PLATFORM_EXTRA[20];
 #define REG8_VAL(a)                                            ((unsigned char)(a))
 #define REG16_VAL(a)                                   ((unsigned short)(a))
 #define REG32_VAL(a)                                   ((unsigned int)(a))
index 5fa576e..fe9f767 100644 (file)
 #include <redboot.h>
 #include <cyg/hal/hal_intr.h>
 #include <cyg/hal/plf_mmap.h>
-#include <cyg/hal/hal_soc.h>         // Hardware definitions
+#include <cyg/hal/hal_soc.h>            // Hardware definitions
 #include <cyg/hal/hal_cache.h>
 
-typedef unsigned long long  u64;
-typedef unsigned int        u32;
-typedef unsigned short      u16;
-typedef unsigned char       u8;
-
-#define SZ_DEC_1M       1000000
-#define PLL_PD_MAX      16      //actual pd+1
-#define PLL_MFI_MAX     15
-#define PLL_MFI_MIN     6       // See TLSbo80174
-#define PLL_MFD_MAX     1024    //actual mfd+1
-#define PLL_MFN_MAX     1022
-#define PLL_MFN_MAX_2   510
-#define PRESC_MAX       8
-#define IPG_DIV_MAX     2
-#define AHB_DIV_MAX     16
-#define ARM_DIV_MAX     4
-
-#define CPLM_SETUP      0
-
-#define PLL_FREQ_MAX    (2 * PLL_REF_CLK * PLL_MFI_MAX)
-#define PLL_FREQ_MIN    ((2 * PLL_REF_CLK * PLL_MFI_MIN) / PLL_PD_MAX)
-#define AHB_CLK_MAX     133333333
-#define IPG_CLK_MAX     (AHB_CLK_MAX / 2)
-#define NFC_CLK_MAX     33333333
-
-#define ERR_WRONG_CLK   -1
-#define ERR_NO_MFI      -2
-#define ERR_NO_MFN      -3
-#define ERR_NO_PD       -4
-#define ERR_NO_PRESC    -5
+typedef unsigned long long     u64;
+typedef unsigned int           u32;
+typedef unsigned short         u16;
+typedef unsigned char          u8;
+
+#define SZ_DEC_1M              1000000
+#define PLL_PD_MAX             16              //actual pd+1
+#define PLL_MFI_MAX            15
+#define PLL_MFI_MIN            6               // See TLSbo80174
+#define PLL_MFD_MAX            1024    //actual mfd+1
+#define PLL_MFN_MAX            1022
+#define PLL_MFN_MAX_2  510
+#define PRESC_MAX              8
+#define IPG_DIV_MAX            2
+#define AHB_DIV_MAX            16
+#define ARM_DIV_MAX            4
+
+#define CPLM_SETUP             0
+
+#define PLL_FREQ_MAX   (2 * PLL_REF_CLK * PLL_MFI_MAX)
+#define PLL_FREQ_MIN   ((2 * PLL_REF_CLK * PLL_MFI_MIN) / PLL_PD_MAX)
+#define AHB_CLK_MAX            133333333
+#define IPG_CLK_MAX            (AHB_CLK_MAX / 2)
+#define NFC_CLK_MAX            33333333
+
+#define ERR_WRONG_CLK  -1
+#define ERR_NO_MFI             -2
+#define ERR_NO_MFN             -3
+#define ERR_NO_PD              -4
+#define ERR_NO_PRESC   -5
 
 u32 pll_clock(enum plls pll);
 u32 get_main_clock(enum main_clocks clk);
@@ -90,17 +90,17 @@ extern int sys_ver;
 #define MXC_PERCLK_NUM  4
 
 RedBoot_cmd("clock",
-           "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
-           "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
-If a divider is zero or no divider is specified, the optimal divider values \n\
-will be chosen. Examples:\n\
-   [clock]         -> Show various clocks\n\
-   [clock 266]     -> Core=266  AHB=133           IPG=66.5\n\
-   [clock 350]     -> Core=350  AHB=117           IPG=58.5\n\
-   [clock 266:4]   -> Core=266  AHB=66.5(Core/4)  IPG=66.5\n\
-   [clock 266:4:2] -> Core=266  AHB=66.5(Core/4)  IPG=33.25(AHB/2)\n",
-           clock_setup
-          );
+                       "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
+                       "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]]\n\n"
+                       "If a divider is zero or no divider is specified, the optimum divider values\n"
+                       "will be chosen. Examples:\n"
+                       "   [clock]         -> Show various clocks\n"
+                       "   [clock 266]     -> Core=266  AHB=133           IPG=66.5\n"
+                       "   [clock 350]     -> Core=350  AHB=117           IPG=58.5\n"
+                       "   [clock 266:4]   -> Core=266  AHB=66.5(Core/4)  IPG=66.5\n"
+                       "   [clock 266:4:2] -> Core=266  AHB=66.5(Core/4)  IPG=33.25(AHB/2)\n",
+                       clock_setup
+       );
 
 /*!
  * This is to calculate various parameters based on reference clock and
@@ -118,55 +118,55 @@ will be chosen. Examples:\n\
  * @return          0 if successful; non-zero otherwise.
  */
 int calc_pll_params(u32 ref, u32 target, int *p_pd,
-                   int *p_mfi, int *p_mfn, int *p_mfd)
+                                       int *p_mfi, int *p_mfn, int *p_mfd)
 {
-    int pd, mfi, mfn;
-    u64 n_target = target, n_ref = ref;
-
-    if (g_clock_src == FREQ_26MHZ) {
-       pll_mfd_fixed = 26 * 16;
-    } else if (g_clock_src == FREQ_27MHZ) {
-       pll_mfd_fixed = 27 * 16;
-    } else {
-       pll_mfd_fixed = 512;
-    }
+       int pd, mfi, mfn;
+       u64 n_target = target, n_ref = ref;
 
-    // Make sure targeted freq is in the valid range. Otherwise the
-    // following calculation might be wrong!!!
-    if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
-       return ERR_WRONG_CLK;
-    }
-    // Use n_target and n_ref to avoid overflow
-    for (pd = 1; pd <= PLL_PD_MAX; pd++) {
-       mfi = (n_target * pd) / (2 * n_ref);
-       if (mfi > PLL_MFI_MAX) {
-           return ERR_NO_MFI;
-       } else if (mfi < PLL_MFI_MIN) {
-           continue;
+       if (g_clock_src == FREQ_26MHZ) {
+               pll_mfd_fixed = 26 * 16;
+       } else if (g_clock_src == FREQ_27MHZ) {
+               pll_mfd_fixed = 27 * 16;
+       } else {
+               pll_mfd_fixed = 512;
        }
-       break;
-    }
-    // Now got pd and mfi already
-    mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
-    // Check mfn within limit and mfn < denominator
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       if (mfn < 0 || mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
-           return ERR_NO_MFN;
+
+       // Make sure targeted freq is in the valid range. Otherwise the
+       // following calculation might be wrong!!!
+       if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
+               return ERR_WRONG_CLK;
        }
-    } else {
-       if (mfn < -PLL_MFN_MAX_2 || mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
-           return ERR_NO_MFN;
+       // Use n_target and n_ref to avoid overflow
+       for (pd = 1; pd <= PLL_PD_MAX; pd++) {
+               mfi = (n_target * pd) / (2 * n_ref);
+               if (mfi > PLL_MFI_MAX) {
+                       return ERR_NO_MFI;
+               } else if (mfi < PLL_MFI_MIN) {
+                       continue;
+               }
+               break;
+       }
+       // Now got pd and mfi already
+       mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
+       // Check mfn within limit and mfn < denominator
+       if (sys_ver == SOC_SILICONID_Rev1_0) {
+               if (mfn < 0 || mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
+                       return ERR_NO_MFN;
+               }
+       } else {
+               if (mfn < -PLL_MFN_MAX_2 || mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
+                       return ERR_NO_MFN;
+               }
        }
-    }
 
-    if (pd > PLL_PD_MAX) {
-       return ERR_NO_PD;
-    }
-    *p_pd = pd;
-    *p_mfi = mfi;
-    *p_mfn = mfn;
-    *p_mfd = pll_mfd_fixed;
-    return 0;
+       if (pd > PLL_PD_MAX) {
+               return ERR_NO_PD;
+       }
+       *p_pd = pd;
+       *p_mfi = mfi;
+       *p_mfn = mfn;
+       *p_mfd = pll_mfd_fixed;
+       return 0;
 }
 
 static u32 per_clk_old[MXC_PERCLK_NUM];
@@ -200,307 +200,307 @@ static u32 per_clk_old[MXC_PERCLK_NUM];
 #define CMD_CLOCK_DEBUG
 int configure_clock(u32 ref, u32 core_clk, u32 ahb_div, u32 ipg_div)
 {
-    u32 pll, presc = 1;
-    int pd, mfi, mfn, mfd;
-    u32 cscr, mpctl0;
-    u32 pcdr0, nfc_div, hdiv, nfc_div_factor;
-    u32 per_div[MXC_PERCLK_NUM];
-    int ret, i, arm_src = 0;
-
-    per_clk_old[0] = get_peri_clock(PER_CLK1);
-    per_clk_old[1] = get_peri_clock(PER_CLK2);
-    per_clk_old[2] = get_peri_clock(PER_CLK3);
-    per_clk_old[3] = get_peri_clock(PER_CLK4);
-diag_printf("per1=%9u\n", per_clk_old[0]);
-diag_printf("per2=%9u\n", per_clk_old[1]);
-diag_printf("per3=%9u\n", per_clk_old[2]);
-diag_printf("per4=%9u\n", per_clk_old[3]);
-    // assume pll default to core clock first
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       pll = core_clk;
-       nfc_div_factor = 1;
-    } else {
-       if (core_clk > 266 * SZ_DEC_1M) {
-           pll = core_clk;
-           arm_src = 1;
+       u32 pll, presc = 1;
+       int pd, mfi, mfn, mfd;
+       u32 cscr, mpctl0;
+       u32 pcdr0, nfc_div, hdiv, nfc_div_factor;
+       u32 per_div[MXC_PERCLK_NUM];
+       int ret, i, arm_src = 0;
+
+       per_clk_old[0] = get_peri_clock(PER_CLK1);
+       per_clk_old[1] = get_peri_clock(PER_CLK2);
+       per_clk_old[2] = get_peri_clock(PER_CLK3);
+       per_clk_old[3] = get_peri_clock(PER_CLK4);
+       diag_printf("per1=%9u\n", per_clk_old[0]);
+       diag_printf("per2=%9u\n", per_clk_old[1]);
+       diag_printf("per3=%9u\n", per_clk_old[2]);
+       diag_printf("per4=%9u\n", per_clk_old[3]);
+       // assume pll default to core clock first
+       if (sys_ver == SOC_SILICONID_Rev1_0) {
+               pll = core_clk;
+               nfc_div_factor = 1;
        } else {
-           pll = core_clk * 3 / 2;
+               if (core_clk > 266 * SZ_DEC_1M) {
+                       pll = core_clk;
+                       arm_src = 1;
+               } else {
+                       pll = core_clk * 3 / 2;
+               }
+               nfc_div_factor = ahb_div;
        }
-       nfc_div_factor = ahb_div;
-    }
 
-    // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
-    // Otherwise, need to calculate presc value below and adjust the targeted pll
-    if (pll < PLL_FREQ_MIN) {
-       int presc_max;
+       // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
+       // Otherwise, need to calculate presc value below and adjust the targeted pll
+       if (pll < PLL_FREQ_MIN) {
+               int presc_max;
 
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           presc_max = PRESC_MAX;
-       } else {
-           presc_max = ARM_DIV_MAX;
-       }
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       presc_max = PRESC_MAX;
+               } else {
+                       presc_max = ARM_DIV_MAX;
+               }
 
-       for (presc = 1; presc <= presc_max; presc++) {
-           if (pll * presc > PLL_FREQ_MIN) {
-               break;
-           }
-       }
-       if (presc == presc_max + 1) {
-           diag_printf("can't make presc=%d\n", presc);
-           return ERR_NO_PRESC;
-       }
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           pll = core_clk * presc;
-       } else {
-           pll = 3 * core_clk * presc / 2;
+               for (presc = 1; presc <= presc_max; presc++) {
+                       if (pll * presc > PLL_FREQ_MIN) {
+                               break;
+                       }
+               }
+               if (presc == presc_max + 1) {
+                       diag_printf("can't make presc=%d\n", presc);
+                       return ERR_NO_PRESC;
+               }
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       pll = core_clk * presc;
+               } else {
+                       pll = 3 * core_clk * presc / 2;
+               }
        }
-    }
-    // pll is now the targeted pll output. Use it along with ref input clock
-    // to get pd, mfi, mfn, mfd
-    if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
+       // pll is now the targeted pll output. Use it along with ref input clock
+       // to get pd, mfi, mfn, mfd
+       if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
 #ifdef CMD_CLOCK_DEBUG
-       diag_printf("can't find pll parameters: %d\n", ret);
+               diag_printf("can't find pll parameters: %d\n", ret);
 #endif
-       return ret;
-    }
+               return ret;
+       }
 #ifdef CMD_CLOCK_DEBUG
-    diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
-               ref, pll, pd, mfi, mfn, mfd);
+       diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
+                               ref, pll, pd, mfi, mfn, mfd);
 #endif
 
-    // blindly increase divider first to avoid too fast ahbclk and ipgclk
-    // in case the core clock increases too much
-    cscr = readl(SOC_CRM_CSCR);
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
-       cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 9) | (1 << 8);
-    } else {
-       if (core_clk > 266 * SZ_DEC_1M) {
-           hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+       // blindly increase divider first to avoid too fast ahbclk and ipgclk
+       // in case the core clock increases too much
+       cscr = readl(SOC_CRM_CSCR);
+       if (sys_ver == SOC_SILICONID_Rev1_0) {
+               hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+               cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 9) | (1 << 8);
        } else {
-           hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
+               if (core_clk > 266 * SZ_DEC_1M) {
+                       hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
+               } else {
+                       hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
+               }
+               cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 8);
        }
-       cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 8);
-    }
-    writel(cscr, SOC_CRM_CSCR);
-
-    // update PLL register
-    if (!((mfd < 10 * mfn) && (10 * mfn < 9 * mfd)))
-       writel(1 << 6, SOC_CRM_MPCTL1);
-
-    mpctl0 = readl(SOC_CRM_MPCTL0);
-    mpctl0 = (mpctl0 & 0xC000C000)  |
-            CPLM_SETUP             |
-            ((pd - 1) << 26)       |
-            ((mfd - 1) << 16)      |
-            (mfi << 10)            |
-            mfn;
-    writel(mpctl0, SOC_CRM_MPCTL0);
-
-    // restart mpll
-    writel((cscr | (1 << 18)), SOC_CRM_CSCR);
-    // check the LF bit to insure lock
-    while ((readl(SOC_CRM_MPCTL1) & (1 << 15)) == 0);
-    // have to add some delay for new values to take effect
-    for (i = 0; i < 100000; i++);
-
-    // PLL locked already so use the new divider values
-    cscr = readl(SOC_CRM_CSCR);
-    cscr &= ~0x0000FF00;
-
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
-    } else {
-       cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
-    }
-    writel(cscr, SOC_CRM_CSCR);
+       writel(cscr, SOC_CRM_CSCR);
+
+       // update PLL register
+       if (!((mfd < 10 * mfn) && (10 * mfn < 9 * mfd)))
+               writel(1 << 6, SOC_CRM_MPCTL1);
+
+       mpctl0 = readl(SOC_CRM_MPCTL0);
+       mpctl0 = (mpctl0 & 0xC000C000)  |
+               CPLM_SETUP                         |
+               ((pd - 1) << 26)           |
+               ((mfd - 1) << 16)          |
+               (mfi << 10)                        |
+               mfn;
+       writel(mpctl0, SOC_CRM_MPCTL0);
+
+       // restart mpll
+       writel((cscr | (1 << 18)), SOC_CRM_CSCR);
+       // check the LF bit to insure lock
+       while ((readl(SOC_CRM_MPCTL1) & (1 << 15)) == 0);
+       // have to add some delay for new values to take effect
+       for (i = 0; i < 100000; i++);
+
+       // PLL locked already so use the new divider values
+       cscr = readl(SOC_CRM_CSCR);
+       cscr &= ~0x0000FF00;
 
-    // Make sure optimal NFC clock but less than NFC_CLK_MAX
-    for (nfc_div = 1; nfc_div <= 16; nfc_div++) {
-       if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
-           break;
+       if (sys_ver == SOC_SILICONID_Rev1_0) {
+               cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
+       } else {
+               cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
        }
-    }
-    pcdr0 = readl(SOC_CRM_PCDR0);
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
-          SOC_CRM_PCDR0);
-    } else {
-       writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
-          SOC_CRM_PCDR0);
-    }
+       writel(cscr, SOC_CRM_CSCR);
 
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       pll = pll_clock(MCU_PLL) + 500000;
-    } else {
-       if (core_clk > (266 * SZ_DEC_1M)) {
-           pll = pll_clock(MCU_PLL) + 500000;
+       // Make sure optimal NFC clock but less than NFC_CLK_MAX
+       for (nfc_div = 1; nfc_div <= 16; nfc_div++) {
+               if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
+                       break;
+               }
+       }
+       pcdr0 = readl(SOC_CRM_PCDR0);
+       if (sys_ver == SOC_SILICONID_Rev1_0) {
+               writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
+                       SOC_CRM_PCDR0);
        } else {
-           pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
+               writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
+                       SOC_CRM_PCDR0);
        }
-    }
-    for (i = 0; i < MXC_PERCLK_NUM; i++) {
-       per_div[i] = (pll / per_clk_old[i]) - 1;
-    }
-    writel((per_div[3] << 24) | (per_div[2] << 16) | (per_div[1] << 8) |
-          (per_div[0]), SOC_CRM_PCDR1);
 
-    return 0;
+       if (sys_ver == SOC_SILICONID_Rev1_0) {
+               pll = pll_clock(MCU_PLL) + 500000;
+       } else {
+               if (core_clk > (266 * SZ_DEC_1M)) {
+                       pll = pll_clock(MCU_PLL) + 500000;
+               } else {
+                       pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
+               }
+       }
+       for (i = 0; i < MXC_PERCLK_NUM; i++) {
+               per_div[i] = (pll / per_clk_old[i]) - 1;
+       }
+       writel((per_div[3] << 24) | (per_div[2] << 16) | (per_div[1] << 8) |
+               (per_div[0]), SOC_CRM_PCDR1);
+
+       return 0;
 }
 
 static void clock_setup(int argc, char *argv[])
 {
-    u32 i, core_clk, ipg_div, data[3], ahb_div, ahb_clk, ahb_clk_in, ipg_clk;
-    u32 presc_max,  ahb_div_max, pll;
-    unsigned long temp;
-    int ret;
-
-    if (argc == 1)
-       goto print_clock;
-    if (g_clock_src == FREQ_27MHZ) {
-       diag_printf("Error: clock setup is not supported for 27MHz source\n\n");
-       return;
-    }
-    for (i = 0;  i < 3;  i++) {
-       if (!parse_num(argv[1], &temp, &argv[1], ":")) {
-           diag_printf("Error: Invalid parameter\n");
-           return;
+       u32 i, core_clk, ipg_div, data[3], ahb_div, ahb_clk, ahb_clk_in, ipg_clk;
+       u32 presc_max,  ahb_div_max, pll;
+       unsigned long temp;
+       int ret;
+
+       if (argc == 1)
+               goto print_clock;
+       if (g_clock_src == FREQ_27MHZ) {
+               diag_printf("Error: clock setup is not supported for 27MHz source\n");
+               return;
        }
-       data[i] = temp;
-    }
+       for (i = 0;  i < 3;  i++) {
+               if (!parse_num(argv[1], &temp, &argv[1], ":")) {
+                       diag_printf("Error: Invalid parameter\n");
+                       return;
+               }
+               data[i] = temp;
+       }
+
+       core_clk = data[0] * SZ_DEC_1M;
+       ahb_div = data[1];  // actual register field + 1
+       ipg_div = data[2];  // actual register field + 1
 
-    core_clk = data[0] * SZ_DEC_1M;
-    ahb_div = data[1];  // actual register field + 1
-    ipg_div = data[2];  // actual register field + 1
-
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       presc_max = PRESC_MAX;
-       ahb_div_max = AHB_DIV_MAX;
-       pll = core_clk;
-       ahb_clk_in = core_clk;
-    } else {
-       presc_max = ARM_DIV_MAX;
-       ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
-       if (core_clk > (266 * SZ_DEC_1M)) {
-           pll = core_clk;
-           ahb_clk_in = core_clk * 2 / 3;
+       if (sys_ver == SOC_SILICONID_Rev1_0) {
+               presc_max = PRESC_MAX;
+               ahb_div_max = AHB_DIV_MAX;
+               pll = core_clk;
+               ahb_clk_in = core_clk;
        } else {
-           pll = 3 * core_clk / 2;
-           ahb_clk_in = core_clk;
+               presc_max = ARM_DIV_MAX;
+               ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
+               if (core_clk > (266 * SZ_DEC_1M)) {
+                       pll = core_clk;
+                       ahb_clk_in = core_clk * 2 / 3;
+               } else {
+                       pll = 3 * core_clk / 2;
+                       ahb_clk_in = core_clk;
+               }
+               ipg_div = 2;
        }
-       ipg_div = 2;
-    }
 
-    if (pll < (PLL_FREQ_MIN / presc_max) || pll > PLL_FREQ_MAX) {
-       diag_printf("Targeted core clock should be within [%d - %d]\n",
-                PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
-       return;
-    }
+       if (pll < (PLL_FREQ_MIN / presc_max) || pll > PLL_FREQ_MAX) {
+               diag_printf("Targeted core clock should be within [%d - %d]\n",
+                                       PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
+               return;
+       }
 
-    // find the ahb divider
-    if (ahb_div > ahb_div_max) {
-       diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
-                ahb_div, ahb_div_max);
-       return;
-    }
-    if (ahb_div == 0) {
-       // no AHBCLK divider specified
-       for (ahb_div = 1; ; ahb_div++) {
-           if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
-               break;
-           }
+       // find the ahb divider
+       if (ahb_div > ahb_div_max) {
+               diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
+                                       ahb_div, ahb_div_max);
+               return;
+       }
+       if (ahb_div == 0) {
+               // no AHBCLK divider specified
+               for (ahb_div = 1; ; ahb_div++) {
+                       if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
+                               break;
+                       }
+               }
+       }
+       if (ahb_div > ahb_div_max || (ahb_clk_in / ahb_div) > AHB_CLK_MAX) {
+               diag_printf("Can't make AHB=%d since max=%d\n",
+                                       core_clk / ahb_div, AHB_CLK_MAX);
+               return;
        }
-    }
-    if (ahb_div > ahb_div_max || (ahb_clk_in / ahb_div) > AHB_CLK_MAX) {
-       diag_printf("Can't make AHB=%d since max=%d\n",
-                core_clk / ahb_div, AHB_CLK_MAX);
-       return;
-    }
 
-    // find the ipg divider
-    ahb_clk = ahb_clk_in / ahb_div;
-    if (ipg_div > IPG_DIV_MAX) {
-       diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
-                   ipg_div, IPG_DIV_MAX);
-       return;
-    }
-    if (ipg_div == 0) {
-       ipg_div++;          // At least =1
-       if (ahb_clk > IPG_CLK_MAX)
-           ipg_div++;      // Make it =2
-    }
-    if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
-       diag_printf("Can't make IPG=%d since max=%d\n",
-                   (ahb_clk / ipg_div), IPG_CLK_MAX);
-       return;
-    }
-    ipg_clk = ahb_clk / ipg_div;
-
-    diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
-               core_clk, ahb_clk, ipg_clk);
-
-    // stop the serial to be ready to adjust the clock
-    hal_delay_us(100000);
-    cyg_hal_plf_serial_stop();
-    // adjust the clock
-    ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
-    // restart the serial driver
-    cyg_hal_plf_serial_init();
-    hal_delay_us(100000);
-
-    if (ret != 0) {
-       diag_printf("Failed to setup clock: %d\n", ret);
-       return;
-    }
+       // find the ipg divider
+       ahb_clk = ahb_clk_in / ahb_div;
+       if (ipg_div > IPG_DIV_MAX) {
+               diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
+                                       ipg_div, IPG_DIV_MAX);
+               return;
+       }
+       if (ipg_div == 0) {
+               ipg_div++;                      // At least =1
+               if (ahb_clk > IPG_CLK_MAX)
+                       ipg_div++;              // Make it =2
+       }
+       if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
+               diag_printf("Can't make IPG=%d since max=%d\n",
+                                       (ahb_clk / ipg_div), IPG_CLK_MAX);
+               return;
+       }
+       ipg_clk = ahb_clk / ipg_div;
+
+       diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
+                               core_clk, ahb_clk, ipg_clk);
+
+       // stop the serial to be ready to adjust the clock
+       hal_delay_us(100000);
+       cyg_hal_plf_serial_stop();
+       // adjust the clock
+       ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
+       // restart the serial driver
+       cyg_hal_plf_serial_init();
+       hal_delay_us(100000);
+
+       if (ret != 0) {
+               diag_printf("Failed to setup clock: %d\n", ret);
+               return;
+       }
 
-    // check for new per clock settings and warn user if there is a change.
-    if (per_clk_old[0] != get_peri_clock(PER_CLK1)) {
-       diag_printf("per_clk1 changed; old clock was: %u\n", per_clk_old[0]);
-    }
-    if (per_clk_old[1] != get_peri_clock(PER_CLK2)) {
-       diag_printf("per_clk2 changed; old clock was: %u\n", per_clk_old[1]);
-    }
-    if (per_clk_old[2] != get_peri_clock(PER_CLK3)) {
-       diag_printf("per_clk3 changed; old clock was: %u\n", per_clk_old[2]);
-    }
-    if (per_clk_old[3] != get_peri_clock(PER_CLK4)) {
-       diag_printf("per_clk4 changed; old clock was: %u\n", per_clk_old[3]);
-    }
+       // check for new per clock settings and warn user if there is a change.
+       if (per_clk_old[0] != get_peri_clock(PER_CLK1)) {
+               diag_printf("per_clk1 changed; old clock was: %u\n", per_clk_old[0]);
+       }
+       if (per_clk_old[1] != get_peri_clock(PER_CLK2)) {
+               diag_printf("per_clk2 changed; old clock was: %u\n", per_clk_old[1]);
+       }
+       if (per_clk_old[2] != get_peri_clock(PER_CLK3)) {
+               diag_printf("per_clk3 changed; old clock was: %u\n", per_clk_old[2]);
+       }
+       if (per_clk_old[3] != get_peri_clock(PER_CLK4)) {
+               diag_printf("per_clk4 changed; old clock was: %u\n", per_clk_old[3]);
+       }
 
-    diag_printf("\n<<<New clock setting>>>\n");
+       diag_printf("\n<<<New clock setting>>>\n");
 
-    // Now printing clocks
+       // Now printing clocks
 print_clock:
-    diag_printf("\nMPLL\t\tSPLL\n");
-    diag_printf("=========================\n");
-    diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(SER_PLL));
-    diag_printf("CPU\t\tAHB\t\tIPG\t\tNFC\t\tUSB\n");
-    diag_printf("========================================================================\n");
-    diag_printf("%-16d%-16d%-16d%-16d%-16d\n\n",
-               get_main_clock(CPU_CLK),
-               get_main_clock(AHB_CLK),
-               get_main_clock(IPG_CLK),
-               get_main_clock(NFC_CLK),
-               get_main_clock(USB_CLK));
-
-    diag_printf("PER1\t\tPER2\t\tPER3\t\tPER4\n");
-    diag_printf("===========================================");
-    diag_printf("=============\n");
-
-    diag_printf("%-16d%-16d%-16d%-16d\n\n",
-               get_peri_clock(PER_CLK1),
-               get_peri_clock(PER_CLK2),
-               get_peri_clock(PER_CLK3),
-               get_peri_clock(PER_CLK4));
-
-    diag_printf("H264\t\tMSHC\t\tSSI1\t\tSSI2\n");
-    diag_printf("========================================================\n");
-    diag_printf("%-16d%-16d%-16d%-16d\n\n",
-               get_peri_clock(H264_BAUD),
-               get_peri_clock(MSHC_BAUD),
-               get_peri_clock(SSI1_BAUD),
-               get_peri_clock(SSI2_BAUD));
-    diag_printf("PERCLK: 1-<UART|GPT|PWM> 2-<SDHC|CSPI> 3-<LCDC> 4-<CSI>\n");
+       diag_printf("\nMPLL\t\tSPLL\n");
+       diag_printf("=========================\n");
+       diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(SER_PLL));
+       diag_printf("CPU\t\tAHB\t\tIPG\t\tNFC\t\tUSB\n");
+       diag_printf("========================================================================\n");
+       diag_printf("%-16d%-16d%-16d%-16d%-16d\n\n",
+                               get_main_clock(CPU_CLK),
+                               get_main_clock(AHB_CLK),
+                               get_main_clock(IPG_CLK),
+                               get_main_clock(NFC_CLK),
+                               get_main_clock(USB_CLK));
+
+       diag_printf("PER1\t\tPER2\t\tPER3\t\tPER4\n");
+       diag_printf("===========================================");
+       diag_printf("=============\n");
+
+       diag_printf("%-16d%-16d%-16d%-16d\n\n",
+                               get_peri_clock(PER_CLK1),
+                               get_peri_clock(PER_CLK2),
+                               get_peri_clock(PER_CLK3),
+                               get_peri_clock(PER_CLK4));
+
+       diag_printf("H264\t\tMSHC\t\tSSI1\t\tSSI2\n");
+       diag_printf("========================================================\n");
+       diag_printf("%-16d%-16d%-16d%-16d\n\n",
+                               get_peri_clock(H264_BAUD),
+                               get_peri_clock(MSHC_BAUD),
+                               get_peri_clock(SSI1_BAUD),
+                               get_peri_clock(SSI2_BAUD));
+       diag_printf("PERCLK: 1-<UART|GPT|PWM> 2-<SDHC|CSPI> 3-<LCDC> 4-<CSI>\n");
 }
 
 /*!
@@ -508,30 +508,30 @@ print_clock:
  */
 u32 pll_clock(enum plls pll)
 {
-    int mfi, mfn, mfd, pdf;
-    u32 pll_out;
-    u32 reg = readl(pll);
-    u64 ref_clk;
+       int mfi, mfn, mfd, pdf;
+       u32 pll_out;
+       u32 reg = readl(pll);
+       u64 ref_clk;
 
-    if ((pll == SER_PLL) && (sys_ver == SOC_SILICONID_Rev2_0)) {
-       writel(reg, pll);
-    }
-    pdf = (reg >> 26) & 0xF;
-    mfd = (reg >> 16) & 0x3FF;
-    mfi = (reg >> 10) & 0xF;
-    if (mfi < 5) {
-       mfi = 5;
-    }
-    mfn = reg & 0x3FF;
-    if (mfn >= 512) {
-       mfn = 1024 - mfn;
-    }
-    ref_clk = g_clock_src;
+       if ((pll == SER_PLL) && (sys_ver == SOC_SILICONID_Rev2_0)) {
+               writel(reg, pll);
+       }
+       pdf = (reg >> 26) & 0xF;
+       mfd = (reg >> 16) & 0x3FF;
+       mfi = (reg >> 10) & 0xF;
+       if (mfi < 5) {
+               mfi = 5;
+       }
+       mfn = reg & 0x3FF;
+       if (mfn >= 512) {
+               mfn = 1024 - mfn;
+       }
+       ref_clk = g_clock_src;
 
-    pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
-             (pdf + 1);
+       pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
+               (pdf + 1);
 
-    return pll_out;
+       return pll_out;
 }
 
 /*!
@@ -539,64 +539,64 @@ u32 pll_clock(enum plls pll)
  */
 u32 get_main_clock(enum main_clocks clk)
 {
-    u32 presc, ahb_div, ipg_pdf, nfc_div;
-    u32 ret_val = 0, usb_div;
-    u32 cscr = readl(SOC_CRM_CSCR);
-    u32 pcdr0 = readl(SOC_CRM_PCDR0);
-
-    if (sys_ver == SOC_SILICONID_Rev1_0) {
-       presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
-    } else {
-       presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
-    }
+       u32 presc, ahb_div, ipg_pdf, nfc_div;
+       u32 ret_val = 0, usb_div;
+       u32 cscr = readl(SOC_CRM_CSCR);
+       u32 pcdr0 = readl(SOC_CRM_PCDR0);
 
-    switch (clk) {
-    case CPU_CLK:
-       if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
-           ret_val = pll_clock(MCU_PLL) / presc;
-       } else {
-           ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
-       }
-       break;
-    case AHB_CLK:
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
-           ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
-       } else {
-           ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
-           ret_val = 2 * pll_clock(MCU_PLL) / (3 * ahb_div);
-       }
-       break;
-    case IPG_CLK:
        if (sys_ver == SOC_SILICONID_Rev1_0) {
-           ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
-           ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
-           ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
+               presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
        } else {
-           ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
-           ret_val = pll_clock(MCU_PLL) / (3*ahb_div);
+               presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
        }
-       break;
-    case NFC_CLK:
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
-           /* AHB/nfc_div */
-           ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
-       } else {
-           nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
-           ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
-           ret_val = 2*pll_clock(MCU_PLL) / (3 * ahb_div * nfc_div);
+
+       switch (clk) {
+       case CPU_CLK:
+               if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
+                       ret_val = pll_clock(MCU_PLL) / presc;
+               } else {
+                       ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
+               }
+               break;
+       case AHB_CLK:
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
+                       ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
+               } else {
+                       ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+                       ret_val = 2 * pll_clock(MCU_PLL) / (3 * ahb_div);
+               }
+               break;
+       case IPG_CLK:
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
+                       ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
+                       ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
+               } else {
+                       ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+                       ret_val = pll_clock(MCU_PLL) / (3 * ahb_div);
+               }
+               break;
+       case NFC_CLK:
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
+                       /* AHB/nfc_div */
+                       ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
+               } else {
+                       nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
+                       ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
+                       ret_val = 2*pll_clock(MCU_PLL) / (3 * ahb_div * nfc_div);
+               }
+               break;
+       case USB_CLK:
+               usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
+               ret_val = pll_clock(SER_PLL) / usb_div;
+               break;
+       default:
+               diag_printf("Unknown clock: %d\n", clk);
+               break;
        }
-       break;
-    case USB_CLK:
-       usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
-       ret_val = pll_clock(SER_PLL) / usb_div;
-       break;
-    default:
-       diag_printf("Unknown clock: %d\n", clk);
-       break;
-    }
-    return ret_val;
+       return ret_val;
 }
 
 /*!
@@ -604,212 +604,212 @@ u32 get_main_clock(enum main_clocks clk)
  */
 u32 get_peri_clock(enum peri_clocks clk)
 {
-    u32 ret_val = 0, div;
-    u32 pcdr0 = readl(SOC_CRM_PCDR0);
-    u32 pcdr1 = readl(SOC_CRM_PCDR1);
-    u32 cscr = readl(SOC_CRM_CSCR);
-
-    switch (clk) {
-    case PER_CLK1:
-       div = (pcdr1 & 0x3F) + 1;
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           ret_val = pll_clock(MCU_PLL) / div;
-       } else {
-           ret_val = 2*pll_clock(MCU_PLL) / (3*div);
-       }
-       break;
-    case PER_CLK2:
-    case SPI1_CLK:
-    case SPI2_CLK:
-       div = ((pcdr1 >> 8) & 0x3F) + 1;
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           ret_val = pll_clock(MCU_PLL) / div;
-       } else {
-           ret_val = 2*pll_clock(MCU_PLL) / (3*div);
-       }
-       break;
-    case PER_CLK3:
-       div = ((pcdr1 >> 16) & 0x3F) + 1;
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           ret_val = pll_clock(MCU_PLL) / div;
-       } else {
-           ret_val = 2*pll_clock(MCU_PLL) / (3*div);
-       }
-       break;
-    case PER_CLK4:
-       div = ((pcdr1 >> 24) & 0x3F) + 1;
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           ret_val = pll_clock(MCU_PLL) / div;
-       } else {
-           ret_val = 2*pll_clock(MCU_PLL) / (3*div);
-       }
-       break;
-    case SSI1_BAUD:
-       div = (pcdr0 >> 16) & 0x3F;
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           if (div < 2) {
-               div = 62 * 2;
-           }
-       } else {
-           div += 4;
-       }
-       if ((cscr & (1 << 22)) != 0) {
-           // This takes care of 0.5*SSIDIV[0] by x2
-           if (sys_ver == SOC_SILICONID_Rev1_0) {
-               ret_val = (2 * pll_clock(MCU_PLL)) / div;
-           } else {
-               ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
-           }
-       } else {
-           ret_val = (2 * pll_clock(SER_PLL)) / div;
-       }
-       break;
-    case SSI2_BAUD:
-       div = (pcdr0 >> 26) & 0x3F;
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           if (div < 2) {
-               div = 62 * 2;
-           }
-       } else {
-           div += 4;
-       }
-       if ((cscr & (1 << 23)) != 0) {
-           if (sys_ver == SOC_SILICONID_Rev1_0) {
-               ret_val = (2 * pll_clock(MCU_PLL)) / div;
-           } else {
-               ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
-           }
-       } else {
-           ret_val = (2 * pll_clock(SER_PLL)) / div;
-       }
-       break;
-    case H264_BAUD:
-       if (sys_ver == SOC_SILICONID_Rev1_0) {
-           div = (pcdr0 >> 8) & 0xF;
-           if (div < 2) {
-               div = 62 * 2;
-           }
-       } else {
-           div = (pcdr0 >> 10) & 0x3F;
-           div += 4;
-       }
-       if ((cscr & (1 << 21)) != 0) {
-           if (sys_ver == SOC_SILICONID_Rev1_0) {
-               ret_val = (2 * pll_clock(MCU_PLL)) / div;
-           } else {
-               ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
-           }
-       } else {
-           ret_val = (2 * pll_clock(SER_PLL)) / div;
-       }
-       break;
-    case MSHC_BAUD:
-       if ((cscr & (1 << 20)) != 0) {
-           if (sys_ver == SOC_SILICONID_Rev1_0) {
-               div = (pcdr0 & 0x1F) + 1;
-               ret_val = pll_clock(MCU_PLL) / div;
-           } else {
-               div = (pcdr0 & 0x3F) + 1;
-               ret_val = 2*pll_clock(MCU_PLL) / (3*div);
-           }
-       } else {
-           div = (pcdr0 & 0x1F) + 1;
-           ret_val = (2 * pll_clock(SER_PLL)) / div;
+       u32 ret_val = 0, div;
+       u32 pcdr0 = readl(SOC_CRM_PCDR0);
+       u32 pcdr1 = readl(SOC_CRM_PCDR1);
+       u32 cscr = readl(SOC_CRM_CSCR);
+
+       switch (clk) {
+       case PER_CLK1:
+               div = (pcdr1 & 0x3F) + 1;
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       ret_val = pll_clock(MCU_PLL) / div;
+               } else {
+                       ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+               }
+               break;
+       case PER_CLK2:
+       case SPI1_CLK:
+       case SPI2_CLK:
+               div = ((pcdr1 >> 8) & 0x3F) + 1;
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       ret_val = pll_clock(MCU_PLL) / div;
+               } else {
+                       ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+               }
+               break;
+       case PER_CLK3:
+               div = ((pcdr1 >> 16) & 0x3F) + 1;
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       ret_val = pll_clock(MCU_PLL) / div;
+               } else {
+                       ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+               }
+               break;
+       case PER_CLK4:
+               div = ((pcdr1 >> 24) & 0x3F) + 1;
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       ret_val = pll_clock(MCU_PLL) / div;
+               } else {
+                       ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+               }
+               break;
+       case SSI1_BAUD:
+               div = (pcdr0 >> 16) & 0x3F;
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       if (div < 2) {
+                               div = 62 * 2;
+                       }
+               } else {
+                       div += 4;
+               }
+               if ((cscr & (1 << 22)) != 0) {
+                       // This takes care of 0.5*SSIDIV[0] by x2
+                       if (sys_ver == SOC_SILICONID_Rev1_0) {
+                               ret_val = (2 * pll_clock(MCU_PLL)) / div;
+                       } else {
+                               ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+                       }
+               } else {
+                       ret_val = (2 * pll_clock(SER_PLL)) / div;
+               }
+               break;
+       case SSI2_BAUD:
+               div = (pcdr0 >> 26) & 0x3F;
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       if (div < 2) {
+                               div = 62 * 2;
+                       }
+               } else {
+                       div += 4;
+               }
+               if ((cscr & (1 << 23)) != 0) {
+                       if (sys_ver == SOC_SILICONID_Rev1_0) {
+                               ret_val = (2 * pll_clock(MCU_PLL)) / div;
+                       } else {
+                               ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+                       }
+               } else {
+                       ret_val = (2 * pll_clock(SER_PLL)) / div;
+               }
+               break;
+       case H264_BAUD:
+               if (sys_ver == SOC_SILICONID_Rev1_0) {
+                       div = (pcdr0 >> 8) & 0xF;
+                       if (div < 2) {
+                               div = 62 * 2;
+                       }
+               } else {
+                       div = (pcdr0 >> 10) & 0x3F;
+                       div += 4;
+               }
+               if ((cscr & (1 << 21)) != 0) {
+                       if (sys_ver == SOC_SILICONID_Rev1_0) {
+                               ret_val = (2 * pll_clock(MCU_PLL)) / div;
+                       } else {
+                               ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
+                       }
+               } else {
+                       ret_val = (2 * pll_clock(SER_PLL)) / div;
+               }
+               break;
+       case MSHC_BAUD:
+               if ((cscr & (1 << 20)) != 0) {
+                       if (sys_ver == SOC_SILICONID_Rev1_0) {
+                               div = (pcdr0 & 0x1F) + 1;
+                               ret_val = pll_clock(MCU_PLL) / div;
+                       } else {
+                               div = (pcdr0 & 0x3F) + 1;
+                               ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
+                       }
+               } else {
+                       div = (pcdr0 & 0x1F) + 1;
+                       ret_val = (2 * pll_clock(SER_PLL)) / div;
+               }
+               break;
+       default:
+               diag_printf("%s(): This clock: %d not supported yet\n",
+                                       __FUNCTION__, clk);
+               break;
        }
-       break;
-    default:
-       diag_printf("%s(): This clock: %d not supported yet \n",
-                   __FUNCTION__, clk);
-       break;
-    }
 
-    return ret_val;
+       return ret_val;
 }
 
 RedBoot_cmd("clko",
-           "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
-           " The output clock is the actual clock source freq divided by 8. Default is FCLK\n\
-        Note that the module clock will be turned on for reading!\n\
-         <0> - display current clko selection \n\
-         <1> - CLK32 \n\
-         <2> - PREMCLK \n\
-         <3> - CLK26M (may see nothing if 26MHz Crystal is not connected) \n\
-         <4> - MPLL Reference CLK \n\
-         <5> - SPLL Reference CLK \n\
-         <6> - MPLL CLK \n\
-         <7> - SPLL CLK \n\
-         <8> - FCLK \n\
-         <9> - AHBCLK \n\
-         <10> - IPG_CLK (PERCLK) \n\
-         <11> - PERCLK1 \n\
-         <12> - PERCLK2 \n\
-         <13> - PERCLK3 \n\
-         <14> - PERCLK4 \n\
-         <15> - SSI 1 Baud \n\
-         <16> - SSI 2 Baud \n\
-         <17> - NFC \n\
-         <18> - MSHC Baud \n\
-         <19> - H264 Baud \n\
-         <20> - CLK60M Always \n\
-         <21> - CLK32K Always \n\
-         <22> - CLK60M \n\
-         <23> - DPTC Ref",
-           clko
-          );
-
-static u8* clko_name[] ={
-    "NULL",
-    "CLK32",
-    "PREMCLK",
-    "CLK26M (may see nothing if 26MHz Crystal is not connected)",
-    "MPLL Reference CLK",
-    "SPLL Reference CLK",
-    "MPLL CLK",
-    "SPLL CLK",
-    "FCLK",
-    "AHBCLK",
-    "IPG_CLK (PERCLK)",
-    "PERCLK1",
-    "PERCLK2",
-    "PERCLK3",
-    "PERCLK4",
-    "SSI 1 Baud",
-    "SSI 2 Baud",
-    "NFC",
-    "MSHC Baud",
-    "H264 Baud",
-    "CLK60M Always",
-    "CLK32K Always",
-    "CLK60M",
-    "DPTC Ref",
+                       "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
+                       " The output clock is the actual clock source freq divided by 8. Default is FCLK\n"
+                       "         Note that the module clock will be turned on for reading!\n"
+                       "          <0> - display current clko selection\n"
+                       "          <1> - CLK32\n"
+                       "          <2> - PREMCLK\n"
+                       "          <3> - CLK26M (may see nothing if 26MHz Crystal is not connected)\n"
+                       "          <4> - MPLL Reference CLK\n"
+                       "          <5> - SPLL Reference CLK\n"
+                       "          <6> - MPLL CLK\n"
+                       "          <7> - SPLL CLK\n"
+                       "          <8> - FCLK\n"
+                       "          <9> - AHBCLK\n"
+                       "          <10> - IPG_CLK (PERCLK)\n"
+                       "          <11> - PERCLK1\n"
+                       "          <12> - PERCLK2\n"
+                       "          <13> - PERCLK3\n"
+                       "          <14> - PERCLK4\n"
+                       "          <15> - SSI 1 Baud\n"
+                       "          <16> - SSI 2 Baud\n"
+                       "          <17> - NFC\n"
+                       "          <18> - MSHC Baud\n"
+                       "          <19> - H264 Baud\n"
+                       "          <20> - CLK60M Always\n"
+                       "          <21> - CLK32K Always\n"
+                       "          <22> - CLK60M\n"
+                       "          <23> - DPTC Ref",
+                       clko
+       );
+
+static u8* clko_name[] = {
+       "NULL",
+       "CLK32",
+       "PREMCLK",
+       "CLK26M (may see nothing if 26MHz Crystal is not connected)",
+       "MPLL Reference CLK",
+       "SPLL Reference CLK",
+       "MPLL CLK",
+       "SPLL CLK",
+       "FCLK",
+       "AHBCLK",
+       "IPG_CLK (PERCLK)",
+       "PERCLK1",
+       "PERCLK2",
+       "PERCLK3",
+       "PERCLK4",
+       "SSI 1 Baud",
+       "SSI 2 Baud",
+       "NFC",
+       "MSHC Baud",
+       "H264 Baud",
+       "CLK60M Always",
+       "CLK32K Always",
+       "CLK60M",
+       "DPTC Ref",
 };
 
-#define CLKO_MAX_INDEX          (sizeof(clko_name) / sizeof(u8*))
+#define CLKO_MAX_INDEX                 (sizeof(clko_name) / sizeof(u8*))
 
 static void clko(int argc,char *argv[])
 {
-    u32 action = 0, ccsr;
+       u32 action = 0, ccsr;
 
-    if (!scan_opts(argc, argv, 1, 0, 0, &action,
-                  OPTION_ARG_TYPE_NUM, "action"))
-       return;
+       if (!scan_opts(argc, argv, 1, 0, 0, &action,
+                                       OPTION_ARG_TYPE_NUM, "action"))
+               return;
 
-    if (action >= CLKO_MAX_INDEX) {
-       diag_printf("%d is not supported\n\n", action);
-       return;
-    }
+       if (action >= CLKO_MAX_INDEX) {
+               diag_printf("%d is not supported\n", action);
+               return;
+       }
 
-    ccsr = readl(SOC_CRM_CCSR);
+       ccsr = readl(SOC_CRM_CCSR);
 
-    if (action != 0) {
-       ccsr = (ccsr & (~0x1F)) + action - 1;
-       writel(ccsr, SOC_CRM_CCSR);
-       diag_printf("Set clko to ");
-    }
+       if (action != 0) {
+               ccsr = (ccsr & (~0x1F)) + action - 1;
+               writel(ccsr, SOC_CRM_CCSR);
+               diag_printf("Set clko to ");
+       }
 
-    ccsr = readl(SOC_CRM_CCSR);
-    diag_printf("%s\n", clko_name[(ccsr & 0x1F) + 1]);
-    diag_printf("CCSR register[0x%08lx] = 0x%08x\n", SOC_CRM_CCSR, ccsr);
+       ccsr = readl(SOC_CRM_CCSR);
+       diag_printf("%s\n", clko_name[(ccsr & 0x1F) + 1]);
+       diag_printf("CCSR register[0x%08lx] = 0x%08x\n", SOC_CRM_CCSR, ccsr);
 }
 
 extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
@@ -817,46 +817,46 @@ extern int flash_erase(void *addr, int len, void **err_addr);
 
 void auto_flash_start(void)
 {
-    void *err_addr;
+       void *err_addr;
        int stat;
-    int nor_update = 1; //todo: need to support NAND
-    u32 src = readl(SERIAL_DOWNLOAD_SRC_REG);
-    u32 dst = readl(SERIAL_DOWNLOAD_TGT_REG);
-    u32 sz = readl(SERIAL_DOWNLOAD_SZ_REG);
-
-    if (readl(SERIAL_DOWNLOAD_MAGIC_REG) != SERIAL_DOWNLOAD_MAGIC) {
-       return;
-    }
+       int nor_update = 1; //todo: need to support NAND
+       u32 src = readl(SERIAL_DOWNLOAD_SRC_REG);
+       u32 dst = readl(SERIAL_DOWNLOAD_TGT_REG);
+       u32 sz = readl(SERIAL_DOWNLOAD_SZ_REG);
 
-    if (nor_update) {
-       // Erase area to be programmed
-       if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
-           diag_printf("BEADDEAD\n");
-       return;
+       if (readl(SERIAL_DOWNLOAD_MAGIC_REG) != SERIAL_DOWNLOAD_MAGIC) {
+               return;
        }
-       diag_printf("BEADBEEF\n");
-       // Now program it
-       if ((stat = flash_program((void *)dst, (void *)src, sz,
-                                 &err_addr)) != 0) {
-           diag_printf("BEADFEEF\n");
+
+       if (nor_update) {
+               // Erase area to be programmed
+               if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
+                       diag_printf("BEADDEAD\n");
+                       return;
+               }
+               diag_printf("BEADBEEF\n");
+               // Now program it
+               if ((stat = flash_program((void *)dst, (void *)src, sz,
+                                                                               &err_addr)) != 0) {
+                       diag_printf("BEADFEEF\n");
+               }
        }
-    }
-    diag_printf("BEADCEEF\n");
+       diag_printf("BEADCEEF\n");
 }
 
 RedBoot_init(auto_flash_start, RedBoot_INIT_LAST);
 
-#define IIM_ERR_SHIFT       8
-#define POLL_FUSE_PRGD      (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
-#define POLL_FUSE_SNSD      (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
+#define IIM_ERR_SHIFT          8
+#define POLL_FUSE_PRGD         (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
+#define POLL_FUSE_SNSD         (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
 
 static void fuse_op_start(void)
 {
-    /* Do not generate interrupt */
-    writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
-    // clear the status bits and error bits
-    writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
-    writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
+       /* Do not generate interrupt */
+       writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
+       // clear the status bits and error bits
+       writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
+       writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
 }
 
 /*
@@ -867,224 +867,223 @@ static void fuse_op_start(void)
  */
 static int poll_fuse_op_done(int action)
 {
+       u32 status, error;
 
-    u32 status, error;
-
-    if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
-       diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
-       return -1;
-    }
+       if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
+               diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
+               return -1;
+       }
 
-    /* Poll busy bit till it is NOT set */
-    while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
-    }
+       /* Poll busy bit till it is NOT set */
+       while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
+       }
 
-    /* Test for successful write */
-    status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
-    error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
+       /* Test for successful write */
+       status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
+       error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
 
-    if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
-       if (error) {
-           diag_printf("Even though the operation seems successful...\n");
-           diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
-                       (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+       if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
+               if (error) {
+                       diag_printf("Even though the operation seems successful...\n");
+                       diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+                                               (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+               }
+               return 0;
        }
-       return 0;
-    }
-    diag_printf("%s(%d) failed\n", __FUNCTION__, action);
-    diag_printf("status address=0x%08lx, value=0x%08x\n",
-               (IIM_BASE_ADDR + IIM_STAT_OFF), status);
-    diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
-               (IIM_BASE_ADDR + IIM_ERR_OFF), error);
-    return -1;
+       diag_printf("%s(%d) failed\n", __FUNCTION__, action);
+       diag_printf("status address=0x%08lx, value=0x%08x\n",
+                               (IIM_BASE_ADDR + IIM_STAT_OFF), status);
+       diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
+                               (IIM_BASE_ADDR + IIM_ERR_OFF), error);
+       return -1;
 }
 
 static void sense_fuse(int bank, int row, int bit)
 {
-    int ret;
-    int addr, addr_l, addr_h, reg_addr;
+       int ret;
+       int addr, addr_l, addr_h, reg_addr;
 
-    fuse_op_start();
+       fuse_op_start();
 
-    addr = ((bank << 11) | (row << 3) | (bit & 0x7));
-    /* Set IIM Program Upper Address */
-    addr_h = (addr >> 8) & 0x000000FF;
-    /* Set IIM Program Lower Address */
-    addr_l = (addr & 0x000000FF);
+       addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+       /* Set IIM Program Upper Address */
+       addr_h = (addr >> 8) & 0x000000FF;
+       /* Set IIM Program Lower Address */
+       addr_l = (addr & 0x000000FF);
 
 #ifdef IIM_FUSE_DEBUG
-    diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
-               __FUNCTION__, addr_h, addr_l);
+       diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
+                               __FUNCTION__, addr_h, addr_l);
 #endif
-    writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
-    writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
-    /* Start sensing */
-    writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
-    if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
-       diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
-                   __FUNCTION__, bank, row, bit);
-    }
-    reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
-    if (ret == 0)
+       writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+       writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+       /* Start sensing */
+       writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
+       if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
+               diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
+                                       __FUNCTION__, bank, row, bit);
+       }
+       reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
+       if (ret == 0)
                diag_printf("fuses at (bank:%d, row:%d) = 0x%02x\n", bank, row, readl(reg_addr));
 }
 
 void do_fuse_read(int argc, char *argv[])
 {
-    unsigned long bank, row;
-
-    if (argc == 1) {
-       diag_printf("Useage: fuse_read <bank> <row>\n");
-       return;
-    } else if (argc == 3) {
-       if (!parse_num(argv[1], &bank, &argv[1], " ")) {
-               diag_printf("Error: Invalid parameter\n");
-           return;
-       }
-       if (!parse_num(argv[2], &row, &argv[2], " ")) {
-               diag_printf("Error: Invalid parameter\n");
+       unsigned long bank, row;
+
+       if (argc == 1) {
+               diag_printf("Usage: fuse_read <bank> <row>\n");
                return;
-           }
+       } else if (argc == 3) {
+               if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+                       diag_printf("Error: Invalid parameter\n");
+                       return;
+               }
+               if (!parse_num(argv[2], &row, &argv[2], " ")) {
+                       diag_printf("Error: Invalid parameter\n");
+                       return;
+               }
 
-       diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
-       sense_fuse(bank, row, 0);
+               diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
+               sense_fuse(bank, row, 0);
 
-    } else {
-       diag_printf("Passing in wrong arguments: %d\n", argc);
-       diag_printf("Useage: fuse_read <bank> <row>\n");
-    }
+       } else {
+               diag_printf("Passing in wrong arguments: %d\n", argc);
+               diag_printf("Usage: fuse_read <bank> <row>\n");
+       }
 }
 
 /* Blow fuses based on the bank, row and bit positions (all 0-based)
 */
 int fuse_blow(int bank, int row, int bit)
 {
-    int addr, addr_l, addr_h, ret = -1;
+       int addr, addr_l, addr_h, ret = -1;
 
-    fuse_op_start();
+       fuse_op_start();
 
-    /* Disable IIM Program Protect */
-    writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+       /* Disable IIM Program Protect */
+       writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
 
-    addr = ((bank << 11) | (row << 3) | (bit & 0x7));
-    /* Set IIM Program Upper Address */
-    addr_h = (addr >> 8) & 0x000000FF;
-    /* Set IIM Program Lower Address */
-    addr_l = (addr & 0x000000FF);
+       addr = ((bank << 11) | (row << 3) | (bit & 0x7));
+       /* Set IIM Program Upper Address */
+       addr_h = (addr >> 8) & 0x000000FF;
+       /* Set IIM Program Lower Address */
+       addr_l = (addr & 0x000000FF);
 
-    diag_printf("blowing fuse bank %d row %d bit %d\n", bank, row, bit & 7);
+       diag_printf("blowing fuse bank %d row %d bit %d\n", bank, row, bit & 7);
 #ifdef IIM_FUSE_DEBUG
-    diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
+       diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
 #endif
 
-    writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
-    writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
-    /* Start Programming */
-    writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
-    if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
-       ret = 0;
-    }
+       writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
+       writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
+       /* Start Programming */
+       writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
+       if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
+               ret = 0;
+       }
 
-    /* Enable IIM Program Protect */
-    writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
-    return ret;
+       /* Enable IIM Program Protect */
+       writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
+       return ret;
 }
 
 /*
  * This command is added for burning IIM fuses
  */
 RedBoot_cmd("fuse_read",
-           "read some fuses",
-           "<bank> <row>",
-           do_fuse_read
-          );
+                       "read some fuses",
+                       "<bank> <row>",
+                       do_fuse_read
+       );
 
 RedBoot_cmd("fuse_blow",
-           "blow some fuses",
-           "<bank> <row> <value>",
-           do_fuse_blow
-          );
+                       "blow some fuses",
+                       "<bank> <row> <value>",
+                       do_fuse_blow
+       );
 
-#define         INIT_STRING              "12345678"
+#define                        INIT_STRING                              "12345678"
 static char ready_to_blow[] = INIT_STRING;
 
 void do_fuse_blow(int argc, char *argv[])
 {
-    unsigned long bank, row, value;
-    int i;
-
-    if (argc == 1) {
-       diag_printf("It is too dangeous for you to use this command.\n");
-       return;
-    } else if (argc == 2) {
-       if (strcasecmp(argv[1], "nandboot") == 0) {
-           diag_printf("%s\n", "fuse blown not needed");
-       }
-       return;
-    } else if (argc == 3) {
-       if (strcasecmp(argv[1], "nandboot") == 0) {
+       unsigned long bank, row, value;
+       int i;
+
+       if (argc == 1) {
+               diag_printf("It is too dangeous for you to use this command.\n");
+               return;
+       } else if (argc == 2) {
+               if (strcasecmp(argv[1], "nandboot") == 0) {
+                       diag_printf("%s\n", "fuse blown not needed");
+               }
+               return;
+       } else if (argc == 3) {
+               if (strcasecmp(argv[1], "nandboot") == 0) {
 #if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
-           diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
+                       diag_printf("No need to blow any fuses for NAND boot on this platform\n");
 #else
-           diag_printf("Ready to burn NAND boot fuses\n");
-           if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
-               diag_printf("NAND BOOT fuse blown failed miserably ...\n");
-           } else {
-               diag_printf("NAND BOOT fuse blown successfully ...\n");
-           }
-       } else {
-           diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
+                       diag_printf("Ready to burn NAND boot fuses\n");
+                       if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
+                               diag_printf("NAND BOOT fuse blown failed miserably ...\n");
+                       } else {
+                               diag_printf("NAND BOOT fuse blown successfully ...\n");
+                       }
+               } else {
+                       diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
 #endif
-       }
-    } else if (argc == 4) {
-       if (!parse_num(argv[1], &bank, &argv[1], " ")) {
-               diag_printf("Error: Invalid fuse bank\n");
-               return;
-       }
-       if (!parse_num(argv[2], &row, &argv[2], " ")) {
-               diag_printf("Error: Invalid fuse row\n");
-               return;
-       }
-       if (!parse_num(argv[3], &value, &argv[3], " ")) {
-               diag_printf("Error: Invalid value\n");
-               return;
-       }
-
-       if (!verify_action("Confirm to blow fuse at bank:%ld row:%ld value:0x%02lx (%ld)",
-                          bank, row, value)) {
-               diag_printf("fuse_blow canceled\n");
-               return;
-       }
+               }
+       } else if (argc == 4) {
+               if (!parse_num(argv[1], &bank, &argv[1], " ")) {
+                       diag_printf("Error: Invalid fuse bank\n");
+                       return;
+               }
+               if (!parse_num(argv[2], &row, &argv[2], " ")) {
+                       diag_printf("Error: Invalid fuse row\n");
+                       return;
+               }
+               if (!parse_num(argv[3], &value, &argv[3], " ")) {
+                       diag_printf("Error: Invalid value\n");
+                       return;
+               }
 
-       for (i = 0; i < 8; i++) {
-               if (((value >> i) & 0x1) == 0) {
-                       continue;
+               if (!verify_action("Confirm to blow fuse at bank:%ld row:%ld value:0x%02lx (%ld)",
+                                                       bank, row, value)) {
+                       diag_printf("fuse_blow canceled\n");
+                       return;
                }
-               if (fuse_blow(bank, row, i) != 0) {
-                       diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
-                                   bank, row, i);
-               } else {
-                       diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
-                                   bank, row, i);
+
+               for (i = 0; i < 8; i++) {
+                       if (((value >> i) & 0x1) == 0) {
+                               continue;
+                       }
+                       if (fuse_blow(bank, row, i) != 0) {
+                               diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
+                                                       bank, row, i);
+                       } else {
+                               diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
+                                                       bank, row, i);
+                       }
                }
+               sense_fuse(bank, row, 0);
+       } else {
+               diag_printf("Passing in wrong arguments: %d\n", argc);
        }
-       sense_fuse(bank, row, 0);
-    } else {
-       diag_printf("Passing in wrong arguments: %d\n", argc);
-    }
-    /* Reset to default string */
-    strcpy(ready_to_blow, INIT_STRING);
+       /* Reset to default string */
+       strcpy(ready_to_blow, INIT_STRING);
 }
 
 /* precondition: m>0 and n>0.  Let g=gcd(m,n). */
 int gcd(int m, int n)
 {
-    int t;
-    while (m > 0) {
-       if (n > m) {t = m; m = n; n = t;} /* swap */
-       m -= n;
-    }
-    return n;
+       int t;
+       while (m > 0) {
+               if (n > m) {t = m; m = n; n = t;} /* swap */
+               m -= n;
+       }
+       return n;
 }
 
 #define CLOCK_SRC_DETECT_MS         100
@@ -1093,53 +1092,53 @@ int gcd(int m, int n)
 void mxc_show_clk_input(void)
 {
 #if 0
-    u32 c1, c2, diff, ipg_real, num = 0;
-    u32 prcs = (readl(CCM_BASE_ADDR + CLKCTL_CCMR) >> 1) & 0x3;
-
-    return;  // FIXME
-
-    switch (prcs) {
-    case 0x01:
-       diag_printf("FPM enabled --> 32KHz input source\n");
-       return;
-    case 0x02:
-       break;
-    default:
-       diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
-       return;
-    }
+       u32 c1, c2, diff, ipg_real, num = 0;
+       u32 prcs = (readl(CCM_BASE_ADDR + CLKCTL_CCMR) >> 1) & 0x3;
 
-    // enable GPT with IPG clock input
-    writel(0x241, GPT_BASE_ADDR + GPTCR);
-    // prescaler = 1
-    writel(0, GPT_BASE_ADDR + GPTPR);
-
-    c1 = readl(GPT_BASE_ADDR + GPTCNT);
-    // use 32KHz input clock to get the delay
-    hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
-    c2 = readl(GPT_BASE_ADDR + GPTCNT);
-    diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
-
-    ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
-
-    if (ipg_real > (CLOCK_IPG_DEFAULT + CLOCK_SRC_DETECT_MARGIN)) {
-       if (g_clock_src != FREQ_27MHZ)
-           num = 27;
-    } else if (ipg_real < (CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN)) {
-       if (g_clock_src != FREQ_26MHZ)
-           num = 26;
-    }
-    if (num != 0) {
-       diag_printf("Error: Actual clock input is %d MHz\n", num);
-       diag_printf("       ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
-                   ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
-       diag_printf("       But clock source defined to be %d\n\n", g_clock_src);
-       hal_delay_us(2000000);
-    } else {
-       diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
-                   ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
-       diag_printf("clock source defined to be %d\n\n", g_clock_src);
-    }
+       return;  // FIXME
+
+       switch (prcs) {
+       case 0x01:
+               diag_printf("FPM enabled --> 32KHz input source\n");
+               return;
+       case 0x02:
+               break;
+       default:
+               diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
+               return;
+       }
+
+       // enable GPT with IPG clock input
+       writel(0x241, GPT_BASE_ADDR + GPTCR);
+       // prescaler = 1
+       writel(0, GPT_BASE_ADDR + GPTPR);
+
+       c1 = readl(GPT_BASE_ADDR + GPTCNT);
+       // use 32KHz input clock to get the delay
+       hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
+       c2 = readl(GPT_BASE_ADDR + GPTCNT);
+       diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
+
+       ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
+
+       if (ipg_real > (CLOCK_IPG_DEFAULT + CLOCK_SRC_DETECT_MARGIN)) {
+               if (g_clock_src != FREQ_27MHZ)
+                       num = 27;
+       } else if (ipg_real < (CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN)) {
+               if (g_clock_src != FREQ_26MHZ)
+                       num = 26;
+       }
+       if (num != 0) {
+               diag_printf("Error: Actual clock input is %d MHz\n", num);
+               diag_printf("       ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n",
+                                       ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+               diag_printf("       But clock source defined to be %d\n", g_clock_src);
+               hal_delay_us(2000000);
+       } else {
+               diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n",
+                                       ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
+               diag_printf("clock source defined to be %d\n", g_clock_src);
+       }
 #endif
 }
 
index 43bf4da..924d8a1 100644 (file)
@@ -46,6 +46,7 @@ cdl_package CYGPKG_HAL_ARM_MX51_3STACK {
         This HAL platform package provides generic
         support for the Freescale MX51 3-Stack Board."
 
+#    compile       board_misc.c board_diag.c mx51_fastlogo.c epson_lcd.c
     compile       board_misc.c board_diag.c
     implements    CYGINT_HAL_DEBUG_GDB_STUBS
     implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
@@ -182,7 +183,7 @@ cdl_package CYGPKG_HAL_ARM_MX51_3STACK {
             display "Global compiler flags"
             flavor  data
             no_define
-            default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
+            default_value { "-mcpu=cortex-a8 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
             description   "
                 This option controls the global compiler flags which are used to
                 compile all packages by default. Individual packages may define
index 7dc0e0c..a5aa96c 100644 (file)
@@ -66,4 +66,7 @@
 
 #define LED_MAX_NUM    8
 
+#define LCD_HEIGHT                  640
+#define LCD_WIDTH                   480
+#define DISPLAY_CHANNEL        28
 #endif /* CYGONCE_FSL_BOARD_H */
index 4619ad0..8a52d7e 100644 (file)
@@ -82,16 +82,67 @@ dcd_##i:                         ;\
     b reset_vector
     .org 0x400
 app_code_jump_v:    .long reset_vector
-app_code_barker:    .long 0xB1
-app_code_csf:       .long 0
+app_code_barker:    .long 0xB1                  // barker code
+app_code_csf:       .long (0x97f40000 - 0x1000) // reserve 4K for csf
 dcd_ptr_ptr:        .long dcd_ptr
-super_root_key:            .long 0
+super_root_key:            .long hab_super_root_key
 dcd_ptr:            .long dcd_data
 app_dest_ptr:       .long 0x97f00000
 
 dcd_data:                  .long 0xB17219E9   // Fixed. can't change.
-#ifdef IMX51_TO_2
-dcd_len:            .long (56*12)
+
+#ifdef IMX51_MDDR
+// DCD
+dcd_len:            .long (38*12)
+// DDR IOMUX configuration
+// Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
+DCDGEN(1, 4, IOMUXC_BASE_ADDR + 0x4b8, 0x000000e7)  // IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK       MAX DS
+DCDGEN(2, 4, IOMUXC_BASE_ADDR + 0x4d4, 0x000000e4)  // DQM0 DS high, slew rate slow
+DCDGEN(3, 4, IOMUXC_BASE_ADDR + 0x4d8, 0x000000e4)  // DQM1 DS high, slew rate slow
+DCDGEN(4, 4, IOMUXC_BASE_ADDR + 0x4dc, 0x000000e4)  // DQM2 DS high, slew rate slow
+DCDGEN(5, 4, IOMUXC_BASE_ADDR + 0x4e0, 0x000000e4)  // DQM3 DS high, slew rate slow
+DCDGEN(6, 4, IOMUXC_BASE_ADDR + 0x4bc, 0x000000c4)  // SDQS0 DS high, slew rate slow
+DCDGEN(7, 4, IOMUXC_BASE_ADDR + 0x4c0, 0x000000c4)  // SDQS1 DS high, slew rate slow
+DCDGEN(8, 4, IOMUXC_BASE_ADDR + 0x4c4, 0x000000c4)  // SDQS2 DS high, slew rate slow
+DCDGEN(9, 4, IOMUXC_BASE_ADDR + 0x4c8, 0x000000c4)  // SDQS3 DS high, slew rate slow
+DCDGEN(10, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000004)  // DRAM_B0
+DCDGEN(11, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000004)  // DRAM_B1
+DCDGEN(12, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000004)  // DRAM_B2
+DCDGEN(13, 4, IOMUXC_BASE_ADDR + 0x82c, 0x00000004)  // DRAM_B3
+DCDGEN(14, 4, IOMUXC_BASE_ADDR + 0x878, 0x00000000)  // DRAM_B0_SR
+DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x880, 0x00000000)  // DRAM_B1_SR
+DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x88c, 0x00000000)  // DRAM_B2_SR
+DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x89c, 0x00000000)  // DRAM_B3_SR
+// Configure CS0
+DCDGEN(18, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x83220000) // ESDCTL0: Enable controller
+DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008) // ESDSCR: Precharge command
+DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
+DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010) // ESDSCR: Refresh command
+DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801a) // ESDSCR: EMR with Half Drive strength
+DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000) // ESDSCR
+DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xC3220000) // ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
+// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+//          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xC33574AA)
+DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000a1700) // ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
+// Configure CS1
+DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x83220000) // ESDCTL1: Enable controller
+DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c) // ESDSCR: Precharge command
+DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
+DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014) // ESDSCR: Refresh command
+DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0033801c) // ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
+DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0060801e) // ESDSCR: EMR with Half Drive strength
+DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004) // ESDSCR
+DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xC3220000) // ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
+// ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
+//          tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
+DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0xC33574AA)
+DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) // ESDSCR - clear "configuration request" bit
+DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00f58000) //Delay line write - -11
+
+#else
+dcd_len:            .long (57*12)
 
 //DCD
 //DDR2 IOMUX configuration
@@ -113,93 +164,55 @@ DCDGEN(15, 4, IOMUXC_BASE_ADDR + 0x4b0, 0xe3)
 DCDGEN(16, 4, IOMUXC_BASE_ADDR + 0x4b4, 0xe3)
 DCDGEN(17, 4, IOMUXC_BASE_ADDR + 0x4cc, 0xe3)
 DCDGEN(18, 4, IOMUXC_BASE_ADDR + 0x4d0, 0xe2)
-//Set drive strength to MAX
-DCDGEN(19, 4, IOMUXC_BASE_ADDR + 0x82c, 0x6)
-DCDGEN(20, 4, IOMUXC_BASE_ADDR + 0x8a4, 0x6)
-DCDGEN(21, 4, IOMUXC_BASE_ADDR + 0x8ac, 0x6)
-DCDGEN(22, 4, IOMUXC_BASE_ADDR + 0x8b8, 0x6)
 //13 ROW, 10 COL, 32Bit, SREF=4 Micron Model
 //CAS=3,  BL=4
-DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
-DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
-DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
-DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
-DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
+DCDGEN(19, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x82a20000)
+DCDGEN(20, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0x82a20000)
+DCDGEN(21, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad0d0)
+DCDGEN(22, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0x333574aa)
+DCDGEN(23, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, 0x333574aa)
 // Init DRAM on CS0
-DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
-DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
-DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00448019)
-DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
-DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
-DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
-DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00408019)
-DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
+DCDGEN(24, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(25, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801a)
+DCDGEN(26, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801b)
+DCDGEN(27, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008019)
+DCDGEN(28, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x07328018)
+DCDGEN(29, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
+DCDGEN(30, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(31, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
+DCDGEN(32, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x06328018)
+DCDGEN(33, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x03808019)
+DCDGEN(34, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00428019)
+DCDGEN(35, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008000)
 
 // Init DRAM on CS1
-DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
-DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
-DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
-DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
-DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
-DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
-DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
-DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
-DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0040801d)
-DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
-
-DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
-DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
-DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
-DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
-DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
-
-#else
-dcd_len:            .long (9*12)
-
-//DCD
-    //    ldr r0, ESDCTL_BASE_W
-    //    /* Set CSD0 */
-    //    ldr r1, =0x80000000
-    //    str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(1, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
-    //    /* Precharge command */
-    //    ldr r1, SDRAM_0x04008008
-    //    str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(2, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
-    //    /* 2 refresh commands */
-    //    ldr r1, SDRAM_0x00008010
-    //    str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(3, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-    //    str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(4, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
-    //    /* LMR with CAS=3 and BL=3 */
-    //    ldr r1, SDRAM_0x00338018
-    //    str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(5, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
-    //    /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
-    //    ldr r1, SDRAM_0xB2220000
-    //    str r1, [r0, #ESDCTL_ESDCTL0]
-DCDGEN(6, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xB2220000)
-    //    /* Timing parameters */
-    //    ldr r1, SDRAM_0xB02567A9
-    //    str r1, [r0, #ESDCTL_ESDCFG0]
-DCDGEN(7, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, 0xB02567A9)
-    //    /* MDDR enable, RLAT=2 */
-    //    ldr r1, SDRAM_0x000A0104
-    //    str r1, [r0, #ESDCTL_ESDMISC]
-DCDGEN(8, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000A0104)
-    //    /* Normal mode */
-    //    ldr r1, =0x00000000
-    //    str r1, [r0, #ESDCTL_ESDSCR]
-DCDGEN(9, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0)
+DCDGEN(36, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(37, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801e)
+DCDGEN(38, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801f)
+DCDGEN(39, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0000801d)
+DCDGEN(40, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0732801c)
+DCDGEN(41, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0400800c)
+DCDGEN(42, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(43, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008014)
+DCDGEN(44, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0632801c)
+DCDGEN(45, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0380801d)
+DCDGEN(46, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x0042801d)
+DCDGEN(47, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008004)
+
+DCDGEN(48, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0xb2a20000)
+DCDGEN(49, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, 0xb2a20000)
+DCDGEN(50, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, 0x000ad6d0)
+DCDGEN(51, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLYGD, 0x90000000)
+DCDGEN(52, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
+
+// Delay settings
+DCDGEN(53, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY1, 0x00048000)
+DCDGEN(54, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY2, 0x000e8000)
+DCDGEN(55, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY3, 0x00ff8000)
+DCDGEN(56, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY4, 0x00fa8000)
+DCDGEN(57, 4, ESDCTL_BASE_ADDR + ESDCTL_ESDCDLY5, 0x00ed8000)
 #endif
-image_len:           .long 256*1024
+image_len:           .long 256 * 1024   // 256K for Redboot and csf
 
 .endm
 
@@ -208,8 +221,17 @@ image_len:           .long 256*1024
 // This macro represents the initial startup code for the platform
     .macro  _platform_setup1
 FSL_BOARD_SETUP_START:
-    // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work???
-    // mcr p15, 0, <Rd>, c1, c1, 0 ; Write Secure Configuration Register data
+        ldr r1, =ROM_BASE_ADDR
+        ldr r3, [r1, #ROM_SI_REV_OFFSET]
+
+        setup_sdram
+
+        ldr r0, =GPC_BASE_ADDR
+        cmp r3, #0x10    // r3 contains the silicon rev
+        ldrls r1, =0x1FC00000
+        ldrhi r1, =0x1A800000
+        str r1, [r0, #4]
+
 #ifdef ENABLE_IMPRECISE_ABORT
         mrs r1, spsr            // save old spsr
         mrs r0, cpsr            // read out the cpsr
@@ -232,176 +254,27 @@ FSL_BOARD_SETUP_START:
     // reconfigure L2 cache aux control reg
     mov r0, #0xC0              // tag RAM
     add r0, r0, #0x4   // data RAM
-    orr r0, r0, #(1 << 25)    // disable write combine
     orr r0, r0, #(1 << 24)    // disable write allocate delay
     orr r0, r0, #(1 << 23)    // disable write allocate combine
     orr r0, r0, #(1 << 22)    // disable write allocate
 
+    cmp r3, #0x10    // r3 contains the silicon rev
+    orrls r0, r0, #(1 << 25)    // disable write combine for TO 2 and lower revs
+
     mcr 15, 1, r0, c9, c0, 2
 
-    /* Reload data from spare area to 0x400 of main area if booting from NAND */
-    ldr r0, NFC_BASE_W
-    cmp pc, r0
-    blo 1f
-    cmp pc, r1
-    bhi 1f
-1:
-    /* Store the boot type, from NAND or SDRAM */
-    mov r11, #SDRAM_NON_FLASH_BOOT
-
-init_spba_start:
-    init_spba
 init_aips_start:
     init_aips
-init_max_start:
-    init_max
 init_m4if_start:
     init_m4if
-init_iomux_start:
-//    init_iomux
-
-    // disable wdog
-    ldr r0, =0x30
-    ldr r1, WDOG1_BASE_W
-    strh r0, [r1]
-
-    /* If SDRAM has been setup, bypass clock/WEIM setup */
-    cmp pc, #SDRAM_BASE_ADDR
-    blo external_boot_cont
-    cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
-    blo internal_boot_cont
-
-external_boot_cont:
-
-init_sdram_start:
-    setup_sdram
-
-
-internal_boot_cont:
-init_clock_start:
-    init_clock
-
-HWInitialise_skip_SDRAM_setup:
-    ldr r0, NFC_BASE_W
-    add r2, r0, #0x1000      // 4K window
-    cmp pc, r0
-    blo Normal_Boot_Continue
-    cmp pc, r2
-    bhi Normal_Boot_Continue
-
-NAND_Boot_Start:
-    /* Copy image from flash to SDRAM first */
-    ldr r1, MXC_REDBOOT_ROM_START
-1:  ldmia r0!, {r3-r10}
-    stmia r1!, {r3-r10}
-    cmp r0, r2
-    blo 1b
-
-    /* Jump to SDRAM */
-    ldr r1, CONST_0x0FFF
-    and r0, pc, r1     /* offset of pc */
-    ldr r1, MXC_REDBOOT_ROM_START
-    add r1, r1, #0x10
-    add pc, r0, r1
-    nop
-    nop
-    nop
-    nop
-    nop
-    nop
-
-NAND_Copy_Main:
-    ldr r11, NFC_IP_BASE_W  //r11: NFC IP register base. Doesn't change
-    ldr r0, [r11, #0x24]
-    and r0, r0, #3
-    cmp r0, #1
-    mov r0, #4096
-    moveq r0, #2048
-    movlt r0, #512
-    ldr r1, =_nand_pg_sz // r1 -> _nand_pg_sz
-    str r0, [r1]    // store the page size into the global variable _nand_pg_sz
-
-    ldr r0, NFC_BASE_W   //r0: nfc base. Reloaded after each page copying
-    ldr r1, _nand_pg_sz //r1: starting flash addr to be copied. Updated constantly
-    add r2, r0, #0x800   //r2: end of 3rd RAM buf. Doesn't change ?? dynamic
-    cmp r1, #2048
-    addgt r2, r2, #2048 // for 4K page, copy 4K instead of 2K
-
-    add r12, r0, #0x1E00  //r12: NFC AXI register base. Doesn't change
-    ldr r14, MXC_REDBOOT_ROM_START
-    add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
-    add r14, r14, r1     //r14: starting SDRAM address for copying. Updated constantly
-
-    //unlock internal buffer
-    mov r3, #0xFF000000
-    add r3, r3, #0x00FF0000
-    str r3, [r11, #0x4]
-    str r3, [r11, #0x8]
-    str r3, [r11, #0xC]
-    str r3, [r11, #0x10]
-    str r3, [r11, #0x14]
-    str r3, [r11, #0x18]
-    str r3, [r11, #0x1C]
-    str r3, [r11, #0x20]
-    mov r4, #0x7
-    mov r3, #0x84
-1:  add r5, r3, r4, lsr #3
-    str r5, [r11, #0x0]
-    subs r4, r4, #0x1
-    bne 1b
-
-    mov r3, #0
-    str r3, [r11, #0x2C]
-
-Nfc_Read_Page:
-    //start_nfc_addr_ops1(pg_no, pg_off);
-    ldr r3, _nand_pg_sz
-    cmp r3, #2048
-    // TODO: need to deal with 512B page
-    movgt r3, r1, lsr #12  // get the page number for 4K page nand
-    moveq r3, r1, lsr #11  // get the page number for 2K page nand
-    mov r3, r3, lsl #16
-    str r3, [r12, #0x4] // set the addr
-
-    // writel((FLASH_Read_Mode1_LG << 8) | FLASH_Read_Mode1, NAND_CMD_REG);
-    mov r3, #0x3000
-    str r3, [r12, #0x0]
-
-    // writel(0x00000000, NAND_CONFIGURATION1_REG);
-    mov r3, #0x0
-    str r3, [r12, #0x34]
-
-    // start auto-read
-    //writel(NAND_LAUNCH_AUTO_READ, NAND_LAUNCH_REG);
-    mov r3, #NAND_LAUNCH_AUTO_READ
-    str r3, [r12, #0x40]
-
-    do_wait_op_done
-
-Copy_Good_Blk:
-    //copying page
-1:  ldmia r0!, {r3-r10}
-    stmia r14!, {r3-r10}
-    cmp r0, r2
-    blo 1b
-    cmp r14, r13
-    bge NAND_Copy_Main_done
-    ldr r3, _nand_pg_sz
-    add r1, r1, r3
-    ldr r0, NFC_BASE_W
-    b Nfc_Read_Page
-
-NAND_Copy_Main_done:
-
-Normal_Boot_Continue:
 
 #ifdef CYG_HAL_STARTUP_ROMRAM     /* enable running from RAM */
-    /* Copy image from flash to SDRAM first */
+    /* Check if need to copy image to Redboot ROM space */
     ldr r0, =0xFFFFF000
     and r0, r0, pc
     ldr r1, MXC_REDBOOT_ROM_START
     cmp r0, r1
-    beq HWInitialise_skip_SDRAM_copy
+    beq skip_copy_to_ddr
 
     add r2, r0, #REDBOOT_IMAGE_SIZE
 
@@ -420,10 +293,24 @@ Normal_Boot_Continue:
     nop
 #endif /* CYG_HAL_STARTUP_ROMRAM */
 
-HWInitialise_skip_SDRAM_copy:
+skip_copy_to_ddr:
+    /* Skip clock setup if already booted up */
+    ldr r0, =IRAM_BASE_ADDR
+    ldr r0, [r0]
+    ldr r1, =FROM_SPI_NOR_FLASH
+    cmp r0, r1
+    beq Normal_Boot_Continue
+    ldr r1, =FROM_MMC_FLASH
+    cmp r0, r1
+    beq Normal_Boot_Continue
+    ldr r1, =FROM_NAND_FLASH
+    cmp r0, r1
+    beq Normal_Boot_Continue
+
+init_clock_start:
+    init_clock
 
-init_cs1_start:
-//    init_cs1 -- moved to plf_hardware_init()
+Normal_Boot_Continue:
 
 /*
  * Note:
@@ -438,24 +325,25 @@ STACK_Setup:
     // Create MMU tables
     bl hal_mmu_init
 
+    /* Workaround for arm errata #709718 */
+    //Setup PRRR so device is always mapped to non-shared
+    mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
+    bic r1, #(3 << 16)
+    mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
+
     // Enable MMU
     ldr r2, =10f
-    ldr r0, =ROM_BASE_ADDRESS
-    ldr r3, [r0, #ROM_SI_REV_OFFSET]
-    cmp r3, #0x1
-    bne skip_L1_workaround
-    // Workaround for L1 cache issue
-    mrc MMU_CP, 0, r1, c10, c2, 1  // Read normal memory remap register
-    bic r1, r1, #(3 << 14)       // Remap inner attribute for TEX[0],C,B = b111 as noncacheable
-    bic r1, r1, #(3 << 6)       // Remap inner attribute for TEX[0],C,B = b011 as noncacheable
-    bic r1, r1, #(3 << 4)       // Remap inner attribute for TEX[0],C,B = b010 as noncacheable
-    mcr MMU_CP, 0, r1, c10, c2, 1  // Write normal memory remap register
-skip_L1_workaround:
-    mrc MMU_CP, 0, r1, MMU_Control, c0      // get c1 value to r1 first
+    mrc MMU_CP, 0, r1, MMU_Control, c0
     orr r1, r1, #7                          // enable MMU bit
     orr r1, r1, #0x800                      // enable z bit
-    orrne r1, r1, #(1 << 28)            // Enable TEX remap, workaround for L1 cache issue
+    orr r1, r1, #(1 << 28)              // Enable TEX remap
     mcr MMU_CP, 0, r1, MMU_Control, c0
+
+    /* Workaround for arm errata #621766 */
+    mrc MMU_CP, 0, r1, MMU_Control, c0, 1
+    orr r1, r1, #(1 << 5)                // enable L1NEON bit
+    mcr MMU_CP, 0, r1, MMU_Control, c0, 1
+
     mov pc,r2    /* Change address spaces */
     nop
     nop
@@ -474,10 +362,6 @@ skip_L1_workaround:
 #define PLATFORM_SETUP1
 #endif
 
-    /* Do nothing */
-    .macro  init_spba
-    .endm  /* init_spba */
-
     /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
     .macro init_aips
         /*
@@ -494,25 +378,36 @@ skip_L1_workaround:
 
     .endm /* init_aips */
 
-    /* MAX (Multi-Layer AHB Crossbar Switch) setup */
-    .macro init_max
-    .endm /* init_max */
-
     .macro    init_clock
         ldr r0, CCM_BASE_ADDR_W
+
+        /* Gate of clocks to the peripherals first */
+        ldr r1, =0x3FFFFFFF
+        str r1, [r0, #CLKCTL_CCGR0]
+        ldr r1, =0x0
+        str r1, [r0, #CLKCTL_CCGR1]
+        str r1, [r0, #CLKCTL_CCGR2]
+        str r1, [r0, #CLKCTL_CCGR3]
+
+        ldr r1, =0x00030000
+        str r1, [r0, #CLKCTL_CCGR4]
+        ldr r1, =0x00FFF030
+        str r1, [r0, #CLKCTL_CCGR5]
+        ldr r1, =0x00000300
+        str r1, [r0, #CLKCTL_CCGR6]
+
         /* Disable IPU and HSC dividers */
         mov r1, #0x60000
         str r1, [r0, #CLKCTL_CCDR]
 
-#ifdef IMX51_TO_2
         /* Make sure to switch the DDR away from PLL 1 */
-        ldr r1, CCM_VAL_0x19239100
+        ldr r1, CCM_VAL_0x19239145
         str r1, [r0, #CLKCTL_CBCDR]
         /* make sure divider effective */
     1:  ldr r1, [r0, #CLKCTL_CDHIPR]
         cmp r1, #0x0
         bne 1b
-#endif
+
         /* Switch ARM to step clock */
         mov r1, #0x4
         str r1, [r0, #CLKCTL_CCSR]
@@ -521,16 +416,16 @@ skip_L1_workaround:
         setup_pll PLL3, 665
         /* Switch peripheral to PLL 3 */
         ldr r0, CCM_BASE_ADDR_W
-        ldr r1, CCM_VAL_0x0000D3C0
+        ldr r1, CCM_VAL_0x000010C0
         str r1, [r0, #CLKCTL_CBCMR]
-        ldr r1, CCM_VAL_0x033B9145
+        ldr r1, CCM_VAL_0x13239145
         str r1, [r0, #CLKCTL_CBCDR]
         setup_pll PLL2, 665
         /* Switch peripheral to PLL 2 */
         ldr r0, CCM_BASE_ADDR_W
-        ldr r1, CCM_VAL_0x013B9145
+        ldr r1, CCM_VAL_0x19239145
         str r1, [r0, #CLKCTL_CBCDR]
-        ldr r1, CCM_VAL_0x0000E3C0
+        ldr r1, CCM_VAL_0x000020C0
         str r1, [r0, #CLKCTL_CBCMR]
 
         setup_pll PLL3, 216
@@ -540,29 +435,41 @@ skip_L1_workaround:
         ldr r1, PLATFORM_CLOCK_DIV_W
         str r1, [r0, #PLATFORM_ICGC]
 
-        /* Switch ARM back to PLL 1. */
         ldr r0, CCM_BASE_ADDR_W
+        /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
+        ldr r1, =ROM_BASE_ADDR
+        ldr r3, [r1, #ROM_SI_REV_OFFSET]
+        cmp r3, #0x10
+        movls r1, #0x1
+        movhi r1, #0
+        str r1, [r0, #CLKCTL_CACRR]
+
+        /* Switch ARM back to PLL 1. */
         mov r1, #0x0
         str r1, [r0, #CLKCTL_CCSR]
 
         /* setup the rest */
-        mov r1, #0
-        str r1, [r0, #CLKCTL_CACRR]
-
         /* Use lp_apm (24MHz) source for perclk */
-#ifdef IMX51_TO_2
         ldr r1, CCM_VAL_0x000020C2
         str r1, [r0, #CLKCTL_CBCMR]
         // ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
-        ldr r1, CCM_VAL_0x59239100
-        str r1, [r0, #CLKCTL_CBCDR]
+#ifdef IMX51_MDDR
+        ldr r1, CCM_VAL_0x61E35100
 #else
-        ldr r1, CCM_VAL_0x0000E3C2
-        str r1, [r0, #CLKCTL_CBCMR]
-        // emi=ahb, all perclk dividers are 1 since using 24MHz
-        ldr r1, CCM_VAL_0x013B9100
-        str r1, [r0, #CLKCTL_CBCDR]
+        ldr r1, CCM_VAL_0x59E35100
 #endif
+        str r1, [r0, #CLKCTL_CBCDR]
+
+        /* Restore the default values in the Gate registers */
+        ldr r1, =0xFFFFFFFF
+        str r1, [r0, #CLKCTL_CCGR0]
+        str r1, [r0, #CLKCTL_CCGR1]
+        str r1, [r0, #CLKCTL_CCGR2]
+        str r1, [r0, #CLKCTL_CCGR3]
+        str r1, [r0, #CLKCTL_CCGR4]
+        str r1, [r0, #CLKCTL_CCGR5]
+        str r1, [r0, #CLKCTL_CCGR6]
+
         /* Use PLL 2 for UART's, get 66.5MHz from it */
         ldr r1, CCM_VAL_0xA5A2A020
         str r1, [r0, #CLKCTL_CSCMR1]
@@ -614,70 +521,64 @@ wait_pll_lock\pll_nr\mhz:
     /* M3IF setup */
     .macro init_m4if
         ldr r1, M4IF_BASE_W
-#ifdef IMX51_TO_2
-        ldr r0, M4IF_0x00240180
-        str r0, [r1, #M4IF_MIF4]
-#else
-        /* IPU accesses with ID=0x1 given highest priority (=0xA) */
-        ldr r0, M4IF_0x00000a01
-        str r0, [r1, #M4IF_FIDBP]
-#endif
-        /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
-        ldr r0, M4IF_0x00000404
+        ldr r0, M4IF_0x00000203
         str r0, [r1, #M4IF_FBPM0]
+
+        ldr r0, =0x0
+        str r0, [r1, #M4IF_FBPM1]
+
+        ldr r0, M4IF_0x00120125
+        str r0, [r1, #M4IF_FPWC]
+
+        ldr r0, M4IF_0x001901A3
+        str r0, [r1, #M4IF_MIF4]
+
     .endm /* init_m4if */
 
     .macro setup_sdram
+        cmp r3, #0x10    // r3 contains the silicon rev
+        bls skip_setup
+        /* Decrease the DRAM SDCLK to HIGH Drive strength */
+        ldr r0, IOMUXC_BASE_ADDR_W
+        ldr r1, =0x000000e5
+        str r1, [r0, #0x4b8]
+        /* Change the delay line configuration */
         ldr r0, ESDCTL_BASE_W
-        /* Set CSD0 */
-        ldr r1, =0x80000000
-        str r1, [r0, #ESDCTL_ESDCTL0]
-        /* Precharge command */
-        ldr r1, SDRAM_0x04008008
-        str r1, [r0, #ESDCTL_ESDSCR]
-        /* 2 refresh commands */
-        ldr r1, SDRAM_0x00008010
-        str r1, [r0, #ESDCTL_ESDSCR]
-        str r1, [r0, #ESDCTL_ESDSCR]
-        /* LMR with CAS=3 and BL=3 */
-        ldr r1, SDRAM_0x00338018
-        str r1, [r0, #ESDCTL_ESDSCR]
-        /* 13 ROW, 10 COL, 32Bit, SREF=4 Micron Model */
-        ldr r1, SDRAM_0xB2220000
-        str r1, [r0, #ESDCTL_ESDCTL0]
-        /* Timing parameters */
-//        ldr r1, SDRAM_0x899F6BBA
-        ldr r1, SDRAM_0xB02567A9
-        str r1, [r0, #ESDCTL_ESDCFG0]
-        /* MDDR enable, RLAT=2 */
-        ldr r1, SDRAM_0x000A0104
-        str r1, [r0, #ESDCTL_ESDMISC]
-        /* Normal mode */
-        ldr r1, =0x00000000
-        str r1, [r0, #ESDCTL_ESDSCR]
+        ldr r1, =0x00f49400
+        str r1, [r0, #ESDCTL_ESDCDLY1]
+        ldr r1, =0x00f49a00
+        str r1, [r0, #ESDCTL_ESDCDLY2]
+        ldr r1, =0x00f49100
+        str r1, [r0, #ESDCTL_ESDCDLY3]
+        ldr r1, =0x00f48900
+        str r1, [r0, #ESDCTL_ESDCDLY4]
+        ldr r1, =0x00f49400
+        str r1, [r0, #ESDCTL_ESDCDLY5]
+skip_setup:
     .endm
 
-    .macro do_wait_op_done
-    1:
-        ldr r3, [r11, #0x2C]
-        ands r3, r3, #NFC_IPC_INT
-        beq 1b
-        mov r3, #0x0
-        str r3, [r11, #0x2C]
-    .endm   // do_wait_op_done
-
-    .macro  init_iomux
-        // do nothing
-    .endm /* init_iomux */
-
 #define PLATFORM_VECTORS         _platform_vectors
     .macro  _platform_vectors
         .globl  _board_BCR, _board_CFG
 _board_BCR:     .long   0       // Board Control register shadow
 _board_CFG:     .long   0       // Board Configuration (read at RESET)
+       .globl  _KARO_MAGIC
+_KARO_MAGIC:
+       .ascii  "KARO_CE6"
+       .globl  _KARO_STRUCT_SIZE
+_KARO_STRUCT_SIZE:
+       .word   0       // reserve space structure length
+
+       .globl  _KARO_CECFG_START
+_KARO_CECFG_START:
+       .rept   1024/4
+       .word   0       // reserve space for CE configuration
+       .endr
+
+       .globl  _KARO_CECFG_END
+_KARO_CECFG_END:
     .endm
 
-WDOG1_BASE_W:           .word   WDOG1_BASE_ADDR
 IIM_SREV_REG_VAL:       .word   IIM_BASE_ADDR + IIM_SREV_OFF
 AIPS1_CTRL_BASE_ADDR_W: .word   AIPS1_CTRL_BASE_ADDR
 AIPS2_CTRL_BASE_ADDR_W: .word   AIPS2_CTRL_BASE_ADDR
@@ -686,11 +587,9 @@ MAX_BASE_ADDR_W:        .word   MAX_BASE_ADDR
 MAX_PARAM1:             .word   0x00302154
 ESDCTL_BASE_W:          .word   ESDCTL_BASE_ADDR
 M4IF_BASE_W:            .word   M4IF_BASE_ADDR
-M4IF_0x00000a01:       .word   0x00000a01
-M4IF_0x00240180:       .word   0x00240180
-M4IF_0x00000404:       .word   0x00000404
-NFC_BASE_W:             .word   NFC_BASE_ADDR_AXI
-NFC_IP_BASE_W:          .word   NFC_IP_BASE
+M4IF_0x00120125:       .word   0x00120125
+M4IF_0x001901A3:       .word   0x001901A3
+M4IF_0x00000203:       .word   0x00000203
 SDRAM_0x04008008:       .word   0x04008008
 SDRAM_0x00008010:       .word   0x00008010
 SDRAM_0x00338018:       .word   0x00338018
@@ -705,14 +604,14 @@ CCM_BASE_ADDR_W:        .word   CCM_BASE_ADDR
 CCM_VAL_0x0000E3C2:     .word   0x0000E3C2
 CCM_VAL_0x000020C2:     .word   0x000020C2
 CCM_VAL_0x013B9100:     .word   0x013B9100
-CCM_VAL_0x59239100:     .word   0x59239100
-CCM_VAL_0x19239100:     .word   0x19239100
+CCM_VAL_0x59E35100:     .word   0x59E35100
+CCM_VAL_0x61E35100:     .word   0x61E35100
+CCM_VAL_0x19239145:     .word   0x19239145
 CCM_VAL_0xA5A2A020:     .word   0xA5A2A020
 CCM_VAL_0x00C30321:     .word   0x00C30321
-CCM_VAL_0x0000D3C0:     .word   0x0000D3C0
-CCM_VAL_0x033B9145:     .word   0x033B9145
-CCM_VAL_0x013B9145:     .word   0x013B9145
-CCM_VAL_0x0000E3C0:     .word   0x0000E3C0
+CCM_VAL_0x000010C0:     .word   0x000010C0
+CCM_VAL_0x13239145:     .word   0x13239145
+CCM_VAL_0x000020C0:     .word   0x000020C0
 PLL_VAL_0x222:          .word   0x222
 PLL_VAL_0x232:          .word   0x232
 BASE_ADDR_W_PLL1:       .word   PLL1_BASE_ADDR
@@ -738,8 +637,7 @@ W_DP_OP_216:            .word   DP_OP_216
 W_DP_MFD_216:           .word   DP_MFD_216
 W_DP_MFN_216:           .word   DP_MFN_216
 PLATFORM_BASE_ADDR_W:   .word   PLATFORM_BASE_ADDR
-PLATFORM_CLOCK_DIV_W:   .word   0x00000725
-_nand_pg_sz:            .word 0
+PLATFORM_CLOCK_DIV_W:   .word   0x00000124
 
 /*---------------------------------------------------------------------------*/
 /* end of hal_platform_setup.h                                               */
index 2235f29..7b2e884 100644 (file)
 extern unsigned int cpld_base_addr;
 
 #define LAN92XX_REG_READ(reg_offset)  \
-    (*(volatile unsigned int *)(cpld_base_addr + reg_offset))
+       (*(volatile unsigned int *)(cpld_base_addr + reg_offset))
 
 #define LAN92XX_REG_WRITE(reg_offset, val)  \
-    (*(volatile unsigned int *)(cpld_base_addr + reg_offset) = (val))
+       (*(volatile unsigned int *)(cpld_base_addr + reg_offset) = (val))
 
-#define LED_IS_ON(n)    ((readw(cpld_base_addr + PBC_LED_CTRL) & (1 << (n))) != 0)
+#define LED_IS_ON(n)   ((readw(cpld_base_addr + PBC_LED_CTRL) & (1 << (n))) != 0)
 #define TURN_LED_ON(n)  writew((readw(cpld_base_addr + PBC_LED_CTRL) | (1 << (n))), cpld_base_addr + PBC_LED_CTRL)
 #define TURN_LED_OFF(n) writew((readw(cpld_base_addr + PBC_LED_CTRL) & (~(1<<(n)))), cpld_base_addr + PBC_LED_CTRL)
 
-#define BOARD_DEBUG_LED(n)   0
+#define BOARD_DEBUG_LED(n)   CYG_EMPTY_STATEMENT
 /*
-#define BOARD_DEBUG_LED(n)                     \
+#define BOARD_DEBUG_LED(n)                     \
     CYG_MACRO_START                            \
-        if (n >= 0 && n < LED_MAX_NUM) {       \
-               if (LED_IS_ON(n))               \
-                       TURN_LED_OFF(n);        \
-               else                            \
+        if (n >= 0 && n < LED_MAX_NUM) {       \
+               if (LED_IS_ON(n))               \
+                       TURN_LED_OFF(n);        \
+               else                            \
                        TURN_LED_ON(n);         \
        }                                       \
     CYG_MACRO_END
@@ -72,27 +72,27 @@ extern unsigned int cpld_base_addr;
 
 extern unsigned int system_rev;
 
-#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_)                                  \
-    CYG_MACRO_START                                                                                  \
-    {                                                                                                              \
-      extern unsigned int system_rev;                                                             \
-             /* Next ATAG_MEM. */                                                                     \
-         _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long);        \
-         _p_->hdr.tag = ATAG_MEM;                                                                    \
-         /* Round up so there's only one bit set in the memory size.                        \
-         * Don't double it if it's already a power of two, though.                                \
-         */                                                                                                          \
-         _p_->u.mem.size  = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE);    \
-         if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE)                                \
-                 _p_->u.mem.size <<= 1;                                                                \
-         if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2)            \
-                 _p_->u.mem.size = 512 * 0x100000;                          \
-         _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram);    \
-         _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size);                                          \
-         _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long);   \
-         _p_->hdr.tag = ATAG_REVISION;                                                               \
-         _p_->u.revision.rev = system_rev;                                                           \
-     }                                                                                               \
-    CYG_MACRO_END
+#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_)                                                             \
+       CYG_MACRO_START                                                                                                         \
+       {                                                                                                                                       \
+               extern unsigned int system_rev;                                                                 \
+               /* Next ATAG_MEM. */                                                                                    \
+               _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header)) / sizeof(long); \
+               _p_->hdr.tag = ATAG_MEM;                                                                                \
+               /* Round up so there's only one bit set in the memory size.             \
+                * Don't double it if it's already a power of two, though.              \
+                */                                                                                                                             \
+               _p_->u.mem.size  = 1<<hal_msbindex(CYGMEM_REGION_ram_SIZE);             \
+               if (_p_->u.mem.size < CYGMEM_REGION_ram_SIZE)                                   \
+                       _p_->u.mem.size <<= 1;                                                                          \
+               if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2)                 \
+                       _p_->u.mem.size = 512 * 0x100000;                                                       \
+               _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram);  \
+               _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size);                              \
+               _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header)) / sizeof(long);     \
+               _p_->hdr.tag = ATAG_REVISION;                                                                   \
+               _p_->u.revision.rev = system_rev;                                                               \
+       }                                                                                                                                       \
+       CYG_MACRO_END
 
 #endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H
index 48462cc..d32f9f0 100644 (file)
@@ -17,13 +17,15 @@ cdl_configuration eCos {
     package -hardware CYGPKG_IO_ETH_DRIVERS current ;
     package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
     package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
-    package -hardware CYGPKG_DEVS_ETH_FEC current ;
+    #package -hardware CYGPKG_DEVS_ETH_FEC current ;
     package -hardware CYGPKG_COMPRESS_ZLIB current ;
     package -hardware CYGPKG_DIAGNOSIS current ;
     package -hardware CYGPKG_IO_FLASH current ;
     package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
     package -hardware CYGPKG_DEVS_IMX_SPI current ;
     package -hardware CYGPKG_DEVS_MXC_I2C current ;
+    package -hardware CYGPKG_DEVS_IMX_IPU current ;
+    package -hardware CYGPKG_IMX_CMDS current ;
     package -template CYGPKG_HAL current ;
     package -template CYGPKG_INFRA current ;
     package -template CYGPKG_REDBOOT current ;
@@ -38,7 +40,11 @@ cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
 };
 
 cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
-    inferred_value 0
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+    inferred_value 1
 };
 
 cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
@@ -53,6 +59,10 @@ cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
     inferred_value 1
 };
 
+cdl_option CYGHWR_DEVS_IPU_3_EX {
+    inferred_value 1
+};
+
 cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
     inferred_value 0
 };
@@ -138,5 +148,5 @@ cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
 };
 
 cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
-    user_value 1 "FSL 200904"
+    user_value 1 "FSL 200938"
 };
diff --git a/packages/hal/arm/mx51/3stack/v2_0/misc/redboot_ROMRAM_mddr.ecm b/packages/hal/arm/mx51/3stack/v2_0/misc/redboot_ROMRAM_mddr.ecm
new file mode 100644 (file)
index 0000000..5379d26
--- /dev/null
@@ -0,0 +1,156 @@
+cdl_savefile_version 1;
+cdl_savefile_command cdl_savefile_version {};
+cdl_savefile_command cdl_savefile_command {};
+cdl_savefile_command cdl_configuration { description hardware template package };
+cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
+cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
+
+cdl_configuration eCos {
+    description "" ;
+    hardware    mx51_3stack ;
+    template    redboot ;
+    package -hardware CYGPKG_HAL_ARM current ;
+    package -hardware CYGPKG_HAL_ARM_MX51 current ;
+    package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ;
+    package -hardware CYGPKG_IO_ETH_DRIVERS current ;
+    package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
+    package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
+    #package -hardware CYGPKG_DEVS_ETH_FEC current ;
+    package -hardware CYGPKG_COMPRESS_ZLIB current ;
+    package -hardware CYGPKG_DIAGNOSIS current ;
+    package -hardware CYGPKG_IO_FLASH current ;
+    package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
+    package -hardware CYGPKG_DEVS_IMX_SPI current ;
+    package -hardware CYGPKG_DEVS_MXC_I2C current ;
+    package -hardware CYGPKG_DEVS_IMX_IPU current ;
+    package -hardware CYGPKG_IMX_CMDS current ;
+    package -template CYGPKG_HAL current ;
+    package -template CYGPKG_INFRA current ;
+    package -template CYGPKG_REDBOOT current ;
+    package -template CYGPKG_ISOINFRA current ;
+    package -template CYGPKG_LIBC_STRING current ;
+    package -template CYGPKG_CRC current ;
+    package CYGPKG_MEMALLOC current ;
+};
+
+cdl_option CYGHWR_MX51_MDDR {
+    inferred_value 1
+};
+
+cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
+    inferred_value 0
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_IMX_SPI_NOR {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MMC {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
+    inferred_value 1
+};
+
+cdl_option CYGHWR_DEVS_IPU_3_EX {
+    inferred_value 1
+};
+
+cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
+    inferred_value 0
+};
+
+cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
+    user_value 4096
+};
+
+cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
+    user_value 0
+};
+
+cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
+    user_value 50
+};
+
+cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
+    inferred_value 0
+};
+
+cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
+    inferred_value 1
+};
+
+cdl_option CYGSEM_HAL_ROM_MONITOR {
+    inferred_value 1
+};
+
+cdl_component CYGBLD_BUILD_REDBOOT {
+    user_value 1
+};
+
+cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
+    inferred_value 0x00040000
+};
+
+cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
+    inferred_value 0x90008000
+};
+
+cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/bsdstring.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
+    inferred_value 1 <cyg/libc/string/string.h>
+};
+
+cdl_component CYG_HAL_STARTUP {
+    user_value ROMRAM
+};
+
+cdl_component CYGPKG_MEMORY_DIAGNOSIS {
+    user_value 1
+};
+
+cdl_option CYGSEM_RAM_PM_DIAGNOSIS {
+    user_value 0
+};
+
+#cdl_component CYGPKG_WDT_DIAGNOSIS {
+#    user_value 1
+#};
+
+cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
+    inferred_value 1
+};
+
+cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
+    inferred_value 4
+};
+
+cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
+    user_value 1 "FSL 200938"
+};
index 1388918..8304b66 100644 (file)
 #include <cyg/hal/hal_cache.h>
 #include <cyg/hal/hal_soc.h>         // Hardware definitions
 #include <cyg/hal/fsl_board.h>             // Platform specifics
+#include <cyg/hal/mx51_iomux.h>
 #include <cyg/io/mxc_i2c.h>
 #include <cyg/io/imx_nfc.h>
 #include <cyg/infra/diag.h>             // diag_printf
 
 // All the MM table layout is here:
 #include <cyg/hal/hal_mm.h>
+#include <cyg/io/imx_spi.h>
 
 externC void* memset(void *, int, size_t);
 extern nfc_iomuxsetup_func_t *nfc_iomux_setup;
 
 unsigned int cpld_base_addr;
 
+struct spi_v2_3_reg spi_nor_reg;
+struct imx_spi_dev imx_spi_nor = {
+    base : CSPI2_BASE_ADDR,
+    freq : 25000000,
+    ss_pol : IMX_SPI_ACTIVE_LOW,
+    ss : 1,
+    fifo_sz : 32,
+    us_delay: 0,
+    reg : &spi_nor_reg,
+};
+
+imx_spi_init_func_t *spi_nor_init;
+imx_spi_xfer_func_t *spi_nor_xfer;
+
 void hal_mmu_init(void)
 {
     unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
@@ -99,6 +115,7 @@ void hal_mmu_init(void)
     X_ARM_MMU_SECTION(0x900, 0x000,   0x080, ARM_CACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
     X_ARM_MMU_SECTION(0x900, 0x900,   0x080, ARM_CACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
     X_ARM_MMU_SECTION(0x900, 0x980,   0x080, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM 0:128M*/
+    X_ARM_MMU_SECTION(0xA00, 0xA00,   0x100, ARM_CACHEABLE, ARM_BUFFERABLE,   ARM_ACCESS_PERM_RW_RW); /* SDRAM */
     X_ARM_MMU_SECTION(0xB80, 0xB80,   0x10,  ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS1 EIM control*/
     X_ARM_MMU_SECTION(0xCC0, 0xCC0,   0x040, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* CS4/5/NAND Flash buffer */
 }
@@ -109,94 +126,47 @@ void mxc_i2c_init(unsigned int module_base)
 
     switch (module_base) {
     case I2C_BASE_ADDR:
-        if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
-            reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA
-            writel(0x11, reg);
-            reg = IOMUXC_BASE_ADDR + 0x600;
-            writel(0x1ad, reg);
-            reg = IOMUXC_BASE_ADDR + 0x9B4;
-            writel(0x1, reg);
-
-            reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL
-            writel(0x11, reg);
-            reg = IOMUXC_BASE_ADDR + 0x614;
-            writel(0x1ad, reg);
-            reg = IOMUXC_BASE_ADDR + 0x9B0;
-            writel(0x1, reg);
-        } else {
-            reg = IOMUXC_BASE_ADDR + 0x230; // i2c SCL
-            writel(0x11, reg);
-            reg = IOMUXC_BASE_ADDR + 0x6e0;
-            writel(0x1ad, reg);
-            reg = IOMUXC_BASE_ADDR + 0xA00;
-            writel(0x1, reg);
-
-            reg = IOMUXC_BASE_ADDR + 0x21C; // i2c SDA
-            writel(0x11, reg);
-            reg = IOMUXC_BASE_ADDR + 0x6cc;
-            writel(0x1ad, reg);
-            reg = IOMUXC_BASE_ADDR + 0xA04;
-            writel(0x1, reg);
-        }
+        reg = IOMUXC_BASE_ADDR + 0x210; // i2c SDA
+        writel(0x11, reg);
+        reg = IOMUXC_BASE_ADDR + 0x600;
+        writel(0x1ad, reg);
+        reg = IOMUXC_BASE_ADDR + 0x9B4;
+        writel(0x1, reg);
+
+        reg = IOMUXC_BASE_ADDR + 0x224; // i2c SCL
+        writel(0x11, reg);
+        reg = IOMUXC_BASE_ADDR + 0x614;
+        writel(0x1ad, reg);
+        reg = IOMUXC_BASE_ADDR + 0x9B0;
+        writel(0x1, reg);
         break;
     case I2C2_BASE_ADDR:
-        if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
-            /* Workaround for Atlas Lite */
-            writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
-            writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
-            reg = readl(GPIO1_BASE_ADDR + 0x0);
-            reg |= 0xC;  // write a 1 on the SCL and SDA lines
-            writel(reg, GPIO1_BASE_ADDR + 0x0);
-            reg = readl(GPIO1_BASE_ADDR + 0x4);
-            reg |= 0xC;  // configure GPIO lines as output
-            writel(reg, GPIO1_BASE_ADDR + 0x4);
-            reg = readl(GPIO1_BASE_ADDR + 0x0);
-            reg &= ~0x4 ; // set SCL low for a few milliseconds
-            writel(reg, GPIO1_BASE_ADDR + 0x0);
-            hal_delay_us(20000);
-            reg |= 0x4;
-            writel(reg, GPIO1_BASE_ADDR + 0x0);
-            hal_delay_us(10);
-            reg = readl(GPIO1_BASE_ADDR + 0x4);
-            reg &= ~0xC;  // configure GPIO lines back as input
-            writel(reg, GPIO1_BASE_ADDR + 0x4);
-
-            writel(0x12, IOMUXC_BASE_ADDR + 0x3CC);  // i2c SCL
-            writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
-            writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
-
-            writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
-            writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
-            writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
-        } else {
-            /* Workaround for Atlas Lite */
-            writel(0x0, IOMUXC_BASE_ADDR + 0x3D4); // i2c SCL
-            writel(0x0, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
-            reg = readl(GPIO1_BASE_ADDR + 0x0);
-            reg |= 0xC;  // write a 1 on the SCL and SDA lines
-            writel(reg, GPIO1_BASE_ADDR + 0x0);
-            reg = readl(GPIO1_BASE_ADDR + 0x4);
-            reg |= 0xC;  // configure GPIO lines as output
-            writel(reg, GPIO1_BASE_ADDR + 0x4);
-            reg = readl(GPIO1_BASE_ADDR + 0x0);
-            reg &= ~0x4 ; // set SCL low for a few milliseconds
-            writel(reg, GPIO1_BASE_ADDR + 0x0);
-            hal_delay_us(20000);
-            reg |= 0x4;
-            writel(reg, GPIO1_BASE_ADDR + 0x0);
-            hal_delay_us(10);
-            reg = readl(GPIO1_BASE_ADDR + 0x4);
-            reg &= ~0xC;  // configure GPIO lines back as input
-            writel(reg, GPIO1_BASE_ADDR + 0x4);
-
-            writel(0x12, IOMUXC_BASE_ADDR + 0x3D4);  // i2c SCL
-            writel(0x3, IOMUXC_BASE_ADDR + 0xA08);
-            writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A0);
-
-            writel(0x12, IOMUXC_BASE_ADDR + 0x3D8); // i2c SDA
-            writel(0x3, IOMUXC_BASE_ADDR + 0xA0C);
-            writel(0x1ed, IOMUXC_BASE_ADDR + 0x8A4);
-        }
+        /* Workaround for Atlas Lite */
+        writel(0x0, IOMUXC_BASE_ADDR + 0x3CC); // i2c SCL
+        writel(0x0, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
+        reg = readl(GPIO1_BASE_ADDR + 0x0);
+        reg |= 0xC;  // write a 1 on the SCL and SDA lines
+        writel(reg, GPIO1_BASE_ADDR + 0x0);
+        reg = readl(GPIO1_BASE_ADDR + 0x4);
+        reg |= 0xC;  // configure GPIO lines as output
+        writel(reg, GPIO1_BASE_ADDR + 0x4);
+        reg = readl(GPIO1_BASE_ADDR + 0x0);
+        reg &= ~0x4 ; // set SCL low for a few milliseconds
+        writel(reg, GPIO1_BASE_ADDR + 0x0);
+        hal_delay_us(20000);
+        reg |= 0x4;
+        writel(reg, GPIO1_BASE_ADDR + 0x0);
+        hal_delay_us(10);
+        reg = readl(GPIO1_BASE_ADDR + 0x4);
+        reg &= ~0xC;  // configure GPIO lines back as input
+        writel(reg, GPIO1_BASE_ADDR + 0x4);
+        writel(0x12, IOMUXC_BASE_ADDR + 0x3CC);  // i2c SCL
+        writel(0x3, IOMUXC_BASE_ADDR + 0x9B8);
+        writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D4);
+
+        writel(0x12, IOMUXC_BASE_ADDR + 0x3D0); // i2c SDA
+        writel(0x3, IOMUXC_BASE_ADDR + 0x9BC);
+        writel(0x1ed, IOMUXC_BASE_ADDR + 0x7D8);
         break;
     default:
         diag_printf("Invalid I2C base: 0x%x\n", module_base);
@@ -209,41 +179,11 @@ void mxc_ata_iomux_setup(void)
     // config NANDF_WE_B pad for pata instance DIOW port
     // config_pad_mode(NANDF_WE_B, ALT1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WE_B);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to Pull (Different from Module Level value: NA)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_WE_B, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WE_B);
 
     // config NANDF_RE_B pad for pata instance DIOR port
     // config_pad_mode(NANDF_RE_B, ALT1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RE_B);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to Pull (Different from Module Level value: NA)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_RE_B, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RE_B);
 
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_ALE);
@@ -252,521 +192,131 @@ void mxc_ata_iomux_setup(void)
     // config NANDF_CLE pad for pata instance PATA_RESET_B port
     // config_pad_mode(NANDF_CLE, ALT1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CLE);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Hyst. Enable to Disabled
-    // Pull / Keep Select to Keep (Different from Module Level value: NA)
-    // Pull Up / Down Config. to 100Kohm PU (Different from Module Level value: NA)
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Pull / Keep Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_CLE, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CLE);
 
     // config NANDF_WP_B pad for pata instance DMACK port
     // config_pad_mode(NANDF_WP_B, ALT1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_WP_B);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to Pull (Different from Module Level value: NA)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_WP_B, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_WP_B);
 
     // config NANDF_RB0 pad for pata instance DMARQ port
     // config_pad_mode(NANDF_RB0, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB0);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled (Different from Module Level value: NA)
-    // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to CFG(360Kohm PD)
-    // config_pad_settings(NANDF_RB0, 0x20c0);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB0);
 
     // config NANDF_RB1 pad for pata instance IORDY port
     // config_pad_mode(NANDF_RB1, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB1);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to NA (CFG in SoC Level however NA in Module Level)
-    // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // config_pad_settings(NANDF_RB1, 0x20e0);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB1);
 
     // config NANDF_RB5 pad for pata instance INTRQ port
     // config_pad_mode(NANDF_RB5, 0x1);
-    writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_RB5);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull Up / Down Config. to 100Kohm PU
-    // Open Drain Enable to Disabled (Different from Module Level value: NA)
-    // Drive Strength to NA (CFG in SoC Level however NA in Module Level)
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // config_pad_settings(NANDF_RB5, 0x20c0);
-    writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_RB5);
+    writel(0x1, IOMUXC_SW_MUX_CTL_PAD_GPIO_NAND);
+    writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_GPIO_NAND);
 
     // config NANDF_CS2 pad for pata instance CS_0 port
     // config_pad_mode(NANDF_CS2, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS2);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Open Drain Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_CS2, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS2);
 
     // config NANDF_CS3 pad for pata instance CS_1 port
     // config_pad_mode(NANDF_CS3, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS3);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Open Drain Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_CS3, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS3);
 
     // config NANDF_CS4 pad for pata instance DA_0 port
     // config_pad_mode(NANDF_CS4, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS4);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_CS4, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS4);
 
     // config NANDF_CS5 pad for pata instance DA_1 port
     // config_pad_mode(NANDF_CS5, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS5);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to NA (CFG in SoC Level however NA in Module Level)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_CS5, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS5);
 
     // config NANDF_CS6 pad for pata instance DA_2 port
     // config_pad_mode(NANDF_CS6, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_CS6);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull / Keep Select to Pull (Different from Module Level value: NA)
-    // Pull Up / Down Config. to NA (CFG in SoC Level however NA in Module Level)
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_CS6, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_CS6);
 
     // config NANDF_D15 pad for pata instance PATA_DATA[15] port
     // config_pad_mode(NANDF_D15, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D15);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D15, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D15);
 
     // config NANDF_D14 pad for pata instance PATA_DATA[14] port
     // config_pad_mode(NANDF_D14, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D14);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D14, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D14);
 
     // config NANDF_D13 pad for pata instance PATA_DATA[13] port
     // config_pad_mode(NANDF_D13, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D13);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D13, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D13);
 
     // config NANDF_D12 pad for pata instance PATA_DATA[12] port
     // config_pad_mode(NANDF_D12, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D12);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D12, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D12);
 
     // config NANDF_D11 pad for pata instance PATA_DATA[11] port
     // config_pad_mode(NANDF_D11, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D11);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D11, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D11);
 
     // config NANDF_D10 pad for pata instance PATA_DATA[10] port
     // config_pad_mode(NANDF_D10, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D10);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D10, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D10);
 
     // config NANDF_D9 pad for pata instance PATA_DATA[9] port
     // config_pad_mode(NANDF_D9, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D9);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D9, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D9);
 
     // config NANDF_D8 pad for pata instance PATA_DATA[8] port
     // config_pad_mode(NANDF_D8, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D8);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D8, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D8);
 
     // config NANDF_D7 pad for pata instance PATA_DATA[7] port
     // config_pad_mode(NANDF_D7, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D7);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull Up / Down Config. to 100Kohm PU
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D7, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D7);
 
     // config NANDF_D6 pad for pata instance PATA_DATA[6] port
     // config_pad_mode(NANDF_D6, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D6);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull Up / Down Config. to 100Kohm PU
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Open Drain Enable to Disabled
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D6, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D6);
 
     // config NANDF_D5 pad for pata instance PATA_DATA[5] port
     // config_pad_mode(NANDF_D5, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D5);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull Up / Down Config. to 100Kohm PU
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D5, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D5);
 
     // config NANDF_D4 pad for pata instance PATA_DATA[4] port
     // config_pad_mode(NANDF_D4, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D4);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Pull Up / Down Config. to 100Kohm PU
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D4, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D4);
 
     // config NANDF_D3 pad for pata instance PATA_DATA[3] port
     // config_pad_mode(NANDF_D3, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D3);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D3, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D3);
 
     // config NANDF_D2 pad for pata instance PATA_DATA[2] port
     // config_pad_mode(NANDF_D2, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D2);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D2, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D2);
 
     // config NANDF_D1 pad for pata instance PATA_DATA[1] port
     // config_pad_mode(NANDF_D1, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D1);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D1, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D1);
 
     // config NANDF_D0 pad for pata instance PATA_DATA[0] port
     // config_pad_mode(NANDF_D0, 0x1);
     writel(0x1, IOMUXC_SW_MUX_CTL_PAD_NANDF_D0);
-    // CONSTANT SETTINGS:
-    // test_ts to Disabled
-    // dse test to regular
-    // strength mode to NA (Different from Module Level value: 4_level)
-    // DDR / CMOS Input Mode to NA
-    // Open Drain Enable to Disabled
-    // Slew Rate to NA
-    // CONFIGURED SETTINGS:
-    // low/high output voltage to CFG(High)
-    // Hyst. Enable to Disabled
-    // Pull / Keep Enable to CFG(Enabled)
-    // Pull / Keep Select to Pull
-    // Pull Up / Down Config. to 100Kohm PU
-    // Drive Strength to CFG(High)
-    // config_pad_settings(NANDF_D0, 0x2004);
     writel(0x2004, IOMUXC_SW_PAD_CTL_PAD_NANDF_D0);
 }
 
@@ -774,8 +324,8 @@ static void mxc_fec_setup(void)
 {
     volatile unsigned int reg;
 
-    /* No FEC support for TO 2.0 yet */
-    if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2)
+    /* No FEC support for TO 2.0 and higher yet */
+    if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) >= 0x2)
         return;
     /*FEC_TX_CLK*/
     writel(0x2, IOMUXC_BASE_ADDR + 0x0390);
@@ -881,230 +431,292 @@ static void mxc_fec_setup(void)
 
 static void mxc_nfc_iomux_setup(void)
 {
-    if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
-        writel(0x0, IOMUXC_BASE_ADDR + 0x108);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x110);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x114);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x118);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x120);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x124);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x128);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x130);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x134);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x138);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x140);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x144);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x148);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x150);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x154);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x158);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x160);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x164);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x168);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x170);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x174);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x178);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x180);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x184);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x188);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x190);
-    } else {
-        writel(0x0, IOMUXC_BASE_ADDR + 0x108);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x110);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x114);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x118);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x120);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x124);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x128);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x130);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x134);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x138);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x140);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x144);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x148);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x150);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x154);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x158);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x160);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x164);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x168);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x170);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x174);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x178);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x180);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x184);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x188);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x190);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x194);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x198);
-        writel(0x0, IOMUXC_BASE_ADDR + 0x19C);
-    }
+    writel(0x0, IOMUXC_BASE_ADDR + 0x108);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x10C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x110);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x114);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x118);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x11C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x120);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x124);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x128);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x12C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x130);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x134);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x138);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x13C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x140);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x144);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x148);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x14C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x150);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x154);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x158);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x15C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x160);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x164);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x168);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x16C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x170);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x174);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x178);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x17C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x180);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x184);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x188);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x18C);
+    writel(0x0, IOMUXC_BASE_ADDR + 0x190);
 }
 
-//
-// Platform specific initialization
-//
+#define REV_ATLAS_LITE_2_0 0x20
 
-void plf_hardware_init(void)
+void setup_core_voltages(void)
 {
-    unsigned long sw_rest_reg, weim_base;
-    unsigned int reg;
-    unsigned char buf[4];
     struct mxc_i2c_request rq;
+    unsigned char buf[4];
+
+    if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+        rq.dev_addr = 0x8;
+        rq.reg_addr_sz = 1;
+        rq.buffer_sz = 3;
+        rq.buffer = buf;
 
-    /* Atlas Workaround needed only for TO 1.0 and 1.1 boards */
-    if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) != 0x2) {
-        if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
-            rq.dev_addr = 0x8;
-            rq.reg_addr = 0x7;
-            rq.reg_addr_sz = 1;
-            rq.buffer_sz = 3;
-            rq.buffer = buf;
+        if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) <= 0x2) {
+            /* Set core voltage to 1.1V */
+            rq.reg_addr = 24;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0x1F)) | 0x14;
+            i2c_xfer(1, &rq, 0);
+
+            /* Setup VCC (SW2) to 1.25 */
+            rq.reg_addr = 25;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+            i2c_xfer(1, &rq, 0);
+
+            /* Setup 1V2_DIG1 (SW3) to 1.25 */
+            rq.reg_addr = 26;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0x1F)) | 0x1A;
+            i2c_xfer(1, &rq, 0);
+            hal_delay_us(50);
+            /* Raise the core frequency to 800MHz */
+            writel(0x0, CCM_BASE_ADDR + CLKCTL_CACRR);
+        } else {
+            /* TO 3.0 */
+            /* Setup VCC (SW2) to 1.225 */
+            rq.reg_addr = 25;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0x1F)) | 0x19;
+            i2c_xfer(1, &rq, 0);
 
+            /* Setup 1V2_DIG1 (SW3) to 1.2 */
+            rq.reg_addr = 26;
             i2c_xfer(1, &rq, 1);
-            /* Make sure we implement this workaround only for boards with Atlas-Lite to turn off the charger */
-            if ((buf[1] == 0x41) && (buf[2] == 0xc8 || buf[2] == 0xc9)) {
-                buf[0] = 0xb4;
-                buf[1] = 0x0;
-                buf[2] = 0x3;
-                rq.dev_addr = 0x8;
-                rq.reg_addr = 0x30;
-                rq.reg_addr_sz = 1;
-                rq.buffer_sz = 3;
-                rq.buffer = buf;
-
-                i2c_xfer(1, &rq, 0);
-            }
+            buf[2] = (buf[2] & (~0x1F)) | 0x18;
+            i2c_xfer(1, &rq, 0);
+        }
+
+        rq.reg_addr = 7;
+        i2c_xfer(1, &rq, 1);
+
+        if (((buf[2] & 0x1F) < REV_ATLAS_LITE_2_0) || (((buf[1] >> 1) & 0x3) == 0)) {
+            /* Set switchers in PWM mode for Atlas 2.0 and lower */
+            /* Setup the switcher mode for SW1 & SW2*/
+            rq.reg_addr = 28;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0xF)) | 0x5;
+            buf[1] = (buf[1] & (~0x3C)) | 0x14;
+            i2c_xfer(1, &rq, 0);
+
+            /* Setup the switcher mode for SW3 & SW4*/
+            rq.reg_addr = 29;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0xF)) | 0x5;
+            buf[1] = (buf[1] & (~0xF)) | 0x5;
+            i2c_xfer(1, &rq, 0);
+        } else {
+            /* Set switchers in Auto in NORMAL mode & STANDBY mode for Atlas 2.0a */
+            /* Setup the switcher mode for SW1 & SW2*/
+            rq.reg_addr = 28;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0xF)) | 0x8;
+            buf[1] = (buf[1] & (~0x3C)) | 0x20;
+            i2c_xfer(1, &rq, 0);
+
+            /* Setup the switcher mode for SW3 & SW4*/
+            rq.reg_addr = 29;
+            i2c_xfer(1, &rq, 1);
+            buf[2] = (buf[2] & (~0xF)) | 0x8;
+            buf[1] = (buf[1] & (~0xF)) | 0x8;
+            i2c_xfer(1, &rq, 0);
         }
     }
-    // CS5 setup
-    writel(0, IOMUXC_BASE_ADDR + 0xF4);
-    weim_base = WEIM_BASE_ADDR + 0x78;
-    writel(0x00410089, weim_base + CSGCR1);
-    writel(0x00000002, weim_base + CSGCR2);
-    // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
-    writel(0x32260000, weim_base + CSRCR1);
-    // APR=0
-    writel(0x00000000, weim_base + CSRCR2);
-    // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
-    writel(0x72080F00, weim_base + CSWCR1);
-    cpld_base_addr = CS5_BASE_ADDR;
-
-    /* Reset interrupt status reg */
-    writew(0x1F, cpld_base_addr + PBC_INT_REST);
-    writew(0x00, cpld_base_addr + PBC_INT_REST);
-    writew(0xFFFF, cpld_base_addr + PBC_INT_MASK);
-
-    /* Reset the XUART and Ethernet controllers */
-    sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET);
-    sw_rest_reg |= 0x9;
-    writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
-    sw_rest_reg &= ~0x9;
-    writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
-
-    if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
-        // UART1
-        //RXD
-        writel(0x0, IOMUXC_BASE_ADDR + 0x228);
-        writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
-        //TXD
-        writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
-        writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
-        //RTS
-        writel(0x0, IOMUXC_BASE_ADDR + 0x230);
-        writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
-        //CTS
-        writel(0x0, IOMUXC_BASE_ADDR + 0x234);
-        writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
-        // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
-        writel(0x00000004, 0x73fa83E8);
-        writel(0x00000004, 0x73fa83Ec);
-    } else {
-        // UART1
-        //RXD
-        writel(0x0, IOMUXC_BASE_ADDR + 0x234);
-        writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E4);
-        //TXD
-        writel(0x0, IOMUXC_BASE_ADDR + 0x238);
-        writel(0x1C5, IOMUXC_BASE_ADDR + 0x6E8);
-        //RTS
-        writel(0x0, IOMUXC_BASE_ADDR + 0x23C);
-        writel(0x1C4, IOMUXC_BASE_ADDR + 0x6EC);
-        //CTS
-        writel(0x0, IOMUXC_BASE_ADDR + 0x240);
-        writel(0x1C4, IOMUXC_BASE_ADDR + 0x6F0);
-        // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
-        writel(0x00000004, 0x73fa83F4);
-        writel(0x00000004, 0x73fa83F0);
-    }
+}
+
+//
+// Platform specific initialization
+//
 
-    // enable ARM clock div by 8
-    writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
+void plf_hardware_init(void)
+{
+       unsigned long sw_rest_reg, weim_base;
+
+       setup_core_voltages();
+       // CS5 setup
+       writel(0, IOMUXC_BASE_ADDR + 0xF4);
+       weim_base = WEIM_BASE_ADDR + 0x78;
+       writel(0x00410089, weim_base + CSGCR1);
+       writel(0x00000002, weim_base + CSGCR2);
+       // RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0
+       writel(0x32260000, weim_base + CSRCR1);
+       // APR=0
+       writel(0x00000000, weim_base + CSRCR2);
+       // WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0, WCSN=0
+       writel(0x72080F00, weim_base + CSWCR1);
+       cpld_base_addr = CS5_BASE_ADDR;
+
+       /* Reset interrupt status reg */
+       writew(0x1F, cpld_base_addr + PBC_INT_REST);
+       writew(0x00, cpld_base_addr + PBC_INT_REST);
+       writew(0xFFFF, cpld_base_addr + PBC_INT_MASK);
+
+       /* Reset the XUART and Ethernet controllers */
+       sw_rest_reg = readw(cpld_base_addr + PBC_SW_RESET);
+       sw_rest_reg |= 0x9;
+       writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
+       sw_rest_reg &= ~0x9;
+       writew(sw_rest_reg, cpld_base_addr + PBC_SW_RESET);
+
+       // UART1
+       //RXD
+       writel(0x0, IOMUXC_BASE_ADDR + 0x228);
+       writel(0x1C5, IOMUXC_BASE_ADDR + 0x618);
+       //TXD
+       writel(0x0, IOMUXC_BASE_ADDR + 0x22c);
+       writel(0x1C5, IOMUXC_BASE_ADDR + 0x61c);
+       //RTS
+       writel(0x0, IOMUXC_BASE_ADDR + 0x230);
+       writel(0x1C4, IOMUXC_BASE_ADDR + 0x620);
+       //CTS
+       writel(0x0, IOMUXC_BASE_ADDR + 0x234);
+       writel(0x1C4, IOMUXC_BASE_ADDR + 0x624);
+       // enable GPIO1_9 for CLKO and GPIO1_8 for CLKO2
+       writel(0x00000004, 0x73fa83E8);
+       writel(0x00000004, 0x73fa83Ec);
+
+       // enable ARM clock div by 8
+       writel(0x010900F0, CCM_BASE_ADDR + CLKCTL_CCOSR);
 #ifdef MXCFLASH_SELECT_NAND
-    nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup;
+       nfc_iomux_setup = (nfc_iomuxsetup_func_t*)mxc_nfc_iomux_setup;
 #endif
-    mxc_fec_setup();
+       mxc_fec_setup();
+
+       spi_nor_init = (imx_spi_init_func_t *)imx_spi_init_v2_3;
+       spi_nor_xfer = (imx_spi_xfer_func_t *)imx_spi_xfer_v2_3;
+}
+
+
+void mxc_ipu_iomux_config(void)
+{
+       // configure display data0~17 for Epson panel
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT0, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT0, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT1, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT2,0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT3, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT4, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT5, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT5, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT6, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT6, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT7, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT7, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT8, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT8, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT9, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT9, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT10, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT10, 0x5);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT11, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT12, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT13, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT14, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT14, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT15, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT15, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT16, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT16, 0x5);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DISP1_DAT17, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DISP1_DAT17, 0x5);
+
+       // DI1_PIN2 and DI1_PIN3, configured to be HSYNC and VSYNC of Epson LCD
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+
+       // PCLK - DISP_CLK
+       // No IOMUX configuration required, as there is no IOMUXing for this pin
+
+       // DRDY - PIN15
+       // No IOMUX configuration required, as there is no IOMUXing for this pin
+
+       // configure this pin to be the SER_DISP_CS
+
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D1_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT4);
+       CONFIG_PIN(IOMUXC_SW_PAD_CTL_PAD_DI1_D1_CS,0x85);
+
+       // configure to be DISPB1_SER_RS
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP1, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP1, 0x85);
+       // configure to be SER_DISP1_CLK
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP2, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP2, 0x85);
+       // configure to be DISPB1_SER_DIO
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP3, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP3, 0xC5);
+       // configure to be DISPB1_SER_DIN
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI_GP4, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT0);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI_GP4, 0xC4);
+       //CS0
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_D0_CS, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_D0_CS, 0x85);
+       // WR
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN11, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11, 0x85);
+       // RD
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN12, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN12, 0x85);
+       // RS
+       CONFIG_PIN(IOMUXC_SW_MUX_CTL_PAD_DI1_PIN13, IOMUX_PIN_SION_REGULAR|IOMUX_SW_MUX_CTL_ALT1);
+       CONFIG_PAD(IOMUXC_SW_PAD_CTL_PAD_DI1_PIN13, 0x85);
+
 }
 
 void mxc_mmc_init(unsigned int base_address)
 {
     switch(base_address) {
     case MMC_SDHC1_BASE_ADDR:
-        if (((system_rev >> MAJOR_NUMBER_OFFSET) & 0xf) == 0x2) {
-            /* SD1 CMD, SION bit */
-            writel(0x10, IOMUXC_BASE_ADDR + 0x394);
-           /* Configure SW PAD */
-            /* SD1 CMD */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x79C);
-            /* SD1 CLK */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A0);
-            /* SD1 DAT0 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A4);
-            /* SD1 DAT1 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x7A8);
-            /* SD1 DAT2 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x7AC);
-            /* SD1 DAT3 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x7B0);
-        } else {
-            /* SD1 CMD, SION bit */
-            writel(0x10, IOMUXC_BASE_ADDR + 0x39c);
-            /* SD1 CD, as gpio1_0 */
-            writel(0x01, IOMUXC_BASE_ADDR + 0x3b4);
-            /* Configure SW PAD */
-            /* SD1 CMD */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x868);
-            /* SD1 CLK */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x86c);
-            /* SD1 DAT0 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x870);
-            /* SD1 DAT1 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x874);
-            /* SD1 DAT2 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x878);
-            /* SD1 DAT3 */
-            writel(0x20d4, IOMUXC_BASE_ADDR + 0x87c);
-            /* SD1 CD as gpio1_0 */
-            writel(0x1e2, IOMUXC_BASE_ADDR + 0x880);
-        }
+        /* SD1 CMD, SION bit */
+        writel(0x10, IOMUXC_BASE_ADDR + 0x394);
+       /* Configure SW PAD */
+        /* SD1 CMD */
+        writel(0xd5, IOMUXC_BASE_ADDR + 0x79C);
+        /* SD1 CLK */
+        writel(0xd5, IOMUXC_BASE_ADDR + 0x7A0);
+        /* SD1 DAT0 */
+        writel(0xd5, IOMUXC_BASE_ADDR + 0x7A4);
+        /* SD1 DAT1 */
+        writel(0xd5, IOMUXC_BASE_ADDR + 0x7A8);
+        /* SD1 DAT2 */
+        writel(0xd5, IOMUXC_BASE_ADDR + 0x7AC);
+        /* SD1 DAT3 */
+        writel(0xd5, IOMUXC_BASE_ADDR + 0x7B0);
         break;
     default:
         break;
@@ -1116,23 +728,70 @@ void increase_core_voltage(bool i)
     unsigned char buf[4];
     struct mxc_i2c_request rq;
 
+    if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+        rq.dev_addr = 0x8;
+        rq.reg_addr = 24;
+        rq.reg_addr_sz = 1;
+        rq.buffer_sz = 3;
+        rq.buffer = buf;
 
-    rq.dev_addr = 0x8;
-    rq.reg_addr = 24;
-    rq.reg_addr_sz = 1;
-    rq.buffer_sz = 3;
-    rq.buffer = buf;
+        i2c_xfer(1, &rq, 1);
 
-    i2c_xfer(1, &rq, 1);
-
-    if (i) {
-        buf[2] = buf[2] & (~0x1F) | 0x17;
+        if (i) {
+            buf[2] = (buf[2] & (~0x1F)) | 0x17; //1.175
+            //buf[2] = (buf[2] & (~0x1F)) | 0x18; //1.2
+        } else {
+            buf[2] = (buf[2] & (~0x1F)) | 0x12;
+        }
+        i2c_xfer(1, &rq, 0);
     } else {
-        buf[2] = buf[2] & (~0x1F) | 0x12;
+        diag_printf("Cannot increase core voltage, failed to initialize I2C2\n");
+    }
+}
+
+void io_cfg_spi(struct imx_spi_dev *dev)
+{
+    unsigned int reg;
+
+    switch (dev->base) {
+    case CSPI1_BASE_ADDR:
+        break;
+    case CSPI2_BASE_ADDR:
+        // Select mux mode: ALT2 mux port: MOSI of instance: ecspi2
+        writel(0x2, IOMUXC_BASE_ADDR + 0x154);
+        writel(0x105, IOMUXC_BASE_ADDR + 0x53C);
+
+        // Select mux mode: ALT2 mux port: MISO of instance: ecspi2.
+        writel(0x2, IOMUXC_BASE_ADDR + 0x128);
+        writel(0x105, IOMUXC_BASE_ADDR + 0x504);
+
+       // de-select SS0 of instance: ecspi1.
+       writel(0x2, IOMUXC_BASE_ADDR + 0x298);
+       writel(0x85, IOMUXC_BASE_ADDR + 0x698);
+       // Select mux mode: ALT2 mux port: SS1 of instance: ecspi2.
+       writel(0x2, IOMUXC_BASE_ADDR + 0x160);
+       writel(0x105, IOMUXC_BASE_ADDR + 0x548);
+
+        // Select mux mode: ALT3 mux port: GPIO mode
+        writel(0x3, IOMUXC_BASE_ADDR + 0x150);
+        writel(0xE0, IOMUXC_BASE_ADDR + 0x538);
+        reg = readl(GPIO3_BASE_ADDR + 0x0);
+        reg |= 0x1000000;  // write a 1
+        writel(reg, GPIO3_BASE_ADDR + 0x0);
+        reg = readl(GPIO3_BASE_ADDR + 0x4);
+        reg |= 0x1000000;  // configure GPIO lines as output
+        writel(reg, GPIO3_BASE_ADDR + 0x4);
+
+        // Select mux mode: ALT2 mux port: SCLK of instance: ecspi2.
+        writel(0x2, IOMUXC_BASE_ADDR + 0x124);
+        writel(0x105, IOMUXC_BASE_ADDR + 0x500);
+        break;
+    default:
+        break;
     }
-    i2c_xfer(1, &rq, 0);
 }
 
+
 #include CYGHWR_MEMORY_LAYOUT_H
 
 typedef void code_fun(void);
diff --git a/packages/hal/arm/mx51/3stack/v2_0/src/epson_lcd.c b/packages/hal/arm/mx51/3stack/v2_0/src/epson_lcd.c
new file mode 100644 (file)
index 0000000..19b8e65
--- /dev/null
@@ -0,0 +1,223 @@
+//==========================================================================
+//
+//      epson_lcd.c
+//
+//      LCD Display Implementation
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/io/ipu_common.h>
+#include <cyg/io/mxc_i2c.h>
+
+#define MX51_ATLAS_PMIC_ADDRESS 0x8
+
+static int pmic_read_reg(unsigned int reg_addr, unsigned char *data, unsigned int count)
+{
+    struct mxc_i2c_request rq;
+
+    rq.dev_addr = MX51_ATLAS_PMIC_ADDRESS;  // dev_addr of Atlas PMIC
+    rq.reg_addr = reg_addr;     // addr of LEC Control0 Reg
+    rq.reg_addr_sz = 1;
+    rq.buffer_sz = count;           // send 3 data in a series
+    rq.buffer = data;
+    i2c_xfer(1, &rq, 1);
+
+    return 1;
+}
+
+static int pmic_write_reg(unsigned int reg_addr, unsigned char *data, unsigned int count)
+{
+    struct mxc_i2c_request rq;
+
+    rq.dev_addr = MX51_ATLAS_PMIC_ADDRESS;  // dev_addr of Atlas PMIC
+    rq.reg_addr = reg_addr;     // addr of LEC Control0 Reg
+    rq.reg_addr_sz = 1;
+    rq.buffer_sz = count;           // send 3 data in a series
+    rq.buffer = data;
+    i2c_xfer(1, &rq, 0);
+
+    return 1;
+}
+
+/*this function use common pins of IPU to simulate a cspi interface*/
+static void epson_lcd_spi_simulate(void)
+{
+    dc_microcode_t microcode = { 0 };
+    microcode.addr = 0x24;
+    microcode.stop = 1;
+    microcode.opcode = "WROD";
+    microcode.lf = 0;
+    microcode.af = 0;
+    microcode.operand = 0;
+    microcode.mapping = 5;
+    microcode.waveform = 7;
+    microcode.gluelogic = 0;
+    microcode.sync = 0;
+    ipu_dc_microcode_config(microcode);
+
+    ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_1, 0x24);  //address of second region
+    ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_START_CHAN_W_8_0, 0x24);  //address of first region
+    ipu_write_field(IPU_DC_RL3_CH_8__COD_NEW_DATA_PRIORITY_CHAN_8, 1);  //MEDIUM PRIORITY FOR DATA
+
+    /*  Data Mapping of 24-bit new data
+       |23..16|15..8|7..0| ==>> bit[15..0]&(0x1FF), just keep the last 17bit for LCD configuration */
+    ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE2_4, 3);
+    ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE1_4, 4);
+    ipu_write_field(IPU_DC_MAP_CONF_2__MAPPING_PNTR_BYTE0_4, 5);
+    ipu_write_field(IPU_DC_MAP_CONF_16__MD_OFFSET_3, 0);
+    ipu_write_field(IPU_DC_MAP_CONF_16__MD_MASK_3, 0x00);
+    ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_4, 15);
+    ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_4, 0x01);
+    ipu_write_field(IPU_DC_MAP_CONF_17__MD_OFFSET_5, 7);
+    ipu_write_field(IPU_DC_MAP_CONF_17__MD_MASK_5, 0xFF);
+
+    /*set clock and cs signal for command.
+       sclk should be more than 90ns interval, derived from base clock. */
+    ipu_di_waveform_config(0, 6, 0, 0, 11);
+    ipu_di_waveform_config(0, 6, 1, 1, 2);
+    ipu_di_waveform_config(0, 6, 2, 0, 0);
+    ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_PERIOD_6, 3);  //base clock, 133MHz/div
+    ipu_write_field(IPU_DI0_DW_GEN_6__DI0_START_PERIOD_6, 0);   //start immediatly
+    ipu_write_field(IPU_DI0_DW_GEN_6__DI0_CST_6, 0);    //pointer for CS
+    ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_VALID_BITS_6, 8);  //8+1 bit, should be more than or equal with 9
+    ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_RS_6, 2);  //RS=0
+    ipu_write_field(IPU_DI0_DW_GEN_6__DI0_SERIAL_CLK_6, 1); //SCLK for command, should be less than 11MHz
+    ipu_write_field(IPU_DI0_SER_CONF__DI0_SER_CLK_POLARITY, 1);
+    ipu_write_field(IPU_IPU_DISP_GEN__MCU_DI_ID_8, 0);  //MCU accesses DC's channel #8 via DI0.
+
+    /* T VALUE, seperate into two parts */
+    ipu_write_field(IPU_IPU_DISP_GEN__MCU_T, T_VALUE);  //diffrenciate
+
+    ipu_write_field(IPU_DC_WR_CH_CONF1_8__MCU_DISP_ID_8, 1);    //display 1
+    ipu_write_field(IPU_DC_WR_CH_CONF1_8__W_SIZE_8, 3); //32 bits are used (RGB)
+
+    ipu_write_field(IPU_DC_DISP_CONF1_1__DISP_TYP_1, 0);    //serial display
+
+    ipu_write_field(IPU_IPU_CONF__DI0_EN, 1);
+    ipu_write_field(IPU_IPU_CONF__DP_EN, 0);
+    ipu_write_field(IPU_IPU_CONF__DC_EN, 1);
+    ipu_write_field(IPU_IPU_CONF__DMFC_EN, 1);
+}
+
+static void epson_lcd_rst(void)
+{
+    ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_4, 1);
+    hal_delay_us(1000);
+    ipu_write_field(IPU_DI1_GENERAL__DI1_POLARITY_4, 0);
+}
+
+void lcd_backlit_on(void)
+{
+    struct mxc_i2c_request rq;
+    unsigned char data[3];
+    unsigned char dataCheck[3];
+    int timeout = 0;
+    int ret = 0xFF;
+    /*duty cycle = (mainDispDutyCycle % 32) / 32; */
+    unsigned char mainDispDutyCycle = 0x20;
+    /*current = mainDispCurrentSet * 3 * 2^mainDispHiCurMode
+       current should be no more than 15 */
+    unsigned char mainDispCurrentSet = 3;
+    unsigned char mainDispHiCurMode = 0;
+
+#ifndef CYGPKG_REDBOOT
+    mxc_i2c2_clock_gate(1);
+#endif
+    if (i2c_init(I2C2_BASE_ADDR, 170000) == 0) {
+        while (timeout < 5) {
+            data[0] = 0x0;
+            data[1] = ((mainDispCurrentSet << 1) & 0xE) | ((mainDispDutyCycle >> 5) & 0x1);
+            data[2] = ((mainDispHiCurMode << 1) & 0x2) | ((mainDispDutyCycle << 3) & 0xF8);
+            pmic_write_reg(0x33, data, 3);
+            dataCheck[0] = 0x0;
+            dataCheck[1] = 0x0;
+            dataCheck[2] = 0x0;
+            pmic_read_reg(0x33, dataCheck, 3);
+
+            if ((dataCheck[0] == data[0]) && (dataCheck[1] == data[1]) && (dataCheck[2] == data[2])) {
+                break;
+            }
+            timeout++;
+            hal_delay_us(20);
+        }
+    } else {
+        diag_printf("ERROR:I2C initialization failed\n");
+    }
+#ifndef CYGPKG_REDBOOT
+    mxc_i2c2_clock_gate(0);
+#endif
+}
+
+void lcd_config(void)
+{
+    /* set these regs to conpensate color. */
+    writel((readl(MIPI_HSC_BASE_ADDR + 0x800) | (1<<16)), MIPI_HSC_BASE_ADDR + 0x800);
+    writel((readl(MIPI_HSC_BASE_ADDR + 0x0) | (1<<10)), MIPI_HSC_BASE_ADDR + 0x0);
+
+    /* simulate spi interface to access LCD regs */
+    epson_lcd_spi_simulate();
+    epson_lcd_rst();
+
+    /* enable chip select */
+    gpio_dir_config(GPIO_PORT3, 4, GPIO_GDIR_OUTPUT);
+    gpio_write_data(GPIO_PORT3, 4, 0);
+    hal_delay_us(300);
+
+    writel(MADCTL, IPU_CTRL_BASE_ADDR);
+    writel(0x0100, IPU_CTRL_BASE_ADDR);
+
+    writel(GAMSET, IPU_CTRL_BASE_ADDR);
+    writel(0x0101, IPU_CTRL_BASE_ADDR);
+
+    writel(COLMOD, IPU_CTRL_BASE_ADDR);
+    writel(0x0160, IPU_CTRL_BASE_ADDR);
+
+    writel(SLPOUT, IPU_CTRL_BASE_ADDR); // SLEEP OUT
+    hal_delay_us(300);
+
+    writel(DISON, IPU_CTRL_BASE_ADDR);  // Display ON
+    hal_delay_us(300);
+
+    /* disable chip select */
+    gpio_dir_config(GPIO_PORT3, 4, GPIO_GDIR_OUTPUT);
+    gpio_write_data(GPIO_PORT3, 4, 1);
+
+    ipu_write_field(IPU_IPU_CONF__DI0_EN, 0);
+    ipu_write_field(IPU_IPU_CONF__DP_EN, 0);
+    ipu_write_field(IPU_IPU_CONF__DC_EN, 0);
+    ipu_write_field(IPU_IPU_CONF__DMFC_EN, 0);
+    hal_delay_us(300);
+}
diff --git a/packages/hal/arm/mx51/3stack/v2_0/src/mx51_fastlogo.c b/packages/hal/arm/mx51/3stack/v2_0/src/mx51_fastlogo.c
new file mode 100644 (file)
index 0000000..2809dee
--- /dev/null
@@ -0,0 +1,295 @@
+//==========================================================================
+//
+//      mx51_fastlogo.c
+//
+//      MX51 Fast Logo Implementation
+//
+//==========================================================================
+//####ECOSGPLCOPYRIGHTBEGIN####
+// -------------------------------------------
+// This file is part of eCos, the Embedded Configurable Operating System.
+// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
+//
+// eCos is free software; you can redistribute it and/or modify it under
+// the terms of the GNU General Public License as published by the Free
+// Software Foundation; either version 2 or (at your option) any later version.
+//
+// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
+// WARRANTY; without even the implied warranty of MERCHANTABILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with eCos; if not, write to the Free Software Foundation, Inc.,
+// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+//
+// As a special exception, if other files instantiate templates or use macros
+// or inline functions from this file, or you compile this file and link it
+// with other works to produce a work based on this file, this file does not
+// by itself cause the resulting work to be covered by the GNU General Public
+// License. However the source code for this file must still be made available
+// in accordance with section (3) of the GNU General Public License.
+//
+// This exception does not invalidate any other reasons why a work based on
+// this file might be covered by the GNU General Public License.
+//
+// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
+// at http://sources.redhat.com/ecos/ecos-license/
+// -------------------------------------------
+//####ECOSGPLCOPYRIGHTEND####
+//==========================================================================
+
+#include <cyg/io/ipu_common.h>
+
+// DI counter definitions
+#define DI_COUNTER_BASECLK      0
+#define DI_COUNTER_IHSYNC        1
+#define DI_COUNTER_OHSYNC       2
+#define DI_COUNTER_OVSYNC       3
+#define DI_COUNTER_ALINE          4
+#define DI_COUNTER_ACLOCK       5
+
+extern display_buffer_info_t display_buffer;
+
+void fastlogo_dma(void)
+{
+    ipu_channel_parameter_t ipu_channel_params;
+    ipu_idmac_channel_enable(DISPLAY_CHANNEL, 0);
+
+    ipu_idmac_params_init(&ipu_channel_params);
+    ipu_channel_params.channel = DISPLAY_CHANNEL;
+    ipu_channel_params.eba0 = (unsigned int)(display_buffer.startAddr) / 8;
+    ipu_channel_params.fw = display_buffer.width - 1;   //frame width
+    ipu_channel_params.fh = display_buffer.height - 1;  //frame height
+    ipu_channel_params.sl = (display_buffer.width * display_buffer.bpp) / 8 - 1;
+    ipu_channel_params.npb = 31;    //16 pixels per burst
+    ipu_channel_params.pfs = 7; //1->4:2:2 non-interleaved, 7->rgb
+
+    switch(display_buffer.bpp) {
+    case 32:
+        ipu_channel_params.bpp = 0;
+        break;
+    case 24:
+        ipu_channel_params.bpp = 1;
+        break;
+    case 18:
+        ipu_channel_params.bpp = 2;
+        break;
+    case 16:
+        ipu_channel_params.bpp = 3;
+        break;
+    default:
+        diag_printf("data bpp format not supported!\n");
+    }
+
+    switch(display_buffer.dataFormat) {
+    case RGB565:
+        ipu_channel_params.wid0 = 5 - 1;    //bits
+        ipu_channel_params.wid1 = 6 - 1;    //bits;
+        ipu_channel_params.wid2 = 5 - 1;    //bits;
+        ipu_channel_params.wid3 = 0;    //bits;
+        ipu_channel_params.ofs0 = 0;
+        ipu_channel_params.ofs1 = 5;
+        ipu_channel_params.ofs2 = 11;
+        ipu_channel_params.ofs3 = 16;
+        break;
+
+    case RGB666:
+        ipu_channel_params.wid0 = 6 - 1;    //bits
+        ipu_channel_params.wid1 = 6 - 1;    //bits;
+        ipu_channel_params.wid2 = 6 - 1;    //bits;
+        ipu_channel_params.wid3 = 0;    //bits;
+        ipu_channel_params.ofs0 = 0;
+        ipu_channel_params.ofs1 = 6;
+        ipu_channel_params.ofs2 = 12;
+        ipu_channel_params.ofs3 = 18;
+        break;
+    case RGB888:
+        ipu_channel_params.wid0 = 8 - 1;    //bits
+        ipu_channel_params.wid1 = 8 - 1;    //bits;
+        ipu_channel_params.wid2 = 8 - 1;    //bits;
+        ipu_channel_params.wid3 = 0;    //bits;
+        ipu_channel_params.ofs0 = 0;
+        ipu_channel_params.ofs1 = 8;
+        ipu_channel_params.ofs2 = 16;
+        ipu_channel_params.ofs3 = 24;
+        break;
+    case RGBA8888:
+        ipu_channel_params.wid0 = 8 - 1;    //bits
+    &