#
cdl_option CYGHWR_HAL_ARM_DUMP_EXCEPTIONS {
# Flavor: bool
- user_value 1
- # value_source user
+ # No user value, uncomment the following line to provide one.
+ # user_value 0
+ # value_source default
# Default value: 0
# Requires: !CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
# CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS == 0
# user_value 0x08000000
# value_source default
# Default value: 0x08000000
- # Legal values: 0x08000000 0x04000000
+ # Legal values: 0x10000000 0x08000000 0x04000000
};
# Enable low level debugging with LED
FDO_FLASH_STATUS = 0x0020,
};
-#if 1
#define MAX_LOOPS 10000
#define wait_for_auto_prog_done() \
CYG_MACRO_START \
} \
nfc_reg_write(0, NFC_IPC_REG); \
CYG_MACRO_END
-#else
-#define wait_for_auto_prog_done() \
- CYG_MACRO_START \
- while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_AUTO_DONE) == 0) {
- }
- nfc_reg_write((nfc_reg_read(NFC_IPC_REG) & ~NFC_IPC_AUTO_DONE),
- NFC_IPC_REG);
- CYG_MACRO_END
-
-// Polls the NANDFC to wait for an operation to complete
-#define wait_op_done()
- CYG_MACRO_START
- while ((nfc_reg_read(NFC_IPC_REG) & NFC_IPC_INT) == 0) {
- }
- nfc_reg_write(0, NFC_IPC_REG);
- CYG_MACRO_END
-#endif
-#if 1
-#include <cyg/hal/plf_mmap.h>
-#define nfc_reg_write(v, r) __nfc_reg_write(v, (void *)(r), #r, __FUNCTION__)
-static inline void __nfc_reg_write(u32 val, void *addr,
- const char *reg, const char *fn)
-{
- unsigned long pa;
- HAL_VIRT_TO_PHYS_ADDRESS((unsigned long)addr, pa);
- diag_printf1("%s: Writing %08x to %s[%04lx]\n", fn, val, reg, pa);
- writel(val, addr);
-}
-
-#define nfc_reg_read(r) __nfc_reg_read((void *)(r), #r, __FUNCTION__)
-static inline u32 __nfc_reg_read(void *addr,
- const char *reg, const char *fn)
-{
- u32 val;
- unsigned long pa;
-
- HAL_VIRT_TO_PHYS_ADDRESS((unsigned long)addr, pa);
- val = readl(addr);
- diag_printf1("%s: Read %08x from %s[%04lx]\n", fn, val, reg, pa);
- return val;
-}
-#else
#define nfc_reg_read(r) readl(r)
#define nfc_reg_write(v, r) writel(v, r)
-#endif
static void write_nfc_ip_reg(u32 val, u32 reg)
{
#include <pkgconf/hal.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_cache.h>
+#include <cyg/hal/hal_misc.h>
#include <cyg/io/nand_bbt.h>
#include <redboot.h>
#include <stdlib.h>
#define _FLASH_PRIVATE_
#include <cyg/io/flash.h>
+#ifdef CYGHWR_FLASH_NAND_BBT_HEADER
#include CYGHWR_FLASH_NAND_BBT_HEADER
+#endif
#include <cyg/io/imx_nfc.h>
u32 id[2];
int i;
-#if 0
- return FLASH_ERR_DRV_WRONG_PART;
-#endif
nfc_printf(NFC_DEBUG_MAX, "%s()\n", __FUNCTION__);
if (nfc_iomux_setup)
nfc_printf(NFC_DEBUG_MIN, "%s: read flash id from chip %d @ %p\n",
__FUNCTION__, cs_line, ptr);
-#if 0
-#if 1
- {
- int i;
- const int nwords = 512 >> 2;
-
- for (i = 0; i < 8; i++) {
- int j;
-
- for (j = 0; j < nwords; j++) {
- ptr[i * nwords + j] = 0xdeadbeef;
- }
- }
- }
-#else
- {
- int i;
- const int nwords = 512 >> 2;
-
- for (i = 0; i < 8; i++) {
- int j;
- for (j = 0; j < nwords; j++) {
- id[i * nwords + j] = 0xdeadbeef;
- }
- }
- }
-#endif
-#endif
NFC_PRESET(MXC_UNLOCK_BLK_END);
NFC_SET_NFC_ACTIVE_CS(cs_line);
NFC_CMD_INPUT(FLASH_Read_ID);
return 0;
}
+static inline void mxc_nfc_buf_clear(unsigned long buf, u8 pattern, int size)
+{
+ int i;
+ u16 *p = (u16 *)buf;
+ u16 fill = pattern;
+
+ fill = (fill << 8) | pattern;
+ for (i = 0; i < size >> 1; i++) {
+ p[i] = fill;
+ }
+}
+
+#ifdef CYGHWR_FLASH_NAND_BBT_HEADER
/*
* check_short_pattern - [GENERIC] check if a pattern is in the buffer
* @buf: the buffer to search
return 0;
}
-static inline void mxc_nfc_buf_clear(unsigned long buf, u8 pattern, int size)
-{
- int i;
- u16 *p = (u16 *)buf;
- u16 fill = pattern;
-
- fill = (fill << 8) | pattern;
- for (i = 0; i < size >> 1; i++) {
- p[i] = fill;
- }
-}
-
static int mxc_nfc_write_bbt(struct nand_bbt_descr *td, struct nand_bbt_descr *md)
{
int ret = -1;
{
return mxc_nfc_update_bbt(g_mxc_nfc_bbt_main_descr, g_mxc_nfc_bbt_mirror_descr);
}
+#else
+static int program_bbt_to_flash(void)
+{
+ return 0;
+}
+#endif
/*!
* Unconditionally erase a block without checking the BI field.
static void do_nand_cmds(int argc, char *argv[])
{
struct cmd *cmd;
-#if 0
- unsigned long ctrl, l2, sid, cs;
- unsigned int d, i;
-
- HAL_FLASH_CACHES_OFF(d, i);
- diag_printf("DCACHE: %d ICACHE: %d\n", d, i);
- HAL_FLASH_CACHES_ON(d, i);
-
- asm volatile(
- "MRC p15, 0, %0, c1, c0, 0;"
- "MRC p15, 0, %1, c1, c0, 1;"
- "MRC p15, 1, %2, c0, c0, 7;"
- "MRC p15, 1, %3, c0, c0, 0;"
- : "=r"(ctrl), "=r"(l2), "=r"(sid), "=r"(cs)
- );
-
- diag_printf("ctrl: %08lx aux: %08lx sid: %08lx cs: %08lx\n", ctrl, l2, sid, cs);
-#endif
if (!mxcnfc_init_ok) {
flash_hwr_init();
#ifdef CYGOPT_REDBOOT_FIS
#include <fis.h>
#endif
+#include CYGBLD_HAL_PLATFORM_H
/*
* write bit fields of special IPU regs
if (!do_logo_load()) {
return;
}
- //mxc_ipu_iomux_config();
+ mxc_ipu_iomux_config();
//lcd_backlit_on();
//lcd_config();
fastlogo_init(&display_buffer);
(paddr) = _v_; \
CYG_MACRO_END
-/*
- * translate the virtual address of ram space to physical address
- * It is dependent on the implementation of hal_mmu_init
- */
-#if 1
/*
* translate the virtual address of ram space to physical address
* It is dependent on the implementation of hal_mmu_init
}
return phy;
}
-#else
-static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
-{
- if (virt < 0x08000000) {
- return virt|0x80000000;
- }
- if((virt & 0xF0000000) == 0x80000000) {
- return virt&(~0x08000000);
- }
- return virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
-{
- /* 0x88000000~0x87FFFFFF is uncacheable meory space which is mapped to SDRAM*/
- if ((phy & 0xF0000000) == 0x80000000) {
- phy |= 0x08000000;
- }
- return phy;
-}
-#endif
//---------------------------------------------------------------------------
#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H
/* xxx00000 */
X_ARM_MMU_SECTION(0x000, 0xF00, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Boot Rom */
X_ARM_MMU_SECTION(0x43f, 0x43f, 0x3c1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Registers */
- X_ARM_MMU_SECTION(0x800, 0x000, SD_SZ, ARM_UNCACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
- X_ARM_MMU_SECTION(0x800, 0x800, SD_SZ, ARM_UNCACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x800, 0x000, SD_SZ, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
+ X_ARM_MMU_SECTION(0x800, 0x800, SD_SZ, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
X_ARM_MMU_SECTION(0x800, 0x880, SD_SZ, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
#ifdef RAM_BANK1_SIZE
X_ARM_MMU_SECTION(0x900, SD_SZ, SD_SZ, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
static void sense_fuse(int bank, int row, int bit)
{
- int ret;
- int addr, addr_l, addr_h, reg_addr;
+ int ret;
+ int addr, addr_l, addr_h, reg_addr;
fuse_op_start();
/* Blow fuses based on the bank, row and bit positions (all 0-based)
*/
-int fuse_blow(int bank,int row,int bit)
+int fuse_blow(int bank, int row, int bit)
{
int addr, addr_l, addr_h, ret = -1;
addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
+ diag_printf("blowing fuse %d %d bit %d addr_h=0x%02x, addr_l=0x%02x\n",
+ bank, row, bit, addr_h, addr_l);
#endif
writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
"read some fuses",
"<bank> <row>",
do_fuse_read
- );
+ );
RedBoot_cmd("fuse_blow",
"blow some fuses",
"<bank> <row> <value>",
do_fuse_blow
- );
+ );
#define INIT_STRING "12345678"
static char ready_to_blow[] = INIT_STRING;
void do_fuse_blow(int argc, char *argv[])
{
unsigned long bank, row, value;
- int i;
+ int i;
if (argc == 1) {
diag_printf("It is too dangeous for you to use this command.\n");
} else if (argc == 3) {
if (strcasecmp(argv[1], "nandboot") == 0 &&
strcasecmp(argv[2], ready_to_blow) == 0) {
-#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31) ||defined(CYGPKG_HAL_ARM_MX35) || defined(CYGPKG_HAL_ARM_MX25)
+#if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || \
+ defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31) || \
+ defined(CYGPKG_HAL_ARM_MX35) || defined(CYGPKG_HAL_ARM_MX25)
diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
#else
#error "Are you sure you want this?"
.macro LED_INIT
// initialize GPIO PF13 for LED on STK5
ldr r10, GPIOF_BASE
+ // PTF_OCR1
+ mov r9, #(3 << (2 * 13))
+ str r9, [r10, #GPIO_OCR1]
// PTF_GIUS
ldr r9, [r10, #GPIO_GIUS]
orr r9, r9, #(1 << 13)
// PTF_DDIR
mov r9,#(1 << 13)
str r9, [r10, #GPIO_DDIR]
- // PTF_OCR1
- mov r9, #(3 << (2 * 13))
- str r9, [r10, #GPIO_OCR1]
.endm
// This macro represents the initial startup code for the platform
init_aipi_start:
init_aipi
+ /* configure GPIO PB22 (OSC26M enable) as output high */
+ ldr r10, GPIOB_BASE
+
+ // PTB_OCR1
+ mov r9, #(3 << (2 * (22 - 16)))
+ str r9, [r10, #GPIO_OCR2]
+ // PTB_DR
+ ldr r9, [r10, #GPIO_DR]
+ orr r9, r9, #(1 << 22)
+ str r9, [r10, #GPIO_DR]
+ // PTB_GIUS
+ ldr r9, [r10, #GPIO_GIUS]
+ orr r9, r9, #(1 << 22)
+ str r9, [r10, #GPIO_GIUS]
+ // PTB_DDIR
+ mov r9,#(1 << 22)
+ str r9, [r10, #GPIO_DDIR]
+
LED_INIT
// setup System Controls
init_max
init_drive_strength_start:
init_drive_strength
-#if 0
-init_cs4_start:
- init_cs4
-#endif
-
-#if 0
-init_cs0_start:
- init_cs0
-#endif
- LED_INIT
// check if sdram has been setup
cmp pc, #SDRAM_BASE_ADDR
// add some delay here
mov r1, #0x1000
1:
- subs r1, r1, #0x1
+ subs r1, r1, #0x1
bne 1b
- ldr r2, SOC_CRM_CSCR2_W
- str r2, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
+ ldr r1, SOC_CRM_CSCR2_W
+ str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)]
// Set divider of H264_CLK to zero, NFC to 3.
- ldr r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
- bic r2, r2, #0x0000FC00
- str r2, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+ ldr r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
+ bic r1, r1, #0x0000FC00
+ str r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)]
/* Configure PCDR1 */
ldr r1, SOC_CRM_PCDR1_W
ldr r1, SDRAM_ESDCFG0_VAL
str r1, [r0, #ESDCTL_ESDCFG0]
+ ldr r1, SDRAM_DLY_VAL
+ str r1, [r0, #ESDCTL_ESDCDLY1]
+ str r1, [r0, #ESDCTL_ESDCDLY2]
+ str r1, [r0, #ESDCTL_ESDCDLY3]
+ str r1, [r0, #ESDCTL_ESDCDLY4]
+ str r1, [r0, #ESDCTL_ESDCDLY5]
+
ldr r1, SDRAM_PRE_ALL_CMD
str r1, [r0, #ESDCTL_ESDCTL0]
.align 5
.ascii "KARO TX27 " __DATE__ " " __TIME__
.align
+
+/* SDRAM configuration */
+#define RA_BITS 2 /* row addr bits - 11 */
+#define CA_BITS (SDRAM_SIZE / SZ_64M) /* 0-2: col addr bits - 8 3: rsrvd */
+#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
+#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
+#define PWDT 1 /* 0: disabled 1: precharge pwdn
+ 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
+#define FP 0 /* 0: not full page 1: full page */
+#define BL 1 /* 0: 4(not for LPDDR) 1: 8 */
+#define PRCT 5 /* 0: disabled *: clks / 2 (0..63) */
+#define ESDCTLVAL (0x80000000 | (RA_BITS << 24) | (CA_BITS << 20) | \
+ (DSIZ << 16) | (SREFR << 13) | (PWDT << 10) | (FP << 8) | \
+ (BL << 7) | (PRCT << 0))
+
+/* SDRAM timing definitions */
+#define SDRAM_CLK 133
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+
+ .macro CK_VAL, name, clks, offs
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .ifle \clks - 16
+ .set \name, \clks - \offs
+ .else
+ .set \name, 0
+ .endif
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs
+ .endif
+ .endm
+
+#if SDRAM_SIZE <= SZ_64M
+/* MT46H16M32LF-75 */
+CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+/* tRC is actually max(tRC,tRFC,tXSR) */
+NS_VAL tRC, 120, 1 /* 0: 20 *: clks - 1 (0..15) */
+#else
+/* MT46H32M32LF-6 or -75 */
+NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 23, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 45, 1 /* clks - 1 (0..15) */
+CK_VAL tCAS, 3, 0 /* clks - 1 (0..3) */
+NS_VAL tRRD, 15, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 23, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */
+#endif
+
+#define ESDCFGVAL ((tXP << 21) | (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tWR << 15) | (tRAS << 12) | (tRRD << 10) | (tCAS << 8) | \
+ (tRCD << 4) | (tRC << 0))
+
// All these constants need to be in the first 2KiB of FLASH
+GPIOB_BASE: .word 0x10015100
GPIOF_BASE: .word 0x10015500
SDRAM_ADDR_MASK: .word 0xffff0000
MXC_REDBOOT_RAM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
CS4_CSCRA_VAL: .word 0x44443302
NFC_BASE_W: .word NFC_BASE
SOC_ESDCTL_BASE_W: .word SOC_ESDCTL_BASE
-SDRAM_ESDCFG0_VAL: .word 0x00395729
+SDRAM_ESDCFG0_VAL: .word ESDCFGVAL
+SDRAM_DLY_VAL: .word 0x002c0000
SDRAM_PRE_ALL_CMD: .word 0x92120000
SDRAM_AUTO_REF_CMD: .word 0xA2120000
SDRAM_SET_MODE_REG_CMD: .word 0xB2120000
-#if SDRAM_SIZE > SZ_64M
-SDRAM_NORMAL_MODE: .word 0x82226485
-#else
-SDRAM_NORMAL_MODE: .word 0x82126485
-#endif
+SDRAM_NORMAL_MODE: .word ESDCTLVAL
CS0_CSCRU_VAL: .word 0x0000CC03
CS0_CSCRL_VAL: .word 0xA0330D01
CS0_CSCRA_VAL: .word 0x00220800
ARM_ACCESS_TYPE_NO_ACCESS(13) | \
ARM_ACCESS_TYPE_NO_ACCESS(14) | \
ARM_ACCESS_TYPE_NO_ACCESS(15) )
-#if 0
-/*
- * translate the virtual address of ram space to physical address
- * It is dependent on the implementation of hal_mmu_init
- */
-static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
-{
- if(virt < 0x08000000) {
- return virt|0xA0000000;
- }
- if((virt & 0xF0000000) == 0xA0000000) {
- return virt&(~0x08000000);
- }
- return virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
-{
- /* 0xA8000000~0xA8FFFFFF is uncacheable meory space which is mapped to SDRAM*/
- if((phy & 0xF0000000) == 0xA0000000) {
- phy |= 0x08000000;
- }
- return phy;
-}
-#endif
// ------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_MM_H
#define ESDCTL_ESDCTL1 0x08
#define ESDCTL_ESDCFG1 0x0C
#define ESDCTL_ESDMISC 0x10
+#define ESDCTL_ESDCDLY1 0x20
+#define ESDCTL_ESDCDLY2 0x24
+#define ESDCTL_ESDCDLY3 0x28
+#define ESDCTL_ESDCDLY4 0x2c
+#define ESDCTL_ESDCDLY5 0x30
#define NFC_BUFSIZE_REG_OFF (0 + 0x00)
#define RAM_BUFFER_ADDRESS_REG_OFF (0 + 0x04)
ARM_ACCESS_TYPE_NO_ACCESS(14) | \
ARM_ACCESS_TYPE_NO_ACCESS(15) )
-#if 0
-/*
- * translate the virtual address of ram space to physical address
- * It is dependent on the implementation of hal_mmu_init
- */
-static unsigned long __inline__ hal_virt_to_phy(unsigned long virt)
-{
- if (virt < 0x08000000) {
- return virt | 0x40000000;
- }
- if ((virt & 0xF0000000) == 0x40000000) {
- return virt & ~0x08000000;
- }
- return virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
-{
- /* 0x48000000~0x48FFFFFF is uncacheable meory space which is mapped to SDRAM*/
- if ((phy & 0xF0000000) == 0x40000000) {
- phy |= 0x08000000;
- }
- return phy;
-}
-#endif
-
// ------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_MM_H
// End of hal_mm.h
+++ /dev/null
-cdl_savefile_version 1;
-cdl_savefile_command cdl_savefile_version {};
-cdl_savefile_command cdl_savefile_command {};
-cdl_savefile_command cdl_configuration { description hardware template package };
-cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
-cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
-cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
-cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
-
-cdl_configuration eCos {
- description "" ;
- hardware mx51_3stack ;
- template redboot ;
- package -hardware CYGPKG_HAL_ARM current ;
- package -hardware CYGPKG_HAL_ARM_MX51 current ;
- package -hardware CYGPKG_HAL_ARM_MX51_3STACK current ;
- package -hardware CYGPKG_IO_ETH_DRIVERS current ;
- package -hardware CYGPKG_DEVS_ETH_ARM_IMX_3STACK current ;
- package -hardware CYGPKG_DEVS_ETH_SMSC_LAN92XX current ;
- #package -hardware CYGPKG_DEVS_ETH_FEC current ;
- package -hardware CYGPKG_COMPRESS_ZLIB current ;
- package -hardware CYGPKG_DIAGNOSIS current ;
- package -hardware CYGPKG_IO_FLASH current ;
- package -hardware CYGPKG_DEVS_FLASH_ONMXC current ;
- #package -hardware CYGPKG_DEVS_IMX_SPI current ;
- package -hardware CYGPKG_DEVS_MXC_I2C current ;
- package -template CYGPKG_HAL current ;
- package -template CYGPKG_INFRA current ;
- package -template CYGPKG_REDBOOT current ;
- package -template CYGPKG_ISOINFRA current ;
- package -template CYGPKG_LIBC_STRING current ;
- package -template CYGPKG_CRC current ;
- package CYGPKG_MEMALLOC current ;
-};
-
-cdl_option CYGHWR_MX51_TO2 {
- inferred_value 1
-};
-
-cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS {
- inferred_value 0
-};
-
-cdl_option CYGHWR_DEVS_FLASH_MXC_NOR {
- inferred_value 0
-};
-
-cdl_option CYGHWR_DEVS_FLASH_MXC_NAND {
- inferred_value 1
-};
-
-cdl_option CYGHWR_DEVS_FLASH_MMC {
- inferred_value 1
-};
-
-cdl_option CYGHWR_DEVS_FLASH_MXC_ATA {
- inferred_value 0
-};
-
-cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK {
- inferred_value 0
-};
-
-cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE {
- user_value 4096
-};
-
-cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
- user_value 0
-};
-
-cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY {
- user_value 50
-};
-
-cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
- inferred_value 0
-};
-
-cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
- inferred_value 1
-};
-
-cdl_option CYGSEM_HAL_ROM_MONITOR {
- inferred_value 1
-};
-
-cdl_component CYGBLD_BUILD_REDBOOT {
- user_value 1
-};
-
-cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE {
- inferred_value 0x00040000
-};
-
-cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT {
- inferred_value 0x90008000
-};
-
-cdl_option CYGBLD_ISO_STRTOK_R_HEADER {
- inferred_value 1 <cyg/libc/string/string.h>
-};
-
-cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER {
- inferred_value 1 <cyg/libc/string/string.h>
-};
-
-cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER {
- inferred_value 1 <cyg/libc/string/bsdstring.h>
-};
-
-cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER {
- inferred_value 1 <cyg/libc/string/string.h>
-};
-
-cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER {
- inferred_value 1 <cyg/libc/string/string.h>
-};
-
-cdl_component CYG_HAL_STARTUP {
- user_value ROMRAM
-};
-
-cdl_component CYGPKG_MEMORY_DIAGNOSIS {
- user_value 1
-};
-
-cdl_option CYGSEM_RAM_PM_DIAGNOSIS {
- user_value 0
-};
-
-#cdl_component CYGPKG_WDT_DIAGNOSIS {
-# user_value 1
-#};
-
-cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE {
- inferred_value 1
-};
-
-cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK {
- inferred_value 4
-};
-
-cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION {
- user_value 1 "FSL 200904"
-};
cdl_option CYGNUM_HAL_ARM_TX51_SDRAM_SIZE {
display "SDRAM size"
flavor data
- legal_values { 0x08000000 0x04000000 }
+ legal_values { 0x10000000 0x08000000 0x04000000 }
default_value { 0x08000000 }
# This is what I would like to do, but define_proc currently does not allow for
# accessing variables
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
-#define REMOVE_THIS_CRAP
-//#define BORKED
-#define USE_DCD
-//#define USE_LED
-//#define MX51_3STACK
-
#include <pkgconf/system.h> // System-wide configuration info
#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
#define TX51_NAND_PAGE_SIZE 2048
#define TX51_NAND_BLKS_PER_PAGE 64
-#ifndef MX51_3STACK
-#define DEBUG_LED_BIT 10
-#define LED_GPIO_BASE GPIO4_BASE_ADDR
-#define LED_MUX_OFFSET 0x1d0
-#define LED_MUX_MODE 0x13
-#else
#define DEBUG_LED_BIT 0
#define LED_GPIO_BASE GPIO1_BASE_ADDR
#define LED_MUX_OFFSET 0x3ac
#define LED_MUX_MODE 0x11
-#endif
#define LED_ON LED_CTRL #1
#define LED_OFF LED_CTRL #0
// This macro represents the initial startup code for the platform
.macro _platform_setup1
-#ifndef BORKED
KARO_TX51_SETUP_START:
mrs r0, CPSR
mov r0, #0x1f
.align 5
10:
LED_BLINK #3
-#endif // BORKED
.endm @ _platform_setup1
/* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
/* Switch peripheral to PLL 2 */
ldr r1, CCM_CBCDR_VAL1
str r1, [r0, #CLKCTL_CBCDR]
+ /* Use lp_apm (24MHz) source for perclk */
ldr r1, CCM_CBCMR_VAL2
str r1, [r0, #CLKCTL_CBCMR]
str r1, [r0, #CLKCTL_CCSR]
/* setup the rest */
- /* Use lp_apm (24MHz) source for perclk */
- ldr r1, CCM_CBCMR_VAL2
- str r1, [r0, #CLKCTL_CBCMR]
@ ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
ldr r1, CCM_CBCDR_VAL3
-
str r1, [r0, #CLKCTL_CBCDR]
/* Restore the default values in the Gate registers */
str r1, [r0, #CLKCTL_CCGR6]
/* Use PLL 2 for UART's, get 66.5MHz from it */
- ldr r1, CCM_VAL_0xA5A2A020
+ ldr r1, CCM_CSCMR1_VAL
str r1, [r0, #CLKCTL_CSCMR1]
- ldr r1, CCM_VAL_0x00C30321
+ ldr r1, CCM_CSCDR1_VAL
str r1, [r0, #CLKCTL_CSCDR1]
/* make sure divider effective */
/* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
ldr r0, M4IF_FBPM0_VAL
str r0, [r1, #M4IF_FBPM0]
+
+ ldr r0, M4IF_FPWC_VAL
+ str r0, [r1, #M4IF_FPWC]
.endm /* init_m4if */
.macro setup_sdram
- cmp r11, #0x10 // r11 contains the silicon rev
- bls skip_setup
#if 0
- /* Decrease the DRAM SDCLK to HIGH Drive strength */
- ldr r0, =IOMUXC_BASE_ADDR
- ldr r1, =0x000000e5
- str r1, [r0, #0x4b8]
- /* Change the delay line configuration */
- ldr r0, =ESDCTL_BASE_ADDR
- ldr r1, =0x00f49400
- str r1, [r0, #ESDCTL_ESDCDLY1]
- ldr r1, =0x00f49a00
- str r1, [r0, #ESDCTL_ESDCDLY2]
- ldr r1, =0x00f49100
- str r1, [r0, #ESDCTL_ESDCDLY3]
- ldr r1, =0x00f48900
- str r1, [r0, #ESDCTL_ESDCDLY4]
- ldr r1, =0x00f49400
- str r1, [r0, #ESDCTL_ESDCDLY5]
+ cmp r11, #0x10 // r11 contains the silicon rev
+ bls skip_setup
+ /* Decrease the DRAM SDCLK pads to HIGH Drive strength */
+ ldr r0, =IOMUXC_BASE_ADDR
+ ldr r1, =0x000000e5
+ str r1, [r0, #0x4b8]
+ /* Change the delay line configuration */
+ ldr r0, =ESDCTL_BASE_ADDR
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY1]
+ ldr r1, =0x00f49a00
+ str r1, [r0, #ESDCTL_ESDCDLY2]
+ ldr r1, =0x00f49100
+ str r1, [r0, #ESDCTL_ESDCDLY3]
+ ldr r1, =0x00f48900
+ str r1, [r0, #ESDCTL_ESDCDLY4]
+ ldr r1, =0x00f49400
+ str r1, [r0, #ESDCTL_ESDCDLY5]
#endif
skip_setup:
.endm
#define RALAT 1
#define LHD 0
-#define RA_BITS 2 /* row addr bits - 11 */
-#define CA_BITS 2 /* 0-2: col addr bits - 8 3: rsrvd */
+#if SDRAM_SIZE <= SZ_128M
+#define RA_BITS (13 - 11) /* row addr bits - 11 */
+#else
+#define RA_BITS (14 - 11) /* row addr bits - 11 */
+#endif
+
+#define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */
#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
#define SRT 0 /* 0: disabled *: 1: self refr. ... */
#define PWDT 0 /* 0: disabled 1: precharge pwdn
2: pwdn after 64 clocks 3: pwdn after 128 clocks */
-#define ESDCTL0_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
+#define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
(DSIZ << 16) | (SRT << 14) | (PWDT << 12))
-#define tRFC 17 /* clks - 1 (0..15) */ // 17
-#define tXSR 19 /* clks - 1 (0..15) */ // 19
-#define tXP 0 /* clks - 1 (0..7) */ // N/A
-#define tWTR 0 /* clks - 1 (0..1) */ // N/A
-#define tRP 1 /* clks - 2 (0..3) */ // 1
-#define tMRD 1 /* clks - 1 (0..3) */ // 1
-#define tWR 0 /* clks - 2 (0..1) */ // 0
-#define tRAS 5 /* clks - 1 (0..15) */ // 5
-#define tRRD 1 /* clks - 1 (0..3) */ // 1
-#define tRCD 2 /* clks - 1 (0..7) */ // 2
-#define tRC 8 /* 0: 20 *: clks - 1 (0..15) */ // 8
-
-#define ESDCFG0_VAL ((((tRFC) - 10) << 28) | ((tXSR) << 24) | ((tXP) << 21) | \
- ((tWTR) << 20) | ((tRP) << 18) | ((tMRD) << 16) | \
- ((tRAS) << 12) | ((tRRD) << 10) | ((tWR) << 7) | \
- ((tRCD) << 4) | ((tRC) << 0))
+#define SDRAM_CLK 200
+#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
+ .macro CK_VAL, name, clks, offs
+ .iflt \clks - \offs
+ .set \name, 0
+ .else
+ .set \name, \clks - \offs
+ .endif
+ .endm
+
+ .macro NS_VAL, name, ns, offs
+ .iflt \ns - \offs
+ .set \name, 0
+ .else
+ CK_VAL \name, NS_TO_CK(\ns), \offs
+ .endif
+ .endm
+
+#if SDRAM_SIZE <= SZ_128M
+/* MT46H32M32LF-6 */
+NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */
+NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */
+NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
+NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
+#else
+/* MT46H64M32LF-5 or -6 */
+NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */
+NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */
+CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
+CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
+NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
+CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
+NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
+NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
+NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
+NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
+NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
+#endif
+
+#define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
+ (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
+ (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \
+ (tRCD << 4) | (tRC << 0))
+/*
+ 0x70655427
+*/
#define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
#define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
#define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
.long dcd_data
app_dest_ptr:
#ifndef RAM_BANK1_SIZE
- .long RAM_BANK0_BASE + RAM_BANK0_SIZE - REDBOOT_OFFSET
+ .long RAM_BANK0_BASE + SDRAM_SIZE - REDBOOT_OFFSET
#else
.long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
#endif
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
- DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL0_VAL)
- DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG0_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG_VAL)
+#ifdef RAM_BANK1_SIZE
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, ESDCTL_VAL)
+ DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, ESDCFG_VAL)
+#endif
DCDGEN(4, ESDCTL_BASE_ADDR + 0x34, 0x00020000 | ((RALAT & 0x3) << 29))
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL)
DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
SRC_BASE_ADDR_W: .long SRC_BASE_ADDR
WDOG_BASE_ADDR_W: .long WDOG_BASE_ADDR
AIPS1_PARAM: .word 0x77777777
-M4IF_M4IF4_VAL: .word 0x00000203
-M4IF_FIDBP_VAL: .word 0x00000a01
-M4IF_FBPM0_VAL: .word 0x00000404
+M4IF_FBPM0_VAL: .word 0x00000103
+M4IF_M4IF4_VAL: .word 0x00230185
+M4IF_FPWC_VAL: .word 0x00240126
MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
CCM_CBCDR_VAL1: .word 0x19239145
CCM_CBCDR_VAL2: .word 0x13239145
-CCM_CBCDR_VAL3: .word 0x61E35100
+#if SDRAM_CLK == 200
+CCM_CBCDR_VAL3: .word 0x59E35100
+#else
+CCM_CBCDR_VAL3: .word 0x21E35100
+#endif
CCM_CBCMR_VAL1: .word 0x000010C0
CCM_CBCMR_VAL2: .word 0x000020C0
+CCM_CSCMR1_VAL: .word 0xA5A2A020
+CCM_CSCDR1_VAL: .word 0x00C30321
BASE_ADDR_PLL1: .long PLL1_BASE_ADDR
BASE_ADDR_PLL2: .long PLL2_BASE_ADDR
BASE_ADDR_PLL3: .long PLL3_BASE_ADDR
-//PLL_VAL_0x222: .word 0x222
-//PLL_VAL_0x232: .word 0x232
PLL_VAL_0x1232: .word 0x1232
W_DP_OP_800: .word DP_OP_800
W_DP_MFD_800: .word DP_MFD_800
W_DP_MFN_216: .word DP_MFN_216
PLATFORM_CLOCK_DIV: .word 0x00000124
-#ifdef REMOVE_THIS_CRAP
-CCM_VAL_0xA5A2A020: .word 0xA5A2A020
-CCM_VAL_0x00C30321: .word 0x00C30321
-#endif
-
/*----------------------------------------------------------------------*/
/* end of hal_platform_setup.h */
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
CYG_MACRO_END
#if !defined(__ASSEMBLER__)
-#ifdef CYGOPT_HAL_ARM_TX51_DEBUG // REMOVE ME
-extern void plf_dumpmem(unsigned long addr, int len);
-#else
-static inline void plf_dumpmem(unsigned long addr, int len)
-{
-}
-#endif // CYGOPT_HAL_ARM_TX51_DEBUG
+void mxc_ipu_iomux_config(void);
enum {
BOARD_TYPE_TX51KARO,
writel(val | (1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
writel(val | (1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
-#if 0
- if (grp != 2 || gpio != 17)
- diag_printf("%s: Changing GPIO_DR[%d]@%08lx from %08lx to %08lx\n", __FUNCTION__,
- grp, GPIO1_BASE_ADDR + ((grp - 1) << 14), val, val | (1 << gpio));
-#endif
}
static inline void gpio_clr_bit(int grp, int gpio)
writel(val & ~(1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_DR);
val = readl(GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
writel(val | (1 << gpio), GPIO1_BASE_ADDR + ((grp - 1) << 14) + GPIO_GDIR);
-#if 0
- if (grp != 2 || gpio != 17)
- diag_printf("%s: Changing GPIO_DR[%d]@%08lx from %08lx to %08lx\n", __FUNCTION__,
- grp, GPIO1_BASE_ADDR + ((grp - 1) << 14), val, val & ~(1 << gpio));
-#endif
}
#endif /* __ASSEMBLER__ */
#define UNCACHED_RAM_BASE_VIRT 0xF0000000
#define SZ_128M 0x08000000
+#define SZ_256M 0x10000000
#define RAM_BANK0_BASE CSD0_BASE_ADDR
#define RAM_BANK1_BASE CSD1_BASE_ADDR
-#define RAM_BANK0_SIZE SZ_128M
+#define RAM_BANK0_SIZE SZ_256M
#if SDRAM_SIZE > RAM_BANK0_SIZE
#define RAM_BANK1_SIZE (SDRAM_SIZE - RAM_BANK0_SIZE)
#endif
CYG_MACRO_END
// Get the physical address from a virtual address:
-#if 1
#define HAL_VIRT_TO_PHYS_ADDRESS(vaddr, paddr) \
CYG_MACRO_START \
(paddr) = hal_virt_to_phy(vaddr); \
CYG_MACRO_END
-#else
-#define HAL_VIRT_TO_PHYS_ADDRESS(vaddr, paddr) \
- CYG_MACRO_START \
- cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
- if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \
- _v_ += SDRAM_BASE_ADDR; \
- else /* Rest of it */ \
- /* no change */ ; \
- (paddr) = _v_; \
- CYG_MACRO_END
-#endif
/*
* translate the virtual address of ram space to physical address
*/
static unsigned long __inline__ hal_ioremap_nocache(unsigned long phy)
{
- /* (CSD0_BASE_ADDR + SZ_128M) .. (CSD0_BASE_ADDR + SZ_256M - 1) is
- uncacheable memory space which is mapped to SDRAM */
+ /* 0xf0000000 .. (0xf0000000 + SDRAM_SIZE) is
+ * uncacheable memory space which is mapped to SDRAM
+ */
if ((phy & 0xF0000000) == CSD0_BASE_ADDR) {
phy = (phy - CSD0_BASE_ADDR) | UNCACHED_RAM_BASE_VIRT;
}
return ret;
}
ret = lp3972_reg_write(0x39, 0xf0);
- if (ret < 0) {
+ if (ret < 0 && ret != -ENOSYS) {
diag_printf("Failed to switch fuse programming voltage: %d\n", ret);
return ret;
}
ret = lp3972_reg_read(0x39);
- if (ret != 0xf0) {
+ if (ret != -ENOSYS && ret != 0xf0) {
diag_printf("Failed to switch fuse programming voltage: %d\n", ret);
return ret;
}
for (i = 0; i < ETHER_ADDR_LEN; i++) {
- int bit;
unsigned char fuse = readl(SOC_FEC_MAC_BASE +
ETHER_ADDR_LEN * 4 - ((i + 1) << 2));
+ int row = SOC_MAC_ADDR_FUSE + ETHER_ADDR_LEN - 1 - i;
- for (bit = 0; bit < 8; bit++) {
- if (((mac_addr[i] >> bit) & 0x1) == 0)
- continue;
- if (((mac_addr[i] >> bit) & 1) == ((fuse >> bit) & 1)) {
- continue;
- }
- if (fuse_blow(SOC_MAC_ADDR_FUSE_BANK,
- SOC_MAC_ADDR_FUSE + ETHER_ADDR_LEN - 1 - i,
- bit)) {
- diag_printf("Failed to blow fuse bank 0 row %d bit %d\n",
- i, bit);
- ret = -1;
- goto out;
- }
+ if (fuse == mac_addr[i]) {
+ continue;
+ }
+ fuse_blow_row(SOC_MAC_ADDR_FUSE_BANK, row, mac_addr[i]);
+ ret = sense_fuse(SOC_MAC_ADDR_FUSE_BANK, row, 0);
+ if (ret != mac_addr[i]) {
+ diag_printf("Failed to verify fuse bank %d row %d; expected %02x got %02x\n",
+ SOC_MAC_ADDR_FUSE_BANK, row, mac_addr[i], ret);
+ goto out;
}
}
#ifdef SOC_MAC_ADDR_LOCK_BIT
- fuse_blow(SOC_MAC_ADDR_FUSE_BANK, SOC_MAC_ADDR_LOCK_FUSE,
- SOC_MAC_ADDR_LOCK_BIT);
+ fuse_blow_row(SOC_MAC_ADDR_FUSE_BANK, SOC_MAC_ADDR_LOCK_FUSE,
+ (1 << SOC_MAC_ADDR_LOCK_BIT));
#endif
out:
lp3972_reg_write(0x39, 0);
}
RedBoot_init(random_init, RedBoot_INIT_FIRST);
-#define WDOG_WRSR ((CYG_WORD16 *)0x10002004)
static void display_board_type(void)
{
- CYG_WORD32 reset_cause;
- const char *dlm = "";
-
- diag_printf("\nBoard Type: Ka-Ro TX51\n");
- diag_printf("Last RESET cause: ");
- HAL_READ_UINT32(SRC_BASE_ADDR + 8, reset_cause);
-
- if ((reset_cause & 9) == 1) {
- diag_printf("%sPOWER_ON RESET", dlm);
- dlm = " | ";
- } else if ((reset_cause & 9) == 9) {
- diag_printf("%sUSER RESET", dlm);
- dlm = " | ";
- }
- if ((reset_cause & 0x11) == 0x11) {
- diag_printf("%sWATCHDOG RESET", dlm);
- dlm = " | ";
- } else if ((reset_cause & 0x11) == 0x10) {
- diag_printf("%sSOFT RESET", dlm);
- dlm = " | ";
- }
- if (*dlm == '\0') {
- diag_printf("UNKNOWN: %08x\n", reset_cause);
- } else {
- diag_printf("\n");
- }
+ diag_printf("\nBoard Type: Ka-Ro TX51-80x%d\n",
+ SDRAM_SIZE > SZ_128M);
}
static void display_board_info(void)
#define UART_WIDTH_32 /* internal UART is 32bit access only */
#if !defined(__ASSEMBLER__)
-extern int fuse_blow(int bank, int row, int bit);
+extern void fuse_blow_row(int bank, int row, int value);
+extern unsigned int sense_fuse(int bank, int row, int bit);
void cyg_hal_plf_serial_init(void);
void cyg_hal_plf_serial_stop(void);
#include "hab_super_root.h"
+//#define IIM_FUSE_DEBUG
//#define CMD_CLOCK_DEBUG
#ifdef CMD_CLOCK_DEBUG
#define dbg(fmt...) \
}
break;
case DDR_CLK:
- if (((cbcdr >> 30) & 0x1) == 0x1) {
+ if (cbcdr & (1 << 30)) {
pll = pll_clock(PLL1);
pdf = (cbcdr >> 27) & 0x7;
} else {
void do_L2_caches(int argc, char *argv[])
{
u32 oldints;
- int L2cache_on=0;
if (argc == 2) {
if (strcasecmp(argv[1], "on") == 0) {
diag_printf("Invalid L2 cache mode: %s\n", argv[1]);
}
} else {
+ int L2cache_on;
+
HAL_L2CACHE_IS_ENABLED(L2cache_on);
- diag_printf("L2 cache: %s\n", L2cache_on?"On":"Off");
+ diag_printf("L2 cache: %s\n", L2cache_on ? "On" : "Off");
}
}
#endif //L2CC_ENABLED
return -1;
}
-static unsigned int sense_fuse(int bank, int row, int bit)
+unsigned int sense_fuse(int bank, int row, int bit)
{
int addr, addr_l, addr_h, reg_addr;
addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
+ diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
__FUNCTION__, addr_h, addr_l);
#endif
writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
/* Blow fuses based on the bank, row and bit positions (all 0-based)
*/
-int fuse_blow(int bank,int row,int bit)
+static int fuse_blow(int bank, int row, int bit)
{
int addr, addr_l, addr_h, ret = -1;
addr_l = (addr & 0x000000FF);
#ifdef IIM_FUSE_DEBUG
- diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
+ diag_printf("blowing fuse %d %d bit %d addr_h=0x%02x, addr_l=0x%02x\n",
+ bank, row, bit, addr_h, addr_l);
#endif
writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
/* Start Programming */
- writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
+ writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
ret = 0;
}
return num;
}
-static void fuse_blow_row(int bank, int row, int value)
+void fuse_blow_row(int bank, int row, int value)
{
unsigned int reg, i;
memcpy(val, s, 2);
val[2]='\0';
value = quick_atoi(val, 2);
- // diag_printf("fuse_blow_row(2, %d, value=0x%x)\n", i, value);
+ // diag_printf("fuse_blow_row(2, %d, value=0x%02x)\n", i, value);
fuse_blow_row(2, i, value);
if ((++s)[0] == '\0') {
bank, row, value);
fuse_blow_row(bank, row, value);
fuse_val = sense_fuse(bank, row, 0);
- diag_printf("fuses at (bank:%ld, row:%ld) = 0x%x\n", bank, row, fuse_val);
+ diag_printf("fuses at (bank:%ld, row:%ld) = 0x%02x\n", bank, row, fuse_val);
} else {
diag_printf("Passing in wrong arguments: %d\n", argc);
static void show_sys_info(void)
{
unsigned int sbmr = readl(SRC_BASE_ADDR + 0x4);
+ const char *dlm = "";
if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
diag_printf("Unrecognized chip version: 0x%08x!!!\n", read_system_rev());
}
diag_printf("Reset reason: ");
- switch (_reset_reason) {
- case 0x09:
- diag_printf("User reset\n");
- break;
- case 0x01:
- diag_printf("Power-on reset\n");
- break;
- case 0x10:
- case 0x11:
- diag_printf("WDOG reset\n");
- break;
- default:
- diag_printf("Unknown: 0x%08x\n", _reset_reason);
+
+ if (_reset_reason & (1 << 0)) {
+ diag_printf("%sPOWER_ON", dlm);
+ dlm = " | ";
+ }
+ if (_reset_reason & (1 << 2)) {
+ diag_printf("%sCSU", dlm);
+ dlm = " | ";
+ }
+ if (_reset_reason & (1 << 3)) {
+ diag_printf("%sUSER", dlm);
+ dlm = " | ";
+ }
+ if (_reset_reason & (1 << 4)) {
+ CYG_WORD16 wrsr;
+
+ HAL_READ_UINT16(WDOG_BASE_ADDR + 4, wrsr);
+ if (wrsr & 0x01) {
+ diag_printf("%sSOFT", dlm);
+ dlm = " | ";
+ }
+ if (wrsr & 0x10) {
+ diag_printf("%sWATCHDOG", dlm);
+ dlm = " | ";
+ }
+ }
+ if (_reset_reason & (1 << 5)) {
+ diag_printf("%sJTAG_HW", dlm);
+ dlm = " | ";
+ }
+ if (_reset_reason & (1 << 6)) {
+ diag_printf("%sJTAG_SW", dlm);
+ dlm = " | ";
+ }
+ if (_reset_reason & (1 << 16)) {
+ diag_printf("%sWARM BOOT", dlm);
+ dlm = " | ";
+ }
+
+ if (*dlm == '\0') {
+ diag_printf("UNKNOWN: %08x\n", _reset_reason);
+ } else {
+ diag_printf(" RESET\n");
}
if (_mxc_fis == MMC_FLASH_BOOT) {
if (!have_net) {
net_init();
+ if (!__local_enet_sc) {
+ diag_printf("Sorry, networking is not available.\n");
+ return;
+ }
}
-#if 0
- if (!have_net) {
- diag_printf("Sorry, networking is not available.\n");
- return;
- }
-#endif
+
init_opts(&opts[0], 'l', true, OPTION_ARG_TYPE_STR,
&ip_addr, &ip_addr_set, "local IP address");
init_opts(&opts[1], 'h', true, OPTION_ARG_TYPE_STR,
projects / karo-tx-redboot.git / commitdiff