From: lothar Date: Mon, 4 Oct 2010 11:38:43 +0000 (+0000) Subject: Bugfix Release STK5 2010-10-04 X-Git-Tag: v1.5.3~22 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-redboot.git;a=commitdiff_plain;h=06e00636bab554f0b6a5c836eeba82088236f1f4 Bugfix Release STK5 2010-10-04 --- diff --git a/build.sh b/build.sh index 9363ba52..b09c9afa 100644 --- a/build.sh +++ b/build.sh @@ -10,8 +10,6 @@ rebuild=false doit=true make_opts= -cmd_prefix=${CROSS_COMPILE-arm-926ejs-linux-gnu-} - error() { if [ -n "${target}" ];then echo "${target} build aborted" @@ -49,10 +47,6 @@ build_host_tools() { cd "$wd" } -if [ `uname -s` = Linux ];then - PATH="/usr/local/arm/cross-gcc-4.2.0/i686-pc-linux-gnu/bin:$PATH" -fi - while getopts "$options" opt;do case $opt in c) @@ -148,13 +142,11 @@ for target in ${targets};do if $clean;then $quiet || echo "Cleaning up build tree for ${target}" - #make ${make_opts} COMMAND_PREFIX=${cmd_prefix} clean make ${make_opts} clean fi $quiet || echo "Compiling ${target}" [ -d "${build_dir}" ] - #make -C "${build_dir}" COMMAND_PREFIX=${cmd_prefix} ${make_opts} make -C "${build_dir}" ${make_opts} cd $wd diff --git a/packages/hal/arm/mx25/var/v2_0/src/soc_misc.c b/packages/hal/arm/mx25/var/v2_0/src/soc_misc.c index 13283fbc..66f5fb02 100644 --- a/packages/hal/arm/mx25/var/v2_0/src/soc_misc.c +++ b/packages/hal/arm/mx25/var/v2_0/src/soc_misc.c @@ -95,7 +95,7 @@ static int find_correct_chip; /* * This functions reads the IIM module and returns the system revision number. * It returns the IIM silicon revision reg value if valid product rev is found. - . Otherwise, it returns -1. + * Otherwise, it returns CHIP_VERSION_NONE. */ static int read_system_rev(void) { @@ -108,9 +108,7 @@ static int read_system_rev(void) * the lowest revision number */ if ((MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) != PROD_SIGNATURE_SUPPORTED_1)) { -#if 0 return CHIP_VERSION_NONE; -#endif } /* Now trying to retrieve the silicon rev from IIM's SREV register */ @@ -132,18 +130,23 @@ void hal_hardware_init(void) if (ver == 0x0) { HAL_PLATFORM_EXTRA[5] = '1'; HAL_PLATFORM_EXTRA[7] = '0'; - system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/ - system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/ + system_rev |= 1 << MAJOR_NUMBER_OFFSET; + system_rev |= 0 << MINOR_NUMBER_OFFSET; } else if (ver == 0x1) { HAL_PLATFORM_EXTRA[5] = '1'; HAL_PLATFORM_EXTRA[7] = '1'; - system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/ - system_rev |= 1 << MINOR_NUMBER_OFFSET; /*Minor Number*/ + system_rev |= 1 << MAJOR_NUMBER_OFFSET; + system_rev |= 1 << MINOR_NUMBER_OFFSET; + } else if (ver == 0x2) { + HAL_PLATFORM_EXTRA[5] = '1'; + HAL_PLATFORM_EXTRA[7] = '1'; + system_rev |= 1 << MAJOR_NUMBER_OFFSET; + system_rev |= 2 << MINOR_NUMBER_OFFSET; } else { - HAL_PLATFORM_EXTRA[5] = 'z'; - HAL_PLATFORM_EXTRA[7] = 'z'; - system_rev |= 1 << MAJOR_NUMBER_OFFSET; /*Major Number*/ - system_rev |= 0 << MINOR_NUMBER_OFFSET; /*Minor Number*/ + HAL_PLATFORM_EXTRA[5] = '-'; + HAL_PLATFORM_EXTRA[7] = '-'; + system_rev |= 1 << MAJOR_NUMBER_OFFSET; + system_rev |= 0 << MINOR_NUMBER_OFFSET; find_correct_chip = CHIP_VERSION_UNKNOWN; } } diff --git a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h index d3d8e100..f5ec325d 100644 --- a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h +++ b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h @@ -63,6 +63,9 @@ #define CYGHWR_HAL_ROM_VADDR 0x0 +#define DEBUG_LED_BIT 13 +#define DEBUG_LED_PORT GPIOF_BASE + #ifndef CYGOPT_HAL_ARM_TX27_DEBUG #define LED_ON #define LED_OFF @@ -76,6 +79,7 @@ #define CYGHWR_LED_MACRO LED_BLINK #\x #define LED_ON bl led_on #define LED_OFF bl led_off + .macro DELAY,ms ldr r10, =\ms 111: @@ -92,12 +96,13 @@ .macro LED_CTRL,val // switch user LED (PF13) on STK5 - ldr r10, GPIOF_BASE + ldr r10, DEBUG_LED_PORT // PTF_DR mov r9, \val cmp r9, #0 - movne r9, #(1 << 13) // LED ON - moveq r9, #0 // LED OFF + ldr r9, [r10, #GPIO_DR] + orrne r9, #(1 << DEBUG_LED_BIT) // LED ON + biceq r9, #(1 << DEBUG_LED_BIT) // LED OFF str r9, [r10, #GPIO_DR] .endm @@ -118,19 +123,35 @@ .macro LED_INIT // initialize GPIO PF13 for LED on STK5 - ldr r10, GPIOF_BASE + ldr r10, DEBUG_LED_PORT + // PTF_DR + ldr r9, [r10, #GPIO_DR] + bic r9, #(1 << DEBUG_LED_BIT) + str r9, [r10, #GPIO_DR] // PTF_OCR1 - mov r9, #(3 << (2 * 13)) + ldr r9, [r10, #GPIO_OCR1] + orr r9, #(3 << (2 * (DEBUG_LED_BIT % 16))) str r9, [r10, #GPIO_OCR1] // PTF_GIUS ldr r9, [r10, #GPIO_GIUS] - orr r9, r9, #(1 << 13) + orr r9, r9, #(1 << DEBUG_LED_BIT) str r9, [r10, #GPIO_GIUS] // PTF_DDIR - mov r9,#(1 << 13) + ldr r9, [r10, #GPIO_DDIR] + orr r9, #(1 << DEBUG_LED_BIT) str r9, [r10, #GPIO_DDIR] .endm + .macro WDOG_RESET + ldr r10, SOC_CRM_BASE_W + ldr r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)] + orr r9, r9, #(1 << 2) /* enable FPM */ + str r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)] + + ldr r10, WDOG_BASE + mov r9, #0 + str r9, [r10, #0] + .endm // This macro represents the initial startup code for the platform // r11 is reserved to contain chip rev info in this file .macro _platform_setup1 @@ -146,9 +167,9 @@ init_aipi_start: /* configure GPIO PB22 (OSC26M enable) as output high */ ldr r10, GPIOB_BASE - // PTB_OCR1 - mov r9, #(3 << (2 * (22 - 16))) + ldr r9, [r10, #GPIO_OCR2] + orr r9, #(3 << (2 * (22 % 16))) str r9, [r10, #GPIO_OCR2] // PTB_DR ldr r9, [r10, #GPIO_DR] @@ -159,7 +180,8 @@ init_aipi_start: orr r9, r9, #(1 << 22) str r9, [r10, #GPIO_GIUS] // PTB_DDIR - mov r9,#(1 << 22) + ldr r9, [r10, #GPIO_DDIR] + orr r9, #(1 << 22) str r9, [r10, #GPIO_DDIR] LED_INIT @@ -175,7 +197,7 @@ init_aipi_start: init_max_start: init_max init_drive_strength_start: - init_drive_strength +@ init_drive_strength // check if sdram has been setup cmp pc, #SDRAM_BASE_ADDR @@ -220,7 +242,11 @@ NAND_Boot_Start: LED_OFF b 4f 3: +#ifdef CYGOPT_HAL_ARM_TX27_DEBUG LED_BLINK #3 +#else + WDOG_RESET +#endif b 3b 4: LED_ON @@ -280,14 +306,12 @@ Nfc_Read_Page: LED_ON strh r8, [r4, #RAM_BUFFER_ADDRESS_REG_OFF] bl nfc_data_output -#if 1 + // check for bad block mov r3, r1, lsl #(32-17) // get rid of block number cmp r3, #(TX27_NAND_PAGE_SIZE << (32-17)) // check if not first or second page in block bhi Copy_Good_Blk -#else - b Copy_Good_Blk -#endif + add r9, r0, #TX27_NAND_PAGE_SIZE //r3 -> spare area buf 0 ldrh r9, [r9, #0x4] and r9, r9, #0xFF00 @@ -388,7 +412,7 @@ NAND_ClockSetup: b 9f .align 5 9: - mov pc,r2 /* Change address spaces */ + mov pc, r2 /* Change address spaces */ 10: nop .endm // _platform_setup1 @@ -422,11 +446,9 @@ NAND_ClockSetup: orr r1, r1, #0x000C0000 // restart SPLL and MPLL orr r1, r1, #0x00000003 // enable SPLL and MPLL str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] - - // add some delay here - mov r1, #0x1000 1: - subs r1, r1, #0x1 + ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] + tst r1, #0x000C0000 bne 1b ldr r1, SOC_CRM_CSCR2_W @@ -586,7 +608,7 @@ NAND_ClockSetup: add r3, r2, #(2 << 24) @ select drive strength via extended mode register: @ 0=full 1=half 2=quarter 3=3-quarter - ldrb r1, [r2, #(0 << 5)] + ldrb r1, [r3, #(0 << 5)] ldrb r1, [r2, #0x033] @ write to SDRAM MODE register (via A0-A12) @@ -613,7 +635,7 @@ led_off: str r9, [r10, #GPIO_DR] mov pc, lr #endif - + nfc_cmd_input: strh r3, [r4, #NAND_FLASH_CMD_REG_OFF] mov r3, #NAND_FLASH_CONFIG2_FCMD_EN @@ -749,6 +771,7 @@ NS_VAL tRC, 138, 1 /* 0: 20 *: clks - 1 (0..15) */ (tRCD << 4) | (tRC << 0)) // All these constants need to be in the first 2KiB of FLASH +WDOG_BASE: .word WDOG_BASE_ADDR GPIOB_BASE: .word 0x10015100 GPIOF_BASE: .word 0x10015500 SDRAM_ADDR_MASK: .word 0xffff0000 diff --git a/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c b/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c index 877a26c3..723810bf 100644 --- a/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c +++ b/packages/hal/arm/mx51/var/v2_0/src/soc_misc.c @@ -77,8 +77,6 @@ int _mxc_fis; unsigned int system_rev = CHIP_REV_1_0; static int find_correct_chip; -static int _reset_reason; - #define SBMR_BT_MEM_CTL_SHIFT 0 #define SBMR_BT_MEM_CTL_MASK (3 << SBMR_BT_MEM_CTL_SHIFT) #define SBMR_BT_MEM_CTL(r) (((r) & SBMR_BT_MEM_CTL_MASK) >> SBMR_BT_MEM_CTL_SHIFT) @@ -211,8 +209,6 @@ void hal_hardware_init(void) _mxc_fis = FROM_NAND_FLASH; #endif - _reset_reason = readl(SRC_BASE_ADDR + 0x8); - find_correct_chip = ver; if (ver != CHIP_VERSION_NONE) { @@ -580,7 +576,8 @@ unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, static void show_sys_info(void) { - unsigned int sbmr = readl(SRC_BASE_ADDR + 0x4); + cyg_uint32 sbmr = readl(SRC_BASE_ADDR + 0x4); + cyg_uint32 srsr = readl(SRC_BASE_ADDR + 0x8); const char *dlm = ""; if (find_correct_chip == CHIP_VERSION_UNKNOWN) { @@ -592,46 +589,46 @@ static void show_sys_info(void) diag_printf("Reset reason: "); - if (_reset_reason & (1 << 0)) { + if (srsr & (1 << 0)) { diag_printf("%sPOWER_ON", dlm); dlm = " | "; } - if (_reset_reason & (1 << 2)) { + if (srsr & (1 << 2)) { diag_printf("%sCSU", dlm); dlm = " | "; } - if (_reset_reason & (1 << 3)) { + if (srsr & (1 << 3)) { diag_printf("%sUSER", dlm); dlm = " | "; } - if (_reset_reason & (1 << 4)) { + if (srsr & (1 << 4)) { CYG_WORD16 wrsr; HAL_READ_UINT16(WDOG_BASE_ADDR + 4, wrsr); - if (wrsr & 0x01) { + if (wrsr & (1 << 0)) { diag_printf("%sSOFT", dlm); dlm = " | "; } - if (wrsr & 0x10) { + if (wrsr & (1 << 1)) { diag_printf("%sWATCHDOG", dlm); dlm = " | "; } } - if (_reset_reason & (1 << 5)) { + if (srsr & (1 << 5)) { diag_printf("%sJTAG_HW", dlm); dlm = " | "; } - if (_reset_reason & (1 << 6)) { + if (srsr & (1 << 6)) { diag_printf("%sJTAG_SW", dlm); dlm = " | "; } - if (_reset_reason & (1 << 16)) { + if (srsr & (1 << 16)) { diag_printf("%sWARM BOOT", dlm); dlm = " | "; } if (*dlm == '\0') { - diag_printf("UNKNOWN: %08x\n", _reset_reason); + diag_printf("UNKNOWN: %08x\n", srsr); } else { diag_printf(" RESET\n"); } @@ -646,7 +643,6 @@ static void show_sys_info(void) diag_printf("Use \"factive [MMC|SPI|NAND]\" to choose fis/fconfig storage\n"); } - diag_printf("SBMR = 0x%08x\n", readl(SRC_BASE_ADDR + 0x4)); diag_printf("Boot switch: "); if ((SBMR_BMOD(sbmr)) == 0) { diag_printf("INTERNAL (GPIO)\n");