From: Lothar Waßmann Date: Fri, 8 Aug 2014 13:26:04 +0000 (+0200) Subject: karo: tx51: setup SDRAM & NAND control pads from DCD X-Git-Tag: KARO-TX51-2014-08-08~2 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-redboot.git;a=commitdiff_plain;h=d84d6fd4dbc18a05c30fe03fa5eda9a0533f8d17 karo: tx51: setup SDRAM & NAND control pads from DCD - Explicitly program the padctl settings for SDRAM and NAND from the DCD to ensure correct settings after soft reset. - Reduce DSE values for SDRAM and NAND control lines for better error margins in NAND detection and SDRAM stress test. - Revert the change of the NFC clock frequency from the previous release, as this is not necessary any more with the improved pad settings. --- diff --git a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h index 7f613221..d02cb1e4 100644 --- a/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h +++ b/packages/hal/arm/mx51/karo/v1_0/include/hal_platform_setup.h @@ -639,6 +639,58 @@ dcd_start: DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDGPR, 0x00020000) DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL) DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000) + + DCDGEN(4, IOMUXC_BASE_ADDR + 0x508, 0x000020e0) @ EIM_SDBA2 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x50c, 0x000020e1) @ EIM_SDODT1 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x510, 0x000020e1) @ EIM_SDODT0 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x820, 0x00000040) @ (Bit6 PUE) GRP_DDRPKS + DCDGEN(4, IOMUXC_BASE_ADDR + 0x82c, 0x00000000) @ (Bit[1..2] DSE D[24..31]) GRP_DRAM_B4 DFT: 0x4 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x830, 0x00000000) @ (Bit9 DDR_INPUT A[0..14] CAS CS[0..1] RAS SDCKE[0..1] + @ SDWE SDBA[0..1]) GRP_INDDR + DCDGEN(4, IOMUXC_BASE_ADDR + 0x838, 0x00000080) @ (Bit7 PKE D[0..31]) GRP_PKEDDR + DCDGEN(4, IOMUXC_BASE_ADDR + 0x83c, 0x00000000) @ (Bit[1..2] DSE A[0..7]) GRP_DDR_A0 DFT: 0x4 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x848, 0x00000000) @ (Bit[1..2] DSE A[8..14] SDBA[0..2]) GRP_DDR_A1 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x84c, 0x00000020) @ (Bit[4..5] PUS A[0..14] CAS RAS SDBA[0..1]) GRP_DDRAPUS + DCDGEN(4, IOMUXC_BASE_ADDR + 0x85c, 0x00000000) @ (Bit8 HYS D[0..7]) GRP_HYSDDR0 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x864, 0x00000000) @ (Bit8 HYS D[8..15]) GRP_HYSDDR1 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x86c, 0x00000000) @ (Bit8 HYS D[16..23]) GRP_HYSDDR2 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x870, 0x00002000) @ (Bit13 A[0..14] CAS CS[0..1] D[0..31] DQM[0..3] RAS + @ SDCKE[0..1] SDCLK SDQS[0..3] SDWE SDBA[0..2] + @ SDODT[0..1]) GRP_HVDDR + DCDGEN(4, IOMUXC_BASE_ADDR + 0x874, 0x00000000) @ (Bit8 HYS D[24..31]) GRP_HYSDDR3 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x878, 0x00000001) @ (Bit0 SRE D[0..7]) GRP_SR_B0 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x87c, 0x00000040) @ (Bit6 PUE A[0..14] CAS RAS SDBA[0..1]) GRP_DDRAPKS + DCDGEN(4, IOMUXC_BASE_ADDR + 0x880, 0x00000001) @ (Bit0 SRE D[8..15]) GRP_SR_B1 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x884, 0x00000020) @ (Bit[4..5] PUS D[0..31]) GRP_DDRPUS + DCDGEN(4, IOMUXC_BASE_ADDR + 0x88c, 0x00000001) @ (Bit0 SRE D[16..23]) GRP_SR_B2 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x890, 0x00000080) @ (Bit7 PKE A[0..14] CAS RAS SDBA[0..1]) GRP_PKEADDR + DCDGEN(4, IOMUXC_BASE_ADDR + 0x89c, 0x00000001) @ (Bit0 SRE D[24..31]) GRP_SR_B4 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x8a0, 0x00000000) @ (Bit9 DDR_INPUT D[0..31] DQM[0..3]) GRP_INMODE1 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x8a4, 0x00000000) @ (Bit[1..2] DSE D[0..7]) GRP_DRAM_B0 DFT: 0x4 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x8ac, 0x00000000) @ (Bit[1..2] DSE D[8..15]) GRP_DRAM_B1 DFT: 0x4 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x8b0, 0x00000001) @ (Bit0 SRE A[0..7]) GRP_SR_A0 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x8b8, 0x00000000) @ (Bit[1..2] DSE D[16..23]) GRP_DRAM_B2 DFT: 0x4 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x8bc, 0x00000001) @ (Bit0 SRE A[8..14] SDBA[0..2]) GRP_SR_A1 + + DCDGEN(4, IOMUXC_BASE_ADDR + 0x4e4, 0x2000) @ NANDF_WE_B + DCDGEN(4, IOMUXC_BASE_ADDR + 0x4e8, 0x2000) @ NANDF_RE_B + DCDGEN(4, IOMUXC_BASE_ADDR + 0x4ec, 0x2000) @ NANDF_ALE + DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f0, 0x2000) @ NANDF_CLE + DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f4, 0x2000) @ NANDF_WP_B + DCDGEN(4, IOMUXC_BASE_ADDR + 0x4f8, 0x2000) @ NANDF_RB0 + + DCDGEN(4, IOMUXC_BASE_ADDR + 0x518, 0x0084) @ NANDF_CS0 + + DCDGEN(4, IOMUXC_BASE_ADDR + 0x538, 0x20e0) @ NANDF_RDY_INT + + DCDGEN(4, IOMUXC_BASE_ADDR + 0x55c, 0x20a4) @ NANDF_D7 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x560, 0x20a4) @ NANDF_D6 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x564, 0x20a4) @ NANDF_D5 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x568, 0x20a4) @ NANDF_D4 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x56c, 0x20a4) @ NANDF_D3 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x570, 0x20a4) @ NANDF_D2 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x574, 0x20a4) @ NANDF_D1 + DCDGEN(4, IOMUXC_BASE_ADDR + 0x578, 0x20a4) @ NANDF_D0 dcd_end: image_len: .long REDBOOT_IMAGE_SIZE @@ -651,12 +703,12 @@ M4IF_FBPM0_VAL: .word 0x00000103 M4IF_M4IF4_VAL: .word 0x00230185 M4IF_FPWC_VAL: .word 0x00240126 MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET -CCM_CBCDR_VAL1: .word 0x19239145 -CCM_CBCDR_VAL2: .word 0x13239145 +CCM_CBCDR_VAL1: .word 0x19235145 +CCM_CBCDR_VAL2: .word 0x13235145 #if (CPU_CLK % SDRAM_CLK == 0) -CCM_CBCDR_VAL3: .word (((CPU_CLK + SDRAM_CLK - 1) / SDRAM_CLK - 1) << 27) | (1 << 30) | 0x01e39100 +CCM_CBCDR_VAL3: .word (((CPU_CLK + SDRAM_CLK - 1) / SDRAM_CLK - 1) << 27) | (1 << 30) | 0x01e35100 #else -CCM_CBCDR_VAL3: .word 0x01e39100 +CCM_CBCDR_VAL3: .word 0x01e35100 #endif #if 0