From 6ff3279564aa8ebd0fbb9254f7d13fd3a01737d2 Mon Sep 17 00:00:00 2001 From: Oliver Wendt Date: Wed, 4 Sep 2013 15:40:13 +0200 Subject: [PATCH] TX27: - workaround for MPLL restart problem in i.MX27 date code 1230 and newer (see /Documentation/TX27PCN2012-09.pdf). - wait after enabling wdt clock in HAL_PLATFORM_RESET() to prevent possible hang in 'reset' command. - fix trampoline code change for archs that use the default CYGARC_HAL_MMU_OFF macro. --- ReleaseNotes.txt | 10 ++ config/TX27-40x0.ecc | 4 +- config/TX27-40x1.ecc | 4 +- .../arm/arch/v2_0/src/redboot_linux_exec.c | 3 +- .../arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl | 2 +- .../karo/v1_0/include/hal_platform_setup.h | 155 +++++++++++------- .../hal/arm/mx27/var/v2_0/include/hal_soc.h | 46 ++++-- .../arm/mx27/var/v2_0/include/hal_var_ints.h | 125 +++++++------- 8 files changed, 205 insertions(+), 144 deletions(-) diff --git a/ReleaseNotes.txt b/ReleaseNotes.txt index cb6b0637..4d9c2874 100755 --- a/ReleaseNotes.txt +++ b/ReleaseNotes.txt @@ -2,6 +2,16 @@ Ka-Ro Electronics GmbH =========================================================== + v1.5.5 (2012-09-25) + Changes: + TX27: + - workaround for MPLL restart problem in i.MX27 date code 1230 + and newer (see /Documentation/TX27PCN2012-09.pdf). + - wait after enabling wdt clock in HAL_PLATFORM_RESET() to + prevent possible hang in 'reset' command. + - fix trampoline code change for archs that use the default + CYGARC_HAL_MMU_OFF macro. + v1.5.4 (2012-09-03) Fixup messed up source code from previous release diff --git a/config/TX27-40x0.ecc b/config/TX27-40x0.ecc index acbbb8c9..0715ffb6 100644 --- a/config/TX27-40x0.ecc +++ b/config/TX27-40x0.ecc @@ -3505,9 +3505,7 @@ cdl_option CYGOPT_HAL_ARM_TX27_DEBUG { # No user value, uncomment the following line to provide one. # user_value 0 # value_source default - # Default value: false - # false (unknown) == 0 - # --> 0 + # Default value: 0 }; # Additional compiler flags diff --git a/config/TX27-40x1.ecc b/config/TX27-40x1.ecc index 6484fbbd..fdc18211 100644 --- a/config/TX27-40x1.ecc +++ b/config/TX27-40x1.ecc @@ -3504,9 +3504,7 @@ cdl_option CYGOPT_HAL_ARM_TX27_DEBUG { # No user value, uncomment the following line to provide one. # user_value 0 # value_source default - # Default value: false - # false (unknown) == 0 - # --> 0 + # Default value: 0 }; # Additional compiler flags diff --git a/packages/hal/arm/arch/v2_0/src/redboot_linux_exec.c b/packages/hal/arm/arch/v2_0/src/redboot_linux_exec.c index b73aa49e..f3dcf09a 100644 --- a/packages/hal/arm/arch/v2_0/src/redboot_linux_exec.c +++ b/packages/hal/arm/arch/v2_0/src/redboot_linux_exec.c @@ -120,8 +120,7 @@ RedBoot_cmd("exec", #endif #define __CYGARC_SET_CTLREG(__paddr__) \ - " mcr p15,0,r0,c1,c0,0\n" \ - " mov pc," #__paddr__ "\n" + " mcr p15,0,r0,c1,c0,0\n" #define CYGARC_HAL_MMU_OFF(__paddr__) \ " mcr p15,0,r0,c7,c10,4\n" \ diff --git a/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl b/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl index b028bfd8..4bc54142 100644 --- a/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl +++ b/packages/hal/arm/mx27/karo/v1_0/cdl/hal_arm_tx27.cdl @@ -219,7 +219,7 @@ cdl_package CYGPKG_HAL_ARM_TX27KARO { cdl_option CYGOPT_HAL_ARM_TX27_DEBUG { display "Enable low level debugging with LED" flavor bool - default_value { false } + default_value { 0 } description " This option enables low level debugging by blink codes of the LED on STK5." diff --git a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h index 6e55447f..295e446c 100644 --- a/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h +++ b/packages/hal/arm/mx27/karo/v1_0/include/hal_platform_setup.h @@ -85,12 +85,10 @@ 111: subs r10, r10, #1 bmi 113f - ldr r9, =3600 + mov r9, #3600 112: subs r9, r9, #1 bne 112b - b 111b - .ltorg 113: .endm @@ -148,9 +146,26 @@ orr r9, r9, #(1 << 2) /* enable FPM */ str r9, [r10, #(SOC_CRM_CSCR - SOC_CRM_BASE)] + ldr r9, [r10, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)] + orr r9, r9, #(1 << 24) /* enable WDT clock */ + str r9, [r10, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)] + + /* Wait for clocks to be enabled */ + mov r10, #0x1000 +111: + subs r10, r10, #1 + bmi 113f + mov r9, #3600 +112: + subs r9, r9, #1 + bne 112b +113: ldr r10, WDOG_BASE - mov r9, #0 - str r9, [r10, #0] + /* enable watchdog timeout */ + mov r9, #0x0034 + strh r9, [r10, #0] + /* wait for watchdog to trigger */ + b . .endm // This macro represents the initial startup code for the platform // r11 is reserved to contain chip rev info in this file @@ -252,6 +267,8 @@ NAND_Boot_Start: LED_ON /* Jump to SDRAM */ bl jump_to_sdram +/* Code and all data used up to here must fit within the first 2KiB of FLASH ROM! */ +Now_in_SDRAM: LED_OFF NAND_Copy_Main: ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying @@ -266,7 +283,7 @@ NAND_Copy_Main: mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN) strh r3, [r4, #NAND_FLASH_CONFIG1_REG_OFF] - //unlock internal buffer + // unlock internal buffer mov r3, #0x2 strh r3, [r4, #0xA] @@ -326,9 +343,9 @@ Nfc_Read_Page: Skip_bad_block: #ifdef CYGOPT_HAL_ARM_TX27_DEBUG LED_BLINK #1 - b Skip_bad_block + b Skip_bad_block #endif - add r1, r1, #(TX27_NAND_BLKS_PER_PAGE*TX27_NAND_PAGE_SIZE) + add r1, r1, #(TX27_NAND_BLKS_PER_PAGE * TX27_NAND_PAGE_SIZE) b Nfc_Read_Page Copy_Good_Blk: @@ -350,54 +367,25 @@ Copy_Good_Blk: NAND_Copy_Main_done: Normal_Boot_Continue: -// bl jump_to_sdram -// Code and all data used up to here must fit within the first 2KiB of FLASH ROM! -#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */ - /* Copy image from flash to SDRAM first */ - ldr r0, =0xFFFFF000 - and r0, r0, pc - ldr r1, MXC_REDBOOT_RAM_START - cmp r0, r1 - beq HWInitialise_skip_SDRAM_copy - - add r2, r0, #REDBOOT_IMAGE_SIZE -1: - ldmia r0!, {r7-r14} - stmia r1!, {r7-r14} - cmp r0, r2 - ble 1b - - bl jump_to_sdram -Now_in_SDRAM: - LED_BLINK #3 -#endif /* CYG_HAL_STARTUP_ROMRAM */ - -HWInitialise_skip_SDRAM_copy: - LED_BLINK #2 - -init_cs0_sync_start: init_cs0_sync NAND_ClockSetup: - ldr r1, =(SOC_CRM_BASE) + ldr r1, SOC_CRM_BASE_W ldr r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)] bic r2, r2, #0x0200 orr r2, r2, #0x01C0 - ldr r1, =(SOC_CRM_BASE) str r2, [r1, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)] /* end of NAND clock divider setup */ // TLSbo76381: enable USB/PP/DMA burst override bits in GPCR - ldr r1, =(SOC_SYSCTRL_GPCR) + ldr r1, =SOC_SYSCTRL_GPCR ldr r2, [r1] orr r2, r2, #0x700 str r2, [r1] // Set up a stack [for calling C code] - ldr r1, =__startup_stack - ldr r2, =RAM_BANK0_BASE - orr sp, r1, r2 + ldr sp, =__startup_stack LED_ON // Create MMU tables @@ -423,9 +411,14 @@ NAND_ClockSetup: .macro init_clock ldr r0, SOC_CRM_BASE_W - // disable MPLL/SPLL first + // disable PLL update first ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] - bic r1, r1, #0x3 + orr r1, r1, #(1 << 31) +#ifdef PLL_REF_CLK_32768HZ + orr r1, r1, #(1 << 3) // disable OSC26M +#else + bic r1, r1, #(1 << 3) // enable 26MHz osc +#endif str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] // configure MPCTL0 @@ -436,27 +429,20 @@ NAND_ClockSetup: ldr r1, CRM_SPCTL0_VAL2_W str r1, [r0, #(SOC_CRM_SPCTL0 - SOC_CRM_BASE)] - ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] -#ifdef PLL_REF_CLK_32768HZ - // Make sure to use CKIL - bic r1, r1, #(3 << 16) -#else - orr r1, r1, #(3 << 16) // select 26MHz -#endif - orr r1, r1, #0x000C0000 // restart SPLL and MPLL - orr r1, r1, #0x00000003 // enable SPLL and MPLL + ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] + orr r1, r1, #(0x3 << 18) // SPLL_RESTART | MPLL_RESTART + orr r1, r1, #(0x3 << 0) // SPLL_ENABLE | MPLL_ENABLE str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] 1: ldr r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] - tst r1, #0x000C0000 + tst r1, #(0x3 << 18) // wait for SPLL/MPLL restart to clear bne 1b ldr r1, SOC_CRM_CSCR2_W str r1, [r0, #(SOC_CRM_CSCR - SOC_CRM_BASE)] // Set divider of H264_CLK to zero, NFC to 3. - ldr r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)] - bic r1, r1, #0x0000FC00 + ldr r1, SOC_CRM_PCDR0_W str r1, [r0, #(SOC_CRM_PCDR0 - SOC_CRM_BASE)] /* Configure PCDR1 */ @@ -470,11 +456,6 @@ NAND_ClockSetup: ldr r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)] orr r1, r1, #0x0780 str r1, [r0, #(SOC_CRM_PCCR1 - SOC_CRM_BASE)] - // make default CLKO to be FCLK - ldr r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)] - and r1, r1, #0xFFFFFFE0 - orr r1, r1, #0x7 - str r1, [r0, #(SOC_CRM_CCSR - SOC_CRM_BASE)] .endm //init_clock .macro init_cs0 @@ -782,8 +763,60 @@ SOC_MAX_MPR_VAL: .word 0x00302145 SOC_CRM_BASE_W: .word SOC_CRM_BASE CRM_MPCTL0_VAL2_W: .word CRM_MPCTL0_VAL2 CRM_SPCTL0_VAL2_W: .word CRM_SPCTL0_VAL2 -SOC_CRM_CSCR2_W: .word CRM_CSCR_VAL2 -SOC_CRM_PCDR1_W: .word 0x09030913 // p1=20 p2=10 p3=4 p4=10 + +#define AHBDIV (MPLL_REF_CLK_kHz * 2 / 3 / 1000 / CYGHWR_HAL_ARM_SOC_SYSTEM_CLOCK) + +#define CSCR_AHB_DIV(n) ((((n) & 3) - 1) << 8) +#define CSCR_ARM_DIV(n) ((((n) & 3) - 1) << 12) +#define CSCR_ARM_SRC(n) ((!!(n)) << 15) +#define CSCR_MCU_SEL(n) ((!!(n)) << 16) +#define CSCR_SP_SEL(n) ((!!(n)) << 17) +#define CSCR_USB_DIV(n) ((((n) & 7) - 1) << 28) + +#define MPLL_CLK_DIV(khz) ((MPLL_REF_CLK_kHz * 2 / 3 + (khz) - 1) / (khz) - 1) +#define MPLL_CLK_DIV2(khz) ((MPLL_REF_CLK_kHz * 4 / 3 + (khz) - 1) / (khz) - 4) +#define SPLL_CLK_DIV(khz) ((SPLL_REF_CLK_kHz + (khz) - 1) / (khz) - 1) +#define SPLL_CLK_DIV2(khz) ((SPLL_REF_CLK_kHz * 2 + (khz) - 1) / (khz) - 4) + +#define PCDR0_SSI2_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 26) +#define PCDR0_CLKO_DIV(n) ((((n) - 1) & 0x7) << 22) +#define PCDR0_SSI1_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 16) +#define PCDR0_H264_DIV(pll, n) ((pll##_CLK_DIV2(n) & 0x3f) << 10) +#define PCDR0_NFC_DIV(n) ((MPLL_CLK_DIV(n) & 0xf) << 6) +#define PCDR0_MSHC_DIV(pll, n) ((pll##_CLK_DIV(n) & 0x3f) << 0) +#define PCDR0_CLKO_EN (1 << 25) + +#define PCDR1_PER1_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 0) +#define PCDR1_PER2_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 8) +#define PCDR1_PER3_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 16) +#define PCDR1_PER4_DIV(n) ((MPLL##_CLK_DIV(n) & 0x3f) << 24) + +#ifndef PLL_REF_CLK_32768HZ +#define MPLL_SRC (1 << 16) +#define SPLL_SRC (1 << 17) +#define FPM_ENABLE (1 << 2) +#else +#define MPLL_SRC (0 << 16) +#define SPLL_SRC (0 << 17) +#define FPM_ENABLE (1 << 2) +#endif + +SOC_CRM_CSCR2_W: .word 0x03f00003 | \ + FPM_ENABLE | MPLL_SRC | SPLL_SRC | \ + CSCR_AHB_DIV(AHBDIV) | \ + CSCR_ARM_DIV(1) | \ + CSCR_USB_DIV(4) | \ + CSCR_ARM_SRC(MPLL_REF_CLK_kHz / 1000 == CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK) +SOC_CRM_PCDR0_W: .word PCDR0_SSI2_DIV(MPLL, 66500) | \ + PCDR0_CLKO_DIV(8) | PCDR0_CLKO_EN | \ + PCDR0_SSI1_DIV(MPLL, 66500) | \ + PCDR0_H264_DIV(MPLL, 133000) | \ + PCDR0_NFC_DIV(16625) | \ + PCDR0_MSHC_DIV(MPLL, 66500) +SOC_CRM_PCDR1_W: .word PCDR1_PER1_DIV(13300) | \ + PCDR1_PER2_DIV(26600) | \ + PCDR1_PER3_DIV(66500) | \ + PCDR1_PER4_DIV(26600) SOC_CRM_PCCR0_W: .word 0x3108480F SOC_CS4_CTL_BASE_W: .word SOC_CS4_CTL_BASE CS4_CSCRU_VAL: .word 0x0000DCF6 diff --git a/packages/hal/arm/mx27/var/v2_0/include/hal_soc.h b/packages/hal/arm/mx27/var/v2_0/include/hal_soc.h index b8d2725c..be43793f 100644 --- a/packages/hal/arm/mx27/var/v2_0/include/hal_soc.h +++ b/packages/hal/arm/mx27/var/v2_0/include/hal_soc.h @@ -149,14 +149,18 @@ extern char HAL_PLATFORM_EXTRA[20]; // PD MFD MFI MFN #define CRM_PLL_PCTL_PARAM(pd, fd, fi, fn) ((((pd)-1)<<26) + (((fd)-1)<<16) + ((fi)<<10) + (((fn) & 0x3ff) << 0)) + +#define SPLL_REF_CLK_kHz 240000 + #if (PLL_REF_CLK == FREQ_32768HZ) #define PLL_REF_CLK_32768HZ // SPCTL0 for 240 MHz #define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 124, 7, 19) #define CRM_SPCTL0_VAL_27MHZ CRM_SPCTL0_VAL - #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(2, 755, 11, -205) + #define CRM_SPCTL0_VAL2 CRM_PLL_PCTL_PARAM(4, 567, 14, 173) #define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL2 #if defined (CLOCK_266_133_66) + #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1500) #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 400, 7, 371) #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL #define CRM_CSCR_VAL 0x33F00307 @@ -164,6 +168,7 @@ extern char HAL_PLATFORM_EXTRA[20]; #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2 #define CRM_CSCR_VAL2 0x33F00107 #elif defined (CLOCK_399_133_66) + #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000) #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89) #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL #define CRM_CSCR_VAL 0x33F00507 @@ -171,6 +176,7 @@ extern char HAL_PLATFORM_EXTRA[20]; #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL2 #define CRM_CSCR_VAL2 0x33F08107 #elif defined (CLOCK_399_100_50) + #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000) #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 100, 11, 89) #define CRM_MPCTL0_VAL_27MHZ CRM_MPCTL0_VAL #define CRM_CSCR_VAL 0x33F00307 @@ -180,34 +186,48 @@ extern char HAL_PLATFORM_EXTRA[20]; #else #error This clock is not supported !!!! #endif // CLOCK_266_133_66 -#else +#else // PLL_REF_CLK == FREQ_32768HZ +#define PLL_VAL_239_999 CRM_PLL_PCTL_PARAM(2, 13, 9, 3) +#define PLL_VAL_240 CRM_PLL_PCTL_PARAM(3, 13, 13, 11) +#define PLL_VAL_265_999 CRM_PLL_PCTL_PARAM(2, 26, 10, 6) +#define PLL_VAL_266 CRM_PLL_PCTL_PARAM(3, 26, 15, 9) +#define PLL_VAL_399 CRM_PLL_PCTL_PARAM(1, 52, 7, 35) +#define PLL_VAL_399_ALT CRM_PLL_PCTL_PARAM(2, 26, 15, 9) +#define PLL_VAL_400 CRM_PLL_PCTL_PARAM(2, 13, 15, 5) +#define PLL_VAL_600 CRM_PLL_PCTL_PARAM(1, 13, 11, 7) +#define PLL_VAL_600_ALT CRM_PLL_PCTL_PARAM(1, 52, 11, 28) +#define PLL_VAL_598_5 CRM_PLL_PCTL_PARAM(1, 104, 11, 53) + // SPCTL0 for 240 MHz - #define CRM_SPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 13, 9, 3) + #define CRM_SPCTL0_VAL PLL_VAL_240 #define CRM_SPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 9, 8, 8) #define CRM_SPCTL0_VAL2 CRM_SPCTL0_VAL #define CRM_SPCTL0_VAL2_27MHZ CRM_SPCTL0_VAL_27MHZ #if defined (CLOCK_266_133_66) - #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(2, 26, 10, 6) - #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 15, 9, 13) // 266.4MHz + #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1500) + #define CRM_MPCTL0_VAL PLL_VAL_266 // 265.999 + #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(2, 15, 9, 13) // 266.4 MHz #define CRM_CSCR_VAL 0x33F30307 - #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 7, 35) - #define CRM_MPCTL0_VAL2_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz + #define CRM_MPCTL0_VAL2 PLL_VAL_399 + #define CRM_MPCTL0_VAL2_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6 MHz #define CRM_CSCR_VAL2 0x33F30107 #elif defined (CLOCK_399_133_66) - #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35) - #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz + #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000) + #define CRM_MPCTL0_VAL PLL_VAL_399 + #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6 MHz #define CRM_CSCR_VAL 0x33F30507 #define CRM_MPCTL0_VAL2 CRM_MPCTL0_VAL #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ #define CRM_CSCR_VAL2 0x33F38107 #elif defined (CLOCK_399_100_50) - #define CRM_MPCTL0_VAL CRM_PLL_PCTL_PARAM(1, 52, 7, 35) - #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6MHz + #define MPLL_REF_CLK_kHz (CYGHWR_HAL_ARM_SOC_PROCESSOR_CLOCK * 1000) + #define CRM_MPCTL0_VAL PLL_VAL_399 + #define CRM_MPCTL0_VAL_27MHZ CRM_PLL_PCTL_PARAM(1, 5, 7, 2) // 399.6 MHz #define CRM_CSCR_VAL 0x33F30307 - #define CRM_MPCTL0_VAL2 CRM_PLL_PCTL_PARAM(1, 52, 11, 28) + #define CRM_MPCTL0_VAL2 PLL_VAL_399 #define CRM_MPCTL0_VAL2_27MHZ CRM_MPCTL0_VAL_27MHZ - #define CRM_CSCR_VAL2 0x33F30307 + #define CRM_CSCR_VAL2 0x33F38307 #else #error This clock is not supported !!!! #endif // CLOCK_266_133_66 diff --git a/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h b/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h index c8191d3a..504d9f49 100644 --- a/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h +++ b/packages/hal/arm/mx27/var/v2_0/include/hal_var_ints.h @@ -41,87 +41,90 @@ //####ECOSGPLCOPYRIGHTEND#### //========================================================================== -#include // registers +#include // registers -#define CYGNUM_HAL_INTERRUPT_GPIO0 0 -#define CYGNUM_HAL_INTERRUPT_GPIO1 1 -#define CYGNUM_HAL_INTERRUPT_GPIO2 2 -#define CYGNUM_HAL_INTERRUPT_GPIO3 3 -#define CYGNUM_HAL_INTERRUPT_GPIO4 4 -#define CYGNUM_HAL_INTERRUPT_GPIO5 5 -#define CYGNUM_HAL_INTERRUPT_GPIO6 6 -#define CYGNUM_HAL_INTERRUPT_GPIO7 7 -#define CYGNUM_HAL_INTERRUPT_GPIO8 8 -#define CYGNUM_HAL_INTERRUPT_GPIO9 9 -#define CYGNUM_HAL_INTERRUPT_GPIO10 10 -#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly! -#define CYGNUM_HAL_INTERRUPT_LCD 12 -#define CYGNUM_HAL_INTERRUPT_UDC 13 -#define CYGNUM_HAL_INTERRUPT_UART1 15 -#define CYGNUM_HAL_INTERRUPT_UART2 16 -#define CYGNUM_HAL_INTERRUPT_UART3 17 -#define CYGNUM_HAL_INTERRUPT_UART4 17 -#define CYGNUM_HAL_INTERRUPT_MCP 18 -#define CYGNUM_HAL_INTERRUPT_SSP 19 -#define CYGNUM_HAL_INTERRUPT_TIMER0 26 -#define CYGNUM_HAL_INTERRUPT_TIMER1 27 -#define CYGNUM_HAL_INTERRUPT_TIMER2 28 -#define CYGNUM_HAL_INTERRUPT_TIMER3 29 -#define CYGNUM_HAL_INTERRUPT_HZ 30 -#define CYGNUM_HAL_INTERRUPT_ALARM 31 +#define CYGNUM_HAL_INTERRUPT_GPIO0 0 +#define CYGNUM_HAL_INTERRUPT_GPIO1 1 +#define CYGNUM_HAL_INTERRUPT_GPIO2 2 +#define CYGNUM_HAL_INTERRUPT_GPIO3 3 +#define CYGNUM_HAL_INTERRUPT_GPIO4 4 +#define CYGNUM_HAL_INTERRUPT_GPIO5 5 +#define CYGNUM_HAL_INTERRUPT_GPIO6 6 +#define CYGNUM_HAL_INTERRUPT_GPIO7 7 +#define CYGNUM_HAL_INTERRUPT_GPIO8 8 +#define CYGNUM_HAL_INTERRUPT_GPIO9 9 +#define CYGNUM_HAL_INTERRUPT_GPIO10 10 +#define CYGNUM_HAL_INTERRUPT_GPIO 11 // Don't use directly! +#define CYGNUM_HAL_INTERRUPT_LCD 12 +#define CYGNUM_HAL_INTERRUPT_UDC 13 +#define CYGNUM_HAL_INTERRUPT_UART1 15 +#define CYGNUM_HAL_INTERRUPT_UART2 16 +#define CYGNUM_HAL_INTERRUPT_UART3 17 +#define CYGNUM_HAL_INTERRUPT_UART4 17 +#define CYGNUM_HAL_INTERRUPT_MCP 18 +#define CYGNUM_HAL_INTERRUPT_SSP 19 +#define CYGNUM_HAL_INTERRUPT_TIMER0 26 +#define CYGNUM_HAL_INTERRUPT_TIMER1 27 +#define CYGNUM_HAL_INTERRUPT_TIMER2 28 +#define CYGNUM_HAL_INTERRUPT_TIMER3 29 +#define CYGNUM_HAL_INTERRUPT_HZ 30 +#define CYGNUM_HAL_INTERRUPT_ALARM 31 // GPIO bits 31..11 can generate interrupts as well, but they all // end up clumped into interrupt signal #11. Using the symbols // below allow for detection of these separately. -#define CYGNUM_HAL_INTERRUPT_GPIO11 (32+11) -#define CYGNUM_HAL_INTERRUPT_GPIO12 (32+12) -#define CYGNUM_HAL_INTERRUPT_GPIO13 (32+13) -#define CYGNUM_HAL_INTERRUPT_GPIO14 (32+14) -#define CYGNUM_HAL_INTERRUPT_GPIO15 (32+15) -#define CYGNUM_HAL_INTERRUPT_GPIO16 (32+16) -#define CYGNUM_HAL_INTERRUPT_GPIO17 (32+17) -#define CYGNUM_HAL_INTERRUPT_GPIO18 (32+18) -#define CYGNUM_HAL_INTERRUPT_GPIO19 (32+19) -#define CYGNUM_HAL_INTERRUPT_GPIO20 (32+20) -#define CYGNUM_HAL_INTERRUPT_GPIO21 (32+21) -#define CYGNUM_HAL_INTERRUPT_GPIO22 (32+22) -#define CYGNUM_HAL_INTERRUPT_GPIO23 (32+23) -#define CYGNUM_HAL_INTERRUPT_GPIO24 (32+24) -#define CYGNUM_HAL_INTERRUPT_GPIO25 (32+25) -#define CYGNUM_HAL_INTERRUPT_GPIO26 (32+26) -#define CYGNUM_HAL_INTERRUPT_GPIO27 (32+27) +#define CYGNUM_HAL_INTERRUPT_GPIO11 (32 + 11) +#define CYGNUM_HAL_INTERRUPT_GPIO12 (32 + 12) +#define CYGNUM_HAL_INTERRUPT_GPIO13 (32 + 13) +#define CYGNUM_HAL_INTERRUPT_GPIO14 (32 + 14) +#define CYGNUM_HAL_INTERRUPT_GPIO15 (32 + 15) +#define CYGNUM_HAL_INTERRUPT_GPIO16 (32 + 16) +#define CYGNUM_HAL_INTERRUPT_GPIO17 (32 + 17) +#define CYGNUM_HAL_INTERRUPT_GPIO18 (32 + 18) +#define CYGNUM_HAL_INTERRUPT_GPIO19 (32 + 19) +#define CYGNUM_HAL_INTERRUPT_GPIO20 (32 + 20) +#define CYGNUM_HAL_INTERRUPT_GPIO21 (32 + 21) +#define CYGNUM_HAL_INTERRUPT_GPIO22 (32 + 22) +#define CYGNUM_HAL_INTERRUPT_GPIO23 (32 + 23) +#define CYGNUM_HAL_INTERRUPT_GPIO24 (32 + 24) +#define CYGNUM_HAL_INTERRUPT_GPIO25 (32 + 25) +#define CYGNUM_HAL_INTERRUPT_GPIO26 (32 + 26) +#define CYGNUM_HAL_INTERRUPT_GPIO27 (32 + 27) -#define CYGNUM_HAL_INTERRUPT_NONE -1 +#define CYGNUM_HAL_ISR_MIN 0 +#define CYGNUM_HAL_ISR_MAX (27 + 32) -#define CYGNUM_HAL_ISR_MIN 0 -#define CYGNUM_HAL_ISR_MAX (27+32) - -#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX+1) +#define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX + 1) // The vector used by the Real time clock -#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 +#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER0 // The vector used by the Ethernet -#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0 +#define CYGNUM_HAL_INTERRUPT_ETH CYGNUM_HAL_INTERRUPT_GPIO0 // method for reading clock interrupt latency #ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY externC void hal_clock_latency(cyg_uint32 *); -# define HAL_CLOCK_LATENCY( _pvalue_ ) \ - hal_clock_latency( (cyg_uint32 *)(_pvalue_) ) +# define HAL_CLOCK_LATENCY( _pvalue_ ) \ + hal_clock_latency( (cyg_uint32 *)(_pvalue_) ) #endif //---------------------------------------------------------------------------- // Reset. -#define HAL_PLATFORM_RESET() \ - CYG_MACRO_START \ - *(volatile unsigned long *)SOC_CRM_PCCR1 |= 0x01000000; \ - *(volatile unsigned short *)SOC_WDOG_BASE = \ - (*(volatile unsigned short *)SOC_WDOG_BASE & ~(1 << 4)) | (1 << 2); \ - /* hang here forever if reset fails */ \ - while (1) { } \ - CYG_MACRO_END +#define HAL_PLATFORM_RESET() \ + CYG_MACRO_START \ + \ + /* Enable WDT clock */ \ + writel(readl(SOC_CRM_PCCR1) | (1 << 24), SOC_CRM_PCCR1); \ + /* Enable FPM */ \ + writel(readl(SOC_CRM_CSCR) | (1 << 2), SOC_CRM_CSCR); \ + HAL_DELAY_US(1000); \ + /* Assert Softreset */ \ + writew(readw(SOC_WDOG_BASE) & ~(1 << 4), SOC_WDOG_BASE); \ + /* hang here forever if reset fails */ \ + while (1) { } \ + CYG_MACRO_END // Fallback (never really used) #define HAL_PLATFORM_RESET_ENTRY 0x00000000 -- 2.39.2