From f678cb04fdc88b277d3569b16248ad2f856449d3 Mon Sep 17 00:00:00 2001 From: lothar Date: Mon, 16 Feb 2009 10:46:49 +0000 Subject: [PATCH] Initial revision --- .../arm/mx37/stk5/v1_0/cdl/hal_arm_tx37.cdl | 368 ++++++ .../stk5/v1_0/include/hal_platform_setup.h | 1098 +++++++++++++++++ .../arm/mx37/stk5/v1_0/include/karo_tx37.h | 124 ++ .../include/pkgconf/lo_mlt_arm_board_romram.h | 33 + .../pkgconf/lo_mlt_arm_board_romram.ldi | 31 + .../include/pkgconf/mlt_arm_board_romram.mlt | 14 + .../include/pkgconf/mlt_arm_tx37_romram.h | 27 + .../include/pkgconf/mlt_arm_tx37_romram.ldi | 33 + .../hal/arm/mx37/stk5/v1_0/include/plf_io.h | 69 ++ .../hal/arm/mx37/stk5/v1_0/include/plf_mmap.h | 65 + .../mx37/stk5/v1_0/misc/redboot_ROMRAM.ecm | 229 ++++ .../hal/arm/mx37/stk5/v1_0/src/redboot_cmds.c | 279 +++++ .../hal/arm/mx37/stk5/v1_0/src/tx37_diag.c | 378 ++++++ .../hal/arm/mx37/stk5/v1_0/src/tx37_misc.c | 487 ++++++++ 14 files changed, 3235 insertions(+) create mode 100644 packages/hal/arm/mx37/stk5/v1_0/cdl/hal_arm_tx37.cdl create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/hal_platform_setup.h create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/karo_tx37.h create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.h create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.ldi create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_board_romram.mlt create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.h create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.ldi create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/plf_io.h create mode 100644 packages/hal/arm/mx37/stk5/v1_0/include/plf_mmap.h create mode 100644 packages/hal/arm/mx37/stk5/v1_0/misc/redboot_ROMRAM.ecm create mode 100644 packages/hal/arm/mx37/stk5/v1_0/src/redboot_cmds.c create mode 100644 packages/hal/arm/mx37/stk5/v1_0/src/tx37_diag.c create mode 100644 packages/hal/arm/mx37/stk5/v1_0/src/tx37_misc.c diff --git a/packages/hal/arm/mx37/stk5/v1_0/cdl/hal_arm_tx37.cdl b/packages/hal/arm/mx37/stk5/v1_0/cdl/hal_arm_tx37.cdl new file mode 100644 index 00000000..1d894114 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/cdl/hal_arm_tx37.cdl @@ -0,0 +1,368 @@ +# ==================================================================== +# +# hal_arm_board.cdl +# +# ==================================================================== +#####ECOSGPLCOPYRIGHTBEGIN#### +## ------------------------------------------- +## This file is part of eCos, the Embedded Configurable Operating System. +## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +## +## eCos is free software; you can redistribute it and/or modify it under +## the terms of the GNU General Public License as published by the Free +## Software Foundation; either version 2 or (at your option) any later version. +## +## eCos is distributed in the hope that it will be useful, but WITHOUT ANY +## WARRANTY; without even the implied warranty of MERCHANTABILITY or +## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +## for more details. +## +## You should have received a copy of the GNU General Public License along +## with eCos; if not, write to the Free Software Foundation, Inc., +## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +## +## As a special exception, if other files instantiate templates or use macros +## or inline functions from this file, or you compile this file and link it +## with other works to produce a work based on this file, this file does not +## by itself cause the resulting work to be covered by the GNU General Public +## License. However the source code for this file must still be made available +## in accordance with section (3) of the GNU General Public License. +## +## This exception does not invalidate any other reasons why a work based on +## this file might be covered by the GNU General Public License. +## +## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +## at http://sources.redhat.com/ecos/ecos-license/ +## ------------------------------------------- +#####ECOSGPLCOPYRIGHTEND#### + +cdl_package CYGPKG_HAL_ARM_MX37_STK5 { + display "KaRo electronics board" + parent CYGPKG_HAL_ARM_MX37 + hardware + include_dir cyg/hal + define_header hal_arm_board.h + description " + This HAL platform package provides generic + support for the Ka-Ro TX37 module on a STK5 base board." + + compile tx37_misc.c tx37_diag.c + implements CYGINT_HAL_DEBUG_GDB_STUBS + implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK + implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT + + #implements CYGHWR_HAL_ARM_DUART_UARTB + implements CYGHWR_HAL_ARM_SOC_UART1 + #implements CYGHWR_HAL_ARM_SOC_UART2 + #implements CYGHWR_HAL_ARM_SOC_UART3 + + define_proc { + puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H " + puts $::cdl_system_header "#define CYGBLD_HAL_VARIANT_H " + puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H " + puts $::cdl_header "#define HAL_PLATFORM_CPU \"Freescale i.MX37 based\"" + puts $::cdl_header "#define HAL_PLATFORM_BOARD \"TX37\"" + puts $::cdl_header "#define HAL_PLATFORM_MACHINE_TYPE 1575" + puts $::cdl_header "#define HAL_ARCH_PROGRAM_NEW_STACK board_program_new_stack" + } + + cdl_component CYG_HAL_STARTUP { + display "Startup type" + flavor data + default_value {"ROM"} + legal_values {"RAM" "ROM" "ROMRAM"} + no_define + define -file system.h CYG_HAL_STARTUP + description " + When targetting the eval board it is possible to build + the system for either RAM bootstrap or ROM bootstrap(s). Select + 'ram' when building programs to load into RAM using eCos GDB + stubs. Select 'rom' when building a stand-alone application + which will be put into ROM, or for the special case of + building the eCos GDB stubs themselves. Using ROMRAM will allow + the program to exist in ROM, but be copied to RAM during startup." + } + + cdl_interface CYGHWR_HAL_ARM_DUART_UARTA { + display "ST16552 UARTA available as diagnostic/debug channel" + description " + The board has a ST16552 DUART chip. This + interface allows a platform to indicate that the specified + serial port can be used as a diagnostic and/or debug channel." + } + + cdl_interface CYGHWR_HAL_ARM_DUART_UARTB { + display "ST16552 UARTB available as diagnostic/debug channel" + description " + The board has a ST16552 DUART chip. This + interface allows a platform to indicate that the specified + serial port can be used as a diagnostic and/or debug channel." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD { + display "Diagnostic serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option selects the baud rate used for the console port. + Note: this should match the value chosen for the GDB port if the + console and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_BAUD { + display "GDB serial port baud rate" + flavor data + legal_values 9600 19200 38400 57600 115200 + default_value 115200 + description " + This option selects the baud rate used for the GDB port. + Note: this should match the value chosen for the console port if the + console and GDB port are the same." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS { + display "Number of communication channels on the board" + flavor data + calculated 3 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL { + display "Debug serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value 0 + description " + The board has three serial ports. This option + chooses which port will be used to connect to a host + running GDB." + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT { + display "Default console channel." + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + calculated 0 + } + + cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL { + display "Console serial port" + active_if CYGPRI_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_CONFIGURABLE + flavor data + legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1 + default_value CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT + description " + The board has only three serial ports. This option + chooses which port will be used for console output." + } + + cdl_component CYGBLD_GLOBAL_OPTIONS { + display "Global build options" + flavor none + no_define + description " + Global build options including control over + compiler flags, linker flags and choice of toolchain." + + + parent CYGPKG_NONE + + cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX { + display "Global command prefix" + flavor data + no_define + default_value { "arm-elf" } + description " + This option specifies the command prefix used when + invoking the build tools." + } + + cdl_option CYGBLD_GLOBAL_CFLAGS { + display "Global compiler flags" + flavor data + no_define + default_value { "-mcpu=arm9 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-builtin -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" } + description " + This option controls the global compiler flags which are used to + compile all packages by default. Individual packages may define + options which override these global flags." + } + + cdl_option CYGBLD_GLOBAL_LDFLAGS { + display "Global linker flags" + flavor data + no_define + default_value { "-Wl,--gc-sections -Wl,-static -g -O2 -nostdlib" } + description " + This option controls the global linker flags. Individual + packages may define options which override these global flags." + } + + cdl_option CYGBLD_BUILD_GDB_STUBS { + display "Build GDB stub ROM image" + default_value 0 + requires { CYG_HAL_STARTUP == "ROM" } + requires CYGSEM_HAL_ROM_MONITOR + requires CYGBLD_BUILD_COMMON_GDB_STUBS + requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + requires CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + requires CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT + requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT + requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM + no_define + description " + This option enables the building of the GDB stubs for the + board. The common HAL controls takes care of most of the + build process, but the final conversion from ELF image to + binary data is handled by the platform CDL, allowing + relocation of the data if necessary." + + make -priority 320 { + /bin/gdb_module.bin : /bin/gdb_module.img + $(OBJCOPY) --remove-section=.fixed_vectors -O binary $< $@ + } + } + } + + cdl_component CYGPKG_HAL_ARM_BOARD_OPTIONS { + display "Ka-Ro TX37 Board build options" + flavor none + no_define + description " + Package specific build options including control over + compiler flags used only in building this package, + and details of which tests are built." + + cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_ADD { + display "Additional compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the board HAL. These flags are used in addition + to the set of global flags." + } + + cdl_option CYGPKG_HAL_ARM_BOARD_CFLAGS_REMOVE { + display "Suppressed compiler flags" + flavor data + no_define + default_value { "" } + description " + This option modifies the set of compiler flags for + building the board HAL. These flags are removed from + the set of global flags if present." + } + + } + + cdl_component CYGHWR_MEMORY_LAYOUT { + display "Memory layout" + flavor data + no_define + calculated { (CYG_HAL_STARTUP == "RAM") ? "arm_board_ram" : + (CYG_HAL_STARTUP == "ROMRAM") ? "arm_board_romram" : + "arm_board_rom" } + + cdl_option CYGHWR_MEMORY_LAYOUT_LDI { + display "Memory layout linker script fragment" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_LDI + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + + cdl_option CYGHWR_MEMORY_LAYOUT_H { + display "Memory layout header file" + flavor data + no_define + define -file system.h CYGHWR_MEMORY_LAYOUT_H + calculated { (CYG_HAL_STARTUP == "RAM") ? "" : + (CYG_HAL_STARTUP == "ROMRAM") ? "" : + "" } + } + } + + cdl_option CYGSEM_HAL_ROM_MONITOR { + display "Behave as a ROM monitor" + flavor bool + default_value 0 + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "ROM" || CYG_HAL_STARTUP == "ROMRAM" } + description " + Enable this option if this program is to be used as a ROM monitor, + i.e. applications will be loaded into RAM on the board, and this + ROM monitor may process exceptions or interrupts generated from the + application. This enables features such as utilizing a separate + interrupt stack when exceptions are generated." + } + + cdl_option CYGSEM_HAL_USE_ROM_MONITOR { + display "Work with a ROM monitor" + flavor booldata + legal_values { "Generic" "GDB_stubs" } + default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 } + parent CYGPKG_HAL_ROM_MONITOR + requires { CYG_HAL_STARTUP == "RAM" } + description " + Support can be enabled for different varieties of ROM monitor. + This support changes various eCos semantics such as the encoding + of diagnostic output, or the overriding of hardware interrupt + vectors. + Firstly there is \"Generic\" support which prevents the HAL + from overriding the hardware vectors that it does not use, to + instead allow an installed ROM monitor to handle them. This is + the most basic support which is likely to be common to most + implementations of ROM monitor. + \"GDB_stubs\" provides support when GDB stubs are included in + the ROM monitor or boot ROM." + } + + cdl_component CYGPKG_REDBOOT_HAL_OPTIONS { + display "Redboot HAL options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + description " + This option lists the target's requirements for a valid Redboot + configuration." + + compile -library=libextras.a redboot_cmds.c + + cdl_option CYGBLD_BUILD_REDBOOT_BIN { + display "Build Redboot ROM binary image" + active_if CYGBLD_BUILD_REDBOOT + default_value 1 + no_define + description "This option enables the conversion of the Redboot ELF + image to a binary image suitable for ROM programming." + + make -priority 325 { + /bin/redboot.bin : /bin/redboot.elf + $(OBJCOPY) --strip-debug $< $(@:.bin=.img) + $(OBJCOPY) -O srec $< $(@:.bin=.srec) + $(OBJCOPY) -O binary $< $@ + $(COMMAND_PREFIX)nm $< | awk 'NF == 3 {print}' | sort > $(<:.elf=.map) + } + } + } + + cdl_component CYGPKG_REDBOOT_HAL_BOARD_OPTIONS { + display "Redboot HAL variant options" + flavor none + no_define + parent CYGPKG_REDBOOT + active_if CYGPKG_REDBOOT + + # RedBoot details + requires { CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT == 0x40008000 } + define_proc { + puts $::cdl_header "#define CYGHWR_REDBOOT_ARM_TRAMPOLINE_ADDRESS 0x00001f00" + } + } +} diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/hal_platform_setup.h b/packages/hal/arm/mx37/stk5/v1_0/include/hal_platform_setup.h new file mode 100644 index 00000000..e6a98e38 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/hal_platform_setup.h @@ -0,0 +1,1098 @@ +#ifndef CYGONCE_HAL_PLATFORM_SETUP_H +#define CYGONCE_HAL_PLATFORM_SETUP_H + +//============================================================================= +// +// hal_platform_setup.h +// +// Platform specific support for HAL (assembly code) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== + +#include // System-wide configuration info +#include CYGBLD_HAL_VARIANT_H // Variant specific configuration +#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration +#include // Variant specific hardware definitions +#include // MMU definitions +#include // Platform specific hardware definitions + +#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#define PLATFORM_SETUP1 _platform_setup1 +#define CYGHWR_HAL_ARM_HAS_MMU + +#ifdef CYG_HAL_STARTUP_ROMRAM +#define CYGSEM_HAL_ROM_RESET_USES_JUMP +#endif + +//#define NFC_2K_BI_SWAP +#define SDRAM_FULL_PAGE_BIT 0x100 +#define SDRAM_FULL_PAGE_MODE 0x37 +#define SDRAM_BURST_MODE 0x33 + +#define CYGHWR_HAL_ROM_VADDR 0x0 + +#if 0 +#define UNALIGNED_ACCESS_ENABLE +#define SET_T_BIT_DISABLE +#define BRANCH_PREDICTION_ENABLE +#endif + + +#define TX37_NAND_PAGE_SIZE 2048 +#define TX37_NAND_BLKS_PER_PAGE 64 + +#define TX37_DEBUG + +#ifndef TX37_DEBUG +#define LED_ON +#define LED_OFF + .macro LED_CTRL,val + .endm + .macro LED_BLINK,val + .endm +#define DELAY +#else +#define CYGHWR_LED_MACRO LED_BLINK #\x +#define LED_ON bl led_on +#define LED_OFF bl led_off + .macro DELAY,ms + ldr r10, =\ms +111: + subs r10, r10, #1 + bmi 113f + ldr r9, =3000 +112: + subs r9, r9, #1 + bne 112b + b 111b + .ltorg +113: + .endm + + .macro LED_CTRL,val + // switch user LED (PF13) on STK5 + ldr r10, GPIO2_BASE_ADDR_W + mov r9, #\val + cmp r9, #0 + movne r9, #(1 << 19) // LED ON + moveq r9, #0 // LED OFF + str r9, [r10, #0x00] @ GPIO_DR + .endm + + .macro LED_BLINK,val + mov r2, \val +211: + subs r2, r2, #1 + bmi 212f + LED_CTRL 1 + DELAY 200 + LED_CTRL 0 + DELAY 300 + b 211b +212: + DELAY 1000 + .endm +#endif + + .macro LED_INIT + // initialize GPIO2[19] for LED on STK5 + ldr r10, IOMUXC_BASE_ADDR_W + @ AUD5_RXC = ALT4 (GPIO2[19]) + mov r9, #4 + str r9, [r10, #0x120] + ldr r10, GPIO2_BASE_ADDR_W + + mov r9, #(1 << 19) + str r9, [r10, #0x00] @ GPIO_DR + + mov r9, #(1 << 19) + str r9, [r10, #0x04] @ GPIO_GDIR + .endm + +//#define ENABLE_IMPRECISE_ABORT + +/* +#define PLATFORM_PREAMBLE flash_header + +//flash header & DCD @ 0x400 +.macro flash_header + b reset_vector +.org 0x400 +app_code_jump_v: .long reset_vector +app_code_barker: .long 0xB1 +app_code_csf: .long 0 +dcd_ptr_ptr: .long dcd_ptr +super_root_key: .long 0 +dcd_ptr: .long dcd_data +app_dest_ptr: .long CYGMEM_REGION_rom - REDBOOT_OFFSET + +dcd_data: .long 0xB17219E9 +dcd_len: .long (49 * 12) + +//DCD +//iomux 1 +// KEY_ROW0 -> EMI_DRAM_D[16] +.long 4 +.long 0xc3fa8008 +.long 0x1 +// 2 +// KEY_ROW1 -> EMI_DRAM_D[17] +.long 4 +.long 0xc3fa800c +.long 0x1 +// 3 +// KEY_ROW2 -> EMI_DRAM_D[18] +.long 4 +.long 0xc3fa8010 +.long 0x1 +// 4 +// KEY_ROW3 -> EMI_DRAM_D[19] +.long 4 +.long 0xc3fa8014 +.long 0x1 +//5 +// KEY_ROW4 -> EMI_DRAM_D[20] +.long 4 +.long 0xc3fa8018 +.long 0x1 +//6 +// KEY_ROW5 -> EMI_DRAM_D[21] +.long 4 +.long 0xc3fa801c +.long 0x1 +// 7 +// KEY_ROW6 -> EMI_DRAM_D[22] +.long 4 +.long 0xc3fa8020 +.long 0x1 +// 8 +// KEY_ROW7 -> EMI_DRAM_D[23] +.long 4 +.long 0xc3fa8024 +.long 0x1 +// 9 +// KEY_ROW7 +// IETM_D0 -> EMI_DRAM_D[24] +.long 4 +.long 0xc3fa8028 +.long 0x1 + +//10 +// IETM_D1 -> EMI_DRAM_D[25] +.long 4 +.long 0xc3fa802c +.long 0x1 + +// 11 +// IETM_D2 -> EMI_DRAM_D[26] +.long 4 +.long 0xc3fa8030 +.long 0x1 + +// 12 +// IETM_D3 -> EMI_DRAM_D[27] +.long 4 +.long 0xc3fa8034 +.long 0x1 + +// 13 +// IETM_D4 -> EMI_DRAM_D[28] +.long 4 +.long 0xc3fa8038 +.long 0x1 + +// 14 +// IETM_D5 -> EMI_DRAM_D[29] +.long 4 +.long 0xc3fa803c +.long 0x1 + +// 15 +// IETM_D6 -> EMI_DRAM_D[30] +.long 4 +.long 0xc3fa8040 +.long 0x1 + +// 16 +// IETM_D7 -> EMI_DRAM_D[31] +.long 4 +.long 0xc3fa8044 +.long 0x1 + +// 17 +// EIM_EB0 -> DRAM_DQM[2] +.long 4 +.long 0xc3fa8048 +.long 0x1 + +// 18 +// EIM_EB1 -> DRAM_DQM[3] +.long 4 +.long 0xc3fa804c +.long 0x1 + +// 19 +// EIM_ECB -> DRAM_SDQS[2] +.long 4 +.long 0xc3fa805c +.long 0x1 + +// 20 +// SW_PAD_CTL_PAD_EIM_ECB -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength +.long 4 +.long 0xc3fa82bc +.long 0x02c4 + +// 21 +// EIM_LBA -> DRAM_SDQS[3] +.long 4 +.long 0xc3fa8060 +.long 0x1 + +// 22 +// SW_PAD_CTL_PAD_EIM_LBA -> DDR input type / Pull/Keeper Enabled / Pull / 100KOhm Pull Down / High Drive Strength +.long 4 +.long 0xc3fa82c0 +.long 0x02c4 + +// 23 +// SW_PAD_CTL_GRP_S7 -> Medium Drive Strength +.long 4 +.long 0xc3fa84a8 +.long 0x2 + +// 24 +// SW_PAD_CTL_GRP_S8 -> Medium Drive Strength +.long 4 +.long 0xc3fa84b0 +.long 0x2 + +// 25 +// SW_PAD_CTL_GRP_S9 -> Medium Drive Strength +.long 4 +.long 0xc3fa84b4 +.long 0x2 + +// 26 +// SW_PAD_CTL_GRP_S10 -> Medium Drive Strength +.long 4 +.long 0xc3fa84e0 +.long 0x2 + +// 27 +// SW_PAD_CTL_PAD_DRAM_DQM0 -> Medium Drive Strength +.long 4 +.long 0xc3fa8278 +.long 0x2 + +// 28 +// SW_PAD_CTL_PAD_DRAM_DQM1 -> Medium Drive Strength +.long 4 +.long 0xc3fa827c +.long 0x2 + +// 29 +// DRAM_SDQS0 -> Medium Drive Strength +.long 4 +.long 0xc3fa8298 +.long 0x2 + +// 30 +// DRAM_SDQS1 -> Medium Drive Strength +.long 4 +.long 0xc3fa829c +.long 0x2 + +// 31 +// SW_PAD_CTL_GRP_S3 -> Medium Drive Strength +.long 4 +.long 0xc3fa84fc +.long 0x2 + +// 32 +// SW_PAD_CTL_GRP_S4 -> Medium Drive Strength +.long 4 +.long 0xc3fa8504 +.long 0x2 + +// 33 +// SW_PAD_CTL_GRP_S5 -> Medium Drive Strength +.long 4 +.long 0xc3fa848c +.long 0x2 + +// 34 +// SW_PAD_CTL_GRP_S6 -> Medium Drive Strength +.long 4 +.long 0xc3fa849c +.long 0x2 + +// 35 +// DRAM_SDCLK -> Medium Drive Strength +.long 4 +.long 0xc3fa8294 +.long 0x2 + +// 36 +// SW_PAD_CTL_PAD_DRAM_RAS -> Medium Drive Strength +.long 4 +.long 0xc3fa8280 +.long 0x2 + +// 37 +// SW_PAD_CTL_PAD_DRAM_CAS -> Medium Drive Strength +.long 4 +.long 0xc3fa8284 +.long 0x2 + +// 38 +// SW_PAD_CTL_PAD_DRAM_SDWE -> Medium Drive Strength +.long 4 +.long 0xc3fa8288 +.long 0x2 + +// 39 +// SW_PAD_CTL_PAD_DRAM_SDCKE0 -> Medium Drive Strength +.long 4 +.long 0xc3fa828c +.long 0x2 + +// 40 +// SW_PAD_CTL_PAD_DRAM_SDCKE1 -> Medium Drive Strength +.long 4 +.long 0xc3fa8290 +.long 0x2 + +// set CSD0 1 +// 41 +.long 4 +.long 0xe3fd9000 +.long 0x80000000 + +// Precharge command 2 +// 42 +.long 4 +.long 0xe3fd9014 +.long 0x04008008 +// refresh commands 3 +// 43 +.long 4 +.long 0xe3fd9014 +.long 0x00008010 + +// 44 +.long 4 +.long 0xe3fd9014 +.long 0x00008010 +// LMR with CAS=3 BL=3 5 +// 45 +.long 4 +.long 0xe3fd9014 +.long 0x00338018 + +// 13row 9 col 32 bit sref=4 micro model 6 +// 46 +.long 4 +.long 0xe3fd9000 +.long 0xB2120000 + +// timing parameter 7 +// 47 +.long 4 +.long 0xe3fd9004 +.long 0x70395729 + +// mddr enable RLAT=2 8 +// 48 +.long 4 +.long 0xe3fd9010 +.long 0x000A0084 + +// Normal mode 9 +// 49 +.long 4 +.long 0xe3fd9014 +.long 0x00000000 + +image_len: .long REDBOOT_IMAGE_SIZE +.endm +*/ + +// This macro represents the initial startup code for the platform + .macro _platform_setup1 +KARO_TX32_SETUP_START: +/* + * ARM1136 init + * - invalidate I/D cache/TLB and drain write buffer; + * - invalidate L2 cache + * - unaligned access + * - branch predictions + */ + // mrc p15, 0, r0, c1, c1, 0 // Read Secure Configuration Register data. Why doesn't work??? + // mcr p15, 0, , c1, c1, 0 ; Write Secure Configuration Register data +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr // save old spsr + mrs r0, cpsr // read out the cpsr + bic r0, r0, #0x100 // clear the A bit + msr spsr, r0 // update spsr + add lr, pc, #0x8 // update lr + movs pc, lr // update cpsr + nop + nop + nop + nop + msr spsr, r1 // restore old spsr +#endif + mov r0, #0 + mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */ + mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */ + mcr 15, 0, r0, c7, c10, 4 /* Data write barrier */ + + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 +#if 0 + /* Reload data from spare area to 0x400 of main area if booting from NAND */ + ldr r0, NFC_BASE_W + cmp pc, r0 + blo 1f + cmp pc, r1 + bhi 1f +#ifdef BARKER_CODE_SWAP_LOC +#if BARKER_CODE_SWAP_LOC != 0x404 +#error FIXME: the following depends on barker code to be 0x404 +#endif + // Recover the word at 0x404 offset using the one stored in the spare area 0 + add r1, r0, #0x400 + add r1, r1, #0x4 + mov r3, #0x1000 + ldr r2, [r0, r3] + str r2, [r1] +#endif +1: +#endif +#ifdef L2CC_ENABLED + /*** L2 Cache setup/invalidation/disable ***/ + /* Disable L2 cache first */ + mov r0, #L2CC_BASE_ADDR + mov r2, #0 + str r2, [r0, #L2_CACHE_CTL_REG] + /* + * Configure L2 Cache: + * - 128k size(16k way) + * - 8-way associativity + * - 0 ws TAG/VALID/DIRTY + * - 4 ws DATA R/W + */ + mov r2, #0xFF000000 + add r2, r2, #0x00F00000 + ldr r1, [r0, #L2_CACHE_AUX_CTL_REG] + and r1, r1, r2 + ldr r2, L2CACHE_PARAM + orr r1, r1, r2 + str r1, [r0, #L2_CACHE_AUX_CTL_REG] + + /* Invalidate L2 */ + mov r1, #0xFF + str r1, [r0, #L2_CACHE_INV_WAY_REG] +L2_loop: + /* Poll Invalidate By Way register */ + ldr r2, [r0, #L2_CACHE_INV_WAY_REG] + ands r2, r2, #0xFF + bne L2_loop + /*** End of L2 operations ***/ +#endif + +/* + * End of ARM1136 init + */ +init_spba_start: + init_spba +init_aips_start: + init_aips +init_max_start: + init_max +init_m4if_start: + init_m4if +init_iomux_start: + init_iomux + + LED_INIT + LED_CTRL 1 + + // disable wdog + ldr r0, =0x30 + ldr r1, WDOG1_BASE_W + strh r0, [r1] + + /* If SDRAM has been setup, bypass clock/WEIM setup */ + cmp pc, #SDRAM_BASE_ADDR + blo external_boot_cont + cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE) + blo internal_boot_cont + +external_boot_cont: +init_sdram_start: + setup_sdram + +internal_boot_cont: +init_clock_start: + init_clock + +HWInitialise_skip_SDRAM_setup: + ldr r0, NFC_BASE_W + add r2, r0, #0x1000 // 4K window + cmp pc, r0 + blo Normal_Boot_Continue + cmp pc, r2 + bhs Normal_Boot_Continue + +NAND_Boot_Start: + /* Copy image from flash to SDRAM first */ + ldr r1, MXC_REDBOOT_ROM_START +1: + ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + blo 1b + + /* Jump to SDRAM */ + ldr r1, CONST_0x0FFF + and r0, pc, r1 /* offset of pc */ + ldr r1, MXC_REDBOOT_ROM_START + add r1, r1, #0x8 + add pc, r0, r1 + nop + +Now_in_SDRAM: +NAND_Copy_Main: + // Check if x16/2kb page + // ldr r7, CCM_BASE_ADDR_W + // ldr r7, [r7, #0xC] + // ands r7, r7, #(1 << 30) + ldr r0, NFC_BASE_W //r0: nfc base. Reloaded after each page copying + mov r1, #TX37_NAND_PAGE_SIZE //r1: starting flash addr to be copied. Updated constantly + // ???? should be dynamic based on the page size kevin todo + add r2, r0, #TX37_NAND_PAGE_SIZE //r2: end of 3rd RAM buf. Doesn't change ?? dynamic + + ldr r11, NFC_IP_BASE_W //r11: NFC IP register base. Doesn't change + add r12, r0, #0x1E00 //r12: NFC AXI register base. Doesn't change + ldr r14, MXC_REDBOOT_ROM_START + add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change + add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly + + //unlock internal buffer + mov r3, #0xFF000000 + add r3, r3, #0x00FF0000 + str r3, [r11, #0x4] + str r3, [r11, #0x8] + str r3, [r11, #0xC] + str r3, [r11, #0x10] + mov r3, #0x20000 // BLS = 2 -> Buffer Lock Set = unlocked + add r3, r3, #0x4 // WPC = 4 -> write protection command = unlock blocks + str r3, [r11, #0x0] // kevin - revist for multiple CS ?? + mov r3, #0 + str r3, [r11, #0x18] + +Nfc_Read_Page: + mov r3, #0x0 + str r3, [r12, #0x0] + mov r3, #NAND_LAUNCH_FCMD + str r3, [r12, #0xC] + do_wait_op_done + +// start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask); + mov r4, r1 + mov r3, #0 + do_addr_input //1st addr cycle + + mov r3, #0 + do_addr_input //2nd addr cycle + + mov r3, r4, lsr #11 + and r3, r3, #0xFF + mov r3, r3, lsl #16 + do_addr_input //3rd addr cycle + + mov r3, r4, lsr #19 + and r3, r3, #0xFF + mov r3, r3, lsl #16 + do_addr_input //4th addr cycle + + mov r3, #0x30 + str r3, [r12, #0x0] + mov r3, #NAND_LAUNCH_FCMD + str r3, [r12, #0xC] + do_wait_op_done + +// write RBA=0 to NFC_CONFIGURATION1 + mov r3, #0 + str r3, [r12, #0x4] + +// writel(mode & 0xFF, NAND_LAUNCH_REG) + mov r3, #0x8 + str r3, [r12, #0xC] + do_wait_op_done + +Copy_Good_Blk: + @ copy page +1: + ldmia r0!, {r3-r10} + stmia r14!, {r3-r10} + cmp r0, r2 + blo 1b + cmp r14, r13 + bge NAND_Copy_Main_done + add r1, r1, #TX37_NAND_PAGE_SIZE + ldr r0, NFC_BASE_W + b Nfc_Read_Page + +NAND_Copy_Main_done: + +Normal_Boot_Continue: +#ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */ + /* Copy image from flash to SDRAM first */ + ldr r0, =0xFFFFF000 + and r0, r0, pc + ldr r1, MXC_REDBOOT_ROM_START + cmp r0, r1 + beq HWInitialise_skip_SDRAM_copy + + add r2, r0, #REDBOOT_IMAGE_SIZE +1: + ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + ble 1b + + /* Jump to SDRAM */ + ldr r1, =0xFFFF + and r0, pc, r1 /* offset of pc */ + ldr r1, MXC_REDBOOT_ROM_START + add r1, r1, #0x8 + add pc, r0, r1 + nop +#endif /* CYG_HAL_STARTUP_ROMRAM */ + +HWInitialise_skip_SDRAM_copy: +/* + * Note: + * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity + */ +STACK_Setup: + // Set up a stack [for calling C code] + ldr r1, =__startup_stack + ldr r2, =RAM_BANK0_BASE + orr sp, r1, r2 + + // Create MMU tables + bl hal_mmu_init + + // Enable MMU + ldr r2, =10f + mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first + orr r1, r1, #7 // enable MMU bit + orr r1, r1, #0x800 // enable z bit + b 9f + .align 5 +9: + mcr MMU_CP, 0, r1, MMU_Control, c0 + mov pc,r2 /* Change address spaces */ + nop +10: + .endm // _platform_setup1 + +#else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) +#define PLATFORM_SETUP1 +#endif + /* Do nothing */ + .macro init_spba + .endm /* init_spba */ + + /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/ + .macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, AIPS1_CTRL_BASE_ADDR_W + ldr r1, AIPS1_PARAM_W + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, AIPS2_CTRL_BASE_ADDR_W + str r1, [r0, #0x00] + str r1, [r0, #0x04] + .endm /* init_aips */ + + /* MAX (Multi-Layer AHB Crossbar Switch) setup */ + .macro init_max + ldr r0, MAX_BASE_ADDR_W +#if 0 + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, MAX_PARAM1 + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =0x10 + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =0x0 + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +#endif + .endm /* init_max */ + + .macro init_clock + /* + * Clock setup + * After this step, + + Module Freq (MHz) + =========================== + ARM core 532 ap_clk + AHB 133 ahb_clk + IP 66.5 ipg_clk + EMI 133 ddr_clk + + * All other clocks can be figured out based on this. + */ + /* + * Step 1: Switch to step clock + */ + ldr r0, CCM_BASE_ADDR_W + mov r1, #0x00000104 + str r1, [r0, #CLKCTL_CCSR] + + /* Step 2: Setup PLL's */ + /* Set PLL1 to be 532MHz */ + ldr r0, PLL1_BASE_ADDR_W + + mov r1, #0x1200 + add r1, r1, #0x22 + str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */ + ldr r1, =0x2 + str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + ldr r1, =0x50 + str r1, [r0, #PLL_DP_OP] + ldr r1, =23 + str r1, [r0, #PLL_DP_MFD] + ldr r1, =13 + str r1, [r0, #PLL_DP_MFN] + + ldr r1, =0x50 + str r1, [r0, #PLL_DP_HFS_OP] + ldr r1, =23 + str r1, [r0, #PLL_DP_HFS_MFD] + ldr r1, =13 + str r1, [r0, #PLL_DP_HFS_MFN] + + /* Now restart PLL 1 */ + ldr r1, PLL_VAL_0x1232 + str r1, [r0, #PLL_DP_CTL] +1: + ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b + + /* + * Step 2: Setup PLL2 to 665 MHz. + */ + ldr r0, PLL2_BASE_ADDR_W + + ldr r1, =0x1200 + add r1, r1, #0x22 + str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */ + ldr r1, =0x2 + str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + ldr r1, =0x60 + str r1, [r0, #PLL_DP_OP] + ldr r1, =95 + str r1, [r0, #PLL_DP_MFD] + ldr r1, =89 + str r1, [r0, #PLL_DP_MFN] + + ldr r1, =0x60 + str r1, [r0, #PLL_DP_HFS_OP] + ldr r1, =95 + str r1, [r0, #PLL_DP_HFS_MFD] + ldr r1, =89 + str r1, [r0, #PLL_DP_HFS_MFN] + + /* Now restart PLL 2 */ + ldr r1, PLL_VAL_0x1232 + str r1, [r0, #PLL_DP_CTL] +1: + ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b + + /* + * Set PLL 3 to 216MHz + */ + ldr r0, PLL3_BASE_ADDR_W + + ldr r1, PLL_VAL_0x222 + str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */ + ldr r1, =0x2 + str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + ldr r1, =0x92 + str r1, [r0, #PLL_DP_OP] + ldr r1, =0x0 + str r1, [r0, #PLL_DP_MFD] + ldr r1, =0x0 + str r1, [r0, #PLL_DP_MFN] + + ldr r1, =0x91 + str r1, [r0, #PLL_DP_HFS_OP] + ldr r1, =0x0 + str r1, [r0, #PLL_DP_HFS_MFD] + ldr r1, =0x0 + str r1, [r0, #PLL_DP_HFS_MFN] + + /* Now restart PLL 3 */ + ldr r1, PLL_VAL_0x232 + str r1, [r0, #PLL_DP_CTL] + +1: + ldr r1, [r0, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b + /* End of PLL 3 setup */ + + /* Setup the ARM platform clock dividers */ + ldr r0, PLATFORM_BASE_ADDR_W + ldr r1, PLATFORM_CLOCK_DIV_W + str r1, [r0, #0x18] + + /* + * Step 3: switching to PLL 1 and restore default register values. + */ + ldr r0, CCM_BASE_ADDR_W + mov r1, #0x00000100 + str r1, [r0, #CLKCTL_CCSR] + + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] + /* Use 133MHz for DDR clock */ + mov r1, #0x1C00 + str r1, [r0, #CLKCTL_CAMR] + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, CCM_VAL_0xA5A6A020 + str r1, [r0, #CLKCTL_CSCMR1] + ldr r1, CCM_VAL_0x01450B21 + str r1, [r0, #CLKCTL_CSCDR1] + + mov r1, #0x1C + str r1, [r0, #CLKCTL_CBCDR7] + mov r1, #1 + str r1, [r0, #4] + .endm /* init_clock */ + + /* M4IF setup */ + .macro init_m4if + /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) + IPU accesses with ID=0x1 given highest priority (=0xA) */ + ldr r1, M4IF_BASE_W + ldr r0, M4IF_0x00000a01 + str r0, [r1, #M4IF_FIDBP] + + ldr r0, M4IF_0x00000404 + str r0, [r1, #M4IF_FBPM0] + .endm /* init_m4if */ + + .macro setup_sdram + ldr r0, ESDCTL_BASE_W + /* Set CSD0 */ + mov r1, #0x80000000 + str r1, [r0, #ESDCTL_ESDCTL0] +1: + @ wait for SDRAM ready + ldr r2, [r0, #ESDCTL_ESDMISC] + and r2, r2, r1 + beq 1b + + /* Precharge command */ + ldr r1, SDRAM_CMD_PRECHG + str r1, [r0, #ESDCTL_ESDSCR] + + /* 2 refresh commands */ + ldr r1, SDRAM_CMD_SLFRFSH + .rept 2 + str r1, [r0, #ESDCTL_ESDSCR] + .endr + + /* LMR with CAS Latency=3 and BurstLength=3->8words */ + ldr r1, SDRAM_CMD_MODEREG + str r1, [r0, #ESDCTL_ESDSCR] + + /* 13 ROW, 9 COL, 32Bit, SREF=4 */ + ldr r1, SDRAM_ESDCTL0_VAL + str r1, [r0, #ESDCTL_ESDCTL0] + + /* Timing parameters */ + ldr r1, SDRAM_ESDCFG0_VAL + str r1, [r0, #ESDCTL_ESDCFG0] + + /* MDDR enable, RALAT=1 */ + ldr r1, SDRAM_ESDMISC_VAL + str r1, [r0, #ESDCTL_ESDMISC] + + /* Normal mode */ + mov r1, #0x00000000 + str r1, [r0, #ESDCTL_ESDSCR] + .endm + + .macro do_wait_op_done +1: + ldr r3, [r11, #0x18] + ands r3, r3, #NFC_IPC_INT + beq 1b + mov r3, #0x0 + str r3, [r11, #0x18] + .endm // do_wait_op_done + + .macro do_addr_input + str r3, [r12, #0x0] + mov r3, #NAND_LAUNCH_FADD + str r3, [r12, #0xC] + do_wait_op_done + .endm // do_addr_input + + /* To support 133MHz DDR */ + .macro init_iomux + ldr r0, IOMUXC_BASE_ADDR_W + + // DDR signal setup for D16-D31 and drive strength + ldr r8, =0x1 + add r1, r0, #8 + add r2, r0, #0x4C +1: + stmia r1!, {r8} + cmp r1, r2 + bls 1b + + str r8, [r0, #0x5C] + str r8, [r0, #0x60] + + add r2, r0, #0x200 + mov r8, #0x2C4 + str r8, [r2, #0xBC] + str r8, [r2, #0xC0] + + ldr r8, =0x2 + str r8, [r0, #0x4A8] + str r8, [r0, #0x4B0] + str r8, [r0, #0x4B4] + str r8, [r0, #0x4E0] + str r8, [r0, #0x4FC] + str r8, [r0, #0x504] + str r8, [r0, #0x48C] + str r8, [r0, #0x49C] + + add r1, r0, #0x278 + add r2, r0, #0x29C +2: + stmia r1!, {r8} + cmp r1, r2 + bls 2b + .endm /* init_iomux */ + +#define PLATFORM_VECTORS _platform_vectors + .macro _platform_vectors + .globl _board_BCR, _board_CFG +_board_BCR: .long 0 // Board Control register shadow +_board_CFG: .long 0 // Board Configuration (read at RESET) + .endm + +KaRo_MSG: .asciz "KARO TX37 " __DATE__ " " __TIME__ "\n" +ARM_PPMRR: .word 0x80000016 +L2CACHE_PARAM: .word 0x0003001B +WDOG1_BASE_W: .word WDOG1_BASE_ADDR +IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF +AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR +AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR +AIPS1_PARAM_W: .word 0x77777777 +MAX_BASE_ADDR_W: .word MAX_BASE_ADDR +MAX_PARAM1: .word 0x00302154 +ESDCTL_BASE_W: .word ESDCTL_BASE +M4IF_BASE_W: .word M4IF_BASE +M4IF_0x00000a01: .word 0x00000a01 +M4IF_0x00000404: .word 0x00000404 +NFC_BASE_W: .word NFC_BASE +NFC_IP_BASE_W: .word NFC_IP_BASE +SDRAM_CMD_PRECHG: .word 0x04008008 +SDRAM_CMD_SLFRFSH: .word 0x00008010 +SDRAM_CMD_MODEREG: .word 0x00338018 +SDRAM_ESDCTL0_VAL: .word 0xB2120000 +SDRAM_0x899F6BBA: .word 0x899F6BBA +SDRAM_0x000A1104: .word 0x000A1104 +SDRAM_ESDCFG0_VAL: .word 0x70395729 +SDRAM_ESDMISC_VAL: .word 0x000A0084 +IOMUXC_BASE_ADDR_W: .word IOMUXC_BASE_ADDR +GPIO2_BASE_ADDR_W: .word GPIO2_BASE_ADDR +MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET +SDRAM_ADDR_MASK: .word 0xfff00000 +CONST_0x0FFF: .word 0x0FFF +CCM_BASE_ADDR_W: .word CCM_BASE_ADDR +PLATFORM_BASE_ADDR_W: .word PLATFORM_BASE_ADDR +PLATFORM_CLOCK_DIV_W: .word 0x00077713 +CCM_VAL_0x01450B21: .word 0x01450B21 +CCM_VAL_0xA5A6A020: .word 0xA5A6A020 +PLL_VAL_0x222: .word 0x222 +PLL_VAL_0x232: .word 0x232 +PLL1_BASE_ADDR_W: .word PLL1_BASE_ADDR +PLL2_BASE_ADDR_W: .word PLL2_BASE_ADDR +PLL3_BASE_ADDR_W: .word PLL3_BASE_ADDR +PLL_VAL_0x1232: .word 0x1232 + +/*--------------------------------------------------------------------------*/ +/* end of hal_platform_setup.h */ +#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */ diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/karo_tx37.h b/packages/hal/arm/mx37/stk5/v1_0/include/karo_tx37.h new file mode 100644 index 00000000..17f52436 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/karo_tx37.h @@ -0,0 +1,124 @@ +#ifndef CYGONCE_KARO_TX37_H +#define CYGONCE_KARO_TX37_H + +//============================================================================= +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== + +#include // Hardware definitions + +#include CYGHWR_MEMORY_LAYOUT_H + +#define SZ_1K 0x00000400 +#define SZ_2K 0x00000800 +#define SZ_4K 0x00001000 +#define SZ_8K 0x00002000 +#define SZ_16K 0x00004000 +#define SZ_32K 0x00008000 +#define SZ_64K 0x00010000 +#define SZ_128K 0x00020000 +#define SZ_256K 0x00040000 +#define SZ_512K 0x00080000 +#define SZ_1M 0x00100000 +#define SZ_2M 0x00200000 +#define SZ_4M 0x00400000 +#define SZ_8M 0x00800000 +#define SZ_16M 0x01000000 +#define SZ_32M 0x02000000 +#define SZ_64M 0x04000000 +#define SZ_128M 0x08000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 +#define SZ_1G 0x40000000 + + +#define RAM_BANK0_BASE SDRAM_BASE_ADDR +#define TX37_SDRAM_SIZE SDRAM_SIZE + +#define GPIO_DR 0x00 + +#define STK5_LED_MASK (1 << 19) +#define STK5_LED_REG_ADDR (GPIO2_BASE_ADDR + GPIO_DR) + +#define LED_MAX_NUM 1 + +#define LED_IS_ON(n) ({ \ + CYG_WORD32 __val; \ + HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \ + __val & STK5_LED_MASK; \ +}) + +#define TURN_LED_ON(n) \ + CYG_MACRO_START \ + CYG_WORD32 __val; \ + HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \ + __val |= STK5_LED_MASK; \ + HAL_WRITE_UINT32(STK5_LED_REG_ADDR, __val); \ + CYG_MACRO_END + +#define TURN_LED_OFF(n) \ + CYG_MACRO_START \ + CYG_WORD32 __val; \ + HAL_READ_UINT32(STK5_LED_REG_ADDR, __val); \ + __val &= ~STK5_LED_MASK; \ + HAL_WRITE_UINT32(STK5_LED_REG_ADDR, __val); \ + CYG_MACRO_END + +#define BOARD_DEBUG_LED(n) \ + CYG_MACRO_START \ + if (n >= 0 && n < LED_MAX_NUM) { \ + if (LED_IS_ON(n)) \ + TURN_LED_OFF(n); \ + else \ + TURN_LED_ON(n); \ + } \ + CYG_MACRO_END + +#define BLINK_LED(l, n) \ + CYG_MACRO_START \ + int _i; \ + for (_i = 0; _i < (n); _i++) { \ + BOARD_DEBUG_LED(l); \ + HAL_DELAY_US(200000); \ + BOARD_DEBUG_LED(l); \ + HAL_DELAY_US(300000); \ + } \ + HAL_DELAY_US(1000000); \ + CYG_MACRO_END + +#endif /* CYGONCE_KARO_TX37_H */ diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.h b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.h new file mode 100644 index 00000000..2893fdab --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.h @@ -0,0 +1,33 @@ +// eCos memory layout - Fri Oct 20 05:56:55 2000 + +// This is a generated file - do not edit +#if !defined(__LINKER_SCRIPT__) && !defined(__ASSEMBLER__) +#include +#include +#endif + +//#define REDBOOT_BOTTOM + +#define REDBOOT_IMAGE_SIZE 0x00040000 +#define REDBOOT_OFFSET 0x00100000 +#define MODULE_SDRAM_SIZE 0x04000000 + +#ifdef REDBOOT_BOTTOM +#define CYGMEM_REGION_ram (0xA0000000 + REDBOOT_OFFSET) +#define CYGMEM_REGION_rom (0xA0000000) +#else +#define CYGMEM_REGION_ram (0xA0000000) +#define CYGMEM_REGION_rom (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - REDBOOT_OFFSET) +#endif + +//#define CYGMEM_REGION_ram (0xA0000000) +#define CYGMEM_REGION_ram_SIZE (MODULE_SDRAM_SIZE) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) +//#define CYGMEM_REGION_rom (0xA1F00000) +#define CYGMEM_REGION_rom_SIZE REDBOOT_OFFSET +#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R) +#if !defined(__LINKER_SCRIPT__) && !defined(__ASSEMBLER__) +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_rom - (size_t) CYG_LABEL_NAME (__heap1)) diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.ldi b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.ldi new file mode 100644 index 00000000..22304202 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/lo_mlt_arm_board_romram.ldi @@ -0,0 +1,31 @@ +// eCos memory layout - Fri Oct 20 05:56:55 2000 + +// This is a generated file - do not edit + +#include +#define __LINKER_SCRIPT__ +#include + +MEMORY +{ + ram : ORIGIN = CYGMEM_REGION_ram, LENGTH = CYGMEM_REGION_ram_SIZE + rom : ORIGIN = CYGMEM_REGION_rom, LENGTH = CYGMEM_REGION_rom_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, CYGMEM_REGION_rom, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, CYGMEM_REGION_ram + 0x20, LMA_EQ_VMA) + SECTION_data (ram, CYGMEM_REGION_ram + 0x8000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_board_romram.mlt b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_board_romram.mlt new file mode 100644 index 00000000..ec24b3b7 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_board_romram.mlt @@ -0,0 +1,14 @@ +version 0 +region ram 0 7F00000 0 ! +region rom 43F00000 100000 1 ! +section fixed_vectors 0 1 0 1 1 0 1 0 20 20 ! +section data 0 1 1 1 1 1 0 0 8000 bss ! +section bss 0 4 0 1 0 1 0 1 heap1 heap1 ! +section heap1 0 8 0 0 0 0 0 0 ! +section rom_vectors 0 1 0 1 1 1 1 1 43F00000 43F00000 text text ! +section text 0 4 0 1 0 1 0 1 fini fini ! +section fini 0 4 0 1 0 1 0 1 rodata rodata ! +section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 ! +section rodata1 0 4 0 1 0 1 0 1 fixup fixup ! +section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table ! +section gcc_except_table 0 4 0 1 0 0 0 1 data ! diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.h b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.h new file mode 100644 index 00000000..ab7d41e8 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.h @@ -0,0 +1,27 @@ +// eCos memory layout - Fri Oct 20 05:56:55 2000 + +// This is a generated file - do not edit +#ifndef __ASSEMBLER__ +#include +#include +#endif +#include // Hardware definitions + +#define SDRAM_BASE_ADDR CSD0_BASE_ADDR +#define SDRAM_SIZE 0x04000000 + +#define REDBOOT_IMAGE_SIZE 0x00040000 +#define REDBOOT_OFFSET 0x00100000 + +#define CYGMEM_REGION_ram SDRAM_BASE_ADDR +#define CYGMEM_REGION_ram_SIZE (SDRAM_SIZE - REDBOOT_OFFSET) +#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W) + +#define CYGMEM_REGION_rom (CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) +#define CYGMEM_REGION_rom_SIZE REDBOOT_OFFSET +#define CYGMEM_REGION_rom_ATTR CYGMEM_REGION_ATTR_R +#ifndef __ASSEMBLER__ +extern char CYG_LABEL_NAME (__heap1) []; +#endif +#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1)) +#define CYGMEM_SECTION_heap1_SIZE (CYGMEM_REGION_rom - (size_t)CYG_LABEL_NAME(__heap1)) diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.ldi b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.ldi new file mode 100644 index 00000000..d3a170ef --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/pkgconf/mlt_arm_tx37_romram.ldi @@ -0,0 +1,33 @@ +// eCos memory layout - Fri Oct 20 05:56:55 2000 + +// This is a generated file - do not edit + +#include +#define __ASSEMBLER__ +#include + +MEMORY +{ + ram : ORIGIN = CYGMEM_REGION_ram, LENGTH = CYGMEM_REGION_ram_SIZE + rom : ORIGIN = CYGMEM_REGION_rom, LENGTH = CYGMEM_REGION_rom_SIZE +} + +SECTIONS +{ + SECTIONS_BEGIN + SECTION_rom_vectors (rom, CYGMEM_REGION_rom, LMA_EQ_VMA) + SECTION_text (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fini (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_rodata1 (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_got (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_extab (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_exidx (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixup (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_gcc_except_table (rom, ALIGN (0x4), LMA_EQ_VMA) + SECTION_fixed_vectors (ram, CYGMEM_REGION_ram + 0x20, LMA_EQ_VMA) + SECTION_data (ram, CYGMEM_REGION_ram + 0x8000, FOLLOWING (.gcc_except_table)) + SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA) + CYG_LABEL_DEFN(__heap1) = ALIGN (0x8); + SECTIONS_END +} diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/plf_io.h b/packages/hal/arm/mx37/stk5/v1_0/include/plf_io.h new file mode 100644 index 00000000..acdacd98 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/plf_io.h @@ -0,0 +1,69 @@ +#ifndef CYGONCE_HAL_ARM_BOARD_PLF_IO_H +#define CYGONCE_HAL_ARM_BOARD_PLF_IO_H + +//============================================================================= +// +// plf_io.h +// +// Platform specific support (register layout, etc) +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//============================================================================= + +#include +#include + +#define CYGHWR_REDBOOT_LINUX_ATAG_MEM(_p_) \ + CYG_MACRO_START \ + { \ + extern unsigned int system_rev; \ + /* Next ATAG_MEM. */ \ + _p_->hdr.size = (sizeof(struct tag_mem32) + sizeof(struct tag_header))/sizeof(long); \ + _p_->hdr.tag = ATAG_MEM; \ + /* Round up so there's only one bit set in the memory size. \ + * Don't double it if it's already a power of two, though. \ + */ \ + _p_->u.mem.size = 1<u.mem.size < CYGMEM_REGION_ram_SIZE) \ + _p_->u.mem.size <<= 1; \ + _p_->u.mem.start = CYGARC_PHYSICAL_ADDRESS(CYGMEM_REGION_ram); \ + _p_ = (struct tag *)((long *)_p_ + _p_->hdr.size); \ + _p_->hdr.size = ((sizeof(struct tag_revision)) + sizeof(struct tag_header))/sizeof(long); \ + _p_->hdr.tag = ATAG_REVISION; \ + _p_->u.revision.rev = system_rev; \ + } \ + CYG_MACRO_END + +#endif // CYGONCE_HAL_ARM_BOARD_PLF_IO_H diff --git a/packages/hal/arm/mx37/stk5/v1_0/include/plf_mmap.h b/packages/hal/arm/mx37/stk5/v1_0/include/plf_mmap.h new file mode 100644 index 00000000..087612b0 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/include/plf_mmap.h @@ -0,0 +1,65 @@ +#ifndef CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H +#define CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H +//============================================================================= +// +// plf_mmap.h +// +// Platform specific memory map support +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//=========================================================================== + +#include + +// Get the pagesize for a particular virtual address: + +// This does not depend on the vaddr. +#define HAL_MM_PAGESIZE(vaddr, pagesize) CYG_MACRO_START \ + (pagesize) = SZ_1M; \ +CYG_MACRO_END + +// Get the physical address from a virtual address: + +#define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \ + cyg_uint32 _v_ = (cyg_uint32)(vaddr); \ + if ( _v_ < 128 * SZ_1M ) /* SDRAM */ \ + _v_ += SDRAM_BASE_ADDR; \ + else /* Rest of it */ \ + /* no change */ ; \ + (paddr) = _v_; \ +CYG_MACRO_END + +//--------------------------------------------------------------------------- +#endif // CYGONCE_HAL_BOARD_PLATFORM_PLF_MMAP_H diff --git a/packages/hal/arm/mx37/stk5/v1_0/misc/redboot_ROMRAM.ecm b/packages/hal/arm/mx37/stk5/v1_0/misc/redboot_ROMRAM.ecm new file mode 100644 index 00000000..a1239d69 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/misc/redboot_ROMRAM.ecm @@ -0,0 +1,229 @@ +cdl_savefile_version 1; +cdl_savefile_command cdl_savefile_version {}; +cdl_savefile_command cdl_savefile_command {}; +cdl_savefile_command cdl_configuration { description hardware template package }; +cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value }; +cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value }; + +cdl_configuration eCos { + description "RedBoot configuration for Ka-Ro TX37 processor module" ; + + # These fields should not be modified. + hardware tx37karo ; + template redboot ; + package -hardware CYGPKG_HAL_ARM current ; + package -hardware CYGPKG_HAL_ARM_MX37 current ; + package -hardware CYGPKG_HAL_ARM_MX37_STK5 v1_0 ; + package -template CYGPKG_HAL current ; + package -template CYGPKG_INFRA current ; + package -template CYGPKG_REDBOOT current ; + package -template CYGPKG_ISOINFRA current ; + package -template CYGPKG_LIBC_STRING current ; + package -template CYGPKG_CRC current ; + package -hardware CYGPKG_IO_ETH_DRIVERS current ; + package -hardware CYGPKG_DEVS_ETH_ARM_TX27 v1_0 ; + package -hardware CYGPKG_DEVS_ETH_FEC current ; + package -hardware CYGPKG_COMPRESS_ZLIB current ; + package -hardware CYGPKG_IO_FLASH current ; + package -hardware CYGPKG_DEVS_FLASH_ONMXC current ; + package -hardware CYGPKG_IO_I2C current ; + package -hardware CYGPKG_DEVICES_WALLCLOCK_DALLAS_DS1307 current ; + package CYGPKG_MEMALLOC current ; + package CYGPKG_DEVS_ETH_PHY current ; + package CYGPKG_LIBC_I18N current ; +}; + +cdl_option CYGFUN_LIBC_STRING_BSD_FUNCS { + inferred_value 0 +}; + +cdl_component CYGDBG_IO_ETH_DRIVERS_DEBUG { + user_value 1 +}; + +cdl_option CYGDBG_IO_ETH_DRIVERS_DEBUG_VERBOSITY { + user_value 0 +}; + +cdl_component CYGPKG_IO_ETH_DRIVERS_STAND_ALONE { + user_value 1 +}; + +cdl_option CYGHWR_DEVS_ETH_PHY_LAN8700 { + user_value 1 +}; + +cdl_option CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK { + inferred_value 0 +}; + +cdl_option CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE { + user_value 4096 +}; + +cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT { + user_value 0 +}; + +cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM { + inferred_value 0 +}; + +cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS { + inferred_value 1 +}; + +cdl_option CYGSEM_HAL_ROM_MONITOR { + inferred_value 1 +}; + +cdl_component CYG_HAL_STARTUP { + user_value ROMRAM +}; + +cdl_component CYGSEM_REDBOOT_ELF { + user_value 1 +}; + +cdl_component CYGBLD_BUILD_REDBOOT { + user_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_GDB { + user_value 0 +}; + +cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { + user_value 1 "Ka-Ro [exec date -I]" +}; + +cdl_option CYGPRI_REDBOOT_ZLIB_FLASH_FORCE { + inferred_value 1 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_MXCUSB { + user_value 0 +}; + +cdl_option CYGBLD_BUILD_REDBOOT_WITH_EXEC { + user_value 1 +}; + +cdl_option CYGDBG_REDBOOT_TICK_GRANULARITY { + user_value 10 +}; + +cdl_option CYGDBG_REDBOOT_NET_DEBUG { + user_value 0 +}; + +cdl_option CYGPKG_REDBOOT_ANY_CONSOLE { + user_value 1 +}; + +cdl_option CYGPKG_REDBOOT_MAX_CMD_LINE { + user_value 1024 +}; + +cdl_option CYGBLD_REDBOOT_MIN_IMAGE_SIZE { + inferred_value 0x00040000 +}; + +cdl_option CYGDAT_REDBOOT_DEFAULT_BOOT_SCRIPT { + user_value 0 0 +}; + +cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_TIMEOUT_RESOLUTION { + user_value 10 +}; + +cdl_option CYGNUM_REDBOOT_BOOT_SCRIPT_DEFAULT_TIMEOUT { + user_value 100 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS { + inferred_value 0xA0108000 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_EXEC_ADDRESS_DEFAULT { + inferred_value 0x40008000 +}; + +cdl_option CYGHWR_REDBOOT_ARM_LINUX_TAGS_ADDRESS { + user_value 0xA0001000 +}; + +cdl_option CYGBLD_ISO_CTYPE_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_STRCONV_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_ABS_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STDLIB_DIV_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_STRTOK_R_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_LOCALE_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_BSD_FUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_MEMFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_STRING_STRFUNCS_HEADER { + inferred_value 1 +}; + +cdl_option CYGBLD_ISO_C_TIME_TYPES_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_C_CLOCK_FUNCS_HEADER { + user_value 1 +}; + +cdl_option CYGBLD_ISO_BSDTYPES_HEADER { + user_value 0 0 +}; + +cdl_option CYGSEM_IO_FLASH_READ_INDIRECT { + inferred_value 1 +}; + +cdl_option CYGSEM_IO_FLASH_VERIFY_PROGRAM { + inferred_value 0 +}; + +cdl_component CYGPRI_REDBOOT_ZLIB_FLASH_FORCE { + inferred_value 1 +}; + +cdl_option CYGNUM_REDBOOT_FIS_DIRECTORY_BLOCK { + inferred_value 2 +}; + +cdl_option CYGDAT_REDBOOT_CUSTOM_VERSION { + user_value 1 "Ka-Ro [exec date -I]" +}; + +cdl_option CYGHWR_DEVS_FLASH_MXC_NAND { + inferred_value 1 +}; + diff --git a/packages/hal/arm/mx37/stk5/v1_0/src/redboot_cmds.c b/packages/hal/arm/mx37/stk5/v1_0/src/redboot_cmds.c new file mode 100644 index 00000000..844cff62 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/src/redboot_cmds.c @@ -0,0 +1,279 @@ +//========================================================================== +// +// redboot_cmds.c +// +// Board [platform] specific RedBoot commands +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +#include +#include +#include +#include +#include // Platform specific hardware definitions + +#ifdef CYGSEM_REDBOOT_FLASH_CONFIG +#include + +#if (REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE) +#error REDBOOT_IMAGE_SIZE != CYGBLD_REDBOOT_MIN_IMAGE_SIZE +#endif + +#endif //CYGSEM_REDBOOT_FLASH_CONFIG + +char HAL_PLATFORM_EXTRA[20] = "PASS x.x [x32 DDR]"; +static void runImg(int argc, char *argv[]); +static void do_mem(int argc, char *argv[]); + +RedBoot_cmd("mem", + "Set a memory location", + "[-h|-b] [-n] [-a
] ", + do_mem + ); + +RedBoot_cmd("run", + "Run an image at a location with MMU off", + "[]", + runImg + ); + +static void do_mem(int argc, char *argv[]) +{ + struct option_info opts[4]; + bool mem_half_word, mem_byte; + bool no_verify; + bool addr_set; + unsigned long address; + unsigned int value; + int ret; + init_opts(&opts[0], 'b', false, OPTION_ARG_TYPE_FLG, + &mem_byte, NULL, "write a byte"); + init_opts(&opts[1], 'h', false, OPTION_ARG_TYPE_FLG, + &mem_half_word, NULL, "write a half-word"); + init_opts(&opts[2], 'a', true, OPTION_ARG_TYPE_NUM, + &address, &addr_set, "address to write to"); + init_opts(&opts[3], 'n', false, OPTION_ARG_TYPE_FLG, + &no_verify, NULL, "noverify"); + + ret = scan_opts(argc, argv, 1, opts, sizeof(opts) / sizeof(opts[0]), + &value, OPTION_ARG_TYPE_NUM, "value to be written"); + if (ret == 0) { + return; + } + if (!addr_set) { + diag_printf("** Error: '-a
' must be specified\n"); + return; + } + if (ret == argc + 1) { + diag_printf("** Error: non-option argument '' must be specified\n"); + return; + } + if (mem_byte && mem_half_word) { + diag_printf("** Error: Should not specify both byte and half-word access\n"); + } else if (mem_byte) { + value &= 0xff; + *(volatile cyg_uint8*)address = (cyg_uint8)value; + if (no_verify) { + diag_printf(" Set 0x%08lX to 0x%02X\n", address, value); + } else { + diag_printf(" Set 0x%08lX to 0x%02X (result 0x%02X)\n", + address, value, (int)*(cyg_uint8*)address ); + } + } else if (mem_half_word) { + if (address & 1) { + diag_printf("** Error: address for half-word access must be half-word aligned\n"); + } else { + value &= 0xffff; + *(volatile cyg_uint16*)address = (cyg_uint16)value; + if (no_verify) { + diag_printf(" Set 0x%08lX to 0x%04X\n", address, value); + } else { + diag_printf(" Set 0x%08lX to 0x%04X (result 0x%04X)\n", + address, value, (int)*(cyg_uint16*)address); + } + } + } else { + if (address & 3) { + diag_printf("** Error: address for word access must be word aligned\n"); + } else { + *(volatile cyg_uint32*)address = (cyg_uint32)value; + if (no_verify) { + diag_printf(" Set 0x%08lX to 0x%08X\n", address, value); + } else { + diag_printf(" Set 0x%08lX to 0x%08X (result 0x%08X)\n", + address, value, (int)*(cyg_uint32*)address); + } + } + } +} + +void launchRunImg(unsigned long addr) +{ + asm volatile ("mov r12, r0;"); + HAL_CLEAN_INVALIDATE_L2(); + HAL_DISABLE_L2(); + HAL_MMU_OFF(); + asm volatile ( + "mov r0, #0;" + "mov r1, r12;" + "mov r11, #0;" + "mov r12, #0;" + "mrs r10, cpsr;" + "bic r10, r10, #0xF0000000;" + "msr cpsr_f, r10;" + "mov pc, r1" + ); +} + +extern unsigned long entry_address; + +static void runImg(int argc,char *argv[]) +{ + unsigned int virt_addr, phys_addr; + + // Default physical entry point for Symbian + if (entry_address == 0xFFFFFFFF) + virt_addr = 0x800000; + else + virt_addr = entry_address; + + if (!scan_opts(argc, argv, 1, 0, 0, &virt_addr, + OPTION_ARG_TYPE_NUM, "virtual address")) + return; + + if (entry_address != 0xFFFFFFFF) + diag_printf("load entry_address=0x%lx\n", entry_address); + HAL_VIRT_TO_PHYS_ADDRESS(virt_addr, phys_addr); + + diag_printf("virt_addr=0x%x\n",virt_addr); + diag_printf("phys_addr=0x%x\n",phys_addr); + + launchRunImg(phys_addr); +} + +#if defined(CYGSEM_REDBOOT_FLASH_CONFIG) && defined(CYG_HAL_STARTUP_ROMRAM) + +RedBoot_cmd("romupdate", + "Update Redboot with currently running image", + "", + romupdate + ); + +extern int flash_program(void *_addr, void *_data, int len, void **err_addr); +extern int flash_erase(void *addr, int len, void **err_addr); +extern char *flash_errmsg(int err); + +#ifdef CYGPKG_IO_FLASH +void romupdate(int argc, char *argv[]) +{ + void *err_addr, *base_addr; + int stat; + + base_addr = (void*)MXC_NAND_BASE_DUMMY; + diag_printf("Updating RedBoot in NAND flash\n"); + + // Erase area to be programmed + if ((stat = flash_erase(base_addr, CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) { + diag_printf("Can't erase region at %p: %s\n", + err_addr, flash_errmsg(stat)); + return; + } + // Now program it + if ((stat = flash_program(base_addr, ram_end - CYGMEM_REGION_rom_SIZE, + CYGBLD_REDBOOT_MIN_IMAGE_SIZE, &err_addr)) != 0) { + diag_printf("Can't program region at %p: %s\n", + err_addr, flash_errmsg(stat)); + } +} +#endif //CYGPKG_IO_FLASH +#endif /* CYG_HAL_STARTUP_ROMRAM */ + +static void setcorevol(int argc, char *argv[]); + +RedBoot_cmd("setcorevol", + "Set the core voltage. Setting is not checked against current core frequency.", + "[1.2 | 1.25 | 1.3 | 1.35 | 1.4 | 1.45 | 1.5 | 1.55 | 1.6]", + setcorevol + ); + +/* + * This function communicates with LP3972 to set the core voltage according to + * the argument + */ +// LW: revisit use I2C routines for LP3972 +unsigned int setCoreVoltage(unsigned int coreVol) +{ + /* Set the core voltage */ + diag_printf("%s: Not yet implemented\n", __FUNCTION__); + return 0; +} + +static void setcorevol(int argc, char *argv[]) +{ + unsigned int coreVol; + + /* check if the number of args is OK. 1 arg expected. argc = 2 */ + if (argc != 2) { + diag_printf("Invalid argument. Need to specify a voltage\n"); + return; + } + + /* check if the argument is valid. */ + if (strcasecmp(argv[1], "1.2") == 0) { + coreVol = 0xC; + } else if (strcasecmp(argv[1], "1.25") == 0) { + coreVol = 0xE; + } else if (strcasecmp(argv[1], "1.3") == 0) { + coreVol = 0x10; + } else if (strcasecmp(argv[1], "1.35") == 0) { + coreVol = 0x12; + } else if (strcasecmp(argv[1], "1.4") == 0) { + coreVol = 0x14; + } else if (strcasecmp(argv[1], "1.45") == 0) { + coreVol = 0x16; + } else if (strcasecmp(argv[1], "1.5") == 0) { + coreVol = 0x18; + } else if (strcasecmp(argv[1], "1.55") == 0) { + coreVol = 0x1A; + } else if (strcasecmp(argv[1], "1.6") == 0) { + coreVol = 0x1C; + } else { + diag_printf("Invalid argument. Type help setcorevol for valid values\n"); + return ; + } + + setCoreVoltage(coreVol); + return; +} diff --git a/packages/hal/arm/mx37/stk5/v1_0/src/tx37_diag.c b/packages/hal/arm/mx37/stk5/v1_0/src/tx37_diag.c new file mode 100644 index 00000000..cf9c506c --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/src/tx37_diag.c @@ -0,0 +1,378 @@ +/*============================================================================= +// +// board_diag.c +// +// HAL diagnostic output code +// +//============================================================================= +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//===========================================================================*/ + +#include + +#include // base types +#include // tracing macros +#include // assertion macros + +#include // basic machine info +#include // interrupt macros +#include // IO macros +#include +#include // Calling-if API +#include // driver API +#include // Helper functions +#include // Hardware definitions +#include // Platform specifics + +extern void cyg_hal_plf_serial_init(void); + +void cyg_hal_plf_comms_init(void) +{ + static int initialized = 0; + + if (initialized) { + return; + } + initialized = 1; + cyg_hal_plf_serial_init(); +} + +//----------------------------------------------------------------------------- +// Based on 3.6864 MHz xtal +#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600 +#define CYG_DEV_SERIAL_BAUD_MSB 0x00 +#define CYG_DEV_SERIAL_BAUD_LSB 0x18 +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200 +#define CYG_DEV_SERIAL_BAUD_MSB 0x00 +#define CYG_DEV_SERIAL_BAUD_LSB 0x0C +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400 +#define CYG_DEV_SERIAL_BAUD_MSB 0x00 +#define CYG_DEV_SERIAL_BAUD_LSB 0x06 +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600 +#define CYG_DEV_SERIAL_BAUD_MSB 0x00 +#define CYG_DEV_SERIAL_BAUD_LSB 0x04 +#endif +#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200 +#define CYG_DEV_SERIAL_BAUD_MSB 0x00 +#define CYG_DEV_SERIAL_BAUD_LSB 0x02 +#endif + +#ifndef CYG_DEV_SERIAL_BAUD_MSB +#error Missing/incorrect serial baud rate defined - CDL error? +#endif + +//----------------------------------------------------------------------------- +// Define the serial registers. The board is equipped with a 16552 +// serial chip. + +#if defined (EXT_UART_x16) +#define HAL_WRITE_UINT_UART HAL_WRITE_UINT16 +#define HAL_READ_UINT_UART HAL_READ_UINT16 +typedef cyg_uint16 uart_width; +#elif defined (EXT_UART_x32) +#define HAL_WRITE_UINT_UART HAL_WRITE_UINT32 +#define HAL_READ_UINT_UART HAL_READ_UINT32 +typedef cyg_uint32 uart_width; +#else //_x8 +#define HAL_WRITE_UINT_UART HAL_WRITE_UINT8 +#define HAL_READ_UINT_UART HAL_READ_UINT8 +typedef cyg_uint8 uart_width; +#endif + +#define CYG_DEV_SERIAL_RHR 0x00 // receiver buffer register, read, dlab = 0 +#define CYG_DEV_SERIAL_THR 0x00 // transmitter holding register, write, dlab = 0 +#define CYG_DEV_SERIAL_DLL 0x00 // divisor latch (LS), read/write, dlab = 1 +#define CYG_DEV_SERIAL_IER 0x01 // interrupt enable register, read/write, dlab = 0 +#define CYG_DEV_SERIAL_DLM 0x01 // divisor latch (MS), read/write, dlab = 1 +#define CYG_DEV_SERIAL_IIR 0x02 // interrupt identification register, read, dlab = 0 +#define CYG_DEV_SERIAL_FCR 0x02 // fifo control register, write, dlab = 0 +#define CYG_DEV_SERIAL_AFR 0x02 // alternate function register, read/write, dlab = 1 +#define CYG_DEV_SERIAL_LCR 0x03 // line control register, read/write +#define CYG_DEV_SERIAL_MCR 0x04 +#define CYG_DEV_SERIAL_MCR_A 0x04 +#define CYG_DEV_SERIAL_MCR_B 0x04 +#define CYG_DEV_SERIAL_LSR 0x05 // line status register, read +#define CYG_DEV_SERIAL_MSR 0x06 // modem status register, read +#define CYG_DEV_SERIAL_SCR 0x07 // scratch pad register + +// The interrupt enable register bits. +#define SIO_IER_ERDAI 0x01 // enable received data available irq +#define SIO_IER_ETHREI 0x02 // enable THR empty interrupt +#define SIO_IER_ELSI 0x04 // enable receiver line status irq +#define SIO_IER_EMSI 0x08 // enable modem status interrupt + +// The interrupt identification register bits. +#define SIO_IIR_IP 0x01 // 0 if interrupt pending +#define SIO_IIR_ID_MASK 0x0e // mask for interrupt ID bits +#define ISR_Tx 0x02 +#define ISR_Rx 0x04 + +// The line status register bits. +#define SIO_LSR_DR 0x01 // data ready +#define SIO_LSR_OE 0x02 // overrun error +#define SIO_LSR_PE 0x04 // parity error +#define SIO_LSR_FE 0x08 // framing error +#define SIO_LSR_BI 0x10 // break interrupt +#define SIO_LSR_THRE 0x20 // transmitter holding register empty +#define SIO_LSR_TEMT 0x40 // transmitter register empty +#define SIO_LSR_ERR 0x80 // any error condition + +// The modem status register bits. +#define SIO_MSR_DCTS 0x01 // delta clear to send +#define SIO_MSR_DDSR 0x02 // delta data set ready +#define SIO_MSR_TERI 0x04 // trailing edge ring indicator +#define SIO_MSR_DDCD 0x08 // delta data carrier detect +#define SIO_MSR_CTS 0x10 // clear to send +#define SIO_MSR_DSR 0x20 // data set ready +#define SIO_MSR_RI 0x40 // ring indicator +#define SIO_MSR_DCD 0x80 // data carrier detect + +// The line control register bits. +#define SIO_LCR_WLS0 0x01 // word length select bit 0 +#define SIO_LCR_WLS1 0x02 // word length select bit 1 +#define SIO_LCR_STB 0x04 // number of stop bits +#define SIO_LCR_PEN 0x08 // parity enable +#define SIO_LCR_EPS 0x10 // even parity select +#define SIO_LCR_SP 0x20 // stick parity +#define SIO_LCR_SB 0x40 // set break +#define SIO_LCR_DLAB 0x80 // divisor latch access bit + +// The FIFO control register +#define SIO_FCR_FCR0 0x01 // enable xmit and rcvr fifos +#define SIO_FCR_FCR1 0x02 // clear RCVR FIFO +#define SIO_FCR_FCR2 0x04 // clear XMIT FIFO + +//----------------------------------------------------------------------------- + + +//#define x_debug_uart_log_buf +#ifdef x_debug_uart_log_buf +#define x_DIAG_BUFSIZE 2048 +static char __x_log_buf[x_DIAG_BUFSIZE]; +static int x_diag_bp = 0; +#endif + + +//============================================================================= +// Compatibility with older stubs +//============================================================================= + +#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +#include // cyg_hal_gdb_interrupt + + +#ifdef __BASE + +#ifdef CYGSEM_HAL_ROM_MONITOR +#define CYG_HAL_STARTUP_ROM +#define CYG_HAL_STARTUP_ROMRAM +#undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS +#endif + +#if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#define HAL_DIAG_USES_HARDWARE +#elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN) +#define HAL_DIAG_USES_HARDWARE +#elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL +#define HAL_DIAG_USES_HARDWARE +#endif + +static channel_data_t channel = { + (uart_width*) _BASE, 0, 0 +}; + +#ifdef HAL_DIAG_USES_HARDWARE + +void hal_diag_init(void) +{ + static int init = 0; + char *msg = "\n\rARM eCos\n\r"; + uart_width lcr; + + if (init++) return; + + init_duart_channel(&channel); + + while (*msg) hal_diag_write_char(*msg++); +} + +#ifdef DEBUG_DIAG +#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS) +#define DIAG_BUFSIZE 32 +#else +#define DIAG_BUFSIZE 2048 +#endif +static char diag_buffer[DIAG_BUFSIZE]; +static int diag_bp = 0; +#endif + +void hal_diag_write_char(char c) +{ + uart_width lsr; + + hal_diag_init(); + + cyg_hal_plf_duart_putc(&channel, c) + +#ifdef DEBUG_DIAG + diag_buffer[diag_bp++] = c; + if (diag_bp == DIAG_BUFSIZE) { + while (1) ; + diag_bp = 0; + } +#endif +} + +void hal_diag_read_char(char *c) +{ + *c = cyg_hal_plf_duart_getc(&channel); +} + +#else // HAL_DIAG relies on GDB + +// Initialize diag port - assume GDB channel is already set up +void hal_diag_init(void) +{ + if (0) init_duart_channel(&channel); // avoid warning +} + +// Actually send character down the wire +static void hal_diag_write_char_serial(char c) +{ + cyg_hal_plf_duart_putc(&channel, c); +} + +static bool hal_diag_read_serial(char *c) +{ + long timeout = 1000000000; // A long time... + + while (!cyg_hal_plf_duart_getc_nonblock(&channel, c)) + if (0 == --timeout) return false; + + return true; +} + +void hal_diag_read_char(char *c) +{ + while (!hal_diag_read_serial(c)) ; +} + +void hal_diag_write_char(char c) +{ + static char line[100]; + static int pos = 0; + + // No need to send CRs + if (c == '\r') return; + + line[pos++] = c; + + if (c == '\n' || pos == sizeof(line)) { + CYG_INTERRUPT_STATE old; + + // Disable interrupts. This prevents GDB trying to interrupt us + // while we are in the middle of sending a packet. The serial + // receive interrupt will be seen when we re-enable interrupts + // later. + +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old); +#else + HAL_DISABLE_INTERRUPTS(old); +#endif + + while (1) { + static char hex[] = "0123456789ABCDEF"; + cyg_uint8 csum = 0; + int i; + char c1; + + hal_diag_write_char_serial('$'); + hal_diag_write_char_serial('O'); + csum += 'O'; + for (i = 0; i < pos; i++) { + char ch = line[i]; + char h = hex[(ch>>4)&0xF]; + char l = hex[ch&0xF]; + hal_diag_write_char_serial(h); + hal_diag_write_char_serial(l); + csum += h; + csum += l; + } + hal_diag_write_char_serial('#'); + hal_diag_write_char_serial(hex[(csum>>4)&0xF]); + hal_diag_write_char_serial(hex[csum&0xF]); + + // Wait for the ACK character '+' from GDB here and handle + // receiving a ^C instead. This is the reason for this clause + // being a loop. + if (!hal_diag_read_serial(&c1)) + continue; // No response - try sending packet again + + if ( c1 == '+' ) + break; // a good acknowledge + +#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT + cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT); + if ( c1 == 3 ) { + // Ctrl-C: breakpoint. + cyg_hal_gdb_interrupt (__builtin_return_address(0)); + break; + } +#endif + // otherwise, loop round again + } + + pos = 0; + + // And re-enable interrupts +#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS + CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old); +#else + HAL_RESTORE_INTERRUPTS(old); +#endif + + } +} +#endif + +#endif // __BASE + +#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG + +/*---------------------------------------------------------------------------*/ diff --git a/packages/hal/arm/mx37/stk5/v1_0/src/tx37_misc.c b/packages/hal/arm/mx37/stk5/v1_0/src/tx37_misc.c new file mode 100644 index 00000000..dd257228 --- /dev/null +++ b/packages/hal/arm/mx37/stk5/v1_0/src/tx37_misc.c @@ -0,0 +1,487 @@ +//========================================================================== +// +// tx37_misc.c +// +// HAL misc board support code for the TX37 board +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================*/ + +#include +#include +#include +#include CYGBLD_HAL_PLATFORM_H + +#include // base types +#include // tracing macros +#include // assertion macros + +#include // IO macros +#include // Register state info +#include +#include // Interrupt names +#include +#include // Hardware definitions +#include // Platform specifics +//#include +#include // diag_printf + +// All the MM table layout is here: +#include + +externC void* memset(void *, int, size_t); + +volatile void *gpio_mcu1 = (volatile void *)GPIO1_BASE_ADDR; +volatile void *gpio_mcu2 = (volatile void *)GPIO2_BASE_ADDR; +volatile void *gpio_mcu3 = (volatile void *)GPIO3_BASE_ADDR; +volatile void *iomux = (volatile void *)IOMUXC_BASE_ADDR; + +/* point to Data Direction Registers (DDIR) of all GPIO ports */ +static volatile cyg_uint32 *const data_dir_reg_ptr_array[3] = { + (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4), + (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4), + (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4) +}; + +/* point to Data Registers (DR) of all GPIO ports */ +static volatile unsigned int *const data_reg_ptr_array[3] = { + (cyg_uint32 *) GPIO1_BASE_ADDR, + (cyg_uint32 *) GPIO2_BASE_ADDR, + (cyg_uint32 *) GPIO3_BASE_ADDR +}; + +/* point to Pad Status Registers (PSR) of all GPIO ports */ +static volatile unsigned int *const pad_status_reg_ptr_array[3] = { + (cyg_uint32 *) ((cyg_uint32) GPIO1_BASE_ADDR + 4 * 2), + (cyg_uint32 *) ((cyg_uint32) GPIO2_BASE_ADDR + 4 * 2), + (cyg_uint32 *) ((cyg_uint32) GPIO3_BASE_ADDR + 4 * 2) +}; + +/* point to IOMUX SW MUX Control Registers*/ +static volatile unsigned int *const iomux_sw_mux_ctrl_reg_array[3] = { + (cyg_uint32 *) ((cyg_uint32) IOMUXC_BASE_ADDR + 0x0008), //the offset of sw_mux_ctrl_reg_array is 0x0004 + (cyg_uint32 *) ((cyg_uint32) IOMUXC_BASE_ADDR + 0x0230), //the offset of sw_pad_ctrl_reg_array is 0x0328 + (cyg_uint32 *) ((cyg_uint32) IOMUXC_BASE_ADDR + 0x0508), //the offset of daisy_sel_in_reg_array is 0x07AC +}; + +#if 1 +#define UARO_URXD 0x00 +#define UARO_UTXD 0x40 +#define UARO_UCR1 0x80 +#define UARO_UCR2 0x84 +#define UARO_UCR3 0x88 +#define UARO_UCR4 0x8c +#define UARO_UFCR 0x90 +#define UARO_USR1 0x94 +#define UARO_USR2 0x98 +#define UARO_UESC 0x9c +#define UARO_UTIM 0xa0 +#define UARO_UBIR 0xa4 +#define UARO_UBMR 0xa8 +#define UARO_UBRC 0xac +#define UARO_ONEMS 0xb0 +#define UARO_UTS 0xb4 + +void plf_uart_init(void) +{ + unsigned long val; + unsigned long UartRefFreq; + + // UART1 + //RXD + writel(0x0, IOMUXC_BASE_ADDR + 0x15C); + writel(0x4, IOMUXC_BASE_ADDR + 0x604); + writel(0x1C5, IOMUXC_BASE_ADDR + 0x3BC); + + //TXD + writel(0x0, IOMUXC_BASE_ADDR + 0x160); + writel(0x1C5, IOMUXC_BASE_ADDR + 0x3C0); + + //RTS + writel(0x0, IOMUXC_BASE_ADDR + 0x164); + writel(0x4, IOMUXC_BASE_ADDR + 0x600); + writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C4); + + //CTS + writel(0x0, IOMUXC_BASE_ADDR + 0x168); + writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C8); + + /* Wait for UART to finish transmitting */ + while (!(readl(UART1_BASE_ADDR + UARO_UTS) & 0x40)); + + /* Disable UART */ + val = readl(UART1_BASE_ADDR + UARO_UCR1); + writel(val & 0xfffffffe, UART1_BASE_ADDR + UARO_UCR1); /* reset UARTEN */ + + /* Set to default POR state */ + writel(0x00000000, UART1_BASE_ADDR + UARO_UCR1); + writel(0x00000000, UART1_BASE_ADDR + UARO_UCR2); + + while (!(readl(UART1_BASE_ADDR + UARO_UCR2) & 1)); /* wait for SRST = 1 */ + + writel(0x00000704, UART1_BASE_ADDR + UARO_UCR3); + writel(0x00008000, UART1_BASE_ADDR + UARO_UCR4); + writel(0x00000801, UART1_BASE_ADDR + UARO_UFCR); + writel(0x0000002B, UART1_BASE_ADDR + UARO_UESC); + writel(0x00000000, UART1_BASE_ADDR + UARO_UTIM); + writel(0x00000000, UART1_BASE_ADDR + UARO_UBIR); + writel(0x00000000, UART1_BASE_ADDR + UARO_UBMR); + writel(0x00000000, UART1_BASE_ADDR + UARO_ONEMS); + writel(0x00000000, UART1_BASE_ADDR + UARO_UTS); + + /* Configure FIFOs */ + writel((1 << 0) | (4 << 7) | (2 << 10), UART1_BASE_ADDR + UARO_UFCR); + UartRefFreq = 66500000 / 2; + + /* Setup One MS timer */ + writel((UartRefFreq / 1000), UART1_BASE_ADDR + UARO_ONEMS); + + /* Set to 8N1 */ + val = readl(UART1_BASE_ADDR + UARO_UCR2); + val &= ~(1 << 8); + val |= (1 << 5); + val |= (1 << 14); /* Ignore RTS */ + val &= ~(1 << 6); + writel(val, UART1_BASE_ADDR + UARO_UCR2); + + /* Enable UART */ + val = readl(UART1_BASE_ADDR + UARO_UCR1); + writel(val | 1, UART1_BASE_ADDR + UARO_UCR1); + + /* Enable FIFOs */ + val = readl(UART1_BASE_ADDR + UARO_UCR2); + val |= (1 << 0); + val |= (1 << 1); + val |= (1 << 2); + writel(val, UART1_BASE_ADDR + UARO_UCR2); + + /* Clear status flags */ + val = readl(UART1_BASE_ADDR + UARO_USR2); + val |= 0x9197; + writel(val, UART1_BASE_ADDR + UARO_USR2); + + /* Clear status flags */ + val = readl(UART1_BASE_ADDR + UARO_USR1); + val |= 0x9c30; + writel(val, UART1_BASE_ADDR + UARO_USR1); + + /* Set the numerator value minus one of the BRM ratio */ + writel((115200 / 100) - 1, UART1_BASE_ADDR + UARO_UBIR); + + /* Set the denominator value minus one of the BRM ratio */ + writel((UartRefFreq / 1600) - 1, UART1_BASE_ADDR + UARO_UBMR); + + writel('+', UART1_BASE_ADDR + UARO_UTXD); +} + +void plf_send_char(unsigned char c) +{ + /* Wait for UART to finish transmitting */ + while (!(readl(UART1_BASE_ADDR + UARO_UTS) & 0x40)); + + writel(c, UART1_BASE_ADDR + UARO_UTXD); +} + +void plf_send_string(const char *spt) +{ + unsigned char achar; + + while ((achar = *(spt++)) != '\0') { + plf_send_char(achar); + } +} + +void plf_printhex(unsigned long val) +{ + int i; + + for (i = 28; i >= 0; i -= 4) { + int digit = (val >> i) & 0xf; + plf_send_char(digit + ((digit < 10) ? '0' : ('A' - 10))); + } +} + +void plf_dumpmem(unsigned long addr, int len) +{ + int i; + + for (i = 0; i < len; i += 4) { + unsigned long *wp = (unsigned long *)(addr + i); + if (i % 16 == 0) { + plf_send_char('\r'); + plf_send_char('\n'); + plf_printhex(addr + i); + plf_send_char(' '); + } + plf_printhex(*wp); + plf_send_char(' '); + } + if (i % 16 == 0) { + plf_send_char('\r'); + plf_send_char('\n'); + } +} + +void hal_mmu_check(void) +{ + unsigned long cr0, cr1; + + asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(cr0) /*:*/); + asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(cr1) /*:*/); + plf_printhex(cr0); + plf_send_char(' '); + plf_printhex(cr1); + plf_send_char('\r'); + plf_send_char('\n'); +} + +#define DBG_FUNC() do { \ + plf_send_string(__FUNCTION__); \ + plf_send_char('\r'); \ + plf_send_char('\n'); \ + } while (0) +#endif + +void hal_mmu_init(void) +{ + unsigned long ttb_base = RAM_BANK0_BASE + 0x4000; + unsigned long i; +#ifdef DEBUG + plf_uart_init(); + DBG_FUNC(); + hal_mmu_check(); +#endif + /* + * Set the TTB register + */ + asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ttb_base) /*:*/); + + /* + * Set the Domain Access Control Register + */ + i = ARM_ACCESS_DACR_DEFAULT; + asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(i) /*:*/); + + /* + * First clear all TT entries - ie Set them to Faulting + */ + memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); + + /* Physical Virtual Size Attributes Function */ + /* Base Base MB cached? buffered? access permissions */ + /* xxx00000 xxx00000 */ + X_ARM_MMU_SECTION(0x000, 0x200, 0x200, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */ + X_ARM_MMU_SECTION(0x100, 0x100, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IRAM */ + X_ARM_MMU_SECTION(0x400, 0x000, TX37_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */ + X_ARM_MMU_SECTION(0x400, 0x400, TX37_SDRAM_SIZE >> 20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */ + X_ARM_MMU_SECTION(0x7ff, 0x7ff, 0x001, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* NAND Flash buffer */ + X_ARM_MMU_SECTION(0x800, 0x800, 0x020, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* IPUv3D */ + X_ARM_MMU_SECTION(0xB00, 0xB00, 0x400, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* periperals */ + +#ifdef DEBUG +#if 1 + plf_printhex(ttb_base); + plf_send_char('\r'); + plf_send_char('\n'); +#endif +#if 0 + plf_dumpmem(ttb_base, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE); +#endif +#if 1 + plf_dumpmem(0xc3fa8000, 0x1000); +#endif +#if 0 + plf_dumpmem(0xc3fa8000, 0x1000); + plf_dumpmem(0xc3fa8000, 0x1000); + plf_dumpmem(0xc3fa8000, 0x1000); +#endif +#endif +} + +// +// Platform specific initialization +// + +void plf_hardware_init(void) +{ + unsigned int v; + +#ifdef DEBUG + DBG_FUNC(); + hal_mmu_check(); +#endif + v = 0x0040174A; // modified + writel(v, NFC_FLASH_CONFIG2_REG); + + writel(0xFFFF0000, UNLOCK_BLK_ADD0_REG); + writel(0xFFFF0000, UNLOCK_BLK_ADD1_REG); + writel(0xFFFF0000, UNLOCK_BLK_ADD2_REG); + writel(0xFFFF0000, UNLOCK_BLK_ADD3_REG); + + v = NFC_WR_PROT_CS0 | NFC_WR_PROT_BLS_UNLOCK | NFC_WR_PROT_WPC; + writel(v, NFC_WR_PROT_REG); + + writel(0, NFC_IPC_REG); +#if 0 + /* PBC setup */ + //Enable UART transceivers also reset the Ethernet/external UART + temp = readw(PBC_BASE + PBC_BCTRL1); + + writew(0x8023, PBC_BASE + PBC_BCTRL1); + + for (i = 0; i < 100000; i++) { + } + + // clear the reset, toggle the LEDs + writew(0xDF, PBC_BASE + PBC_BCTRL1_CLR); + + for (i = 0; i < 100000; i++) { + } + + dummy = readb(0xB4000008); + dummy = readb(0xB4000007); + dummy = readb(0xB4000008); + dummy = readb(0xB4000007); +#endif + +#if 0 + /* Reset interrupt status reg */ + writew(0x1F, PBC_INT_REST); + writew(0x00, PBC_INT_REST); + writew(0xFFFF, PBC_INT_MASK); +#endif + // UART1 + //RXD + writel(0x0, IOMUXC_BASE_ADDR + 0x15C); + writel(0x4, IOMUXC_BASE_ADDR + 0x604); + writel(0x1C5, IOMUXC_BASE_ADDR + 0x3BC); + + //TXD + writel(0x0, IOMUXC_BASE_ADDR + 0x160); + writel(0x1C5, IOMUXC_BASE_ADDR + 0x3C0); + + //RTS + writel(0x0, IOMUXC_BASE_ADDR + 0x164); + writel(0x4, IOMUXC_BASE_ADDR + 0x600); + writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C4); + + //CTS + writel(0x0, IOMUXC_BASE_ADDR + 0x168); + writel(0x1C4, IOMUXC_BASE_ADDR + 0x3C8); +} + +#if 0 +static void configure_gpio(cyg_uint32 port, cyg_uint32 pin, + cyg_uint32 io_select, cyg_uint32 dir) +{ + cyg_uint32 tmp, rnum, roffset, cfg_val; + + if ((io_select & 0x200) == 0x200) { + rnum = (io_select >> 12) & 0xff; + roffset = (io_select >> 10) & 0x3; + cfg_val = (io_select & 0xff); + tmp = iomux_sw_mux_ctrl_reg_array[port][rnum]; + tmp &= ~(0xff << (roffset * 8)); + tmp |= (cfg_val << (roffset * 8)); + iomux_sw_mux_ctrl_reg_array[port][rnum] = tmp; + } + if ((io_select & 0x100) == 0x100) { + /* Configure the direction of GPIO */ + if (dir) { + *data_dir_reg_ptr_array[port] |= (1 << pin); + } else { + *data_dir_reg_ptr_array[port] &= ~(1 << pin); + } + } +} + +static void configure_pad(cyg_uint32 port, cyg_uint32 reg_index, cyg_uint32 val) +{ + iomux_sw_mux_ctrl_reg_array[port][reg_index] = val; +} +#endif + +#include CYGHWR_MEMORY_LAYOUT_H + +typedef void code_fun(void); + +void board_program_new_stack(void *func) +{ + register CYG_ADDRESS stack_ptr asm("sp"); + register CYG_ADDRESS old_stack asm("r4"); + register code_fun *new_func asm("r0"); + old_stack = stack_ptr; + stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS); + new_func = (code_fun*)func; + new_func(); + stack_ptr = old_stack; +} + +#define SRC_SRSR 0x08 + +static void display_board_info(void) +{ + char *reset_cause = "UNKNOWN"; + CYG_WORD32 srsr; + + DBG_FUNC(); + diag_printf("\nBoard Type: Ka-Ro TX37\n"); + + HAL_READ_UINT32(SRC_BASE_ADDR + SRC_SRSR, srsr); + switch (srsr) { + case (1 << 0): + reset_cause = "POWER_ON RESET"; + break; + case (1 << 2): + reset_cause = "EXTERNAL RESET"; + break; + case (1 << 3): + reset_cause = "COLD RESET"; + break; + case (1 << 4): + reset_cause = "WATCHDOG RESET"; + break; + case (1 << 5): + reset_cause = "JTAG RESET"; + break; + case (1 << 16): + reset_cause = "SOFT RESET"; + break; + } + + diag_printf("Last RESET cause: %s\n", reset_cause); +} + +RedBoot_init(display_board_info, RedBoot_INIT_LAST); -- 2.39.2