arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c

   1 /*
   2  * Freescale i.MX28 RAM init
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <config.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/iomux-mx28.h>
  30 #include <asm/arch/imx-regs.h>
  31
  32 #include "mx28_init.h"
  33
  34 extern void mx28_ddr2_setup(void) __attribute__((weak,
  35                 alias("mx28_ddr2_setup_missing")));
  36
  37 static void mx28_ddr2_setup_missing(void)
  38 {
  39         serial_puts("platform specific mx28_ddr_setup() is missing\n");
  40 }
  41
  42 static void mx28_mem_init_clock(void)
  43 {
  44         struct mx28_clkctrl_regs *clkctrl_regs =
  45                 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
  46
  47         /* Gate EMI clock */
  48         writel(CLKCTRL_FRAC0_CLKGATEEMI,
  49                 &clkctrl_regs->hw_clkctrl_frac0_set);
  50
  51         /* EMI = 205MHz */
  52         writel(CLKCTRL_FRAC0_EMIFRAC_MASK,
  53                 &clkctrl_regs->hw_clkctrl_frac0_set);
  54         writel((~21 << CLKCTRL_FRAC0_EMIFRAC_OFFSET) &
  55                 CLKCTRL_FRAC0_EMIFRAC_MASK,
  56                 &clkctrl_regs->hw_clkctrl_frac0_clr);
  57
  58         /* Ungate EMI clock */
  59         writel(CLKCTRL_FRAC0_CLKGATEEMI,
  60                 &clkctrl_regs->hw_clkctrl_frac0_clr);
  61
  62         early_delay(11000);
  63
  64         writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) |
  65                 (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET),
  66                 &clkctrl_regs->hw_clkctrl_emi);
  67
  68         /* Unbypass EMI */
  69         writel(CLKCTRL_CLKSEQ_BYPASS_EMI,
  70                 &clkctrl_regs->hw_clkctrl_clkseq_clr);
  71
  72         early_delay(10000);
  73 }
  74
  75 static void mx28_mem_setup_cpu_and_hbus(void)
  76 {
  77         struct mx28_clkctrl_regs *clkctrl_regs =
  78                 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
  79
  80         /* CPU = 454MHz and ungate CPU clock */
  81         clrsetbits_le32(&clkctrl_regs->hw_clkctrl_frac0,
  82                 CLKCTRL_FRAC0_CPUFRAC_MASK | CLKCTRL_FRAC0_CLKGATECPU,
  83                 19 << CLKCTRL_FRAC0_CPUFRAC_OFFSET);
  84
  85         /* Set CPU bypass */
  86         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  87                 &clkctrl_regs->hw_clkctrl_clkseq_set);
  88
  89         /* HBUS = 151MHz */
  90         writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set);
  91         writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK,
  92                 &clkctrl_regs->hw_clkctrl_hbus_clr);
  93
  94         early_delay(10000);
  95
  96         /* CPU clock divider = 1 */
  97         clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu,
  98                         CLKCTRL_CPU_DIV_CPU_MASK, 1);
  99
 100         /* Disable CPU bypass */
 101         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
 102                 &clkctrl_regs->hw_clkctrl_clkseq_clr);
 103 }
 104
 105 static void mx28_mem_setup_vdda(void)
 106 {
 107         struct mx28_power_regs *power_regs =
 108                 (struct mx28_power_regs *)MXS_POWER_BASE;
 109
 110         writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
 111                 (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
 112                 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
 113                 &power_regs->hw_power_vddactrl);
 114 }
 115
 116 static void mx28_mem_setup_vddd(void)
 117 {
 118         struct mx28_power_regs *power_regs =
 119                 (struct mx28_power_regs *)MXS_POWER_BASE;
 120
 121         writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
 122                 (0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
 123                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
 124                 &power_regs->hw_power_vdddctrl);
 125 }
 126
 127 #define HW_DIGCTRL_SCRATCH0     0x8001c280
 128 #define HW_DIGCTRL_SCRATCH1     0x8001c290
 129 static void data_abort_memdetect_handler(void) __attribute__((naked));
 130 static void data_abort_memdetect_handler(void)
 131 {
 132         asm volatile("subs pc, r14, #4");
 133 }
 134
 135 static void mx28_mem_get_size(void)
 136 {
 137         uint32_t sz, da;
 138         uint32_t *vt = (uint32_t *)0x20;
 139
 140         /* Replace the DABT handler. */
 141         da = vt[4];
 142         vt[4] = (uint32_t)&data_abort_memdetect_handler;
 143
 144         sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
 145         writel(sz, HW_DIGCTRL_SCRATCH0);
 146         writel(sz, HW_DIGCTRL_SCRATCH1);
 147
 148         /* Restore the old DABT handler. */
 149         vt[4] = da;
 150 }
 151
 152 void mx28_mem_init(void)
 153 {
 154         struct mx28_clkctrl_regs *clkctrl_regs =
 155                 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 156         struct mx28_pinctrl_regs *pinctrl_regs =
 157                 (struct mx28_pinctrl_regs *)MXS_PINCTRL_BASE;
 158
 159         /* Set DDR2 mode */
 160         writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
 161                 &pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
 162
 163         /* Power up PLL0 */
 164         writel(CLKCTRL_PLL0CTRL0_POWER,
 165                 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
 166
 167         early_delay(11000);
 168
 169         mx28_mem_init_clock();
 170
 171         mx28_mem_setup_vdda();
 172
 173         /*
 174          * Configure the DRAM registers
 175          */
 176
 177         /* Clear START bit from DRAM_CTL16 */
 178         clrbits_le32(MXS_DRAM_BASE + 0x40, 1);
 179
 180         mx28_ddr2_setup();
 181
 182         /* Clear SREFRESH bit from DRAM_CTL17 */
 183         clrbits_le32(MXS_DRAM_BASE + 0x44, 1);
 184
 185         /* Set START bit in DRAM_CTL16 */
 186         setbits_le32(MXS_DRAM_BASE + 0x40, 1);
 187
 188         /* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
 189         while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
 190                 ;
 191
 192         mx28_mem_setup_vddd();
 193
 194         early_delay(10000);
 195
 196         mx28_mem_setup_cpu_and_hbus();
 197
 198         mx28_mem_get_size();
 199 }