arch/arm/cpu/arm926ejs/mx28/spl_power_init.c

   1 /*
   2  * Freescale i.MX28 Boot PMIC init
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <config.h>
  28 #include <asm/io.h>
  29 #include <asm/arch/imx-regs.h>
  30
  31 #include "mx28_init.h"
  32
  33 #ifdef CONFIG_SYS_SPL_VDDD_VAL
  34 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
  35 #else
  36 #define VDDD_VAL        1350
  37 #endif
  38 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
  39 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
  40 #else
  41 #define VDDIO_VAL       3300
  42 #endif
  43 #ifdef CONFIG_SYS_SPL_VDDA_VAL
  44 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
  45 #else
  46 #define VDDA_VAL        1800
  47 #endif
  48 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
  49 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
  50 #else
  51 #define VDDMEM_VAL      1500
  52 #endif
  53
  54 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
  55 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
  56 #else
  57 #define VDDD_BO_VAL     150
  58 #endif
  59 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
  60 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
  61 #else
  62 #define VDDIO_BO_VAL    150
  63 #endif
  64 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
  65 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
  66 #else
  67 #define VDDA_BO_VAL     175
  68 #endif
  69 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
  70 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
  71 #else
  72 #define VDDMEM_BO_VAL   25
  73 #endif
  74
  75 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
  76 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
  77 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
  78 #endif
  79 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
  80 #else
  81 /* Brownout default at 3V */
  82 #define BATT_BO_VAL     ((3000 - 2400) / 40)
  83 #endif
  84
  85 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
  86 static const int fixed_batt_supply = 1;
  87 #else
  88 static const int fixed_batt_supply;
  89 #endif
  90
  91 static struct mx28_power_regs *power_regs = (void *)MXS_POWER_BASE;
  92
  93 static void mx28_power_clock2xtal(void)
  94 {
  95         struct mx28_clkctrl_regs *clkctrl_regs =
  96                 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
  97
  98         /* Set XTAL as CPU reference clock */
  99         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
 100                 &clkctrl_regs->hw_clkctrl_clkseq_set);
 101 }
 102
 103 static void mx28_power_clock2pll(void)
 104 {
 105         struct mx28_clkctrl_regs *clkctrl_regs =
 106                 (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
 107
 108         writel(CLKCTRL_PLL0CTRL0_POWER,
 109                 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
 110         early_delay(100);
 111         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
 112                 &clkctrl_regs->hw_clkctrl_clkseq_clr);
 113 }
 114
 115 static void mx28_power_clear_auto_restart(void)
 116 {
 117         struct mx28_rtc_regs *rtc_regs =
 118                 (struct mx28_rtc_regs *)MXS_RTC_BASE;
 119
 120         writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr);
 121         while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST)
 122                 ;
 123
 124         writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
 125         while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
 126                 ;
 127
 128         /*
 129          * Due to the hardware design bug of mx28 EVK-A
 130          * we need to set the AUTO_RESTART bit.
 131          */
 132         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
 133                 return;
 134
 135         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
 136                 ;
 137
 138         setbits_le32(&rtc_regs->hw_rtc_persistent0,
 139                         RTC_PERSISTENT0_AUTO_RESTART);
 140         writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
 141         writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
 142         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
 143                 ;
 144         while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
 145                 ;
 146 }
 147
 148 static void mx28_power_set_linreg(void)
 149 {
 150         /* Set linear regulator 25mV below switching converter */
 151         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 152                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 153                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 154
 155         clrsetbits_le32(&power_regs->hw_power_vddactrl,
 156                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
 157                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
 158
 159         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 160                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
 161                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 162 }
 163
 164 static void mx28_power_setup_5v_detect(void)
 165 {
 166         /* Start 5V detection */
 167         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 168                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
 169                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
 170                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
 171 }
 172
 173 static void mx28_src_power_init(void)
 174 {
 175         /* Improve efficieny and reduce transient ripple */
 176         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
 177                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
 178
 179         clrsetbits_le32(&power_regs->hw_power_dclimits,
 180                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
 181                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
 182
 183         if (!fixed_batt_supply) {
 184                 /* FIXME: This requires the LRADC to be set up! */
 185                 setbits_le32(&power_regs->hw_power_battmonitor,
 186                         POWER_BATTMONITOR_EN_BATADJ);
 187         } else {
 188                 clrbits_le32(&power_regs->hw_power_battmonitor,
 189                         POWER_BATTMONITOR_EN_BATADJ);
 190         }
 191
 192         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
 193         clrsetbits_le32(&power_regs->hw_power_loopctrl,
 194                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
 195                         POWER_LOOPCTRL_RCSCALE_THRESH |
 196                         POWER_LOOPCTRL_EN_RCSCALE_8X);
 197
 198         clrsetbits_le32(&power_regs->hw_power_minpwr,
 199                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 200
 201         if (!fixed_batt_supply) {
 202                 /* 5V to battery handoff ... FIXME */
 203                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 204                 early_delay(30);
 205                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 206         }
 207 }
 208
 209 static void mx28_power_init_4p2_params(void)
 210 {
 211         /* Setup 4P2 parameters */
 212         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 213                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
 214                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
 215
 216         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 217                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
 218                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
 219
 220         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 221                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
 222                 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
 223                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
 224
 225         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 226                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 227                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 228 }
 229
 230 static void mx28_enable_4p2_dcdc_input(int xfer)
 231 {
 232         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
 233         uint32_t prev_5v_brnout, prev_5v_droop;
 234
 235         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
 236                                 POWER_5VCTRL_PWDN_5VBRNOUT;
 237         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
 238                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
 239
 240         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 241         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 242                 &power_regs->hw_power_reset);
 243
 244         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
 245
 246         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
 247                         POWER_5VCTRL_ENABLE_DCDC)) {
 248                 return;
 249         }
 250
 251         /*
 252          * Recording orignal values that will be modified temporarlily
 253          * to handle a chip bug. See chip errata for CQ ENGR00115837
 254          */
 255         tmp = readl(&power_regs->hw_power_5vctrl);
 256         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
 257         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
 258
 259         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
 260
 261         /*
 262          * Disable mechanisms that get erroneously tripped by when setting
 263          * the DCDC4P2 EN_DCDC
 264          */
 265         clrbits_le32(&power_regs->hw_power_5vctrl,
 266                 POWER_5VCTRL_VBUSVALID_5VDETECT |
 267                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
 268
 269         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
 270
 271         if (xfer) {
 272                 setbits_le32(&power_regs->hw_power_5vctrl,
 273                                 POWER_5VCTRL_DCDC_XFER);
 274                 early_delay(20);
 275                 clrbits_le32(&power_regs->hw_power_5vctrl,
 276                                 POWER_5VCTRL_DCDC_XFER);
 277
 278                 setbits_le32(&power_regs->hw_power_5vctrl,
 279                                 POWER_5VCTRL_ENABLE_DCDC);
 280         } else {
 281                 setbits_le32(&power_regs->hw_power_dcdc4p2,
 282                                 POWER_DCDC4P2_ENABLE_DCDC);
 283         }
 284
 285         early_delay(25);
 286
 287         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 288                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
 289
 290         if (vbus_5vdetect)
 291                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
 292
 293         if (!pwd_bo)
 294                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 295
 296         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
 297                 writel(POWER_CTRL_VBUS_VALID_IRQ,
 298                         &power_regs->hw_power_ctrl_clr);
 299
 300         if (prev_5v_brnout) {
 301                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 302                         &power_regs->hw_power_5vctrl_set);
 303                 writel(POWER_RESET_UNLOCK_KEY,
 304                         &power_regs->hw_power_reset);
 305         } else {
 306                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 307                         &power_regs->hw_power_5vctrl_clr);
 308                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 309                         &power_regs->hw_power_reset);
 310         }
 311
 312         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
 313                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
 314                         &power_regs->hw_power_ctrl_clr);
 315
 316         if (prev_5v_droop)
 317                 clrbits_le32(&power_regs->hw_power_ctrl,
 318                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 319         else
 320                 setbits_le32(&power_regs->hw_power_ctrl,
 321                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 322 }
 323
 324 static void mx28_power_init_4p2_regulator(void)
 325 {
 326         uint32_t tmp, tmp2;
 327
 328         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
 329
 330         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
 331
 332         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 333                 &power_regs->hw_power_5vctrl_clr);
 334         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
 335
 336         /* Power up the 4p2 rail and logic/control */
 337         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 338                 &power_regs->hw_power_5vctrl_clr);
 339
 340         /*
 341          * Start charging up the 4p2 capacitor. We ramp of this charge
 342          * gradually to avoid large inrush current from the 5V cable which can
 343          * cause transients/problems
 344          */
 345         mx28_enable_4p2_dcdc_input(0);
 346
 347         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 348                 /*
 349                  * If we arrived here, we were unable to recover from mx23 chip
 350                  * errata 5837. 4P2 is disabled and sufficient battery power is
 351                  * not present. Exiting to not enable DCDC power during 5V
 352                  * connected state.
 353                  */
 354                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 355                         POWER_DCDC4P2_ENABLE_DCDC);
 356                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 357                         &power_regs->hw_power_5vctrl_set);
 358                 hang();
 359         }
 360
 361         /*
 362          * Here we set the 4p2 brownout level to something very close to 4.2V.
 363          * We then check the brownout status. If the brownout status is false,
 364          * the voltage is already close to the target voltage of 4.2V so we
 365          * can go ahead and set the 4P2 current limit to our max target limit.
 366          * If the brownout status is true, we need to ramp us the current limit
 367          * so that we don't cause large inrush current issues. We step up the
 368          * current limit until the brownout status is false or until we've
 369          * reached our maximum defined 4p2 current limit.
 370          */
 371         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 372                         POWER_DCDC4P2_BO_MASK,
 373                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
 374
 375         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
 376                 setbits_le32(&power_regs->hw_power_5vctrl,
 377                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 378         } else {
 379                 tmp = (readl(&power_regs->hw_power_5vctrl) &
 380                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
 381                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 382                 while (tmp < 0x3f) {
 383                         if (!(readl(&power_regs->hw_power_sts) &
 384                                         POWER_STS_DCDC_4P2_BO)) {
 385                                 tmp = readl(&power_regs->hw_power_5vctrl);
 386                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 387                                 early_delay(100);
 388                                 writel(tmp, &power_regs->hw_power_5vctrl);
 389                                 break;
 390                         } else {
 391                                 tmp++;
 392                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
 393                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 394                                 tmp2 |= tmp <<
 395                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 396                                 writel(tmp2, &power_regs->hw_power_5vctrl);
 397                                 early_delay(100);
 398                         }
 399                 }
 400         }
 401
 402         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 403         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 404 }
 405
 406 static void mx28_power_init_dcdc_4p2_source(void)
 407 {
 408         if (!(readl(&power_regs->hw_power_dcdc4p2) &
 409                 POWER_DCDC4P2_ENABLE_DCDC)) {
 410                 hang();
 411         }
 412
 413         mx28_enable_4p2_dcdc_input(1);
 414
 415         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 416                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 417                         POWER_DCDC4P2_ENABLE_DCDC);
 418                 writel(POWER_5VCTRL_ENABLE_DCDC,
 419                         &power_regs->hw_power_5vctrl_clr);
 420                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 421                         &power_regs->hw_power_5vctrl_set);
 422         }
 423 }
 424
 425 static void mx28_power_enable_4p2(void)
 426 {
 427         uint32_t vdddctrl, vddactrl, vddioctrl;
 428         uint32_t tmp;
 429
 430         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
 431         vddactrl = readl(&power_regs->hw_power_vddactrl);
 432         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
 433
 434         setbits_le32(&power_regs->hw_power_vdddctrl,
 435                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 436                 POWER_VDDDCTRL_PWDN_BRNOUT);
 437
 438         setbits_le32(&power_regs->hw_power_vddactrl,
 439                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 440                 POWER_VDDACTRL_PWDN_BRNOUT);
 441
 442         setbits_le32(&power_regs->hw_power_vddioctrl,
 443                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
 444
 445         mx28_power_init_4p2_params();
 446         mx28_power_init_4p2_regulator();
 447
 448         /* Shutdown battery (none present) */
 449         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 450         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 451         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
 452
 453         mx28_power_init_dcdc_4p2_source();
 454
 455         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 456         early_delay(20);
 457         writel(vddactrl, &power_regs->hw_power_vddactrl);
 458         early_delay(20);
 459         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 460
 461         /*
 462          * Check if FET is enabled on either powerout and if so,
 463          * disable load.
 464          */
 465         tmp = 0;
 466         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
 467                         POWER_VDDDCTRL_DISABLE_FET);
 468         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
 469                         POWER_VDDACTRL_DISABLE_FET);
 470         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
 471                         POWER_VDDIOCTRL_DISABLE_FET);
 472         if (tmp)
 473                 writel(POWER_CHARGE_ENABLE_LOAD,
 474                         &power_regs->hw_power_charge_clr);
 475 }
 476
 477 static void mx28_boot_valid_5v(void)
 478 {
 479         /*
 480          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
 481          * disconnect event. FIXME
 482          */
 483         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
 484                 &power_regs->hw_power_5vctrl_set);
 485
 486         /* Configure polarity to check for 5V disconnection. */
 487         writel(POWER_CTRL_POLARITY_VBUSVALID |
 488                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
 489                 &power_regs->hw_power_ctrl_clr);
 490
 491         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
 492                 &power_regs->hw_power_ctrl_clr);
 493
 494         mx28_power_enable_4p2();
 495 }
 496
 497 static void mx28_powerdown(void)
 498 {
 499         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
 500         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 501                 &power_regs->hw_power_reset);
 502 }
 503
 504 static void mx28_handle_5v_conflict(void)
 505 {
 506         uint32_t tmp;
 507
 508         setbits_le32(&power_regs->hw_power_vddioctrl,
 509                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
 510
 511         for (;;) {
 512                 tmp = readl(&power_regs->hw_power_sts);
 513
 514                 if (tmp & POWER_STS_VDDIO_BO) {
 515                         mx28_powerdown();
 516                         break;
 517                 }
 518
 519                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
 520                         mx28_boot_valid_5v();
 521                         break;
 522                 } else {
 523                         mx28_powerdown();
 524                         break;
 525                 }
 526         }
 527 }
 528
 529 static inline int mx28_get_batt_volt(void)
 530 {
 531         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
 532
 533         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
 534         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
 535         volt *= 8;
 536         return volt;
 537 }
 538
 539 static inline int mx28_is_batt_ready(void)
 540 {
 541         return mx28_get_batt_volt() >= 3600;
 542 }
 543
 544 static void mx28_5v_boot(void)
 545 {
 546         /*
 547          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
 548          * but their implementation always returns 1 so we omit it here.
 549          */
 550         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 551                 mx28_boot_valid_5v();
 552                 return;
 553         }
 554
 555         early_delay(1000);
 556         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 557                 mx28_boot_valid_5v();
 558                 return;
 559         }
 560
 561         mx28_handle_5v_conflict();
 562 }
 563
 564 static void mx28_fixed_batt_boot(void)
 565 {
 566         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 567
 568         setbits_le32(&power_regs->hw_power_5vctrl,
 569                 POWER_5VCTRL_PWDN_5VBRNOUT |
 570                 POWER_5VCTRL_ENABLE_DCDC |
 571                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
 572                 POWER_5VCTRL_PWDN_5VBRNOUT |
 573                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 574
 575         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 576
 577         clrbits_le32(&power_regs->hw_power_vdddctrl,
 578                 POWER_VDDDCTRL_DISABLE_FET |
 579                 POWER_VDDDCTRL_ENABLE_LINREG |
 580                 POWER_VDDDCTRL_DISABLE_STEPPING);
 581
 582         clrbits_le32(&power_regs->hw_power_vddactrl,
 583                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 584                 POWER_VDDACTRL_DISABLE_STEPPING);
 585
 586         clrbits_le32(&power_regs->hw_power_vddioctrl,
 587                 POWER_VDDIOCTRL_DISABLE_FET |
 588                 POWER_VDDIOCTRL_DISABLE_STEPPING);
 589
 590         /* Stop 5V detection */
 591         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
 592                 &power_regs->hw_power_5vctrl_clr);
 593 }
 594
 595 static void mx28_init_batt_bo(void)
 596 {
 597         clrsetbits_le32(&power_regs->hw_power_battmonitor,
 598                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
 599                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
 600
 601         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 602         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 603 }
 604
 605 static void mx28_switch_vddd_to_dcdc_source(void)
 606 {
 607         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 608                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 609                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 610
 611         clrbits_le32(&power_regs->hw_power_vdddctrl,
 612                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 613                 POWER_VDDDCTRL_DISABLE_STEPPING);
 614 }
 615
 616 static inline int mx28_is_batt_good(void)
 617 {
 618         uint32_t volt;
 619
 620         volt = mx28_get_batt_volt();
 621
 622         if ((volt >= 2400) && (volt <= 4300))
 623                 return 1;
 624
 625         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 626                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 627                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 628         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 629                 &power_regs->hw_power_5vctrl_clr);
 630
 631         clrsetbits_le32(&power_regs->hw_power_charge,
 632                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 633                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
 634
 635         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
 636         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 637                 &power_regs->hw_power_5vctrl_clr);
 638
 639         early_delay(500000);
 640
 641         volt = mx28_get_batt_volt();
 642
 643         if (volt >= 3500)
 644                 return 0;
 645
 646         if (volt >= 2400)
 647                 return 1;
 648
 649         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 650                 &power_regs->hw_power_charge_clr);
 651         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 652
 653         return 0;
 654 }
 655
 656 static void mx28_power_configure_power_source(void)
 657 {
 658         mx28_src_power_init();
 659
 660         if (!fixed_batt_supply)
 661                 mx28_5v_boot();
 662         else
 663                 mx28_fixed_batt_boot();
 664
 665         mx28_power_clock2pll();
 666
 667         mx28_init_batt_bo();
 668         mx28_switch_vddd_to_dcdc_source();
 669 }
 670
 671 static void mx28_enable_output_rail_protection(void)
 672 {
 673         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 674                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 675
 676         setbits_le32(&power_regs->hw_power_vdddctrl,
 677                         POWER_VDDDCTRL_PWDN_BRNOUT);
 678
 679         setbits_le32(&power_regs->hw_power_vddactrl,
 680                         POWER_VDDACTRL_PWDN_BRNOUT);
 681
 682         setbits_le32(&power_regs->hw_power_vddioctrl,
 683                         POWER_VDDIOCTRL_PWDN_BRNOUT);
 684 }
 685
 686 static inline int mx28_get_vddio_power_source_off(void)
 687 {
 688         uint32_t tmp;
 689
 690         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
 691                 !(readl(&power_regs->hw_power_5vctrl) &
 692                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
 693
 694                 tmp = readl(&power_regs->hw_power_vddioctrl);
 695                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
 696                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 697                                 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
 698                                 return 1;
 699                         }
 700                 }
 701
 702                 if (!(readl(&power_regs->hw_power_5vctrl) &
 703                         POWER_5VCTRL_ENABLE_DCDC)) {
 704                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
 705                                 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
 706                                 return 1;
 707                         }
 708                 }
 709         }
 710
 711         return 0;
 712 }
 713
 714 static inline int mx28_get_vddd_power_source_off(void)
 715 {
 716         uint32_t tmp;
 717
 718         tmp = readl(&power_regs->hw_power_vdddctrl);
 719         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
 720                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 721                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
 722                         return 1;
 723                 }
 724         }
 725
 726         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 727                 if (!(readl(&power_regs->hw_power_5vctrl) &
 728                         POWER_5VCTRL_ENABLE_DCDC)) {
 729                         return 1;
 730                 }
 731         }
 732
 733         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
 734                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
 735                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
 736                         return 1;
 737                 }
 738         }
 739
 740         return 0;
 741 }
 742
 743 static inline int mx28_get_vdda_power_source_off(void)
 744 {
 745         uint32_t tmp;
 746
 747         tmp = readl(&power_regs->hw_power_vddactrl);
 748         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
 749                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
 750                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS)
 751                         return 1;
 752         }
 753
 754         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 755                 if (!(readl(&power_regs->hw_power_5vctrl) &
 756                         POWER_5VCTRL_ENABLE_DCDC))
 757                         return 1;
 758         }
 759
 760         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
 761                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
 762                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW)
 763                         return 1;
 764         }
 765         return 0;
 766 }
 767
 768 static inline void mx28_power_set_vddx(
 769         uint32_t new_target, uint32_t new_brownout,
 770         uint32_t *reg, const char *name,
 771         uint32_t min_trg, uint32_t max_trg,
 772         uint8_t step_size,
 773         uint32_t trg_mask, uint32_t trg_shift,
 774         uint32_t bo_mask, uint32_t bo_shift,
 775         int powered_by_linreg)
 776 {
 777         uint32_t cur_target, cur_brownout;
 778         uint32_t diff;
 779
 780         if (new_target < min_trg || new_target > max_trg)
 781                 new_target = (new_target > max_trg) ? max_trg : min_trg;
 782
 783         if (new_brownout / step_size > 7)
 784                 new_brownout = 7 * step_size;
 785
 786         cur_target = readl(reg);
 787
 788         cur_brownout = (cur_target & bo_mask) >> bo_shift;
 789         cur_brownout *= step_size;
 790
 791         cur_target = (cur_target & trg_mask) >> trg_shift;
 792         cur_target *= step_size;
 793         cur_target += min_trg;
 794         if (cur_target > max_trg)
 795                 cur_target = max_trg;
 796
 797         if (new_target == cur_target && new_brownout == cur_brownout)
 798                 return;
 799
 800         if (new_target > cur_target) {
 801                 setbits_le32(reg, bo_mask);
 802                 do {
 803                         if (new_target - cur_target > 100)
 804                                 diff = cur_target + 100;
 805                         else
 806                                 diff = new_target;
 807
 808                         diff -= min_trg;
 809                         diff /= step_size;
 810
 811                         clrsetbits_le32(reg, trg_mask, diff);
 812
 813                         if (powered_by_linreg) {
 814                                 early_delay(1500);
 815                         } else {
 816                                 while (!(readl(&power_regs->hw_power_sts) &
 817                                         POWER_STS_DC_OK)) {
 818                                 }
 819                         }
 820
 821                         cur_target = readl(reg);
 822                         cur_target &= trg_mask;
 823                         cur_target *= step_size;
 824                         cur_target += min_trg;
 825                 } while (new_target > cur_target);
 826         } else {
 827                 do {
 828                         if (cur_target - new_target > 100)
 829                                 diff = cur_target - 100;
 830                         else
 831                                 diff = new_target;
 832
 833                         diff -= min_trg;
 834                         diff /= step_size;
 835
 836                         clrsetbits_le32(reg, trg_mask, diff);
 837
 838                         if (powered_by_linreg) {
 839                                 early_delay(1500);
 840                         } else {
 841                                 while (!(readl(&power_regs->hw_power_sts) &
 842                                         POWER_STS_DC_OK)) {
 843                                 }
 844                         }
 845
 846                         cur_target = readl(reg);
 847                         cur_target &= trg_mask;
 848                         cur_target *= step_size;
 849                         cur_target += min_trg;
 850                 } while (new_target < cur_target);
 851         }
 852
 853         clrsetbits_le32(reg, bo_mask, (new_brownout / step_size) << bo_shift);
 854 }
 855
 856 #define __mx28_power_set_vddx(trg, bo, min, max, step, reg, name, lr)   \
 857         mx28_power_set_vddx(trg, bo,                                    \
 858                         &power_regs->hw_power_##reg##ctrl, #name,       \
 859                         min, max, step,                                 \
 860                         POWER_##name##CTRL_TRG_MASK,                    \
 861                         POWER_##name##CTRL_TRG_OFFSET,                  \
 862                         POWER_##name##CTRL_BO_OFFSET_MASK,              \
 863                         POWER_##name##CTRL_BO_OFFSET_OFFSET, lr)
 864
 865 static inline void mx28_power_set_vddd(uint32_t target, uint32_t brownout)
 866 {
 867         int powered_by_linreg = mx28_get_vddd_power_source_off();
 868         uint32_t bo_int = 0;
 869
 870         if (powered_by_linreg) {
 871                 bo_int = readl(&power_regs->hw_power_vdddctrl);
 872                 clrbits_le32(&power_regs->hw_power_vdddctrl,
 873                         POWER_CTRL_ENIRQ_VDDD_BO);
 874         }
 875
 876         __mx28_power_set_vddx(target, brownout, 800, 1575, 25, vddd, VDDD,
 877                         powered_by_linreg);
 878
 879         if (powered_by_linreg) {
 880                 writel(POWER_CTRL_VDDD_BO_IRQ,
 881                         &power_regs->hw_power_ctrl_clr);
 882                 if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO)
 883                         setbits_le32(&power_regs->hw_power_vdddctrl,
 884                                 POWER_CTRL_ENIRQ_VDDD_BO);
 885         }
 886 }
 887
 888 static inline void mx28_power_set_vddio(uint32_t target, uint32_t brownout)
 889 {
 890         int powered_by_linreg = mx28_get_vddio_power_source_off();
 891         uint32_t bo_int = 0;
 892
 893         if (powered_by_linreg) {
 894                 bo_int = readl(&power_regs->hw_power_vddioctrl);
 895                 clrbits_le32(&power_regs->hw_power_vddioctrl,
 896                         POWER_CTRL_ENIRQ_VDDIO_BO);
 897         }
 898         __mx28_power_set_vddx(target, brownout, 2800, 3600, 50, vddio, VDDIO,
 899                         powered_by_linreg);
 900         if (powered_by_linreg) {
 901                 writel(POWER_CTRL_VDDIO_BO_IRQ,
 902                         &power_regs->hw_power_ctrl_clr);
 903                 if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
 904                         setbits_le32(&power_regs->hw_power_vddioctrl,
 905                                 POWER_CTRL_ENIRQ_VDDIO_BO);
 906         }
 907 }
 908
 909 static inline void mx28_power_set_vdda(uint32_t target, uint32_t brownout)
 910 {
 911         int powered_by_linreg = mx28_get_vdda_power_source_off();
 912         uint32_t bo_int = 0;
 913
 914         if (powered_by_linreg) {
 915                 bo_int = readl(&power_regs->hw_power_vddioctrl);
 916                 clrbits_le32(&power_regs->hw_power_vddioctrl,
 917                         POWER_CTRL_ENIRQ_VDDIO_BO);
 918         }
 919         __mx28_power_set_vddx(target, brownout, 1500, 2275, 25, vdda, VDDA,
 920                 powered_by_linreg);
 921         if (powered_by_linreg) {
 922                 writel(POWER_CTRL_VDDIO_BO_IRQ,
 923                         &power_regs->hw_power_ctrl_clr);
 924                 if (bo_int & POWER_CTRL_ENIRQ_VDDIO_BO)
 925                         setbits_le32(&power_regs->hw_power_vddioctrl,
 926                                 POWER_CTRL_ENIRQ_VDDIO_BO);
 927         }
 928 }
 929
 930 static inline void mx28_power_set_vddmem(uint32_t target, uint32_t brownout)
 931 {
 932         __mx28_power_set_vddx(target, brownout, 1100, 1750, 25, vddmem, VDDMEM,
 933                         0);
 934
 935         clrbits_le32(&power_regs->hw_power_vddmemctrl,
 936                 POWER_VDDMEMCTRL_ENABLE_LINREG |
 937                 POWER_VDDMEMCTRL_ENABLE_ILIMIT);
 938 }
 939
 940 void mx28_power_init(void)
 941 {
 942         mx28_power_clock2xtal();
 943         mx28_power_clear_auto_restart();
 944         mx28_power_set_linreg();
 945         if (!fixed_batt_supply)
 946                 mx28_power_setup_5v_detect();
 947
 948         mx28_power_configure_power_source();
 949         mx28_enable_output_rail_protection();
 950
 951         mx28_power_set_vddio(VDDIO_VAL, VDDIO_BO_VAL);
 952
 953         mx28_power_set_vddd(VDDD_VAL, VDDD_BO_VAL);
 954
 955         mx28_power_set_vdda(VDDA_VAL, VDDA_BO_VAL);
 956
 957         mx28_power_set_vddmem(VDDMEM_VAL, VDDMEM_BO_VAL);
 958
 959         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 960                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
 961                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
 962                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 963         if (!fixed_batt_supply)
 964                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 965                         &power_regs->hw_power_5vctrl_set);
 966 }
 967
 968 #ifdef  CONFIG_SPL_MX28_PSWITCH_WAIT
 969 void mx28_power_wait_pswitch(void)
 970 {
 971         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
 972                 ;
 973 }
 974 #endif