2 * Freescale i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/arch/dma.h>
34 #include <asm/arch/gpio.h>
35 #include <asm/arch/iomux.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 /* 1 second delay should be plenty of time for block reset. */
42 #define RESET_MAX_TIMEOUT 1000000
44 #define MXS_BLOCK_SFTRST (1 << 31)
45 #define MXS_BLOCK_CLKGATE (1 << 30)
47 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
48 inline void lowlevel_init(void) {}
50 #define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \
51 RTC_PERSISTENT0_ALARM_WAKE | \
52 RTC_PERSISTENT0_THERMAL_RESET)
54 static int wait_rtc_stat(u32 mask)
58 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
59 u32 old_val = readl(&rtc_regs->hw_rtc_stat);
61 debug("stat=%x\n", old_val);
63 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
66 debug("stat: %x -> %x\n", old_val, val);
72 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
75 void reset_cpu(ulong ignored) __attribute__((noreturn));
77 void reset_cpu(ulong ignored)
79 struct mxs_rtc_regs *rtc_regs =
80 (struct mxs_rtc_regs *)MXS_RTC_BASE;
81 struct mxs_lcdif_regs *lcdif_regs =
82 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
86 * Shut down the LCD controller as it interferes with BootROM boot mode
89 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
91 reg = readl(&rtc_regs->hw_rtc_persistent0);
92 if (reg & BOOT_CAUSE_MASK) {
93 writel(reg & ~BOOT_CAUSE_MASK, &rtc_regs->hw_rtc_persistent0);
94 wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0);
97 /* Wait 1 mS before doing the actual watchdog reset */
98 writel(1, &rtc_regs->hw_rtc_watchdog);
99 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
101 /* Endless loop, reset will exit from here */
106 void enable_caches(void)
108 #ifndef CONFIG_SYS_ICACHE_OFF
111 #ifndef CONFIG_SYS_DCACHE_OFF
116 #define MX28_HW_DIGCTL_MICROSECONDS (void *)0x8001c0c0
118 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
121 uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS);
123 /* Wait for at least one microsecond for the bit mask to be set */
124 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) {
125 if ((readl(®->reg) & mask) == mask) {
126 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1)
136 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
139 uint32_t start = readl(MX28_HW_DIGCTL_MICROSECONDS);
141 /* Wait for at least one microsecond for the bit mask to be cleared */
142 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1 || --timeout) {
143 if ((readl(®->reg) & mask) == 0) {
144 while (readl(MX28_HW_DIGCTL_MICROSECONDS) - start <= 1)
154 int mxs_reset_block(struct mxs_register_32 *reg)
157 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
159 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
160 printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
161 reg, readl(®->reg));
166 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
169 writel(MXS_BLOCK_SFTRST, ®->reg_set);
171 /* Wait for CLKGATE being set */
172 if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
173 printf("TIMEOUT waiting for CLKGATE[%p] to set: %08x\n",
174 reg, readl(®->reg));
179 writel(MXS_BLOCK_SFTRST, ®->reg_clr);
181 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT)) {
182 printf("TIMEOUT waiting for SFTRST[%p] to clear: %08x\n",
183 reg, readl(®->reg));
188 writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
190 if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT)) {
191 printf("TIMEOUT waiting for CLKGATE[%p] to clear: %08x\n",
192 reg, readl(®->reg));
199 void mx28_fixup_vt(uint32_t start_addr)
201 uint32_t *vt = (uint32_t *)0x20;
204 for (i = 0; i < 8; i++)
205 vt[i] = start_addr + (4 * i);
208 #ifdef CONFIG_ARCH_MISC_INIT
209 int arch_misc_init(void)
211 mx28_fixup_vt(gd->relocaddr);
216 #ifdef CONFIG_ARCH_CPU_INIT
217 int arch_cpu_init(void)
219 struct mxs_clkctrl_regs *clkctrl_regs =
220 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
221 extern uint32_t _start;
223 mx28_fixup_vt((uint32_t)&_start);
228 /* Clear bypass bit */
229 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
230 &clkctrl_regs->hw_clkctrl_clkseq_set);
232 /* Set GPMI clock to ref_gpmi / 12 */
233 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
234 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
239 * Configure GPIO unit
243 #ifdef CONFIG_APBH_DMA
252 #if defined(CONFIG_DISPLAY_CPUINFO)
253 static const char *get_cpu_type(void)
255 struct mxs_digctl_regs *digctl_regs =
256 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
258 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
259 case HW_DIGCTL_CHIPID_MX28:
266 static const char *get_cpu_rev(void)
268 struct mxs_digctl_regs *digctl_regs =
269 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
270 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
272 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
273 case HW_DIGCTL_CHIPID_MX28:
285 int print_cpuinfo(void)
287 struct mxs_spl_data *data = (struct mxs_spl_data *)
288 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
290 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
293 mxc_get_clock(MXC_ARM_CLK) / 1000000);
294 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
299 #define pr_clk(n, c) { \
300 unsigned long clk = c; \
301 printf("%-5s %3lu.%03lu MHz\n", #n ":", clk / 1000000, \
302 clk / 1000 % 1000); \
305 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
307 pr_clk(CPU, mxc_get_clock(MXC_ARM_CLK));
308 pr_clk(APBH, mxc_get_clock(MXC_AHB_CLK));
309 pr_clk(APBX, mxc_get_clock(MXC_XBUS_CLK));
310 pr_clk(IO0, mxc_get_clock(MXC_IO0_CLK) * 1000);
311 pr_clk(IO1, mxc_get_clock(MXC_IO1_CLK) * 1000);
312 pr_clk(EMI, mxc_get_clock(MXC_EMI_CLK) * 1000000);
313 pr_clk(GPMI, mxc_get_clock(MXC_GPMI_CLK));
318 * Initializes on-chip ethernet controllers.
320 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
321 int cpu_eth_init(bd_t *bis)
323 struct mxs_clkctrl_regs *clkctrl_regs =
324 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
326 /* Turn on ENET clocks */
327 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
328 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
330 /* Set up ENET PLL for 50 MHz */
331 /* Power on ENET PLL */
332 writel(CLKCTRL_PLL2CTRL0_POWER,
333 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
338 * Enable pad output; must be done BEFORE enabling PLL
339 * according to i.MX28 Ref. Manual Rev. 1, 2010 p. 883
341 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
343 /* Gate on ENET PLL */
344 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
345 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
351 static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
354 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
356 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
360 void mx28_adjust_mac(int dev_id, unsigned char *mac)
361 __attribute__((weak, alias("__mx28_adjust_mac")));
363 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
365 #define MXS_OCOTP_MAX_TIMEOUT 1000000
366 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
368 struct mxs_ocotp_regs *ocotp_regs =
369 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
374 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
376 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
377 MXS_OCOTP_MAX_TIMEOUT)) {
378 printf("MXS FEC: Can't get MAC from OCOTP\n");
382 data = readl(&ocotp_regs->hw_ocotp_cust0);
384 mac[2] = (data >> 24) & 0xff;
385 mac[3] = (data >> 16) & 0xff;
386 mac[4] = (data >> 8) & 0xff;
387 mac[5] = data & 0xff;
388 mx28_adjust_mac(dev_id, mac);
391 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
397 int mxs_dram_init(void)
399 struct mxs_spl_data *data = (struct mxs_spl_data *)
400 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
402 if (data->mem_dram_size == 0) {
404 "Error, the RAM size passed up from SPL is 0!\n");
408 gd->ram_size = data->mem_dram_size;
413 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,