561c04db279f9161979fb23e310d3c7c295a46c0
[karo-tx-uboot.git] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c
1 /*
2  * Freescale i.MX28 Boot PMIC init
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <config.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14
15 #include "mxs_init.h"
16
17 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
18 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
19                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
20 #else
21 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
22                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
23 #endif
24 #ifdef CONFIG_SYS_SPL_VDDD_VAL
25 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
26 #else
27 #define VDDD_VAL        1350
28 #endif
29 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
30 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
31 #else
32 #define VDDIO_VAL       3300
33 #endif
34 #ifdef CONFIG_SYS_SPL_VDDA_VAL
35 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
36 #else
37 #define VDDA_VAL        1800
38 #endif
39 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
40 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
41 #else
42 #define VDDMEM_VAL      1700
43 #endif
44
45 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
46 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
47 #else
48 #define VDDD_BO_VAL     150
49 #endif
50 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
51 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
52 #else
53 #define VDDIO_BO_VAL    150
54 #endif
55 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
56 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
57 #else
58 #define VDDA_BO_VAL     175
59 #endif
60 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
61 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
62 #else
63 #define VDDMEM_BO_VAL   25
64 #endif
65
66 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
67 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
68 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
69 #endif
70 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
71 #else
72 /* Brownout default at 3V */
73 #define BATT_BO_VAL     ((3000 - 2400) / 40)
74 #endif
75
76 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
77 static const int fixed_batt_supply = 1;
78 #else
79 static const int fixed_batt_supply;
80 #endif
81
82 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
83
84 /**
85  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
86  *
87  * This function switches the CPU core clock from PLL to 24MHz XTAL
88  * oscilator. This is necessary if the PLL is being reconfigured to
89  * prevent crash of the CPU core.
90  */
91 static void mxs_power_clock2xtal(void)
92 {
93         struct mxs_clkctrl_regs *clkctrl_regs =
94                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
95
96         debug("SPL: Switching CPU clock to 24MHz XTAL\n");
97
98         /* Set XTAL as CPU reference clock */
99         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100                 &clkctrl_regs->hw_clkctrl_clkseq_set);
101 }
102
103 /**
104  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
105  *
106  * This function switches the CPU core clock from 24MHz XTAL oscilator
107  * to PLL. This can only be called once the PLL has re-locked and once
108  * the PLL is stable after reconfiguration.
109  */
110 static void mxs_power_clock2pll(void)
111 {
112         struct mxs_clkctrl_regs *clkctrl_regs =
113                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
114
115         debug("SPL: Switching CPU core clock source to PLL\n");
116
117         /*
118          * TODO: Are we really? It looks like we turn on PLL0, but we then
119          * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
120          * set by mxs_power_clock2xtal()). Clearing this bit here seems to
121          * introduce some instability (causing the CPU core to hang). Maybe
122          * we aren't giving PLL0 enough time to stabilise?
123          */
124         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
125                         CLKCTRL_PLL0CTRL0_POWER);
126         early_delay(100);
127
128         /*
129          * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
130          * wait on the PLL0 LOCK bit?
131          */
132         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
133                         CLKCTRL_CLKSEQ_BYPASS_CPU);
134 }
135
136 static int mxs_power_wait_rtc_stat(u32 mask)
137 {
138         int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
139         u32 val;
140         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
141
142         while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
143                 early_delay(1);
144                 if (timeout-- < 0)
145                         break;
146         }
147         return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
148 }
149
150 /**
151  * mxs_power_set_auto_restart() - Set the auto-restart bit
152  *
153  * This function ungates the RTC block and sets the AUTO_RESTART
154  * bit to work around a design bug on MX28EVK Rev. A .
155  */
156 static int mxs_power_set_auto_restart(int on)
157 {
158         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
159
160         debug("SPL: Setting auto-restart bit\n");
161
162         if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
163                 return 1;
164
165         /* Do nothing if flag already set */
166         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
167                 return 0;
168
169         if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
170                                 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
171                 return 0;
172
173         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
174                 return 1;
175
176         clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
177                         !on * RTC_PERSISTENT0_AUTO_RESTART,
178                         !!on * RTC_PERSISTENT0_AUTO_RESTART);
179         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
180                 return 1;
181
182         return 0;
183 }
184
185 /**
186  * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
187  *
188  * This function configures the VDDIO, VDDA and VDDD linear regulators output
189  * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
190  * converter. This is the recommended setting for the case where we use both
191  * linear regulators and DC-DC converter to power the VDDIO rail.
192  */
193 static void mxs_power_set_linreg(void)
194 {
195         /* Set linear regulator 25mV below switching converter */
196         debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
197         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
198                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
199                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
200
201         debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
202         clrsetbits_le32(&power_regs->hw_power_vddactrl,
203                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
204                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
205
206         debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
207         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
208                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
209                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
210 }
211
212 /**
213  * mxs_get_batt_volt() - Measure battery input voltage
214  *
215  * This function retrieves the battery input voltage and returns it.
216  */
217 static int mxs_get_batt_volt(void)
218 {
219         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
220
221         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
222         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
223         volt *= 8;
224
225         debug("SPL: Battery Voltage = %dmV\n", volt);
226         return volt;
227 }
228
229 /**
230  * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
231  *
232  * This function checks if the battery input voltage is higher than 3.6V and
233  * therefore allows the system to successfully boot using this power source.
234  */
235 static int mxs_is_batt_ready(void)
236 {
237         return (mxs_get_batt_volt() >= 3600);
238 }
239
240 /**
241  * mxs_is_batt_good() - Test if battery is operational at all
242  *
243  * This function starts recharging the battery and tests if the input current
244  * provided by the 5V input recharging the battery is also sufficient to power
245  * the DC-DC converter.
246  */
247 static int mxs_is_batt_good(void)
248 {
249         uint32_t volt = mxs_get_batt_volt();
250
251         if ((volt >= 2400) && (volt <= 4300)) {
252                 debug("SPL: Battery is good\n");
253                 return 1;
254         }
255
256         clrsetbits_le32(&power_regs->hw_power_5vctrl,
257                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
258                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
259         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
260                 &power_regs->hw_power_5vctrl_clr);
261
262         clrsetbits_le32(&power_regs->hw_power_charge,
263                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
264                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
265
266         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
267         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
268                 &power_regs->hw_power_5vctrl_clr);
269
270         early_delay(500000);
271
272         volt = mxs_get_batt_volt();
273
274         if (volt >= 3500) {
275                 debug("SPL: Battery Voltage too high\n");
276                 return 0;
277         }
278
279         if (volt >= 2400) {
280                 debug("SPL: Battery is good\n");
281                 return 1;
282         }
283
284         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
285                 &power_regs->hw_power_charge_clr);
286         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
287
288         if (volt >= 3500) {
289                 return 0;
290         }
291         if (volt >= 2400) {
292                 return 1;
293         }
294         debug("SPL: Battery Voltage too low\n");
295         return 0;
296 }
297
298 /**
299  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
300  *
301  * This function enables the 5V detection comparator and sets the 5V valid
302  * threshold to 4.4V . We use 4.4V threshold here to make sure that even
303  * under high load, the voltage drop on the 5V input won't be so critical
304  * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
305  * converter and thus making the system crash.
306  */
307 static void mxs_power_setup_5v_detect(void)
308 {
309         /* Start 5V detection */
310         debug("SPL: Starting 5V input detection comparator\n");
311         clrsetbits_le32(&power_regs->hw_power_5vctrl,
312                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
313                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
314                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
315 }
316
317 /**
318  * mxs_src_power_init() - Preconfigure the power block
319  *
320  * This function configures reasonable values for the DC-DC control loop
321  * and battery monitor.
322  */
323 static void mxs_src_power_init(void)
324 {
325         debug("SPL: Pre-Configuring power block\n");
326
327         /* Improve efficieny and reduce transient ripple */
328         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
329                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
330
331         clrsetbits_le32(&power_regs->hw_power_dclimits,
332                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
333                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
334
335         if (!fixed_batt_supply) {
336                 /* FIXME: This requires the LRADC to be set up! */
337                 setbits_le32(&power_regs->hw_power_battmonitor,
338                         POWER_BATTMONITOR_EN_BATADJ);
339         } else {
340                 clrbits_le32(&power_regs->hw_power_battmonitor,
341                         POWER_BATTMONITOR_EN_BATADJ);
342         }
343
344         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
345         clrsetbits_le32(&power_regs->hw_power_loopctrl,
346                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
347                         POWER_LOOPCTRL_RCSCALE_THRESH |
348                         POWER_LOOPCTRL_EN_RCSCALE_8X);
349
350         clrsetbits_le32(&power_regs->hw_power_minpwr,
351                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
352
353         if (!fixed_batt_supply) {
354                 /* 5V to battery handoff ... FIXME */
355                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
356                 early_delay(30);
357                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
358         }
359 }
360
361 /**
362  * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
363  *
364  * This function configures the necessary parameters for the 4P2 linear
365  * regulator to supply the DC-DC converter from 5V input.
366  */
367 static void mxs_power_init_4p2_params(void)
368 {
369         debug("SPL: Configuring common 4P2 regulator params\n");
370
371         /* Setup 4P2 parameters */
372         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
373                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
374                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
375
376         clrsetbits_le32(&power_regs->hw_power_5vctrl,
377                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
378                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
379
380         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
381                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
382                 DCDC4P2_DROPOUT_CONFIG);
383
384         clrsetbits_le32(&power_regs->hw_power_5vctrl,
385                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
386                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
387 }
388
389 /**
390  * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
391  * @xfer:       Select if the input shall be enabled or disabled
392  *
393  * This function enables or disables the 4P2 input into the DC-DC converter.
394  */
395 static void mxs_enable_4p2_dcdc_input(int xfer)
396 {
397         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
398         uint32_t prev_5v_brnout, prev_5v_droop;
399
400         debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
401
402         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
403                         POWER_5VCTRL_ENABLE_DCDC)) {
404                 return;
405         }
406
407         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
408                                 POWER_5VCTRL_PWDN_5VBRNOUT;
409         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
410                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
411
412         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
413         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
414                 &power_regs->hw_power_reset);
415
416         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
417
418         /*
419          * Recording orignal values that will be modified temporarlily
420          * to handle a chip bug. See chip errata for CQ ENGR00115837
421          */
422         tmp = readl(&power_regs->hw_power_5vctrl);
423         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
424         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
425
426         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
427
428         /*
429          * Disable mechanisms that get erroneously tripped by when setting
430          * the DCDC4P2 EN_DCDC
431          */
432         clrbits_le32(&power_regs->hw_power_5vctrl,
433                 POWER_5VCTRL_VBUSVALID_5VDETECT |
434                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
435
436         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
437
438         if (xfer) {
439                 setbits_le32(&power_regs->hw_power_5vctrl,
440                                 POWER_5VCTRL_DCDC_XFER);
441                 early_delay(20);
442                 clrbits_le32(&power_regs->hw_power_5vctrl,
443                                 POWER_5VCTRL_DCDC_XFER);
444
445                 setbits_le32(&power_regs->hw_power_5vctrl,
446                                 POWER_5VCTRL_ENABLE_DCDC);
447         } else {
448                 setbits_le32(&power_regs->hw_power_dcdc4p2,
449                                 POWER_DCDC4P2_ENABLE_DCDC);
450         }
451
452         early_delay(25);
453
454         clrsetbits_le32(&power_regs->hw_power_5vctrl,
455                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
456
457         if (vbus_5vdetect)
458                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
459
460         if (!pwd_bo)
461                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
462
463         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
464                 writel(POWER_CTRL_VBUS_VALID_IRQ,
465                         &power_regs->hw_power_ctrl_clr);
466
467         if (prev_5v_brnout) {
468                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
469                         &power_regs->hw_power_5vctrl_set);
470                 writel(POWER_RESET_UNLOCK_KEY,
471                         &power_regs->hw_power_reset);
472         } else {
473                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
474                         &power_regs->hw_power_5vctrl_clr);
475                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
476                         &power_regs->hw_power_reset);
477         }
478
479         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
480                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
481                         &power_regs->hw_power_ctrl_clr);
482
483         if (prev_5v_droop)
484                 clrbits_le32(&power_regs->hw_power_ctrl,
485                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
486         else
487                 setbits_le32(&power_regs->hw_power_ctrl,
488                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
489 }
490
491 /**
492  * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
493  *
494  * This function enables the 4P2 regulator and switches the DC-DC converter
495  * to use the 4P2 input.
496  */
497 static void mxs_power_init_4p2_regulator(void)
498 {
499         uint32_t tmp, tmp2;
500
501         debug("SPL: Enabling 4P2 regulator\n");
502
503         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
504
505         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
506
507         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
508                 &power_regs->hw_power_5vctrl_clr);
509         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
510
511         /* Power up the 4p2 rail and logic/control */
512         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
513                 &power_regs->hw_power_5vctrl_clr);
514
515         /*
516          * Start charging up the 4p2 capacitor. We ramp of this charge
517          * gradually to avoid large inrush current from the 5V cable which can
518          * cause transients/problems
519          */
520         debug("SPL: Charging 4P2 capacitor\n");
521         mxs_enable_4p2_dcdc_input(0);
522
523         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
524                 /*
525                  * If we arrived here, we were unable to recover from mx23 chip
526                  * errata 5837. 4P2 is disabled and sufficient battery power is
527                  * not present. Exiting to not enable DCDC power during 5V
528                  * connected state.
529                  */
530                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
531                         POWER_DCDC4P2_ENABLE_DCDC);
532                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
533                         &power_regs->hw_power_5vctrl_set);
534
535                 debug("SPL: Unable to recover from mx23 errata 5837\n");
536                 hang();
537         }
538
539         /*
540          * Here we set the 4p2 brownout level to something very close to 4.2V.
541          * We then check the brownout status. If the brownout status is false,
542          * the voltage is already close to the target voltage of 4.2V so we
543          * can go ahead and set the 4P2 current limit to our max target limit.
544          * If the brownout status is true, we need to ramp up the current limit
545          * so that we don't cause large inrush current issues. We step up the
546          * current limit until the brownout status is false or until we've
547          * reached our maximum defined 4p2 current limit.
548          */
549         debug("SPL: Setting 4P2 brownout level\n");
550         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
551                         POWER_DCDC4P2_BO_MASK,
552                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
553
554         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
555                 setbits_le32(&power_regs->hw_power_5vctrl,
556                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
557         } else {
558                 tmp = (readl(&power_regs->hw_power_5vctrl) &
559                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
560                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
561                 while (tmp < 0x3f) {
562                         if (!(readl(&power_regs->hw_power_sts) &
563                                         POWER_STS_DCDC_4P2_BO)) {
564                                 tmp = readl(&power_regs->hw_power_5vctrl);
565                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
566                                 early_delay(100);
567                                 writel(tmp, &power_regs->hw_power_5vctrl);
568                                 break;
569                         } else {
570                                 tmp++;
571                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
572                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
573                                 tmp2 |= tmp <<
574                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
575                                 writel(tmp2, &power_regs->hw_power_5vctrl);
576                                 early_delay(100);
577                         }
578                 }
579         }
580
581         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
582         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
583 }
584
585 /**
586  * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
587  *
588  * This function configures the DC-DC converter to be supplied from the 4P2
589  * linear regulator.
590  */
591 static void mxs_power_init_dcdc_4p2_source(void)
592 {
593         debug("SPL: Switching DC-DC converters to 4P2\n");
594
595         if (!(readl(&power_regs->hw_power_dcdc4p2) &
596                 POWER_DCDC4P2_ENABLE_DCDC)) {
597                 debug("SPL: Already switched - aborting\n");
598                 hang();
599         }
600
601         mxs_enable_4p2_dcdc_input(1);
602
603         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
604                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
605                         POWER_DCDC4P2_ENABLE_DCDC);
606                 writel(POWER_5VCTRL_ENABLE_DCDC,
607                         &power_regs->hw_power_5vctrl_clr);
608                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
609                         &power_regs->hw_power_5vctrl_set);
610         }
611 }
612
613 /**
614  * mxs_power_enable_4p2() - Power up the 4P2 regulator
615  *
616  * This function drives the process of powering up the 4P2 linear regulator
617  * and switching the DC-DC converter input over to the 4P2 linear regulator.
618  */
619 static void mxs_power_enable_4p2(void)
620 {
621         uint32_t vdddctrl, vddactrl, vddioctrl;
622         uint32_t tmp;
623
624         debug("SPL: Powering up 4P2 regulator\n");
625
626         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
627         vddactrl = readl(&power_regs->hw_power_vddactrl);
628         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
629
630         setbits_le32(&power_regs->hw_power_vdddctrl,
631                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
632                 POWER_VDDDCTRL_PWDN_BRNOUT);
633
634         setbits_le32(&power_regs->hw_power_vddactrl,
635                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
636                 POWER_VDDACTRL_PWDN_BRNOUT);
637
638         setbits_le32(&power_regs->hw_power_vddioctrl,
639                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
640
641         mxs_power_init_4p2_params();
642         mxs_power_init_4p2_regulator();
643
644         /* Shutdown battery (none present) */
645         if (!mxs_is_batt_ready()) {
646                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
647                                 POWER_DCDC4P2_BO_MASK);
648                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
649                                 &power_regs->hw_power_ctrl_clr);
650                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
651                                 &power_regs->hw_power_ctrl_clr);
652         }
653
654         mxs_power_init_dcdc_4p2_source();
655
656         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
657         early_delay(20);
658         writel(vddactrl, &power_regs->hw_power_vddactrl);
659         early_delay(20);
660         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
661
662         /*
663          * Check if FET is enabled on either powerout and if so,
664          * disable load.
665          */
666         tmp = 0;
667         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
668                         POWER_VDDDCTRL_DISABLE_FET);
669         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
670                         POWER_VDDACTRL_DISABLE_FET);
671         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
672                         POWER_VDDIOCTRL_DISABLE_FET);
673         if (tmp)
674                 writel(POWER_CHARGE_ENABLE_LOAD,
675                         &power_regs->hw_power_charge_clr);
676
677         debug("SPL: 4P2 regulator powered-up\n");
678 }
679
680 /**
681  * mxs_boot_valid_5v() - Boot from 5V supply
682  *
683  * This function configures the power block to boot from valid 5V input.
684  * This is called only if the 5V is reliable and can properly supply the
685  * CPU. This function proceeds to configure the 4P2 converter to be supplied
686  * from the 5V input.
687  */
688 static void mxs_boot_valid_5v(void)
689 {
690         debug("SPL: Booting from 5V supply\n");
691
692         /*
693          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
694          * disconnect event. FIXME
695          */
696         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
697                 &power_regs->hw_power_5vctrl_set);
698
699         /* Configure polarity to check for 5V disconnection. */
700         writel(POWER_CTRL_POLARITY_VBUSVALID |
701                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
702                 &power_regs->hw_power_ctrl_clr);
703
704         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
705                 &power_regs->hw_power_ctrl_clr);
706
707         mxs_power_enable_4p2();
708 }
709
710 /**
711  * mxs_powerdown() - Shut down the system
712  *
713  * This function powers down the CPU completely.
714  */
715 static void mxs_powerdown(void)
716 {
717         debug("Powering Down\n");
718
719         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
720         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
721                 &power_regs->hw_power_reset);
722 }
723
724 /**
725  * mxs_batt_boot() - Configure the power block to boot from battery input
726  *
727  * This function configures the power block to boot from the battery voltage
728  * supply.
729  */
730 static void mxs_batt_boot(void)
731 {
732         debug("SPL: Configuring power block to boot from battery\n");
733
734         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
735         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
736
737         clrbits_le32(&power_regs->hw_power_dcdc4p2,
738                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
739         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
740
741         /* 5V to battery handoff. */
742         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
743         early_delay(30);
744         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
745
746         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
747
748         clrsetbits_le32(&power_regs->hw_power_minpwr,
749                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
750
751         mxs_power_set_linreg();
752
753         clrbits_le32(&power_regs->hw_power_vdddctrl,
754                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
755
756         clrbits_le32(&power_regs->hw_power_vddactrl,
757                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
758
759         clrbits_le32(&power_regs->hw_power_vddioctrl,
760                 POWER_VDDIOCTRL_DISABLE_FET);
761
762         setbits_le32(&power_regs->hw_power_5vctrl,
763                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
764
765         setbits_le32(&power_regs->hw_power_5vctrl,
766                 POWER_5VCTRL_ENABLE_DCDC);
767
768         clrsetbits_le32(&power_regs->hw_power_5vctrl,
769                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
770                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
771
772         mxs_power_enable_4p2();
773 }
774
775 /**
776  * mxs_handle_5v_conflict() - Test if the 5V input is reliable
777  *
778  * This function tests if the 5V input can reliably supply the system. If it
779  * can, then proceed to configuring the system to boot from 5V source, otherwise
780  * try booting from battery supply. If we can not boot from battery supply
781  * either, shut down the system.
782  */
783 static void mxs_handle_5v_conflict(void)
784 {
785         uint32_t tmp;
786
787         debug("SPL: Resolving 5V conflict\n");
788
789         setbits_le32(&power_regs->hw_power_vddioctrl,
790                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
791
792         for (;;) {
793                 tmp = readl(&power_regs->hw_power_sts);
794
795                 if (tmp & POWER_STS_VDDIO_BO) {
796                         /*
797                          * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
798                          * becomes unreliable
799                          */
800                         debug("SPL: VDDIO has a brownout\n");
801                         mxs_powerdown();
802                         break;
803                 }
804
805                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
806                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
807                         mxs_boot_valid_5v();
808                         break;
809                 } else {
810                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
811                         mxs_powerdown();
812                         break;
813                 }
814
815                 /*
816                  * TODO: I can't see this being reached. We'll either
817                  * powerdown or boot from a stable 5V supply.
818                  */
819                 if (tmp & POWER_STS_PSWITCH_MASK) {
820                         debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
821                         mxs_batt_boot();
822                         break;
823                 }
824         }
825 }
826
827 /**
828  * mxs_5v_boot() - Configure the power block to boot from 5V input
829  *
830  * This function handles configuration of the power block when supplied by
831  * a 5V input.
832  */
833 static void mxs_5v_boot(void)
834 {
835         debug("SPL: Configuring power block to boot from 5V input\n");
836
837         /*
838          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
839          * but their implementation always returns 1 so we omit it here.
840          */
841         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
842                 debug("SPL: 5V VDD good\n");
843                 mxs_boot_valid_5v();
844                 return;
845         }
846
847         early_delay(1000);
848         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
849                 debug("SPL: 5V VDD good (after delay)\n");
850                 mxs_boot_valid_5v();
851                 return;
852         }
853
854         debug("SPL: 5V VDD not good\n");
855         mxs_handle_5v_conflict();
856 }
857
858 static void mxs_fixed_batt_boot(void)
859 {
860         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
861
862         setbits_le32(&power_regs->hw_power_5vctrl,
863                 POWER_5VCTRL_ENABLE_DCDC |
864                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
865                 POWER_5VCTRL_PWDN_5VBRNOUT |
866                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
867
868         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
869
870         clrbits_le32(&power_regs->hw_power_vdddctrl,
871                 POWER_VDDDCTRL_DISABLE_FET |
872                 POWER_VDDDCTRL_ENABLE_LINREG |
873                 POWER_VDDDCTRL_DISABLE_STEPPING);
874
875         clrbits_le32(&power_regs->hw_power_vddactrl,
876                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
877                 POWER_VDDACTRL_DISABLE_STEPPING);
878
879         clrbits_le32(&power_regs->hw_power_vddioctrl,
880                 POWER_VDDIOCTRL_DISABLE_FET |
881                 POWER_VDDIOCTRL_DISABLE_STEPPING);
882
883         /* Stop 5V detection */
884         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
885                 &power_regs->hw_power_5vctrl_clr);
886 }
887
888 /**
889  * mxs_init_batt_bo() - Configure battery brownout threshold
890  *
891  * This function configures the battery input brownout threshold. The value
892  * at which the battery brownout happens is configured to 3.0V in the code.
893  */
894 static void mxs_init_batt_bo(void)
895 {
896         debug("SPL: Initialising battery brown-out level to 3.0V\n");
897
898         /* Brownout at 3V */
899         clrsetbits_le32(&power_regs->hw_power_battmonitor,
900                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
901                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
902
903         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
904         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
905 }
906
907 /**
908  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
909  *
910  * This function turns off the VDDD linear regulator and therefore makes
911  * the VDDD rail be supplied only by the DC-DC converter.
912  */
913 static void mxs_switch_vddd_to_dcdc_source(void)
914 {
915         debug("SPL: Switching VDDD to DC-DC converters\n");
916
917         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
918                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
919                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
920
921         clrbits_le32(&power_regs->hw_power_vdddctrl,
922                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
923                 POWER_VDDDCTRL_DISABLE_STEPPING);
924 }
925
926 /**
927  * mxs_power_configure_power_source() - Configure power block source
928  *
929  * This function is the core of the power configuration logic. The function
930  * selects the power block input source and configures the whole power block
931  * accordingly. After the configuration is complete and the system is stable
932  * again, the function switches the CPU clock source back to PLL. Finally,
933  * the function switches the voltage rails to DC-DC converter.
934  */
935 static void mxs_power_configure_power_source(void)
936 {
937         struct mxs_lradc_regs *lradc_regs =
938                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
939
940         debug("SPL: Configuring power source\n");
941
942         mxs_src_power_init();
943
944         if (!fixed_batt_supply) {
945                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
946                         if (mxs_is_batt_ready()) {
947                                 /* 5V source detected, good battery detected. */
948                                 mxs_batt_boot();
949                         } else {
950                                 if (!mxs_is_batt_good()) {
951                                         /* 5V source detected, bad battery detected. */
952                                         writel(LRADC_CONVERSION_AUTOMATIC,
953                                                 &lradc_regs->hw_lradc_conversion_clr);
954                                         clrbits_le32(&power_regs->hw_power_battmonitor,
955                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
956                                 }
957                                 mxs_5v_boot();
958                         }
959                 } else {
960                         /* 5V not detected, booting from battery. */
961                         mxs_batt_boot();
962                 }
963         } else {
964                 mxs_fixed_batt_boot();
965         }
966
967         /*
968          * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
969          * from USB VBUS
970          */
971         mxs_power_clock2pll();
972
973         mxs_init_batt_bo();
974
975         mxs_switch_vddd_to_dcdc_source();
976
977 #ifdef CONFIG_SOC_MX23
978         /* Fire up the VDDMEM LinReg now that we're all set. */
979         debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
980         writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
981                 &power_regs->hw_power_vddmemctrl);
982 #endif
983 }
984
985 /**
986  * mxs_enable_output_rail_protection() - Enable power rail protection
987  *
988  * This function enables overload protection on the power rails. This is
989  * triggered if the power rails' voltage drops rapidly due to overload and
990  * in such case, the supply to the powerrail is cut-off, protecting the
991  * CPU from damage. Note that under such condition, the system will likely
992  * crash or misbehave.
993  */
994 static void mxs_enable_output_rail_protection(void)
995 {
996         debug("SPL: Enabling output rail protection\n");
997
998         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
999                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1000
1001         setbits_le32(&power_regs->hw_power_vdddctrl,
1002                         POWER_VDDDCTRL_PWDN_BRNOUT);
1003
1004         setbits_le32(&power_regs->hw_power_vddactrl,
1005                         POWER_VDDACTRL_PWDN_BRNOUT);
1006
1007         setbits_le32(&power_regs->hw_power_vddioctrl,
1008                         POWER_VDDIOCTRL_PWDN_BRNOUT);
1009 }
1010
1011 /**
1012  * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1013  *
1014  * This function tests if the VDDIO rail is supplied by linear regulator
1015  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1016  * returns 0 if powered by the DC-DC converter.
1017  */
1018 static int mxs_get_vddio_power_source_off(void)
1019 {
1020         uint32_t tmp;
1021
1022         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1023                 !(readl(&power_regs->hw_power_5vctrl) &
1024                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1025
1026                 tmp = readl(&power_regs->hw_power_vddioctrl);
1027                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1028                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1029                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1030                                 return 1;
1031                         }
1032                 }
1033
1034                 if (!(readl(&power_regs->hw_power_5vctrl) &
1035                         POWER_5VCTRL_ENABLE_DCDC)) {
1036                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1037                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1038                                 return 1;
1039                         }
1040                 }
1041         }
1042
1043         return 0;
1044 }
1045
1046 /**
1047  * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1048  *
1049  * This function tests if the VDDD rail is supplied by linear regulator
1050  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1051  * returns 0 if powered by the DC-DC converter.
1052  */
1053 static int mxs_get_vddd_power_source_off(void)
1054 {
1055         uint32_t tmp;
1056
1057         tmp = readl(&power_regs->hw_power_vdddctrl);
1058         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1059                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1060                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1061                         return 1;
1062                 }
1063         }
1064
1065         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1066                 if (!(readl(&power_regs->hw_power_5vctrl) &
1067                         POWER_5VCTRL_ENABLE_DCDC)) {
1068                         return 1;
1069                 }
1070         }
1071
1072         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1073                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1074                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1075                         return 1;
1076                 }
1077         }
1078
1079         return 0;
1080 }
1081
1082 static int mxs_get_vdda_power_source_off(void)
1083 {
1084         uint32_t tmp;
1085
1086         tmp = readl(&power_regs->hw_power_vddactrl);
1087         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1088                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1089                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1090                         return 1;
1091                 }
1092         }
1093
1094         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1095                 if (!(readl(&power_regs->hw_power_5vctrl) &
1096                         POWER_5VCTRL_ENABLE_DCDC)) {
1097                         return 1;
1098                 }
1099         }
1100
1101         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1102                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1103                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1104                         return 1;
1105                 }
1106         }
1107
1108         return 0;
1109 }
1110
1111 struct mxs_vddx_cfg {
1112         uint32_t                *reg;
1113         uint8_t                 step_mV;
1114         uint16_t                lowest_mV;
1115         uint16_t                highest_mV;
1116         int                     (*powered_by_linreg)(void);
1117         uint32_t                trg_mask;
1118         uint32_t                bo_irq;
1119         uint32_t                bo_enirq;
1120         uint32_t                bo_offset_mask;
1121         uint32_t                bo_offset_offset;
1122         uint16_t                bo_min_mV;
1123         uint16_t                bo_max_mV;
1124 };
1125
1126 #define POWER_REG(n)            &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1127
1128 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1129         .reg                    = POWER_REG(hw_power_vddioctrl),
1130 #if defined(CONFIG_SOC_MX23)
1131         .step_mV                = 25,
1132 #else
1133         .step_mV                = 50,
1134 #endif
1135         .lowest_mV              = 2800,
1136         .highest_mV             = 3600,
1137         .powered_by_linreg      = mxs_get_vddio_power_source_off,
1138         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
1139         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
1140         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
1141         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1142         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1143         .bo_min_mV              = 2700,
1144         .bo_max_mV              = 3475,
1145 };
1146
1147 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1148         .reg                    = POWER_REG(hw_power_vdddctrl),
1149         .step_mV                = 25,
1150         .lowest_mV              = 800,
1151         .highest_mV             = 1575,
1152         .powered_by_linreg      = mxs_get_vddd_power_source_off,
1153         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
1154         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
1155         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
1156         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
1157         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1158         .bo_min_mV              = 800,
1159         .bo_max_mV              = 1475,
1160 };
1161
1162 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1163         .reg                    = POWER_REG(hw_power_vddactrl),
1164         .step_mV                = 25,
1165         .lowest_mV              = 1800,
1166         .highest_mV             = 3600,
1167         .powered_by_linreg      = mxs_get_vdda_power_source_off,
1168         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
1169         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
1170         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
1171         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
1172         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1173         .bo_min_mV              = 1400,
1174         .bo_max_mV              = 2175,
1175 };
1176
1177 #ifdef CONFIG_SOC_MX23
1178 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1179         .reg                    = POWER_REG(hw_power_vddmemctrl),
1180         .step_mV                = 50,
1181         .lowest_mV              = 1500,
1182         .highest_mV             = 1700,
1183         .powered_by_linreg      = NULL,
1184         .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
1185         .bo_irq                 = 0,
1186         .bo_enirq               = 0,
1187         .bo_offset_mask         = 0,
1188         .bo_offset_offset       = 0,
1189 };
1190 #endif
1191
1192 /**
1193  * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1194  * @cfg:                Configuration data of the DC-DC converter rail
1195  * @new_target:         New target voltage of the DC-DC converter rail
1196  * @new_brownout:       New brownout trigger voltage
1197  *
1198  * This function configures the output voltage on the DC-DC converter rail.
1199  * The rail is selected by the @cfg argument. The new voltage target is
1200  * selected by the @new_target and the voltage is specified in mV. The
1201  * new brownout value is selected by the @new_brownout argument and the
1202  * value is also in mV.
1203  */
1204 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1205                                 uint32_t new_target, uint32_t bo_offset)
1206 {
1207         uint32_t cur_target, diff, bo_int = 0;
1208         int powered_by_linreg = 0;
1209         int adjust_up;
1210
1211         if (new_target < cfg->lowest_mV) {
1212                 new_target = cfg->lowest_mV;
1213         }
1214         if (new_target > cfg->highest_mV) {
1215                 new_target = cfg->highest_mV;
1216         }
1217
1218         if (new_target - bo_offset < cfg->bo_min_mV) {
1219                 bo_offset = new_target - cfg->bo_min_mV;
1220         } else if (new_target - bo_offset > cfg->bo_max_mV) {
1221                 bo_offset = new_target - cfg->bo_max_mV;
1222         }
1223
1224         bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1225
1226         cur_target = readl(cfg->reg);
1227         cur_target &= cfg->trg_mask;
1228         cur_target *= cfg->step_mV;
1229         cur_target += cfg->lowest_mV;
1230
1231         adjust_up = new_target > cur_target;
1232         if (cfg->powered_by_linreg)
1233                 powered_by_linreg = cfg->powered_by_linreg();
1234
1235         if (adjust_up && cfg->bo_irq) {
1236                 if (powered_by_linreg) {
1237                         bo_int = readl(&power_regs->hw_power_ctrl);
1238                         writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1239                 }
1240                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1241         }
1242
1243         do {
1244                 if (abs(new_target - cur_target) > 100) {
1245                         if (adjust_up)
1246                                 diff = cur_target + 100;
1247                         else
1248                                 diff = cur_target - 100;
1249                 } else {
1250                         diff = new_target;
1251                 }
1252
1253                 diff -= cfg->lowest_mV;
1254                 diff /= cfg->step_mV;
1255
1256                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1257
1258                 if (powered_by_linreg ||
1259                         (readl(&power_regs->hw_power_sts) &
1260                                 POWER_STS_VDD5V_GT_VDDIO)) {
1261                         early_delay(500);
1262                 } else {
1263                         while (!(readl(&power_regs->hw_power_sts) &
1264                                         POWER_STS_DC_OK)) {
1265
1266                         }
1267                 }
1268
1269                 cur_target = readl(cfg->reg);
1270                 cur_target &= cfg->trg_mask;
1271                 cur_target *= cfg->step_mV;
1272                 cur_target += cfg->lowest_mV;
1273         } while (new_target > cur_target);
1274
1275         if (cfg->bo_irq) {
1276                 if (adjust_up && powered_by_linreg) {
1277                         writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1278                         if (bo_int & cfg->bo_enirq)
1279                                 writel(cfg->bo_enirq,
1280                                         &power_regs->hw_power_ctrl_set);
1281                 }
1282
1283                 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1284                                 bo_offset << cfg->bo_offset_offset);
1285         }
1286 }
1287
1288 /**
1289  * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1290  *
1291  * This function starts and configures the LRADC block. This allows the
1292  * power initialization code to measure battery voltage and based on this
1293  * knowledge, decide whether to boot at all, boot from battery or boot
1294  * from 5V input.
1295  */
1296 static void mxs_setup_batt_detect(void)
1297 {
1298         debug("SPL: Starting battery voltage measurement logic\n");
1299
1300         mxs_lradc_init();
1301         mxs_lradc_enable_batt_measurement();
1302         early_delay(10);
1303 }
1304
1305 /**
1306  * mxs_ungate_power() - Ungate the POWER block
1307  *
1308  * This function ungates clock to the power block. In case the power block
1309  * was still gated at this point, it will not be possible to configure the
1310  * block and therefore the power initialization would fail. This function
1311  * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1312  */
1313 static void mxs_ungate_power(void)
1314 {
1315 #ifdef CONFIG_SOC_MX23
1316         writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1317 #endif
1318 }
1319
1320 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1321 #define auto_restart 1
1322 #else
1323 #define auto_restart 0
1324 #endif
1325
1326 /**
1327  * mxs_power_init() - The power block init main function
1328  *
1329  * This function calls all the power block initialization functions in
1330  * proper sequence to start the power block.
1331  */
1332 #define VDDX_VAL(v)     (v) / 1000, (v) / 100 % 10
1333
1334 void mxs_power_init(void)
1335 {
1336         debug("SPL: Initialising Power Block\n");
1337
1338         mxs_ungate_power();
1339
1340         mxs_power_clock2xtal();
1341         if (mxs_power_set_auto_restart(auto_restart)) {
1342                 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1343         }
1344         mxs_power_set_linreg();
1345
1346         if (!fixed_batt_supply) {
1347                 mxs_power_setup_5v_detect();
1348                 mxs_setup_batt_detect();
1349         }
1350
1351         mxs_power_configure_power_source();
1352         mxs_enable_output_rail_protection();
1353
1354         debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1355                 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1356         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1357         debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1358                 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1359         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1360         debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1361                 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1362         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1363 #ifdef CONFIG_SOC_MX23
1364         debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1365                 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1366         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1367 #else
1368         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1369                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1370 #endif
1371         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1372                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1373                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1374                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1375         if (!fixed_batt_supply)
1376                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1377                         &power_regs->hw_power_5vctrl_set);
1378 }
1379
1380 #ifdef  CONFIG_SPL_MXS_PSWITCH_WAIT
1381 /**
1382  * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1383  *
1384  * This function waits until the power-switch was pressed to start booting
1385  * the board.
1386  */
1387 void mxs_power_wait_pswitch(void)
1388 {
1389         debug("SPL: Waiting for power switch input\n");
1390         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1391                 ;
1392 }
1393 #endif