karo: tx6: remove unreachable 'return' statements
[karo-tx-uboot.git] / arch / arm / cpu / arm926ejs / mxs / spl_power_init.c
1 /*
2  * Freescale i.MX28 Boot PMIC init
3  *
4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5  * on behalf of DENX Software Engineering GmbH
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9
10 #include <common.h>
11 #include <config.h>
12 #include <asm/io.h>
13 #include <asm/arch/imx-regs.h>
14
15 #include "mxs_init.h"
16
17 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
18 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
19                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
20 #else
21 #define DCDC4P2_DROPOUT_CONFIG  POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
22                                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
23 #endif
24 #ifdef CONFIG_SYS_SPL_VDDD_VAL
25 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
26 #else
27 #define VDDD_VAL        1350
28 #endif
29 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
30 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
31 #else
32 #define VDDIO_VAL       3300
33 #endif
34 #ifdef CONFIG_SYS_SPL_VDDA_VAL
35 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
36 #else
37 #define VDDA_VAL        1800
38 #endif
39 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
40 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
41 #else
42 #define VDDMEM_VAL      1700
43 #endif
44
45 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
46 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
47 #else
48 #define VDDD_BO_VAL     150
49 #endif
50 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
51 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
52 #else
53 #define VDDIO_BO_VAL    150
54 #endif
55 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
56 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
57 #else
58 #define VDDA_BO_VAL     175
59 #endif
60 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
61 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
62 #else
63 #define VDDMEM_BO_VAL   25
64 #endif
65
66 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
67 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
68 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
69 #endif
70 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
71 #else
72 /* Brownout default at 3V */
73 #define BATT_BO_VAL     ((3000 - 2400) / 40)
74 #endif
75
76 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
77 static const int fixed_batt_supply = 1;
78 #else
79 static const int fixed_batt_supply;
80 #endif
81
82 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
83
84 /**
85  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
86  *
87  * This function switches the CPU core clock from PLL to 24MHz XTAL
88  * oscilator. This is necessary if the PLL is being reconfigured to
89  * prevent crash of the CPU core.
90  */
91 static void mxs_power_clock2xtal(void)
92 {
93         struct mxs_clkctrl_regs *clkctrl_regs =
94                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
95
96         debug("SPL: Switching CPU clock to 24MHz XTAL\n");
97
98         /* Set XTAL as CPU reference clock */
99         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100                 &clkctrl_regs->hw_clkctrl_clkseq_set);
101 }
102
103 /**
104  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
105  *
106  * This function switches the CPU core clock from 24MHz XTAL oscilator
107  * to PLL. This can only be called once the PLL has re-locked and once
108  * the PLL is stable after reconfiguration.
109  */
110 static void mxs_power_clock2pll(void)
111 {
112         struct mxs_clkctrl_regs *clkctrl_regs =
113                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
114
115         debug("SPL: Switching CPU core clock source to PLL\n");
116
117         /*
118          * TODO: Are we really? It looks like we turn on PLL0, but we then
119          * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
120          * set by mxs_power_clock2xtal()). Clearing this bit here seems to
121          * introduce some instability (causing the CPU core to hang). Maybe
122          * we aren't giving PLL0 enough time to stabilise?
123          */
124         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
125                         CLKCTRL_PLL0CTRL0_POWER);
126         early_delay(100);
127
128         /*
129          * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
130          * wait on the PLL0 LOCK bit?
131          */
132         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
133                         CLKCTRL_CLKSEQ_BYPASS_CPU);
134 }
135
136 static int mxs_power_wait_rtc_stat(u32 mask)
137 {
138         int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
139         u32 val;
140         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
141
142         while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
143                 early_delay(1);
144                 if (timeout-- < 0)
145                         break;
146         }
147         return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
148 }
149
150 /**
151  * mxs_power_set_auto_restart() - Set the auto-restart bit
152  *
153  * This function ungates the RTC block and sets the AUTO_RESTART
154  * bit to work around a design bug on MX28EVK Rev. A .
155  */
156 static int mxs_power_set_auto_restart(int on)
157 {
158         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
159
160         debug("SPL: Setting auto-restart bit\n");
161
162         if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
163                 return 1;
164
165         /* Do nothing if flag already set */
166         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
167                 return 0;
168
169         if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
170                                 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
171                 return 0;
172
173         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
174                 return 1;
175
176         clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
177                         !on * RTC_PERSISTENT0_AUTO_RESTART,
178                         !!on * RTC_PERSISTENT0_AUTO_RESTART);
179         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
180                 return 1;
181
182         return 0;
183 }
184
185 /**
186  * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
187  *
188  * This function configures the VDDIO, VDDA and VDDD linear regulators output
189  * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
190  * converter. This is the recommended setting for the case where we use both
191  * linear regulators and DC-DC converter to power the VDDIO rail.
192  */
193 static void mxs_power_set_linreg(void)
194 {
195         /* Set linear regulator 25mV below switching converter */
196         debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
197         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
198                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
199                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
200
201         debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
202         clrsetbits_le32(&power_regs->hw_power_vddactrl,
203                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
204                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
205
206         debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
207         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
208                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
209                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
210 }
211
212 /**
213  * mxs_get_batt_volt() - Measure battery input voltage
214  *
215  * This function retrieves the battery input voltage and returns it.
216  */
217 static int mxs_get_batt_volt(void)
218 {
219         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
220
221         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
222         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
223         volt *= 8;
224
225         debug("SPL: Battery Voltage = %dmV\n", volt);
226         return volt;
227 }
228
229 /**
230  * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
231  *
232  * This function checks if the battery input voltage is higher than 3.6V and
233  * therefore allows the system to successfully boot using this power source.
234  */
235 static int mxs_is_batt_ready(void)
236 {
237         return (mxs_get_batt_volt() >= 3600);
238 }
239
240 /**
241  * mxs_is_batt_good() - Test if battery is operational at all
242  *
243  * This function starts recharging the battery and tests if the input current
244  * provided by the 5V input recharging the battery is also sufficient to power
245  * the DC-DC converter.
246  */
247 static int mxs_is_batt_good(void)
248 {
249         uint32_t volt = mxs_get_batt_volt();
250
251         if ((volt >= 2400) && (volt <= 4300)) {
252                 debug("SPL: Battery is good\n");
253                 return 1;
254         }
255
256         clrsetbits_le32(&power_regs->hw_power_5vctrl,
257                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
258                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
259         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
260                 &power_regs->hw_power_5vctrl_clr);
261
262         clrsetbits_le32(&power_regs->hw_power_charge,
263                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
264                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
265
266         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
267         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
268                 &power_regs->hw_power_5vctrl_clr);
269
270         early_delay(500000);
271
272         volt = mxs_get_batt_volt();
273
274         if (volt >= 3500) {
275                 debug("SPL: Battery Voltage too high\n");
276                 return 0;
277         }
278
279         if (volt >= 2400) {
280                 debug("SPL: Battery is good\n");
281                 return 1;
282         }
283
284         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
285                 &power_regs->hw_power_charge_clr);
286         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
287
288         if (volt >= 3500) {
289                 return 0;
290         }
291         if (volt >= 2400) {
292                 return 1;
293         }
294         debug("SPL: Battery Voltage too low\n");
295         return 0;
296 }
297
298 /**
299  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
300  *
301  * This function enables the 5V detection comparator and sets the 5V valid
302  * threshold to 4.4V . We use 4.4V threshold here to make sure that even
303  * under high load, the voltage drop on the 5V input won't be so critical
304  * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
305  * converter and thus making the system crash.
306  */
307 static void mxs_power_setup_5v_detect(void)
308 {
309         /* Start 5V detection */
310         debug("SPL: Starting 5V input detection comparator\n");
311         clrsetbits_le32(&power_regs->hw_power_5vctrl,
312                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
313                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
314                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
315 }
316
317 /**
318  * mxs_src_power_init() - Preconfigure the power block
319  *
320  * This function configures reasonable values for the DC-DC control loop
321  * and battery monitor.
322  */
323 static void mxs_src_power_init(void)
324 {
325         debug("SPL: Pre-Configuring power block\n");
326
327         debug("SPL: Pre-Configuring power block\n");
328
329         /* Improve efficieny and reduce transient ripple */
330         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
331                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
332
333         clrsetbits_le32(&power_regs->hw_power_dclimits,
334                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
335                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
336
337         if (!fixed_batt_supply) {
338                 /* FIXME: This requires the LRADC to be set up! */
339                 setbits_le32(&power_regs->hw_power_battmonitor,
340                         POWER_BATTMONITOR_EN_BATADJ);
341         } else {
342                 clrbits_le32(&power_regs->hw_power_battmonitor,
343                         POWER_BATTMONITOR_EN_BATADJ);
344         }
345
346         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
347         clrsetbits_le32(&power_regs->hw_power_loopctrl,
348                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
349                         POWER_LOOPCTRL_RCSCALE_THRESH |
350                         POWER_LOOPCTRL_EN_RCSCALE_8X);
351
352         clrsetbits_le32(&power_regs->hw_power_minpwr,
353                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
354
355         if (!fixed_batt_supply) {
356                 /* 5V to battery handoff ... FIXME */
357                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
358                 early_delay(30);
359                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
360         }
361 }
362
363 /**
364  * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
365  *
366  * This function configures the necessary parameters for the 4P2 linear
367  * regulator to supply the DC-DC converter from 5V input.
368  */
369 static void mxs_power_init_4p2_params(void)
370 {
371         debug("SPL: Configuring common 4P2 regulator params\n");
372
373         debug("SPL: Configuring common 4P2 regulator params\n");
374
375         /* Setup 4P2 parameters */
376         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
377                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
378                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
379
380         clrsetbits_le32(&power_regs->hw_power_5vctrl,
381                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
382                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
383
384         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
385                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
386                 DCDC4P2_DROPOUT_CONFIG);
387
388         clrsetbits_le32(&power_regs->hw_power_5vctrl,
389                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
390                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
391 }
392
393 /**
394  * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
395  * @xfer:       Select if the input shall be enabled or disabled
396  *
397  * This function enables or disables the 4P2 input into the DC-DC converter.
398  */
399 static void mxs_enable_4p2_dcdc_input(int xfer)
400 {
401         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
402         uint32_t prev_5v_brnout, prev_5v_droop;
403
404         debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
405
406         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
407                         POWER_5VCTRL_ENABLE_DCDC)) {
408                 return;
409         }
410
411         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
412                                 POWER_5VCTRL_PWDN_5VBRNOUT;
413         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
414                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
415
416         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
417         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
418                 &power_regs->hw_power_reset);
419
420         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
421
422         /*
423          * Recording orignal values that will be modified temporarlily
424          * to handle a chip bug. See chip errata for CQ ENGR00115837
425          */
426         tmp = readl(&power_regs->hw_power_5vctrl);
427         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
428         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
429
430         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
431
432         /*
433          * Disable mechanisms that get erroneously tripped by when setting
434          * the DCDC4P2 EN_DCDC
435          */
436         clrbits_le32(&power_regs->hw_power_5vctrl,
437                 POWER_5VCTRL_VBUSVALID_5VDETECT |
438                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
439
440         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
441
442         if (xfer) {
443                 setbits_le32(&power_regs->hw_power_5vctrl,
444                                 POWER_5VCTRL_DCDC_XFER);
445                 early_delay(20);
446                 clrbits_le32(&power_regs->hw_power_5vctrl,
447                                 POWER_5VCTRL_DCDC_XFER);
448
449                 setbits_le32(&power_regs->hw_power_5vctrl,
450                                 POWER_5VCTRL_ENABLE_DCDC);
451         } else {
452                 setbits_le32(&power_regs->hw_power_dcdc4p2,
453                                 POWER_DCDC4P2_ENABLE_DCDC);
454         }
455
456         early_delay(25);
457
458         clrsetbits_le32(&power_regs->hw_power_5vctrl,
459                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
460
461         if (vbus_5vdetect)
462                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
463
464         if (!pwd_bo)
465                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
466
467         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
468                 writel(POWER_CTRL_VBUS_VALID_IRQ,
469                         &power_regs->hw_power_ctrl_clr);
470
471         if (prev_5v_brnout) {
472                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
473                         &power_regs->hw_power_5vctrl_set);
474                 writel(POWER_RESET_UNLOCK_KEY,
475                         &power_regs->hw_power_reset);
476         } else {
477                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
478                         &power_regs->hw_power_5vctrl_clr);
479                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
480                         &power_regs->hw_power_reset);
481         }
482
483         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
484                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
485                         &power_regs->hw_power_ctrl_clr);
486
487         if (prev_5v_droop)
488                 clrbits_le32(&power_regs->hw_power_ctrl,
489                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
490         else
491                 setbits_le32(&power_regs->hw_power_ctrl,
492                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
493 }
494
495 /**
496  * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
497  *
498  * This function enables the 4P2 regulator and switches the DC-DC converter
499  * to use the 4P2 input.
500  */
501 static void mxs_power_init_4p2_regulator(void)
502 {
503         uint32_t tmp, tmp2;
504
505         debug("SPL: Enabling 4P2 regulator\n");
506
507         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
508
509         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
510
511         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
512                 &power_regs->hw_power_5vctrl_clr);
513         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
514
515         /* Power up the 4p2 rail and logic/control */
516         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
517                 &power_regs->hw_power_5vctrl_clr);
518
519         /*
520          * Start charging up the 4p2 capacitor. We ramp of this charge
521          * gradually to avoid large inrush current from the 5V cable which can
522          * cause transients/problems
523          */
524         debug("SPL: Charging 4P2 capacitor\n");
525         mxs_enable_4p2_dcdc_input(0);
526
527         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
528                 /*
529                  * If we arrived here, we were unable to recover from mx23 chip
530                  * errata 5837. 4P2 is disabled and sufficient battery power is
531                  * not present. Exiting to not enable DCDC power during 5V
532                  * connected state.
533                  */
534                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
535                         POWER_DCDC4P2_ENABLE_DCDC);
536                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
537                         &power_regs->hw_power_5vctrl_set);
538
539                 debug("SPL: Unable to recover from mx23 errata 5837\n");
540                 hang();
541         }
542
543         /*
544          * Here we set the 4p2 brownout level to something very close to 4.2V.
545          * We then check the brownout status. If the brownout status is false,
546          * the voltage is already close to the target voltage of 4.2V so we
547          * can go ahead and set the 4P2 current limit to our max target limit.
548          * If the brownout status is true, we need to ramp up the current limit
549          * so that we don't cause large inrush current issues. We step up the
550          * current limit until the brownout status is false or until we've
551          * reached our maximum defined 4p2 current limit.
552          */
553         debug("SPL: Setting 4P2 brownout level\n");
554         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
555                         POWER_DCDC4P2_BO_MASK,
556                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
557
558         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
559                 setbits_le32(&power_regs->hw_power_5vctrl,
560                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
561         } else {
562                 tmp = (readl(&power_regs->hw_power_5vctrl) &
563                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
564                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
565                 while (tmp < 0x3f) {
566                         if (!(readl(&power_regs->hw_power_sts) &
567                                         POWER_STS_DCDC_4P2_BO)) {
568                                 tmp = readl(&power_regs->hw_power_5vctrl);
569                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
570                                 early_delay(100);
571                                 writel(tmp, &power_regs->hw_power_5vctrl);
572                                 break;
573                         } else {
574                                 tmp++;
575                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
576                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
577                                 tmp2 |= tmp <<
578                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
579                                 writel(tmp2, &power_regs->hw_power_5vctrl);
580                                 early_delay(100);
581                         }
582                 }
583         }
584
585         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
586         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
587 }
588
589 /**
590  * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
591  *
592  * This function configures the DC-DC converter to be supplied from the 4P2
593  * linear regulator.
594  */
595 static void mxs_power_init_dcdc_4p2_source(void)
596 {
597         debug("SPL: Switching DC-DC converters to 4P2\n");
598
599         debug("SPL: Switching DC-DC converters to 4P2\n");
600
601         if (!(readl(&power_regs->hw_power_dcdc4p2) &
602                 POWER_DCDC4P2_ENABLE_DCDC)) {
603                 debug("SPL: Already switched - aborting\n");
604                 hang();
605         }
606
607         mxs_enable_4p2_dcdc_input(1);
608
609         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
610                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
611                         POWER_DCDC4P2_ENABLE_DCDC);
612                 writel(POWER_5VCTRL_ENABLE_DCDC,
613                         &power_regs->hw_power_5vctrl_clr);
614                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
615                         &power_regs->hw_power_5vctrl_set);
616         }
617 }
618
619 /**
620  * mxs_power_enable_4p2() - Power up the 4P2 regulator
621  *
622  * This function drives the process of powering up the 4P2 linear regulator
623  * and switching the DC-DC converter input over to the 4P2 linear regulator.
624  */
625 static void mxs_power_enable_4p2(void)
626 {
627         uint32_t vdddctrl, vddactrl, vddioctrl;
628         uint32_t tmp;
629
630         debug("SPL: Powering up 4P2 regulator\n");
631
632         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
633         vddactrl = readl(&power_regs->hw_power_vddactrl);
634         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
635
636         setbits_le32(&power_regs->hw_power_vdddctrl,
637                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
638                 POWER_VDDDCTRL_PWDN_BRNOUT);
639
640         setbits_le32(&power_regs->hw_power_vddactrl,
641                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
642                 POWER_VDDACTRL_PWDN_BRNOUT);
643
644         setbits_le32(&power_regs->hw_power_vddioctrl,
645                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
646
647         mxs_power_init_4p2_params();
648         mxs_power_init_4p2_regulator();
649
650         /* Shutdown battery (none present) */
651         if (!mxs_is_batt_ready()) {
652                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
653                                 POWER_DCDC4P2_BO_MASK);
654                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
655                                 &power_regs->hw_power_ctrl_clr);
656                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
657                                 &power_regs->hw_power_ctrl_clr);
658         }
659
660         mxs_power_init_dcdc_4p2_source();
661
662         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
663         early_delay(20);
664         writel(vddactrl, &power_regs->hw_power_vddactrl);
665         early_delay(20);
666         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
667
668         /*
669          * Check if FET is enabled on either powerout and if so,
670          * disable load.
671          */
672         tmp = 0;
673         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
674                         POWER_VDDDCTRL_DISABLE_FET);
675         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
676                         POWER_VDDACTRL_DISABLE_FET);
677         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
678                         POWER_VDDIOCTRL_DISABLE_FET);
679         if (tmp)
680                 writel(POWER_CHARGE_ENABLE_LOAD,
681                         &power_regs->hw_power_charge_clr);
682
683         debug("SPL: 4P2 regulator powered-up\n");
684 }
685
686 /**
687  * mxs_boot_valid_5v() - Boot from 5V supply
688  *
689  * This function configures the power block to boot from valid 5V input.
690  * This is called only if the 5V is reliable and can properly supply the
691  * CPU. This function proceeds to configure the 4P2 converter to be supplied
692  * from the 5V input.
693  */
694 static void mxs_boot_valid_5v(void)
695 {
696         debug("SPL: Booting from 5V supply\n");
697
698         debug("SPL: Booting from 5V supply\n");
699
700         /*
701          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
702          * disconnect event. FIXME
703          */
704         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
705                 &power_regs->hw_power_5vctrl_set);
706
707         /* Configure polarity to check for 5V disconnection. */
708         writel(POWER_CTRL_POLARITY_VBUSVALID |
709                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
710                 &power_regs->hw_power_ctrl_clr);
711
712         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
713                 &power_regs->hw_power_ctrl_clr);
714
715         mxs_power_enable_4p2();
716 }
717
718 /**
719  * mxs_powerdown() - Shut down the system
720  *
721  * This function powers down the CPU completely.
722  */
723 static void mxs_powerdown(void)
724 {
725         debug("Powering Down\n");
726
727         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
728         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
729                 &power_regs->hw_power_reset);
730 }
731
732 /**
733  * mxs_batt_boot() - Configure the power block to boot from battery input
734  *
735  * This function configures the power block to boot from the battery voltage
736  * supply.
737  */
738 static void mxs_batt_boot(void)
739 {
740         debug("SPL: Configuring power block to boot from battery\n");
741
742         debug("SPL: Configuring power block to boot from battery\n");
743
744         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
745         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
746
747         clrbits_le32(&power_regs->hw_power_dcdc4p2,
748                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
749         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
750
751         /* 5V to battery handoff. */
752         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
753         early_delay(30);
754         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
755
756         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
757
758         clrsetbits_le32(&power_regs->hw_power_minpwr,
759                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
760
761         mxs_power_set_linreg();
762
763         clrbits_le32(&power_regs->hw_power_vdddctrl,
764                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
765
766         clrbits_le32(&power_regs->hw_power_vddactrl,
767                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
768
769         clrbits_le32(&power_regs->hw_power_vddioctrl,
770                 POWER_VDDIOCTRL_DISABLE_FET);
771
772         setbits_le32(&power_regs->hw_power_5vctrl,
773                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
774
775         setbits_le32(&power_regs->hw_power_5vctrl,
776                 POWER_5VCTRL_ENABLE_DCDC);
777
778         clrsetbits_le32(&power_regs->hw_power_5vctrl,
779                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
780                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
781
782         mxs_power_enable_4p2();
783 }
784
785 /**
786  * mxs_handle_5v_conflict() - Test if the 5V input is reliable
787  *
788  * This function tests if the 5V input can reliably supply the system. If it
789  * can, then proceed to configuring the system to boot from 5V source, otherwise
790  * try booting from battery supply. If we can not boot from battery supply
791  * either, shut down the system.
792  */
793 static void mxs_handle_5v_conflict(void)
794 {
795         uint32_t tmp;
796
797         debug("SPL: Resolving 5V conflict\n");
798
799         setbits_le32(&power_regs->hw_power_vddioctrl,
800                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
801
802         for (;;) {
803                 tmp = readl(&power_regs->hw_power_sts);
804
805                 if (tmp & POWER_STS_VDDIO_BO) {
806                         /*
807                          * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
808                          * becomes unreliable
809                          */
810                         debug("SPL: VDDIO has a brownout\n");
811                         mxs_powerdown();
812                         break;
813                 }
814
815                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
816                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
817                         mxs_boot_valid_5v();
818                         break;
819                 } else {
820                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
821                         mxs_powerdown();
822                         break;
823                 }
824
825                 /*
826                  * TODO: I can't see this being reached. We'll either
827                  * powerdown or boot from a stable 5V supply.
828                  */
829                 if (tmp & POWER_STS_PSWITCH_MASK) {
830                         debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
831                         mxs_batt_boot();
832                         break;
833                 }
834         }
835 }
836
837 /**
838  * mxs_5v_boot() - Configure the power block to boot from 5V input
839  *
840  * This function handles configuration of the power block when supplied by
841  * a 5V input.
842  */
843 static void mxs_5v_boot(void)
844 {
845         debug("SPL: Configuring power block to boot from 5V input\n");
846
847         debug("SPL: Configuring power block to boot from 5V input\n");
848
849         /*
850          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
851          * but their implementation always returns 1 so we omit it here.
852          */
853         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
854                 debug("SPL: 5V VDD good\n");
855                 mxs_boot_valid_5v();
856                 return;
857         }
858
859         early_delay(1000);
860         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
861                 debug("SPL: 5V VDD good (after delay)\n");
862                 mxs_boot_valid_5v();
863                 return;
864         }
865
866         debug("SPL: 5V VDD not good\n");
867         mxs_handle_5v_conflict();
868 }
869
870 static void mxs_fixed_batt_boot(void)
871 {
872         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
873
874         setbits_le32(&power_regs->hw_power_5vctrl,
875                 POWER_5VCTRL_ENABLE_DCDC |
876                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
877                 POWER_5VCTRL_PWDN_5VBRNOUT |
878                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
879
880         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
881
882         clrbits_le32(&power_regs->hw_power_vdddctrl,
883                 POWER_VDDDCTRL_DISABLE_FET |
884                 POWER_VDDDCTRL_ENABLE_LINREG |
885                 POWER_VDDDCTRL_DISABLE_STEPPING);
886
887         clrbits_le32(&power_regs->hw_power_vddactrl,
888                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
889                 POWER_VDDACTRL_DISABLE_STEPPING);
890
891         clrbits_le32(&power_regs->hw_power_vddioctrl,
892                 POWER_VDDIOCTRL_DISABLE_FET |
893                 POWER_VDDIOCTRL_DISABLE_STEPPING);
894
895         /* Stop 5V detection */
896         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
897                 &power_regs->hw_power_5vctrl_clr);
898 }
899
900 /**
901  * mxs_init_batt_bo() - Configure battery brownout threshold
902  *
903  * This function configures the battery input brownout threshold. The value
904  * at which the battery brownout happens is configured to 3.0V in the code.
905  */
906 static void mxs_init_batt_bo(void)
907 {
908         debug("SPL: Initialising battery brown-out level to 3.0V\n");
909
910         debug("SPL: Initialising battery brown-out level to 3.0V\n");
911
912         /* Brownout at 3V */
913         clrsetbits_le32(&power_regs->hw_power_battmonitor,
914                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
915                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
916
917         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
918         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
919 }
920
921 /**
922  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
923  *
924  * This function turns off the VDDD linear regulator and therefore makes
925  * the VDDD rail be supplied only by the DC-DC converter.
926  */
927 static void mxs_switch_vddd_to_dcdc_source(void)
928 {
929         debug("SPL: Switching VDDD to DC-DC converters\n");
930
931         debug("SPL: Switching VDDD to DC-DC converters\n");
932
933         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
934                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
935                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
936
937         clrbits_le32(&power_regs->hw_power_vdddctrl,
938                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
939                 POWER_VDDDCTRL_DISABLE_STEPPING);
940 }
941
942 /**
943  * mxs_power_configure_power_source() - Configure power block source
944  *
945  * This function is the core of the power configuration logic. The function
946  * selects the power block input source and configures the whole power block
947  * accordingly. After the configuration is complete and the system is stable
948  * again, the function switches the CPU clock source back to PLL. Finally,
949  * the function switches the voltage rails to DC-DC converter.
950  */
951 static void mxs_power_configure_power_source(void)
952 {
953         struct mxs_lradc_regs *lradc_regs =
954                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
955
956         debug("SPL: Configuring power source\n");
957
958         mxs_src_power_init();
959
960         if (!fixed_batt_supply) {
961                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
962                         if (mxs_is_batt_ready()) {
963                                 /* 5V source detected, good battery detected. */
964                                 mxs_batt_boot();
965                         } else {
966                                 if (!mxs_is_batt_good()) {
967                                         /* 5V source detected, bad battery detected. */
968                                         writel(LRADC_CONVERSION_AUTOMATIC,
969                                                 &lradc_regs->hw_lradc_conversion_clr);
970                                         clrbits_le32(&power_regs->hw_power_battmonitor,
971                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
972                                 }
973                                 mxs_5v_boot();
974                         }
975                 } else {
976                         /* 5V not detected, booting from battery. */
977                         mxs_batt_boot();
978                 }
979         } else {
980                 mxs_fixed_batt_boot();
981         }
982
983         /*
984          * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
985          * from USB VBUS
986          */
987         mxs_power_clock2pll();
988
989         mxs_init_batt_bo();
990
991         mxs_switch_vddd_to_dcdc_source();
992
993 #ifdef CONFIG_SOC_MX23
994         /* Fire up the VDDMEM LinReg now that we're all set. */
995         debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
996         writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
997                 &power_regs->hw_power_vddmemctrl);
998 #endif
999 }
1000
1001 /**
1002  * mxs_enable_output_rail_protection() - Enable power rail protection
1003  *
1004  * This function enables overload protection on the power rails. This is
1005  * triggered if the power rails' voltage drops rapidly due to overload and
1006  * in such case, the supply to the powerrail is cut-off, protecting the
1007  * CPU from damage. Note that under such condition, the system will likely
1008  * crash or misbehave.
1009  */
1010 static void mxs_enable_output_rail_protection(void)
1011 {
1012         debug("SPL: Enabling output rail protection\n");
1013
1014         debug("SPL: Enabling output rail protection\n");
1015
1016         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1017                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1018
1019         setbits_le32(&power_regs->hw_power_vdddctrl,
1020                         POWER_VDDDCTRL_PWDN_BRNOUT);
1021
1022         setbits_le32(&power_regs->hw_power_vddactrl,
1023                         POWER_VDDACTRL_PWDN_BRNOUT);
1024
1025         setbits_le32(&power_regs->hw_power_vddioctrl,
1026                         POWER_VDDIOCTRL_PWDN_BRNOUT);
1027 }
1028
1029 /**
1030  * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1031  *
1032  * This function tests if the VDDIO rail is supplied by linear regulator
1033  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1034  * returns 0 if powered by the DC-DC converter.
1035  */
1036 static int mxs_get_vddio_power_source_off(void)
1037 {
1038         uint32_t tmp;
1039
1040         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1041                 !(readl(&power_regs->hw_power_5vctrl) &
1042                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1043
1044                 tmp = readl(&power_regs->hw_power_vddioctrl);
1045                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1046                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1047                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1048                                 return 1;
1049                         }
1050                 }
1051
1052                 if (!(readl(&power_regs->hw_power_5vctrl) &
1053                         POWER_5VCTRL_ENABLE_DCDC)) {
1054                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1055                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1056                                 return 1;
1057                         }
1058                 }
1059         }
1060
1061         return 0;
1062 }
1063
1064 /**
1065  * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1066  *
1067  * This function tests if the VDDD rail is supplied by linear regulator
1068  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1069  * returns 0 if powered by the DC-DC converter.
1070  */
1071 static int mxs_get_vddd_power_source_off(void)
1072 {
1073         uint32_t tmp;
1074
1075         tmp = readl(&power_regs->hw_power_vdddctrl);
1076         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1077                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1078                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1079                         return 1;
1080                 }
1081         }
1082
1083         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1084                 if (!(readl(&power_regs->hw_power_5vctrl) &
1085                         POWER_5VCTRL_ENABLE_DCDC)) {
1086                         return 1;
1087                 }
1088         }
1089
1090         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1091                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1092                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1093                         return 1;
1094                 }
1095         }
1096
1097         return 0;
1098 }
1099
1100 static int mxs_get_vdda_power_source_off(void)
1101 {
1102         uint32_t tmp;
1103
1104         tmp = readl(&power_regs->hw_power_vddactrl);
1105         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1106                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1107                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1108                         return 1;
1109                 }
1110         }
1111
1112         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1113                 if (!(readl(&power_regs->hw_power_5vctrl) &
1114                         POWER_5VCTRL_ENABLE_DCDC)) {
1115                         return 1;
1116                 }
1117         }
1118
1119         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1120                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1121                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1122                         return 1;
1123                 }
1124         }
1125
1126         return 0;
1127 }
1128
1129 struct mxs_vddx_cfg {
1130         uint32_t                *reg;
1131         uint8_t                 step_mV;
1132         uint16_t                lowest_mV;
1133         uint16_t                highest_mV;
1134         int                     (*powered_by_linreg)(void);
1135         uint32_t                trg_mask;
1136         uint32_t                bo_irq;
1137         uint32_t                bo_enirq;
1138         uint32_t                bo_offset_mask;
1139         uint32_t                bo_offset_offset;
1140         uint16_t                bo_min_mV;
1141         uint16_t                bo_max_mV;
1142 };
1143
1144 #define POWER_REG(n)            &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1145
1146 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1147         .reg                    = POWER_REG(hw_power_vddioctrl),
1148 #if defined(CONFIG_SOC_MX23)
1149         .step_mV                = 25,
1150 #else
1151         .step_mV                = 50,
1152 #endif
1153         .lowest_mV              = 2800,
1154         .highest_mV             = 3600,
1155         .powered_by_linreg      = mxs_get_vddio_power_source_off,
1156         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
1157         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
1158         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
1159         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1160         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1161         .bo_min_mV              = 2700,
1162         .bo_max_mV              = 3475,
1163 };
1164
1165 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1166         .reg                    = POWER_REG(hw_power_vdddctrl),
1167         .step_mV                = 25,
1168         .lowest_mV              = 800,
1169         .highest_mV             = 1575,
1170         .powered_by_linreg      = mxs_get_vddd_power_source_off,
1171         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
1172         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
1173         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
1174         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
1175         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1176         .bo_min_mV              = 800,
1177         .bo_max_mV              = 1475,
1178 };
1179
1180 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1181         .reg                    = POWER_REG(hw_power_vddactrl),
1182         .step_mV                = 25,
1183         .lowest_mV              = 1800,
1184         .highest_mV             = 3600,
1185         .powered_by_linreg      = mxs_get_vdda_power_source_off,
1186         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
1187         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
1188         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
1189         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
1190         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1191         .bo_min_mV              = 1400,
1192         .bo_max_mV              = 2175,
1193 };
1194
1195 #ifdef CONFIG_SOC_MX23
1196 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1197         .reg                    = POWER_REG(hw_power_vddmemctrl),
1198         .step_mV                = 50,
1199         .lowest_mV              = 1500,
1200         .highest_mV             = 1700,
1201         .powered_by_linreg      = NULL,
1202         .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
1203         .bo_irq                 = 0,
1204         .bo_enirq               = 0,
1205         .bo_offset_mask         = 0,
1206         .bo_offset_offset       = 0,
1207 };
1208 #endif
1209
1210 /**
1211  * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1212  * @cfg:                Configuration data of the DC-DC converter rail
1213  * @new_target:         New target voltage of the DC-DC converter rail
1214  * @new_brownout:       New brownout trigger voltage
1215  *
1216  * This function configures the output voltage on the DC-DC converter rail.
1217  * The rail is selected by the @cfg argument. The new voltage target is
1218  * selected by the @new_target and the voltage is specified in mV. The
1219  * new brownout value is selected by the @new_brownout argument and the
1220  * value is also in mV.
1221  */
1222 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1223                                 uint32_t new_target, uint32_t bo_offset)
1224 {
1225         uint32_t cur_target, diff, bo_int = 0;
1226         int powered_by_linreg = 0;
1227         int adjust_up;
1228
1229         if (new_target < cfg->lowest_mV) {
1230                 new_target = cfg->lowest_mV;
1231         }
1232         if (new_target > cfg->highest_mV) {
1233                 new_target = cfg->highest_mV;
1234         }
1235
1236         if (new_target - bo_offset < cfg->bo_min_mV) {
1237                 bo_offset = new_target - cfg->bo_min_mV;
1238         } else if (new_target - bo_offset > cfg->bo_max_mV) {
1239                 bo_offset = new_target - cfg->bo_max_mV;
1240         }
1241
1242         bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1243
1244         cur_target = readl(cfg->reg);
1245         cur_target &= cfg->trg_mask;
1246         cur_target *= cfg->step_mV;
1247         cur_target += cfg->lowest_mV;
1248
1249         adjust_up = new_target > cur_target;
1250         if (cfg->powered_by_linreg)
1251                 powered_by_linreg = cfg->powered_by_linreg();
1252
1253         if (adjust_up && cfg->bo_irq) {
1254                 if (powered_by_linreg) {
1255                         bo_int = readl(&power_regs->hw_power_ctrl);
1256                         writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1257                 }
1258                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1259         }
1260
1261         do {
1262                 if (abs(new_target - cur_target) > 100) {
1263                         if (adjust_up)
1264                                 diff = cur_target + 100;
1265                         else
1266                                 diff = cur_target - 100;
1267                 } else {
1268                         diff = new_target;
1269                 }
1270
1271                 diff -= cfg->lowest_mV;
1272                 diff /= cfg->step_mV;
1273
1274                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1275
1276                 if (powered_by_linreg ||
1277                         (readl(&power_regs->hw_power_sts) &
1278                                 POWER_STS_VDD5V_GT_VDDIO)) {
1279                         early_delay(500);
1280                 } else {
1281                         while (!(readl(&power_regs->hw_power_sts) &
1282                                         POWER_STS_DC_OK)) {
1283
1284                         }
1285                 }
1286
1287                 cur_target = readl(cfg->reg);
1288                 cur_target &= cfg->trg_mask;
1289                 cur_target *= cfg->step_mV;
1290                 cur_target += cfg->lowest_mV;
1291         } while (new_target > cur_target);
1292
1293         if (cfg->bo_irq) {
1294                 if (adjust_up && powered_by_linreg) {
1295                         writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1296                         if (bo_int & cfg->bo_enirq)
1297                                 writel(cfg->bo_enirq,
1298                                         &power_regs->hw_power_ctrl_set);
1299                 }
1300
1301                 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1302                                 bo_offset << cfg->bo_offset_offset);
1303         }
1304 }
1305
1306 /**
1307  * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1308  *
1309  * This function starts and configures the LRADC block. This allows the
1310  * power initialization code to measure battery voltage and based on this
1311  * knowledge, decide whether to boot at all, boot from battery or boot
1312  * from 5V input.
1313  */
1314 static void mxs_setup_batt_detect(void)
1315 {
1316         debug("SPL: Starting battery voltage measurement logic\n");
1317
1318         mxs_lradc_init();
1319         mxs_lradc_enable_batt_measurement();
1320         early_delay(10);
1321 }
1322
1323 /**
1324  * mxs_ungate_power() - Ungate the POWER block
1325  *
1326  * This function ungates clock to the power block. In case the power block
1327  * was still gated at this point, it will not be possible to configure the
1328  * block and therefore the power initialization would fail. This function
1329  * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1330  */
1331 static void mxs_ungate_power(void)
1332 {
1333 #ifdef CONFIG_SOC_MX23
1334         writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1335 #endif
1336 }
1337
1338 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1339 #define auto_restart 1
1340 #else
1341 #define auto_restart 0
1342 #endif
1343
1344 /**
1345  * mxs_power_init() - The power block init main function
1346  *
1347  * This function calls all the power block initialization functions in
1348  * proper sequence to start the power block.
1349  */
1350 #define VDDX_VAL(v)     (v) / 1000, (v) / 100 % 10
1351
1352 void mxs_power_init(void)
1353 {
1354         debug("SPL: Initialising Power Block\n");
1355
1356         debug("SPL: Initialising Power Block\n");
1357
1358         mxs_ungate_power();
1359
1360         mxs_power_clock2xtal();
1361         if (mxs_power_set_auto_restart(auto_restart)) {
1362                 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1363         }
1364         mxs_power_set_linreg();
1365
1366         if (!fixed_batt_supply) {
1367                 mxs_power_setup_5v_detect();
1368                 mxs_setup_batt_detect();
1369         }
1370
1371         mxs_power_configure_power_source();
1372         mxs_enable_output_rail_protection();
1373
1374         debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1375                 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1376         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1377         debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1378                 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1379         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1380         debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1381                 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1382         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1383 #ifdef CONFIG_SOC_MX23
1384         debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1385                 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1386         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1387 #else
1388         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1389                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1390 #endif
1391         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1392                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1393                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1394                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1395         if (!fixed_batt_supply)
1396                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1397                         &power_regs->hw_power_5vctrl_set);
1398 }
1399
1400 #ifdef  CONFIG_SPL_MXS_PSWITCH_WAIT
1401 /**
1402  * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1403  *
1404  * This function waits until the power-switch was pressed to start booting
1405  * the board.
1406  */
1407 void mxs_power_wait_pswitch(void)
1408 {
1409         debug("SPL: Waiting for power switch input\n");
1410         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1411                 ;
1412 }
1413 #endif