2 * Freescale i.MX28 Boot PMIC init
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
17 #ifdef CONFIG_SYS_MXS_VDD5V_ONLY
18 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
19 POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2
21 #define DCDC4P2_DROPOUT_CONFIG POWER_DCDC4P2_DROPOUT_CTRL_100MV | \
22 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL
24 #ifdef CONFIG_SYS_SPL_VDDD_VAL
25 #define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL
29 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
30 #define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL
32 #define VDDIO_VAL 3300
34 #ifdef CONFIG_SYS_SPL_VDDA_VAL
35 #define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL
39 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
40 #define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL
42 #define VDDMEM_VAL 1700
45 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
46 #define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL
48 #define VDDD_BO_VAL 150
50 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
51 #define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL
53 #define VDDIO_BO_VAL 150
55 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
56 #define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL
58 #define VDDA_BO_VAL 175
60 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
61 #define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL
63 #define VDDMEM_BO_VAL 25
66 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
67 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
68 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
70 #define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
72 /* Brownout default at 3V */
73 #define BATT_BO_VAL ((3000 - 2400) / 40)
76 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
77 static const int fixed_batt_supply = 1;
79 static const int fixed_batt_supply;
82 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
85 * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
87 * This function switches the CPU core clock from PLL to 24MHz XTAL
88 * oscilator. This is necessary if the PLL is being reconfigured to
89 * prevent crash of the CPU core.
91 static void mxs_power_clock2xtal(void)
93 struct mxs_clkctrl_regs *clkctrl_regs =
94 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
96 debug("SPL: Switching CPU clock to 24MHz XTAL\n");
98 /* Set XTAL as CPU reference clock */
99 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
100 &clkctrl_regs->hw_clkctrl_clkseq_set);
104 * mxs_power_clock2pll() - Switch CPU core clock source to PLL
106 * This function switches the CPU core clock from 24MHz XTAL oscilator
107 * to PLL. This can only be called once the PLL has re-locked and once
108 * the PLL is stable after reconfiguration.
110 static void mxs_power_clock2pll(void)
112 struct mxs_clkctrl_regs *clkctrl_regs =
113 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
115 debug("SPL: Switching CPU core clock source to PLL\n");
117 writel(CLKCTRL_PLL0CTRL0_POWER,
118 &clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
120 * The PLL is documented to lock within 10 µs from setting
126 * TODO: Should the PLL0 FORCE_LOCK bit be set here followed by a
127 * wait on the PLL0 LOCK bit?
129 writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
130 &clkctrl_regs->hw_clkctrl_clkseq_clr);
133 static int mxs_power_wait_rtc_stat(u32 mask)
135 int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
137 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
139 while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
144 return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
148 * mxs_power_set_auto_restart() - Set the auto-restart bit
150 * This function ungates the RTC block and sets the AUTO_RESTART
151 * bit to work around a design bug on MX28EVK Rev. A .
153 static int mxs_power_set_auto_restart(int on)
155 struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
157 debug("SPL: Setting auto-restart bit\n");
159 if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
162 /* Do nothing if flag already set */
163 if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
166 if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
167 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
170 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
173 clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
174 !on * RTC_PERSISTENT0_AUTO_RESTART,
175 !!on * RTC_PERSISTENT0_AUTO_RESTART);
176 if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
183 * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
185 * This function configures the VDDIO, VDDA and VDDD linear regulators output
186 * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
187 * converter. This is the recommended setting for the case where we use both
188 * linear regulators and DC-DC converter to power the VDDIO rail.
190 static void mxs_power_set_linreg(void)
192 /* Set linear regulator 25mV below switching converter */
193 debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
194 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
195 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
196 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
198 debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
199 clrsetbits_le32(&power_regs->hw_power_vddactrl,
200 POWER_VDDACTRL_LINREG_OFFSET_MASK,
201 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
203 debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
204 clrsetbits_le32(&power_regs->hw_power_vddioctrl,
205 POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
206 POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
210 * mxs_get_batt_volt() - Measure battery input voltage
212 * This function retrieves the battery input voltage and returns it.
214 static int mxs_get_batt_volt(void)
216 uint32_t volt = readl(&power_regs->hw_power_battmonitor);
218 volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
219 volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
222 debug("SPL: Battery Voltage = %dmV\n", volt);
227 * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
229 * This function checks if the battery input voltage is higher than 3.6V and
230 * therefore allows the system to successfully boot using this power source.
232 static int mxs_is_batt_ready(void)
234 return (mxs_get_batt_volt() >= 3600);
238 * mxs_is_batt_good() - Test if battery is operational at all
240 * This function starts recharging the battery and tests if the input current
241 * provided by the 5V input recharging the battery is also sufficient to power
242 * the DC-DC converter.
244 static int mxs_is_batt_good(void)
246 uint32_t volt = mxs_get_batt_volt();
248 if ((volt >= 2400) && (volt <= 4300)) {
249 debug("SPL: Battery is good\n");
253 clrsetbits_le32(&power_regs->hw_power_5vctrl,
254 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
255 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
256 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
257 &power_regs->hw_power_5vctrl_clr);
259 clrsetbits_le32(&power_regs->hw_power_charge,
260 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
261 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
263 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
264 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
265 &power_regs->hw_power_5vctrl_clr);
269 volt = mxs_get_batt_volt();
272 debug("SPL: Battery Voltage too high\n");
277 debug("SPL: Battery is good\n");
281 writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
282 &power_regs->hw_power_charge_clr);
283 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
291 debug("SPL: Battery Voltage too low\n");
296 * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
298 * This function enables the 5V detection comparator and sets the 5V valid
299 * threshold to 4.4V . We use 4.4V threshold here to make sure that even
300 * under high load, the voltage drop on the 5V input won't be so critical
301 * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
302 * converter and thus making the system crash.
304 static void mxs_power_setup_5v_detect(void)
306 /* Start 5V detection */
307 debug("SPL: Starting 5V input detection comparator\n");
308 clrsetbits_le32(&power_regs->hw_power_5vctrl,
309 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
310 POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
311 POWER_5VCTRL_PWRUP_VBUS_CMPS);
315 * mxs_src_power_init() - Preconfigure the power block
317 * This function configures reasonable values for the DC-DC control loop
318 * and battery monitor.
320 static void mxs_src_power_init(void)
322 debug("SPL: Pre-Configuring power block\n");
324 /* Improve efficieny and reduce transient ripple */
325 writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
326 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
328 clrsetbits_le32(&power_regs->hw_power_dclimits,
329 POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
330 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
332 if (!fixed_batt_supply) {
333 /* FIXME: This requires the LRADC to be set up! */
334 setbits_le32(&power_regs->hw_power_battmonitor,
335 POWER_BATTMONITOR_EN_BATADJ);
337 clrbits_le32(&power_regs->hw_power_battmonitor,
338 POWER_BATTMONITOR_EN_BATADJ);
341 /* Increase the RCSCALE level for quick DCDC response to dynamic load */
342 clrsetbits_le32(&power_regs->hw_power_loopctrl,
343 POWER_LOOPCTRL_EN_RCSCALE_MASK,
344 POWER_LOOPCTRL_RCSCALE_THRESH |
345 POWER_LOOPCTRL_EN_RCSCALE_8X);
347 clrsetbits_le32(&power_regs->hw_power_minpwr,
348 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
350 if (!fixed_batt_supply) {
351 /* 5V to battery handoff ... FIXME */
352 writel(POWER_5VCTRL_DCDC_XFER,
353 &power_regs->hw_power_5vctrl_set);
355 writel(POWER_5VCTRL_DCDC_XFER,
356 &power_regs->hw_power_5vctrl_clr);
361 * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
363 * This function configures the necessary parameters for the 4P2 linear
364 * regulator to supply the DC-DC converter from 5V input.
366 static void mxs_power_init_4p2_params(void)
368 debug("SPL: Configuring common 4P2 regulator params\n");
370 /* Setup 4P2 parameters */
371 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
372 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
373 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
375 clrsetbits_le32(&power_regs->hw_power_5vctrl,
376 POWER_5VCTRL_HEADROOM_ADJ_MASK,
377 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
379 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
380 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
381 DCDC4P2_DROPOUT_CONFIG);
383 clrsetbits_le32(&power_regs->hw_power_5vctrl,
384 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
385 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
389 * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
390 * @xfer: Select if the input shall be enabled or disabled
392 * This function enables or disables the 4P2 input into the DC-DC converter.
394 static void mxs_enable_4p2_dcdc_input(int xfer)
396 uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
397 uint32_t prev_5v_brnout, prev_5v_droop;
399 debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
401 if (xfer && (readl(&power_regs->hw_power_5vctrl) &
402 POWER_5VCTRL_ENABLE_DCDC)) {
406 prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
407 POWER_5VCTRL_PWDN_5VBRNOUT;
408 prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
409 POWER_CTRL_ENIRQ_VDD5V_DROOP;
411 writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_clr);
412 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
413 &power_regs->hw_power_reset);
415 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, &power_regs->hw_power_ctrl_clr);
418 * Recording orignal values that will be modified temporarlily
419 * to handle a chip bug. See chip errata for CQ ENGR00115837
421 tmp = readl(&power_regs->hw_power_5vctrl);
422 vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
423 vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
425 pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
428 * Disable mechanisms that get erroneously tripped by when setting
429 * the DCDC4P2 EN_DCDC
431 writel(POWER_5VCTRL_VBUSVALID_5VDETECT |
432 POWER_5VCTRL_VBUSVALID_TRSH_MASK,
433 &power_regs->hw_power_5vctrl);
435 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
438 writel(POWER_5VCTRL_DCDC_XFER,
439 &power_regs->hw_power_5vctrl);
441 writel(POWER_5VCTRL_DCDC_XFER,
442 &power_regs->hw_power_5vctrl_clr);
444 writel(POWER_5VCTRL_ENABLE_DCDC,
445 &power_regs->hw_power_5vctrl_set);
447 writel(POWER_DCDC4P2_ENABLE_DCDC,
448 &power_regs->hw_power_dcdc4p2);
453 clrsetbits_le32(&power_regs->hw_power_5vctrl,
454 POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
457 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
460 writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_clr);
462 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
463 writel(POWER_CTRL_VBUS_VALID_IRQ,
464 &power_regs->hw_power_ctrl_clr);
466 if (prev_5v_brnout) {
467 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
468 &power_regs->hw_power_5vctrl_set);
469 writel(POWER_RESET_UNLOCK_KEY,
470 &power_regs->hw_power_reset);
472 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
473 &power_regs->hw_power_5vctrl_clr);
474 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
475 &power_regs->hw_power_reset);
478 while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
479 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
480 &power_regs->hw_power_ctrl_clr);
483 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
484 &power_regs->hw_power_ctrl_set);
486 writel(POWER_CTRL_ENIRQ_VDD5V_DROOP,
487 &power_regs->hw_power_ctrl_clr);
491 * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
493 * This function enables the 4P2 regulator and switches the DC-DC converter
494 * to use the 4P2 input.
496 static void mxs_power_init_4p2_regulator(void)
500 debug("SPL: Enabling 4P2 regulator\n");
502 setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
504 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
506 writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
507 &power_regs->hw_power_5vctrl_clr);
508 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
510 /* Power up the 4p2 rail and logic/control */
511 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
512 &power_regs->hw_power_5vctrl_clr);
515 * Start charging up the 4p2 capacitor. We ramp of this charge
516 * gradually to avoid large inrush current from the 5V cable which can
517 * cause transients/problems
519 debug("SPL: Charging 4P2 capacitor\n");
520 mxs_enable_4p2_dcdc_input(0);
522 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
524 * If we arrived here, we were unable to recover from mx23 chip
525 * errata 5837. 4P2 is disabled and sufficient battery power is
526 * not present. Exiting to not enable DCDC power during 5V
529 clrbits_le32(&power_regs->hw_power_dcdc4p2,
530 POWER_DCDC4P2_ENABLE_DCDC);
531 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
532 &power_regs->hw_power_5vctrl_set);
534 debug("SPL: Unable to recover from mx23 errata 5837\n");
539 * Here we set the 4p2 brownout level to something very close to 4.2V.
540 * We then check the brownout status. If the brownout status is false,
541 * the voltage is already close to the target voltage of 4.2V so we
542 * can go ahead and set the 4P2 current limit to our max target limit.
543 * If the brownout status is true, we need to ramp up the current limit
544 * so that we don't cause large inrush current issues. We step up the
545 * current limit until the brownout status is false or until we've
546 * reached our maximum defined 4p2 current limit.
548 debug("SPL: Setting 4P2 brownout level\n");
549 clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
550 POWER_DCDC4P2_BO_MASK,
551 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
553 if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
554 writel(0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET,
555 &power_regs->hw_power_5vctrl_set);
557 tmp = (readl(&power_regs->hw_power_5vctrl) &
558 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
559 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
561 if (!(readl(&power_regs->hw_power_sts) &
562 POWER_STS_DCDC_4P2_BO)) {
563 tmp = readl(&power_regs->hw_power_5vctrl);
564 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
566 writel(tmp, &power_regs->hw_power_5vctrl);
570 tmp2 = readl(&power_regs->hw_power_5vctrl);
571 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
573 POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
574 writel(tmp2, &power_regs->hw_power_5vctrl);
580 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
581 writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
585 * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
587 * This function configures the DC-DC converter to be supplied from the 4P2
590 static void mxs_power_init_dcdc_4p2_source(void)
592 debug("SPL: Switching DC-DC converters to 4P2\n");
594 if (!(readl(&power_regs->hw_power_dcdc4p2) &
595 POWER_DCDC4P2_ENABLE_DCDC)) {
596 debug("SPL: Already switched - aborting\n");
600 mxs_enable_4p2_dcdc_input(1);
602 if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
603 clrbits_le32(&power_regs->hw_power_dcdc4p2,
604 POWER_DCDC4P2_ENABLE_DCDC);
605 writel(POWER_5VCTRL_ENABLE_DCDC,
606 &power_regs->hw_power_5vctrl_clr);
607 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
608 &power_regs->hw_power_5vctrl_set);
613 * mxs_power_enable_4p2() - Power up the 4P2 regulator
615 * This function drives the process of powering up the 4P2 linear regulator
616 * and switching the DC-DC converter input over to the 4P2 linear regulator.
618 static void mxs_power_enable_4p2(void)
620 uint32_t vdddctrl, vddactrl, vddioctrl;
623 debug("SPL: Powering up 4P2 regulator\n");
625 vdddctrl = readl(&power_regs->hw_power_vdddctrl);
626 vddactrl = readl(&power_regs->hw_power_vddactrl);
627 vddioctrl = readl(&power_regs->hw_power_vddioctrl);
629 setbits_le32(&power_regs->hw_power_vdddctrl,
630 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
631 POWER_VDDDCTRL_PWDN_BRNOUT);
633 setbits_le32(&power_regs->hw_power_vddactrl,
634 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
635 POWER_VDDACTRL_PWDN_BRNOUT);
637 setbits_le32(&power_regs->hw_power_vddioctrl,
638 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
640 mxs_power_init_4p2_params();
641 mxs_power_init_4p2_regulator();
643 /* Shutdown battery (none present) */
644 if (!mxs_is_batt_ready()) {
645 clrbits_le32(&power_regs->hw_power_dcdc4p2,
646 POWER_DCDC4P2_BO_MASK);
647 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
648 &power_regs->hw_power_ctrl_clr);
649 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
650 &power_regs->hw_power_ctrl_clr);
653 mxs_power_init_dcdc_4p2_source();
655 writel(vdddctrl, &power_regs->hw_power_vdddctrl);
657 writel(vddactrl, &power_regs->hw_power_vddactrl);
659 writel(vddioctrl, &power_regs->hw_power_vddioctrl);
662 * Check if FET is enabled on either powerout and if so,
666 tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
667 POWER_VDDDCTRL_DISABLE_FET);
668 tmp |= !(readl(&power_regs->hw_power_vddactrl) &
669 POWER_VDDACTRL_DISABLE_FET);
670 tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
671 POWER_VDDIOCTRL_DISABLE_FET);
673 writel(POWER_CHARGE_ENABLE_LOAD,
674 &power_regs->hw_power_charge_clr);
676 debug("SPL: 4P2 regulator powered-up\n");
680 * mxs_boot_valid_5v() - Boot from 5V supply
682 * This function configures the power block to boot from valid 5V input.
683 * This is called only if the 5V is reliable and can properly supply the
684 * CPU. This function proceeds to configure the 4P2 converter to be supplied
687 static void mxs_boot_valid_5v(void)
689 debug("SPL: Booting from 5V supply\n");
692 * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
693 * disconnect event. FIXME
695 writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
696 &power_regs->hw_power_5vctrl_set);
698 /* Configure polarity to check for 5V disconnection. */
699 writel(POWER_CTRL_POLARITY_VBUSVALID |
700 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
701 &power_regs->hw_power_ctrl_clr);
703 writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
704 &power_regs->hw_power_ctrl_clr);
706 mxs_power_enable_4p2();
710 * mxs_powerdown() - Shut down the system
712 * This function powers down the CPU completely.
714 static void mxs_powerdown(void)
716 debug("Powering Down\n");
718 writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
719 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
720 &power_regs->hw_power_reset);
724 * mxs_batt_boot() - Configure the power block to boot from battery input
726 * This function configures the power block to boot from the battery voltage
729 static void mxs_batt_boot(void)
731 debug("SPL: Configuring power block to boot from battery\n");
733 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
734 &power_regs->hw_power_5vctrl_clr);
735 writel(POWER_5VCTRL_ENABLE_DCDC,
736 &power_regs->hw_power_5vctrl_clr);
738 clrbits_le32(&power_regs->hw_power_dcdc4p2,
739 POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
740 writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
742 /* 5V to battery handoff. */
743 writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_set);
745 writel(POWER_5VCTRL_DCDC_XFER, &power_regs->hw_power_5vctrl_clr);
747 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
749 clrsetbits_le32(&power_regs->hw_power_minpwr,
750 POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
752 mxs_power_set_linreg();
754 clrbits_le32(&power_regs->hw_power_vdddctrl,
755 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
757 clrbits_le32(&power_regs->hw_power_vddactrl,
758 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
760 clrbits_le32(&power_regs->hw_power_vddioctrl,
761 POWER_VDDIOCTRL_DISABLE_FET);
763 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
764 &power_regs->hw_power_5vctrl_set);
766 writel(POWER_5VCTRL_ENABLE_DCDC, &power_regs->hw_power_5vctrl_set);
768 clrsetbits_le32(&power_regs->hw_power_5vctrl,
769 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
770 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
772 mxs_power_enable_4p2();
776 * mxs_handle_5v_conflict() - Test if the 5V input is reliable
778 * This function tests if the 5V input can reliably supply the system. If it
779 * can, then proceed to configuring the system to boot from 5V source, otherwise
780 * try booting from battery supply. If we can not boot from battery supply
781 * either, shut down the system.
783 static void mxs_handle_5v_conflict(void)
787 debug("SPL: Resolving 5V conflict\n");
789 setbits_le32(&power_regs->hw_power_vddioctrl,
790 POWER_VDDIOCTRL_BO_OFFSET_MASK);
793 tmp = readl(&power_regs->hw_power_sts);
795 if (tmp & POWER_STS_VDDIO_BO) {
797 * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
800 debug("SPL: VDDIO has a brownout\n");
805 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
806 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
810 debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
816 * TODO: I can't see this being reached. We'll either
817 * powerdown or boot from a stable 5V supply.
819 if (tmp & POWER_STS_PSWITCH_MASK) {
820 debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
828 * mxs_5v_boot() - Configure the power block to boot from 5V input
830 * This function handles configuration of the power block when supplied by
833 static void mxs_5v_boot(void)
835 debug("SPL: Configuring power block to boot from 5V input\n");
838 * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
839 * but their implementation always returns 1 so we omit it here.
841 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
842 debug("SPL: 5V VDD good\n");
848 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
849 debug("SPL: 5V VDD good (after delay)\n");
854 debug("SPL: 5V VDD not good\n");
855 mxs_handle_5v_conflict();
858 static void mxs_fixed_batt_boot(void)
860 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
862 writel(POWER_5VCTRL_ENABLE_DCDC |
863 POWER_5VCTRL_ILIMIT_EQ_ZERO |
864 POWER_5VCTRL_PWDN_5VBRNOUT |
865 POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
866 &power_regs->hw_power_5vctrl_set);
868 writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
870 clrbits_le32(&power_regs->hw_power_vdddctrl,
871 POWER_VDDDCTRL_DISABLE_FET |
872 POWER_VDDDCTRL_ENABLE_LINREG |
873 POWER_VDDDCTRL_DISABLE_STEPPING);
875 clrbits_le32(&power_regs->hw_power_vddactrl,
876 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
877 POWER_VDDACTRL_DISABLE_STEPPING);
879 clrbits_le32(&power_regs->hw_power_vddioctrl,
880 POWER_VDDIOCTRL_DISABLE_FET |
881 POWER_VDDIOCTRL_DISABLE_STEPPING);
883 /* Stop 5V detection */
884 writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
885 &power_regs->hw_power_5vctrl_clr);
889 * mxs_init_batt_bo() - Configure battery brownout threshold
891 * This function configures the battery input brownout threshold. The value
892 * at which the battery brownout happens is configured to 3.0V in the code.
894 static void mxs_init_batt_bo(void)
896 debug("SPL: Initialising battery brown-out level to %u.%uV\n",
897 (BATT_BO_VAL * 40 + 2400) / 1000,
898 (BATT_BO_VAL * 40 + 2400) / 100 % 10);
901 clrsetbits_le32(&power_regs->hw_power_battmonitor,
902 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
903 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
905 writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
906 writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
910 * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
912 * This function turns off the VDDD linear regulator and therefore makes
913 * the VDDD rail be supplied only by the DC-DC converter.
915 static void mxs_switch_vddd_to_dcdc_source(void)
917 debug("SPL: Switching VDDD to DC-DC converters\n");
919 clrsetbits_le32(&power_regs->hw_power_vdddctrl,
920 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
921 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
923 clrbits_le32(&power_regs->hw_power_vdddctrl,
924 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
925 POWER_VDDDCTRL_DISABLE_STEPPING);
929 * mxs_power_configure_power_source() - Configure power block source
931 * This function is the core of the power configuration logic. The function
932 * selects the power block input source and configures the whole power block
933 * accordingly. After the configuration is complete and the system is stable
934 * again, the function switches the CPU clock source back to PLL. Finally,
935 * the function switches the voltage rails to DC-DC converter.
937 static void mxs_power_configure_power_source(void)
939 struct mxs_lradc_regs *lradc_regs =
940 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
942 debug("SPL: Configuring power source\n");
944 mxs_src_power_init();
946 if (!fixed_batt_supply) {
947 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
948 if (mxs_is_batt_ready()) {
949 /* 5V source detected, good battery detected. */
952 if (!mxs_is_batt_good()) {
953 /* 5V source detected, bad battery detected. */
954 writel(LRADC_CONVERSION_AUTOMATIC,
955 &lradc_regs->hw_lradc_conversion_clr);
956 clrbits_le32(&power_regs->hw_power_battmonitor,
957 POWER_BATTMONITOR_BATT_VAL_MASK);
962 /* 5V not detected, booting from battery. */
966 mxs_fixed_batt_boot();
970 * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
973 mxs_power_clock2pll();
977 mxs_switch_vddd_to_dcdc_source();
979 #ifdef CONFIG_SOC_MX23
980 /* Fire up the VDDMEM LinReg now that we're all set. */
981 debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
982 writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
983 &power_regs->hw_power_vddmemctrl);
988 * mxs_enable_output_rail_protection() - Enable power rail protection
990 * This function enables overload protection on the power rails. This is
991 * triggered if the power rails' voltage drops rapidly due to overload and
992 * in such case, the supply to the powerrail is cut-off, protecting the
993 * CPU from damage. Note that under such condition, the system will likely
994 * crash or misbehave.
996 static void mxs_enable_output_rail_protection(void)
998 debug("SPL: Enabling output rail protection\n");
1000 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1001 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1003 setbits_le32(&power_regs->hw_power_vdddctrl,
1004 POWER_VDDDCTRL_PWDN_BRNOUT);
1006 setbits_le32(&power_regs->hw_power_vddactrl,
1007 POWER_VDDACTRL_PWDN_BRNOUT);
1009 setbits_le32(&power_regs->hw_power_vddioctrl,
1010 POWER_VDDIOCTRL_PWDN_BRNOUT);
1014 * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1016 * This function tests if the VDDIO rail is supplied by linear regulator
1017 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1018 * returns 0 if powered by the DC-DC converter.
1020 static int mxs_get_vddio_power_source_off(void)
1024 if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1025 !(readl(&power_regs->hw_power_5vctrl) &
1026 POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1028 tmp = readl(&power_regs->hw_power_vddioctrl);
1029 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1030 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1031 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1036 if (!(readl(&power_regs->hw_power_5vctrl) &
1037 POWER_5VCTRL_ENABLE_DCDC)) {
1038 if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1039 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1049 * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1051 * This function tests if the VDDD rail is supplied by linear regulator
1052 * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1053 * returns 0 if powered by the DC-DC converter.
1055 static int mxs_get_vddd_power_source_off(void)
1059 tmp = readl(&power_regs->hw_power_vdddctrl);
1060 if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1061 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1062 POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1067 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1068 if (!(readl(&power_regs->hw_power_5vctrl) &
1069 POWER_5VCTRL_ENABLE_DCDC)) {
1074 if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1075 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1076 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1084 static int mxs_get_vdda_power_source_off(void)
1088 tmp = readl(&power_regs->hw_power_vddactrl);
1089 if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1090 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1091 POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1096 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1097 if (!(readl(&power_regs->hw_power_5vctrl) &
1098 POWER_5VCTRL_ENABLE_DCDC)) {
1103 if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1104 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1105 POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1113 struct mxs_vddx_cfg {
1117 uint16_t highest_mV;
1118 int (*powered_by_linreg)(void);
1122 uint32_t bo_offset_mask;
1123 uint32_t bo_offset_offset;
1128 #define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1130 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1131 .reg = POWER_REG(hw_power_vddioctrl),
1132 #if defined(CONFIG_SOC_MX23)
1139 .powered_by_linreg = mxs_get_vddio_power_source_off,
1140 .trg_mask = POWER_VDDIOCTRL_TRG_MASK,
1141 .bo_irq = POWER_CTRL_VDDIO_BO_IRQ,
1142 .bo_enirq = POWER_CTRL_ENIRQ_VDDIO_BO,
1143 .bo_offset_mask = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1144 .bo_offset_offset = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1149 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1150 .reg = POWER_REG(hw_power_vdddctrl),
1154 .powered_by_linreg = mxs_get_vddd_power_source_off,
1155 .trg_mask = POWER_VDDDCTRL_TRG_MASK,
1156 .bo_irq = POWER_CTRL_VDDD_BO_IRQ,
1157 .bo_enirq = POWER_CTRL_ENIRQ_VDDD_BO,
1158 .bo_offset_mask = POWER_VDDDCTRL_BO_OFFSET_MASK,
1159 .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1164 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1165 .reg = POWER_REG(hw_power_vddactrl),
1169 .powered_by_linreg = mxs_get_vdda_power_source_off,
1170 .trg_mask = POWER_VDDACTRL_TRG_MASK,
1171 .bo_irq = POWER_CTRL_VDDA_BO_IRQ,
1172 .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO,
1173 .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK,
1174 .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1179 #ifdef CONFIG_SOC_MX23
1180 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1181 .reg = POWER_REG(hw_power_vddmemctrl),
1185 .powered_by_linreg = NULL,
1186 .trg_mask = POWER_VDDMEMCTRL_TRG_MASK,
1189 .bo_offset_mask = 0,
1190 .bo_offset_offset = 0,
1195 * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1196 * @cfg: Configuration data of the DC-DC converter rail
1197 * @new_target: New target voltage of the DC-DC converter rail
1198 * @new_brownout: New brownout trigger voltage
1200 * This function configures the output voltage on the DC-DC converter rail.
1201 * The rail is selected by the @cfg argument. The new voltage target is
1202 * selected by the @new_target and the voltage is specified in mV. The
1203 * new brownout value is selected by the @new_brownout argument and the
1204 * value is also in mV.
1206 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1207 uint32_t new_target, uint32_t bo_offset)
1209 uint32_t cur_target, diff, bo_int = 0;
1210 int powered_by_linreg = 0;
1213 if (new_target < cfg->lowest_mV) {
1214 new_target = cfg->lowest_mV;
1216 if (new_target > cfg->highest_mV) {
1217 new_target = cfg->highest_mV;
1220 if (new_target - bo_offset < cfg->bo_min_mV) {
1221 bo_offset = new_target - cfg->bo_min_mV;
1222 } else if (new_target - bo_offset > cfg->bo_max_mV) {
1223 bo_offset = new_target - cfg->bo_max_mV;
1226 bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1228 cur_target = readl(cfg->reg);
1229 cur_target &= cfg->trg_mask;
1230 cur_target *= cfg->step_mV;
1231 cur_target += cfg->lowest_mV;
1233 adjust_up = new_target > cur_target;
1234 if (cfg->powered_by_linreg)
1235 powered_by_linreg = cfg->powered_by_linreg();
1237 if (adjust_up && cfg->bo_irq) {
1238 if (powered_by_linreg) {
1239 bo_int = readl(&power_regs->hw_power_ctrl);
1240 writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1242 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1246 if (abs(new_target - cur_target) > 100) {
1248 diff = cur_target + 100;
1250 diff = cur_target - 100;
1255 diff -= cfg->lowest_mV;
1256 diff /= cfg->step_mV;
1258 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1260 if (powered_by_linreg ||
1261 (readl(&power_regs->hw_power_sts) &
1262 POWER_STS_VDD5V_GT_VDDIO)) {
1265 while (!(readl(&power_regs->hw_power_sts) &
1271 cur_target = readl(cfg->reg);
1272 cur_target &= cfg->trg_mask;
1273 cur_target *= cfg->step_mV;
1274 cur_target += cfg->lowest_mV;
1275 } while (new_target > cur_target);
1278 if (adjust_up && powered_by_linreg) {
1279 writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1280 if (bo_int & cfg->bo_enirq)
1281 writel(cfg->bo_enirq,
1282 &power_regs->hw_power_ctrl_set);
1285 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1286 bo_offset << cfg->bo_offset_offset);
1291 * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1293 * This function starts and configures the LRADC block. This allows the
1294 * power initialization code to measure battery voltage and based on this
1295 * knowledge, decide whether to boot at all, boot from battery or boot
1298 static void mxs_setup_batt_detect(void)
1300 debug("SPL: Starting battery voltage measurement logic\n");
1303 mxs_lradc_enable_batt_measurement();
1308 * mxs_ungate_power() - Ungate the POWER block
1310 * This function ungates clock to the power block. In case the power block
1311 * was still gated at this point, it will not be possible to configure the
1312 * block and therefore the power initialization would fail. This function
1313 * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1315 static void mxs_ungate_power(void)
1317 #ifdef CONFIG_SOC_MX23
1318 writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1322 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1323 #define auto_restart 1
1325 #define auto_restart 0
1329 * mxs_power_init() - The power block init main function
1331 * This function calls all the power block initialization functions in
1332 * proper sequence to start the power block.
1334 #define VDDX_VAL(v) (v) / 1000, (v) / 100 % 10
1336 void mxs_power_init(void)
1338 debug("SPL: Initialising Power Block\n");
1342 mxs_power_clock2xtal();
1343 if (mxs_power_set_auto_restart(auto_restart)) {
1344 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1346 mxs_power_set_linreg();
1348 if (!fixed_batt_supply) {
1349 mxs_power_setup_5v_detect();
1350 mxs_setup_batt_detect();
1353 mxs_power_configure_power_source();
1354 mxs_enable_output_rail_protection();
1356 debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1357 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1358 mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1359 debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1360 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1361 mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1362 debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1363 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1364 mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1365 #ifdef CONFIG_SOC_MX23
1366 debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1367 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1368 mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1370 clrbits_le32(&power_regs->hw_power_vddmemctrl,
1371 POWER_VDDMEMCTRL_ENABLE_LINREG);
1373 writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1374 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1375 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1376 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1377 if (!fixed_batt_supply)
1378 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1379 &power_regs->hw_power_5vctrl_set);
1382 #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT
1384 * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1386 * This function waits until the power-switch was pressed to start booting
1389 void mxs_power_wait_pswitch(void)
1391 debug("SPL: Waiting for power switch input\n");
1392 while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))