arch/arm/cpu/arm926ejs/mxs/spl_power_init.c

   1 /*
   2  * Freescale i.MX28 Boot PMIC init
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <config.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/imx-regs.h>
  14
  15 #include "mxs_init.h"
  16
  17 #ifdef CONFIG_SYS_SPL_VDDD_VAL
  18 #define VDDD_VAL        CONFIG_SYS_SPL_VDDD_VAL
  19 #else
  20 #define VDDD_VAL        1350
  21 #endif
  22 #ifdef CONFIG_SYS_SPL_VDDIO_VAL
  23 #define VDDIO_VAL       CONFIG_SYS_SPL_VDDIO_VAL
  24 #else
  25 #define VDDIO_VAL       3300
  26 #endif
  27 #ifdef CONFIG_SYS_SPL_VDDA_VAL
  28 #define VDDA_VAL        CONFIG_SYS_SPL_VDDA_VAL
  29 #else
  30 #define VDDA_VAL        1800
  31 #endif
  32 #ifdef CONFIG_SYS_SPL_VDDMEM_VAL
  33 #define VDDMEM_VAL      CONFIG_SYS_SPL_VDDMEM_VAL
  34 #else
  35 #define VDDMEM_VAL      1700
  36 #endif
  37
  38 #ifdef CONFIG_SYS_SPL_VDDD_BO_VAL
  39 #define VDDD_BO_VAL     CONFIG_SYS_SPL_VDDD_BO_VAL
  40 #else
  41 #define VDDD_BO_VAL     150
  42 #endif
  43 #ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL
  44 #define VDDIO_BO_VAL    CONFIG_SYS_SPL_VDDIO_BO_VAL
  45 #else
  46 #define VDDIO_BO_VAL    150
  47 #endif
  48 #ifdef CONFIG_SYS_SPL_VDDA_BO_VAL
  49 #define VDDA_BO_VAL     CONFIG_SYS_SPL_VDDA_BO_VAL
  50 #else
  51 #define VDDA_BO_VAL     175
  52 #endif
  53 #ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL
  54 #define VDDMEM_BO_VAL   CONFIG_SYS_SPL_VDDMEM_BO_VAL
  55 #else
  56 #define VDDMEM_BO_VAL   25
  57 #endif
  58
  59 #ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL
  60 #if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640
  61 #error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range
  62 #endif
  63 #define BATT_BO_VAL     (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40)
  64 #else
  65 /* Brownout default at 3V */
  66 #define BATT_BO_VAL     ((3000 - 2400) / 40)
  67 #endif
  68
  69 #ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY
  70 static const int fixed_batt_supply = 1;
  71 #else
  72 static const int fixed_batt_supply;
  73 #endif
  74
  75 static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE;
  76
  77 /**
  78  * mxs_power_clock2xtal() - Switch CPU core clock source to 24MHz XTAL
  79  *
  80  * This function switches the CPU core clock from PLL to 24MHz XTAL
  81  * oscilator. This is necessary if the PLL is being reconfigured to
  82  * prevent crash of the CPU core.
  83  */
  84 static void mxs_power_clock2xtal(void)
  85 {
  86         struct mxs_clkctrl_regs *clkctrl_regs =
  87                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  88
  89         debug("SPL: Switching CPU clock to 24MHz XTAL\n");
  90
  91         /* Set XTAL as CPU reference clock */
  92         writel(CLKCTRL_CLKSEQ_BYPASS_CPU,
  93                 &clkctrl_regs->hw_clkctrl_clkseq_set);
  94 }
  95
  96 /**
  97  * mxs_power_clock2pll() - Switch CPU core clock source to PLL
  98  *
  99  * This function switches the CPU core clock from 24MHz XTAL oscilator
 100  * to PLL. This can only be called once the PLL has re-locked and once
 101  * the PLL is stable after reconfiguration.
 102  */
 103 static void mxs_power_clock2pll(void)
 104 {
 105         struct mxs_clkctrl_regs *clkctrl_regs =
 106                 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 107
 108         debug("SPL: Switching CPU core clock source to PLL\n");
 109
 110         /*
 111          * TODO: Are we really? It looks like we turn on PLL0, but we then
 112          * set the CLKCTRL_CLKSEQ_BYPASS_CPU bit of the (which was already
 113          * set by mxs_power_clock2xtal()). Clearing this bit here seems to
 114          * introduce some instability (causing the CPU core to hang). Maybe
 115          * we aren't giving PLL0 enough time to stabilise?
 116          */
 117         setbits_le32(&clkctrl_regs->hw_clkctrl_pll0ctrl0,
 118                         CLKCTRL_PLL0CTRL0_POWER);
 119         early_delay(100);
 120
 121         /*
 122          * TODO: Should the PLL0 FORCE_LOCK bit be set here followed be a
 123          * wait on the PLL0 LOCK bit?
 124          */
 125         setbits_le32(&clkctrl_regs->hw_clkctrl_clkseq,
 126                         CLKCTRL_CLKSEQ_BYPASS_CPU);
 127 }
 128
 129 static int mxs_power_wait_rtc_stat(u32 mask)
 130 {
 131         int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */
 132         u32 val;
 133         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 134
 135         while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) {
 136                 early_delay(1);
 137                 if (timeout-- < 0)
 138                         break;
 139         }
 140         return !!(readl(&rtc_regs->hw_rtc_stat) & mask);
 141 }
 142
 143 /**
 144  * mxs_power_set_auto_restart() - Set the auto-restart bit
 145  *
 146  * This function ungates the RTC block and sets the AUTO_RESTART
 147  * bit to work around a design bug on MX28EVK Rev. A .
 148  */
 149 static int mxs_power_set_auto_restart(int on)
 150 {
 151         struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE;
 152
 153         debug("SPL: Setting auto-restart bit\n");
 154
 155         if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0))
 156                 return 1;
 157
 158         /* Do nothing if flag already set */
 159         if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
 160                 return 0;
 161
 162         if ((!(readl(&rtc_regs->hw_rtc_persistent0) &
 163                                 RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0)
 164                 return 0;
 165
 166         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
 167                 return 1;
 168
 169         clrsetbits_le32(&rtc_regs->hw_rtc_persistent0,
 170                         !on * RTC_PERSISTENT0_AUTO_RESTART,
 171                         !!on * RTC_PERSISTENT0_AUTO_RESTART);
 172         if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0))
 173                 return 1;
 174
 175         return 0;
 176 }
 177
 178 /**
 179  * mxs_power_set_linreg() - Set linear regulators 25mV below DC-DC converter
 180  *
 181  * This function configures the VDDIO, VDDA and VDDD linear regulators output
 182  * to be 25mV below the VDDIO, VDDA and VDDD output from the DC-DC switching
 183  * converter. This is the recommended setting for the case where we use both
 184  * linear regulators and DC-DC converter to power the VDDIO rail.
 185  */
 186 static void mxs_power_set_linreg(void)
 187 {
 188         /* Set linear regulator 25mV below switching converter */
 189         debug("SPL: Setting VDDD 25mV below DC-DC converters\n");
 190         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 191                         POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 192                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 193
 194         debug("SPL: Setting VDDA 25mV below DC-DC converters\n");
 195         clrsetbits_le32(&power_regs->hw_power_vddactrl,
 196                         POWER_VDDACTRL_LINREG_OFFSET_MASK,
 197                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
 198
 199         debug("SPL: Setting VDDIO 25mV below DC-DC converters\n");
 200         clrsetbits_le32(&power_regs->hw_power_vddioctrl,
 201                         POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
 202                         POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
 203 }
 204
 205 /**
 206  * mxs_get_batt_volt() - Measure battery input voltage
 207  *
 208  * This function retrieves the battery input voltage and returns it.
 209  */
 210 static int mxs_get_batt_volt(void)
 211 {
 212         uint32_t volt = readl(&power_regs->hw_power_battmonitor);
 213
 214         volt &= POWER_BATTMONITOR_BATT_VAL_MASK;
 215         volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET;
 216         volt *= 8;
 217
 218         debug("SPL: Battery Voltage = %dmV\n", volt);
 219         return volt;
 220 }
 221
 222 /**
 223  * mxs_is_batt_ready() - Test if the battery provides enough voltage to boot
 224  *
 225  * This function checks if the battery input voltage is higher than 3.6V and
 226  * therefore allows the system to successfully boot using this power source.
 227  */
 228 static int mxs_is_batt_ready(void)
 229 {
 230         return (mxs_get_batt_volt() >= 3600);
 231 }
 232
 233 /**
 234  * mxs_is_batt_good() - Test if battery is operational at all
 235  *
 236  * This function starts recharging the battery and tests if the input current
 237  * provided by the 5V input recharging the battery is also sufficient to power
 238  * the DC-DC converter.
 239  */
 240 static int mxs_is_batt_good(void)
 241 {
 242         uint32_t volt = mxs_get_batt_volt();
 243
 244         if ((volt >= 2400) && (volt <= 4300)) {
 245                 debug("SPL: Battery is good\n");
 246                 return 1;
 247         }
 248
 249         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 250                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 251                 0x3 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 252         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 253                 &power_regs->hw_power_5vctrl_clr);
 254
 255         clrsetbits_le32(&power_regs->hw_power_charge,
 256                 POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 257                 POWER_CHARGE_STOP_ILIMIT_10MA | 0x3);
 258
 259         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_clr);
 260         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 261                 &power_regs->hw_power_5vctrl_clr);
 262
 263         early_delay(500000);
 264
 265         volt = mxs_get_batt_volt();
 266
 267         if (volt >= 3500) {
 268                 debug("SPL: Battery Voltage too high\n");
 269                 return 0;
 270         }
 271
 272         if (volt >= 2400) {
 273                 debug("SPL: Battery is good\n");
 274                 return 1;
 275         }
 276
 277         writel(POWER_CHARGE_STOP_ILIMIT_MASK | POWER_CHARGE_BATTCHRG_I_MASK,
 278                 &power_regs->hw_power_charge_clr);
 279         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 280
 281         if (volt >= 3500) {
 282                 return 0;
 283         }
 284         if (volt >= 2400) {
 285                 return 1;
 286         }
 287         debug("SPL: Battery Voltage too low\n");
 288         return 0;
 289 }
 290
 291 /**
 292  * mxs_power_setup_5v_detect() - Start the 5V input detection comparator
 293  *
 294  * This function enables the 5V detection comparator and sets the 5V valid
 295  * threshold to 4.4V . We use 4.4V threshold here to make sure that even
 296  * under high load, the voltage drop on the 5V input won't be so critical
 297  * to cause undervolt on the 4P2 linear regulator supplying the DC-DC
 298  * converter and thus making the system crash.
 299  */
 300 static void mxs_power_setup_5v_detect(void)
 301 {
 302         /* Start 5V detection */
 303         debug("SPL: Starting 5V input detection comparator\n");
 304         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 305                         POWER_5VCTRL_VBUSVALID_TRSH_MASK,
 306                         POWER_5VCTRL_VBUSVALID_TRSH_4V4 |
 307                         POWER_5VCTRL_PWRUP_VBUS_CMPS);
 308 }
 309
 310 /**
 311  * mxs_src_power_init() - Preconfigure the power block
 312  *
 313  * This function configures reasonable values for the DC-DC control loop
 314  * and battery monitor.
 315  */
 316 static void mxs_src_power_init(void)
 317 {
 318         debug("SPL: Pre-Configuring power block\n");
 319
 320         /* Improve efficieny and reduce transient ripple */
 321         writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST |
 322                 POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set);
 323
 324         clrsetbits_le32(&power_regs->hw_power_dclimits,
 325                         POWER_DCLIMITS_POSLIMIT_BUCK_MASK,
 326                         0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET);
 327
 328         if (!fixed_batt_supply) {
 329                 /* FIXME: This requires the LRADC to be set up! */
 330                 setbits_le32(&power_regs->hw_power_battmonitor,
 331                         POWER_BATTMONITOR_EN_BATADJ);
 332         } else {
 333                 clrbits_le32(&power_regs->hw_power_battmonitor,
 334                         POWER_BATTMONITOR_EN_BATADJ);
 335         }
 336
 337         /* Increase the RCSCALE level for quick DCDC response to dynamic load */
 338         clrsetbits_le32(&power_regs->hw_power_loopctrl,
 339                         POWER_LOOPCTRL_EN_RCSCALE_MASK,
 340                         POWER_LOOPCTRL_RCSCALE_THRESH |
 341                         POWER_LOOPCTRL_EN_RCSCALE_8X);
 342
 343         clrsetbits_le32(&power_regs->hw_power_minpwr,
 344                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 345
 346         if (!fixed_batt_supply) {
 347                 /* 5V to battery handoff ... FIXME */
 348                 setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 349                 early_delay(30);
 350                 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 351         }
 352 }
 353
 354 /**
 355  * mxs_power_init_4p2_params() - Configure the parameters of the 4P2 regulator
 356  *
 357  * This function configures the necessary parameters for the 4P2 linear
 358  * regulator to supply the DC-DC converter from 5V input.
 359  */
 360 static void mxs_power_init_4p2_params(void)
 361 {
 362         debug("SPL: Configuring common 4P2 regulator params\n");
 363
 364         /* Setup 4P2 parameters */
 365         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 366                 POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK,
 367                 POWER_DCDC4P2_TRG_4V2 | (31 << POWER_DCDC4P2_CMPTRIP_OFFSET));
 368
 369         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 370                 POWER_5VCTRL_HEADROOM_ADJ_MASK,
 371                 0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
 372
 373         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 374                 POWER_DCDC4P2_DROPOUT_CTRL_MASK,
 375                 POWER_DCDC4P2_DROPOUT_CTRL_100MV |
 376                 POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
 377
 378         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 379                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 380                 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 381 }
 382
 383 /**
 384  * mxs_enable_4p2_dcdc_input() - Enable or disable the DCDC input from 4P2
 385  * @xfer:       Select if the input shall be enabled or disabled
 386  *
 387  * This function enables or disables the 4P2 input into the DC-DC converter.
 388  */
 389 static void mxs_enable_4p2_dcdc_input(int xfer)
 390 {
 391         uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
 392         uint32_t prev_5v_brnout, prev_5v_droop;
 393
 394         debug("SPL: %s 4P2 DC-DC Input\n", xfer ? "Enabling" : "Disabling");
 395
 396         prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
 397                                 POWER_5VCTRL_PWDN_5VBRNOUT;
 398         prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
 399                                 POWER_CTRL_ENIRQ_VDD5V_DROOP;
 400
 401         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 402         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 403                 &power_regs->hw_power_reset);
 404
 405         clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
 406
 407         if (xfer && (readl(&power_regs->hw_power_5vctrl) &
 408                         POWER_5VCTRL_ENABLE_DCDC)) {
 409                 return;
 410         }
 411
 412         /*
 413          * Recording orignal values that will be modified temporarlily
 414          * to handle a chip bug. See chip errata for CQ ENGR00115837
 415          */
 416         tmp = readl(&power_regs->hw_power_5vctrl);
 417         vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
 418         vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
 419
 420         pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
 421
 422         /*
 423          * Disable mechanisms that get erroneously tripped by when setting
 424          * the DCDC4P2 EN_DCDC
 425          */
 426         clrbits_le32(&power_regs->hw_power_5vctrl,
 427                 POWER_5VCTRL_VBUSVALID_5VDETECT |
 428                 POWER_5VCTRL_VBUSVALID_TRSH_MASK);
 429
 430         writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
 431
 432         if (xfer) {
 433                 setbits_le32(&power_regs->hw_power_5vctrl,
 434                                 POWER_5VCTRL_DCDC_XFER);
 435                 early_delay(20);
 436                 clrbits_le32(&power_regs->hw_power_5vctrl,
 437                                 POWER_5VCTRL_DCDC_XFER);
 438
 439                 setbits_le32(&power_regs->hw_power_5vctrl,
 440                                 POWER_5VCTRL_ENABLE_DCDC);
 441         } else {
 442                 setbits_le32(&power_regs->hw_power_dcdc4p2,
 443                                 POWER_DCDC4P2_ENABLE_DCDC);
 444         }
 445
 446         early_delay(25);
 447
 448         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 449                         POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
 450
 451         if (vbus_5vdetect)
 452                 writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
 453
 454         if (!pwd_bo)
 455                 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
 456
 457         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
 458                 writel(POWER_CTRL_VBUS_VALID_IRQ,
 459                         &power_regs->hw_power_ctrl_clr);
 460
 461         if (prev_5v_brnout) {
 462                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 463                         &power_regs->hw_power_5vctrl_set);
 464                 writel(POWER_RESET_UNLOCK_KEY,
 465                         &power_regs->hw_power_reset);
 466         } else {
 467                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
 468                         &power_regs->hw_power_5vctrl_clr);
 469                 writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 470                         &power_regs->hw_power_reset);
 471         }
 472
 473         while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
 474                 writel(POWER_CTRL_VDD5V_DROOP_IRQ,
 475                         &power_regs->hw_power_ctrl_clr);
 476
 477         if (prev_5v_droop)
 478                 clrbits_le32(&power_regs->hw_power_ctrl,
 479                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 480         else
 481                 setbits_le32(&power_regs->hw_power_ctrl,
 482                                 POWER_CTRL_ENIRQ_VDD5V_DROOP);
 483 }
 484
 485 /**
 486  * mxs_power_init_4p2_regulator() - Start the 4P2 regulator
 487  *
 488  * This function enables the 4P2 regulator and switches the DC-DC converter
 489  * to use the 4P2 input.
 490  */
 491 static void mxs_power_init_4p2_regulator(void)
 492 {
 493         uint32_t tmp, tmp2;
 494
 495         debug("SPL: Enabling 4P2 regulator\n");
 496
 497         setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
 498
 499         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set);
 500
 501         writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 502                 &power_regs->hw_power_5vctrl_clr);
 503         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK);
 504
 505         /* Power up the 4p2 rail and logic/control */
 506         writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 507                 &power_regs->hw_power_5vctrl_clr);
 508
 509         /*
 510          * Start charging up the 4p2 capacitor. We ramp of this charge
 511          * gradually to avoid large inrush current from the 5V cable which can
 512          * cause transients/problems
 513          */
 514         debug("SPL: Charging 4P2 capacitor\n");
 515         mxs_enable_4p2_dcdc_input(0);
 516
 517         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 518                 /*
 519                  * If we arrived here, we were unable to recover from mx23 chip
 520                  * errata 5837. 4P2 is disabled and sufficient battery power is
 521                  * not present. Exiting to not enable DCDC power during 5V
 522                  * connected state.
 523                  */
 524                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 525                         POWER_DCDC4P2_ENABLE_DCDC);
 526                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 527                         &power_regs->hw_power_5vctrl_set);
 528
 529                 debug("SPL: Unable to recover from mx23 errata 5837\n");
 530                 hang();
 531         }
 532
 533         /*
 534          * Here we set the 4p2 brownout level to something very close to 4.2V.
 535          * We then check the brownout status. If the brownout status is false,
 536          * the voltage is already close to the target voltage of 4.2V so we
 537          * can go ahead and set the 4P2 current limit to our max target limit.
 538          * If the brownout status is true, we need to ramp up the current limit
 539          * so that we don't cause large inrush current issues. We step up the
 540          * current limit until the brownout status is false or until we've
 541          * reached our maximum defined 4p2 current limit.
 542          */
 543         debug("SPL: Setting 4P2 brownout level\n");
 544         clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
 545                         POWER_DCDC4P2_BO_MASK,
 546                         22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */
 547
 548         if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
 549                 setbits_le32(&power_regs->hw_power_5vctrl,
 550                         0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 551         } else {
 552                 tmp = (readl(&power_regs->hw_power_5vctrl) &
 553                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
 554                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 555                 while (tmp < 0x3f) {
 556                         if (!(readl(&power_regs->hw_power_sts) &
 557                                         POWER_STS_DCDC_4P2_BO)) {
 558                                 tmp = readl(&power_regs->hw_power_5vctrl);
 559                                 tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 560                                 early_delay(100);
 561                                 writel(tmp, &power_regs->hw_power_5vctrl);
 562                                 break;
 563                         } else {
 564                                 tmp++;
 565                                 tmp2 = readl(&power_regs->hw_power_5vctrl);
 566                                 tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
 567                                 tmp2 |= tmp <<
 568                                         POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
 569                                 writel(tmp2, &power_regs->hw_power_5vctrl);
 570                                 early_delay(100);
 571                         }
 572                 }
 573         }
 574
 575         clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
 576         writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 577 }
 578
 579 /**
 580  * mxs_power_init_dcdc_4p2_source() - Switch DC-DC converter to 4P2 source
 581  *
 582  * This function configures the DC-DC converter to be supplied from the 4P2
 583  * linear regulator.
 584  */
 585 static void mxs_power_init_dcdc_4p2_source(void)
 586 {
 587         debug("SPL: Switching DC-DC converters to 4P2\n");
 588
 589         if (!(readl(&power_regs->hw_power_dcdc4p2) &
 590                 POWER_DCDC4P2_ENABLE_DCDC)) {
 591                 debug("SPL: Already switched - aborting\n");
 592                 hang();
 593         }
 594
 595         mxs_enable_4p2_dcdc_input(1);
 596
 597         if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
 598                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 599                         POWER_DCDC4P2_ENABLE_DCDC);
 600                 writel(POWER_5VCTRL_ENABLE_DCDC,
 601                         &power_regs->hw_power_5vctrl_clr);
 602                 writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
 603                         &power_regs->hw_power_5vctrl_set);
 604         }
 605 }
 606
 607 /**
 608  * mxs_power_enable_4p2() - Power up the 4P2 regulator
 609  *
 610  * This function drives the process of powering up the 4P2 linear regulator
 611  * and switching the DC-DC converter input over to the 4P2 linear regulator.
 612  */
 613 static void mxs_power_enable_4p2(void)
 614 {
 615         uint32_t vdddctrl, vddactrl, vddioctrl;
 616         uint32_t tmp;
 617
 618         debug("SPL: Powering up 4P2 regulator\n");
 619
 620         vdddctrl = readl(&power_regs->hw_power_vdddctrl);
 621         vddactrl = readl(&power_regs->hw_power_vddactrl);
 622         vddioctrl = readl(&power_regs->hw_power_vddioctrl);
 623
 624         setbits_le32(&power_regs->hw_power_vdddctrl,
 625                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 626                 POWER_VDDDCTRL_PWDN_BRNOUT);
 627
 628         setbits_le32(&power_regs->hw_power_vddactrl,
 629                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 630                 POWER_VDDACTRL_PWDN_BRNOUT);
 631
 632         setbits_le32(&power_regs->hw_power_vddioctrl,
 633                 POWER_VDDIOCTRL_DISABLE_FET | POWER_VDDIOCTRL_PWDN_BRNOUT);
 634
 635         mxs_power_init_4p2_params();
 636         mxs_power_init_4p2_regulator();
 637
 638         /* Shutdown battery (none present) */
 639         if (!mxs_is_batt_ready()) {
 640                 clrbits_le32(&power_regs->hw_power_dcdc4p2,
 641                                 POWER_DCDC4P2_BO_MASK);
 642                 writel(POWER_CTRL_DCDC4P2_BO_IRQ,
 643                                 &power_regs->hw_power_ctrl_clr);
 644                 writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
 645                                 &power_regs->hw_power_ctrl_clr);
 646         }
 647
 648         mxs_power_init_dcdc_4p2_source();
 649
 650         writel(vdddctrl, &power_regs->hw_power_vdddctrl);
 651         early_delay(20);
 652         writel(vddactrl, &power_regs->hw_power_vddactrl);
 653         early_delay(20);
 654         writel(vddioctrl, &power_regs->hw_power_vddioctrl);
 655
 656         /*
 657          * Check if FET is enabled on either powerout and if so,
 658          * disable load.
 659          */
 660         tmp = 0;
 661         tmp |= !(readl(&power_regs->hw_power_vdddctrl) &
 662                         POWER_VDDDCTRL_DISABLE_FET);
 663         tmp |= !(readl(&power_regs->hw_power_vddactrl) &
 664                         POWER_VDDACTRL_DISABLE_FET);
 665         tmp |= !(readl(&power_regs->hw_power_vddioctrl) &
 666                         POWER_VDDIOCTRL_DISABLE_FET);
 667         if (tmp)
 668                 writel(POWER_CHARGE_ENABLE_LOAD,
 669                         &power_regs->hw_power_charge_clr);
 670
 671         debug("SPL: 4P2 regulator powered-up\n");
 672 }
 673
 674 /**
 675  * mxs_boot_valid_5v() - Boot from 5V supply
 676  *
 677  * This function configures the power block to boot from valid 5V input.
 678  * This is called only if the 5V is reliable and can properly supply the
 679  * CPU. This function proceeds to configure the 4P2 converter to be supplied
 680  * from the 5V input.
 681  */
 682 static void mxs_boot_valid_5v(void)
 683 {
 684         debug("SPL: Booting from 5V supply\n");
 685
 686         /*
 687          * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V
 688          * disconnect event. FIXME
 689          */
 690         writel(POWER_5VCTRL_VBUSVALID_5VDETECT,
 691                 &power_regs->hw_power_5vctrl_set);
 692
 693         /* Configure polarity to check for 5V disconnection. */
 694         writel(POWER_CTRL_POLARITY_VBUSVALID |
 695                 POWER_CTRL_POLARITY_VDD5V_GT_VDDIO,
 696                 &power_regs->hw_power_ctrl_clr);
 697
 698         writel(POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_VDD5V_GT_VDDIO_IRQ,
 699                 &power_regs->hw_power_ctrl_clr);
 700
 701         mxs_power_enable_4p2();
 702 }
 703
 704 /**
 705  * mxs_powerdown() - Shut down the system
 706  *
 707  * This function powers down the CPU completely.
 708  */
 709 static void mxs_powerdown(void)
 710 {
 711         debug("Powering Down\n");
 712
 713         writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
 714         writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
 715                 &power_regs->hw_power_reset);
 716 }
 717
 718 /**
 719  * mxs_batt_boot() - Configure the power block to boot from battery input
 720  *
 721  * This function configures the power block to boot from the battery voltage
 722  * supply.
 723  */
 724 static void mxs_batt_boot(void)
 725 {
 726         debug("SPL: Configuring power block to boot from battery\n");
 727
 728         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
 729         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC);
 730
 731         clrbits_le32(&power_regs->hw_power_dcdc4p2,
 732                         POWER_DCDC4P2_ENABLE_DCDC | POWER_DCDC4P2_ENABLE_4P2);
 733         writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_clr);
 734
 735         /* 5V to battery handoff. */
 736         setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 737         early_delay(30);
 738         clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
 739
 740         writel(POWER_CTRL_ENIRQ_DCDC4P2_BO, &power_regs->hw_power_ctrl_clr);
 741
 742         clrsetbits_le32(&power_regs->hw_power_minpwr,
 743                         POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS);
 744
 745         mxs_power_set_linreg();
 746
 747         clrbits_le32(&power_regs->hw_power_vdddctrl,
 748                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG);
 749
 750         clrbits_le32(&power_regs->hw_power_vddactrl,
 751                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG);
 752
 753         clrbits_le32(&power_regs->hw_power_vddioctrl,
 754                 POWER_VDDIOCTRL_DISABLE_FET);
 755
 756         setbits_le32(&power_regs->hw_power_5vctrl,
 757                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 758
 759         setbits_le32(&power_regs->hw_power_5vctrl,
 760                 POWER_5VCTRL_ENABLE_DCDC);
 761
 762         clrsetbits_le32(&power_regs->hw_power_5vctrl,
 763                 POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
 764                 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
 765
 766         mxs_power_enable_4p2();
 767 }
 768
 769 /**
 770  * mxs_handle_5v_conflict() - Test if the 5V input is reliable
 771  *
 772  * This function tests if the 5V input can reliably supply the system. If it
 773  * can, then proceed to configuring the system to boot from 5V source, otherwise
 774  * try booting from battery supply. If we can not boot from battery supply
 775  * either, shut down the system.
 776  */
 777 static void mxs_handle_5v_conflict(void)
 778 {
 779         uint32_t tmp;
 780
 781         debug("SPL: Resolving 5V conflict\n");
 782
 783         setbits_le32(&power_regs->hw_power_vddioctrl,
 784                         POWER_VDDIOCTRL_BO_OFFSET_MASK);
 785
 786         for (;;) {
 787                 tmp = readl(&power_regs->hw_power_sts);
 788
 789                 if (tmp & POWER_STS_VDDIO_BO) {
 790                         /*
 791                          * If VDDIO has a brownout, then the VDD5V_GT_VDDIO
 792                          * becomes unreliable
 793                          */
 794                         debug("SPL: VDDIO has a brownout\n");
 795                         mxs_powerdown();
 796                         break;
 797                 }
 798
 799                 if (tmp & POWER_STS_VDD5V_GT_VDDIO) {
 800                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is set\n");
 801                         mxs_boot_valid_5v();
 802                         break;
 803                 } else {
 804                         debug("SPL: POWER_STS_VDD5V_GT_VDDIO is not set\n");
 805                         mxs_powerdown();
 806                         break;
 807                 }
 808
 809                 /*
 810                  * TODO: I can't see this being reached. We'll either
 811                  * powerdown or boot from a stable 5V supply.
 812                  */
 813                 if (tmp & POWER_STS_PSWITCH_MASK) {
 814                         debug("SPL: POWER_STS_PSWITCH_MASK is set\n");
 815                         mxs_batt_boot();
 816                         break;
 817                 }
 818         }
 819 }
 820
 821 /**
 822  * mxs_5v_boot() - Configure the power block to boot from 5V input
 823  *
 824  * This function handles configuration of the power block when supplied by
 825  * a 5V input.
 826  */
 827 static void mxs_5v_boot(void)
 828 {
 829         debug("SPL: Configuring power block to boot from 5V input\n");
 830
 831         /*
 832          * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID,
 833          * but their implementation always returns 1 so we omit it here.
 834          */
 835         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 836                 debug("SPL: 5V VDD good\n");
 837                 mxs_boot_valid_5v();
 838                 return;
 839         }
 840
 841         early_delay(1000);
 842         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 843                 debug("SPL: 5V VDD good (after delay)\n");
 844                 mxs_boot_valid_5v();
 845                 return;
 846         }
 847
 848         debug("SPL: 5V VDD not good\n");
 849         mxs_handle_5v_conflict();
 850 }
 851
 852 static void mxs_fixed_batt_boot(void)
 853 {
 854         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 855
 856         setbits_le32(&power_regs->hw_power_5vctrl,
 857                 POWER_5VCTRL_ENABLE_DCDC |
 858                 POWER_5VCTRL_ILIMIT_EQ_ZERO |
 859                 POWER_5VCTRL_PWDN_5VBRNOUT |
 860                 POWER_5VCTRL_PWD_CHARGE_4P2_MASK);
 861
 862         writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set);
 863
 864         clrbits_le32(&power_regs->hw_power_vdddctrl,
 865                 POWER_VDDDCTRL_DISABLE_FET |
 866                 POWER_VDDDCTRL_ENABLE_LINREG |
 867                 POWER_VDDDCTRL_DISABLE_STEPPING);
 868
 869         clrbits_le32(&power_regs->hw_power_vddactrl,
 870                 POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG |
 871                 POWER_VDDACTRL_DISABLE_STEPPING);
 872
 873         clrbits_le32(&power_regs->hw_power_vddioctrl,
 874                 POWER_VDDIOCTRL_DISABLE_FET |
 875                 POWER_VDDIOCTRL_DISABLE_STEPPING);
 876
 877         /* Stop 5V detection */
 878         writel(POWER_5VCTRL_PWRUP_VBUS_CMPS,
 879                 &power_regs->hw_power_5vctrl_clr);
 880 }
 881
 882 /**
 883  * mxs_init_batt_bo() - Configure battery brownout threshold
 884  *
 885  * This function configures the battery input brownout threshold. The value
 886  * at which the battery brownout happens is configured to 3.0V in the code.
 887  */
 888 static void mxs_init_batt_bo(void)
 889 {
 890         debug("SPL: Initialising battery brown-out level to 3.0V\n");
 891
 892         /* Brownout at 3V */
 893         clrsetbits_le32(&power_regs->hw_power_battmonitor,
 894                 POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
 895                 BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
 896
 897         writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 898         writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
 899 }
 900
 901 /**
 902  * mxs_switch_vddd_to_dcdc_source() - Switch VDDD rail to DC-DC converter
 903  *
 904  * This function turns off the VDDD linear regulator and therefore makes
 905  * the VDDD rail be supplied only by the DC-DC converter.
 906  */
 907 static void mxs_switch_vddd_to_dcdc_source(void)
 908 {
 909         debug("SPL: Switching VDDD to DC-DC converters\n");
 910
 911         clrsetbits_le32(&power_regs->hw_power_vdddctrl,
 912                 POWER_VDDDCTRL_LINREG_OFFSET_MASK,
 913                 POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
 914
 915         clrbits_le32(&power_regs->hw_power_vdddctrl,
 916                 POWER_VDDDCTRL_DISABLE_FET | POWER_VDDDCTRL_ENABLE_LINREG |
 917                 POWER_VDDDCTRL_DISABLE_STEPPING);
 918 }
 919
 920 /**
 921  * mxs_power_configure_power_source() - Configure power block source
 922  *
 923  * This function is the core of the power configuration logic. The function
 924  * selects the power block input source and configures the whole power block
 925  * accordingly. After the configuration is complete and the system is stable
 926  * again, the function switches the CPU clock source back to PLL. Finally,
 927  * the function switches the voltage rails to DC-DC converter.
 928  */
 929 static void mxs_power_configure_power_source(void)
 930 {
 931         struct mxs_lradc_regs *lradc_regs =
 932                 (struct mxs_lradc_regs *)MXS_LRADC_BASE;
 933
 934         debug("SPL: Configuring power source\n");
 935
 936         mxs_src_power_init();
 937
 938         if (!fixed_batt_supply) {
 939                 if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
 940                         if (mxs_is_batt_ready()) {
 941                                 /* 5V source detected, good battery detected. */
 942                                 mxs_batt_boot();
 943                         } else {
 944                                 if (!mxs_is_batt_good()) {
 945                                         /* 5V source detected, bad battery detected. */
 946                                         writel(LRADC_CONVERSION_AUTOMATIC,
 947                                                 &lradc_regs->hw_lradc_conversion_clr);
 948                                         clrbits_le32(&power_regs->hw_power_battmonitor,
 949                                                 POWER_BATTMONITOR_BATT_VAL_MASK);
 950                                 }
 951                                 mxs_5v_boot();
 952                         }
 953                 } else {
 954                         /* 5V not detected, booting from battery. */
 955                         mxs_batt_boot();
 956                 }
 957         } else {
 958                 mxs_fixed_batt_boot();
 959         }
 960
 961         /*
 962          * TODO: Do not switch CPU clock to PLL if we are VDD5V is sourced
 963          * from USB VBUS
 964          */
 965         mxs_power_clock2pll();
 966
 967         mxs_init_batt_bo();
 968
 969         mxs_switch_vddd_to_dcdc_source();
 970
 971 #ifdef CONFIG_SOC_MX23
 972         /* Fire up the VDDMEM LinReg now that we're all set. */
 973         debug("SPL: Enabling mx23 VDDMEM linear regulator\n");
 974         writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
 975                 &power_regs->hw_power_vddmemctrl);
 976 #endif
 977 }
 978
 979 /**
 980  * mxs_enable_output_rail_protection() - Enable power rail protection
 981  *
 982  * This function enables overload protection on the power rails. This is
 983  * triggered if the power rails' voltage drops rapidly due to overload and
 984  * in such case, the supply to the powerrail is cut-off, protecting the
 985  * CPU from damage. Note that under such condition, the system will likely
 986  * crash or misbehave.
 987  */
 988 static void mxs_enable_output_rail_protection(void)
 989 {
 990         debug("SPL: Enabling output rail protection\n");
 991
 992         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
 993                 POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr);
 994
 995         setbits_le32(&power_regs->hw_power_vdddctrl,
 996                         POWER_VDDDCTRL_PWDN_BRNOUT);
 997
 998         setbits_le32(&power_regs->hw_power_vddactrl,
 999                         POWER_VDDACTRL_PWDN_BRNOUT);
1000
1001         setbits_le32(&power_regs->hw_power_vddioctrl,
1002                         POWER_VDDIOCTRL_PWDN_BRNOUT);
1003 }
1004
1005 /**
1006  * mxs_get_vddio_power_source_off() - Get VDDIO rail power source
1007  *
1008  * This function tests if the VDDIO rail is supplied by linear regulator
1009  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1010  * returns 0 if powered by the DC-DC converter.
1011  */
1012 static int mxs_get_vddio_power_source_off(void)
1013 {
1014         uint32_t tmp;
1015
1016         if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) &&
1017                 !(readl(&power_regs->hw_power_5vctrl) &
1018                         POWER_5VCTRL_ILIMIT_EQ_ZERO)) {
1019
1020                 tmp = readl(&power_regs->hw_power_vddioctrl);
1021                 if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
1022                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1023                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1024                                 return 1;
1025                         }
1026                 }
1027
1028                 if (!(readl(&power_regs->hw_power_5vctrl) &
1029                         POWER_5VCTRL_ENABLE_DCDC)) {
1030                         if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
1031                                 POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
1032                                 return 1;
1033                         }
1034                 }
1035         }
1036
1037         return 0;
1038 }
1039
1040 /**
1041  * mxs_get_vddd_power_source_off() - Get VDDD rail power source
1042  *
1043  * This function tests if the VDDD rail is supplied by linear regulator
1044  * or by the DC-DC converter. Returns 1 if powered by linear regulator,
1045  * returns 0 if powered by the DC-DC converter.
1046  */
1047 static int mxs_get_vddd_power_source_off(void)
1048 {
1049         uint32_t tmp;
1050
1051         tmp = readl(&power_regs->hw_power_vdddctrl);
1052         if (tmp & POWER_VDDDCTRL_DISABLE_FET) {
1053                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1054                         POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
1055                         return 1;
1056                 }
1057         }
1058
1059         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1060                 if (!(readl(&power_regs->hw_power_5vctrl) &
1061                         POWER_5VCTRL_ENABLE_DCDC)) {
1062                         return 1;
1063                 }
1064         }
1065
1066         if (!(tmp & POWER_VDDDCTRL_ENABLE_LINREG)) {
1067                 if ((tmp & POWER_VDDDCTRL_LINREG_OFFSET_MASK) ==
1068                         POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW) {
1069                         return 1;
1070                 }
1071         }
1072
1073         return 0;
1074 }
1075
1076 static int mxs_get_vdda_power_source_off(void)
1077 {
1078         uint32_t tmp;
1079
1080         tmp = readl(&power_regs->hw_power_vddactrl);
1081         if (tmp & POWER_VDDACTRL_DISABLE_FET) {
1082                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1083                         POWER_VDDACTRL_LINREG_OFFSET_0STEPS) {
1084                         return 1;
1085                 }
1086         }
1087
1088         if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) {
1089                 if (!(readl(&power_regs->hw_power_5vctrl) &
1090                         POWER_5VCTRL_ENABLE_DCDC)) {
1091                         return 1;
1092                 }
1093         }
1094
1095         if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) {
1096                 if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) ==
1097                         POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) {
1098                         return 1;
1099                 }
1100         }
1101
1102         return 0;
1103 }
1104
1105 struct mxs_vddx_cfg {
1106         uint32_t                *reg;
1107         uint8_t                 step_mV;
1108         uint16_t                lowest_mV;
1109         uint16_t                highest_mV;
1110         int                     (*powered_by_linreg)(void);
1111         uint32_t                trg_mask;
1112         uint32_t                bo_irq;
1113         uint32_t                bo_enirq;
1114         uint32_t                bo_offset_mask;
1115         uint32_t                bo_offset_offset;
1116         uint16_t                bo_min_mV;
1117         uint16_t                bo_max_mV;
1118 };
1119
1120 #define POWER_REG(n)            &((struct mxs_power_regs *)MXS_POWER_BASE)->n
1121
1122 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
1123         .reg                    = POWER_REG(hw_power_vddioctrl),
1124 #if defined(CONFIG_SOC_MX23)
1125         .step_mV                = 25,
1126 #else
1127         .step_mV                = 50,
1128 #endif
1129         .lowest_mV              = 2800,
1130         .highest_mV             = 3600,
1131         .powered_by_linreg      = mxs_get_vddio_power_source_off,
1132         .trg_mask               = POWER_VDDIOCTRL_TRG_MASK,
1133         .bo_irq                 = POWER_CTRL_VDDIO_BO_IRQ,
1134         .bo_enirq               = POWER_CTRL_ENIRQ_VDDIO_BO,
1135         .bo_offset_mask         = POWER_VDDIOCTRL_BO_OFFSET_MASK,
1136         .bo_offset_offset       = POWER_VDDIOCTRL_BO_OFFSET_OFFSET,
1137         .bo_min_mV              = 2700,
1138         .bo_max_mV              = 3475,
1139 };
1140
1141 static const struct mxs_vddx_cfg mxs_vddd_cfg = {
1142         .reg                    = POWER_REG(hw_power_vdddctrl),
1143         .step_mV                = 25,
1144         .lowest_mV              = 800,
1145         .highest_mV             = 1575,
1146         .powered_by_linreg      = mxs_get_vddd_power_source_off,
1147         .trg_mask               = POWER_VDDDCTRL_TRG_MASK,
1148         .bo_irq                 = POWER_CTRL_VDDD_BO_IRQ,
1149         .bo_enirq               = POWER_CTRL_ENIRQ_VDDD_BO,
1150         .bo_offset_mask         = POWER_VDDDCTRL_BO_OFFSET_MASK,
1151         .bo_offset_offset       = POWER_VDDDCTRL_BO_OFFSET_OFFSET,
1152         .bo_min_mV              = 800,
1153         .bo_max_mV              = 1475,
1154 };
1155
1156 static const struct mxs_vddx_cfg mxs_vdda_cfg = {
1157         .reg                    = POWER_REG(hw_power_vddactrl),
1158         .step_mV                = 25,
1159         .lowest_mV              = 1800,
1160         .highest_mV             = 3600,
1161         .powered_by_linreg      = mxs_get_vdda_power_source_off,
1162         .trg_mask               = POWER_VDDACTRL_TRG_MASK,
1163         .bo_irq                 = POWER_CTRL_VDDA_BO_IRQ,
1164         .bo_enirq               = POWER_CTRL_ENIRQ_VDDA_BO,
1165         .bo_offset_mask         = POWER_VDDACTRL_BO_OFFSET_MASK,
1166         .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
1167         .bo_min_mV              = 1400,
1168         .bo_max_mV              = 2175,
1169 };
1170
1171 #ifdef CONFIG_SOC_MX23
1172 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
1173         .reg                    = POWER_REG(hw_power_vddmemctrl),
1174         .step_mV                = 50,
1175         .lowest_mV              = 1500,
1176         .highest_mV             = 1700,
1177         .powered_by_linreg      = NULL,
1178         .trg_mask               = POWER_VDDMEMCTRL_TRG_MASK,
1179         .bo_irq                 = 0,
1180         .bo_enirq               = 0,
1181         .bo_offset_mask         = 0,
1182         .bo_offset_offset       = 0,
1183 };
1184 #endif
1185
1186 /**
1187  * mxs_power_set_vddx() - Configure voltage on DC-DC converter rail
1188  * @cfg:                Configuration data of the DC-DC converter rail
1189  * @new_target:         New target voltage of the DC-DC converter rail
1190  * @new_brownout:       New brownout trigger voltage
1191  *
1192  * This function configures the output voltage on the DC-DC converter rail.
1193  * The rail is selected by the @cfg argument. The new voltage target is
1194  * selected by the @new_target and the voltage is specified in mV. The
1195  * new brownout value is selected by the @new_brownout argument and the
1196  * value is also in mV.
1197  */
1198 static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg,
1199                                 uint32_t new_target, uint32_t bo_offset)
1200 {
1201         uint32_t cur_target, diff, bo_int = 0;
1202         int powered_by_linreg = 0;
1203         int adjust_up;
1204
1205         if (new_target < cfg->lowest_mV) {
1206                 new_target = cfg->lowest_mV;
1207         }
1208         if (new_target > cfg->highest_mV) {
1209                 new_target = cfg->highest_mV;
1210         }
1211
1212         if (new_target - bo_offset < cfg->bo_min_mV) {
1213                 bo_offset = new_target - cfg->bo_min_mV;
1214         } else if (new_target - bo_offset > cfg->bo_max_mV) {
1215                 bo_offset = new_target - cfg->bo_max_mV;
1216         }
1217
1218         bo_offset = DIV_ROUND_CLOSEST(bo_offset, cfg->step_mV);
1219
1220         cur_target = readl(cfg->reg);
1221         cur_target &= cfg->trg_mask;
1222         cur_target *= cfg->step_mV;
1223         cur_target += cfg->lowest_mV;
1224
1225         adjust_up = new_target > cur_target;
1226         if (cfg->powered_by_linreg)
1227                 powered_by_linreg = cfg->powered_by_linreg();
1228
1229         if (adjust_up && cfg->bo_irq) {
1230                 if (powered_by_linreg) {
1231                         bo_int = readl(&power_regs->hw_power_ctrl);
1232                         writel(cfg->bo_enirq, &power_regs->hw_power_ctrl_clr);
1233                 }
1234                 setbits_le32(cfg->reg, cfg->bo_offset_mask);
1235         }
1236
1237         do {
1238                 if (abs(new_target - cur_target) > 100) {
1239                         if (adjust_up)
1240                                 diff = cur_target + 100;
1241                         else
1242                                 diff = cur_target - 100;
1243                 } else {
1244                         diff = new_target;
1245                 }
1246
1247                 diff -= cfg->lowest_mV;
1248                 diff /= cfg->step_mV;
1249
1250                 clrsetbits_le32(cfg->reg, cfg->trg_mask, diff);
1251
1252                 if (powered_by_linreg ||
1253                         (readl(&power_regs->hw_power_sts) &
1254                                 POWER_STS_VDD5V_GT_VDDIO)) {
1255                         early_delay(500);
1256                 } else {
1257                         while (!(readl(&power_regs->hw_power_sts) &
1258                                         POWER_STS_DC_OK)) {
1259
1260                         }
1261                 }
1262
1263                 cur_target = readl(cfg->reg);
1264                 cur_target &= cfg->trg_mask;
1265                 cur_target *= cfg->step_mV;
1266                 cur_target += cfg->lowest_mV;
1267         } while (new_target > cur_target);
1268
1269         if (cfg->bo_irq) {
1270                 if (adjust_up && powered_by_linreg) {
1271                         writel(cfg->bo_irq, &power_regs->hw_power_ctrl_clr);
1272                         if (bo_int & cfg->bo_enirq)
1273                                 writel(cfg->bo_enirq,
1274                                         &power_regs->hw_power_ctrl_set);
1275                 }
1276
1277                 clrsetbits_le32(cfg->reg, cfg->bo_offset_mask,
1278                                 bo_offset << cfg->bo_offset_offset);
1279         }
1280 }
1281
1282 /**
1283  * mxs_setup_batt_detect() - Start the battery voltage measurement logic
1284  *
1285  * This function starts and configures the LRADC block. This allows the
1286  * power initialization code to measure battery voltage and based on this
1287  * knowledge, decide whether to boot at all, boot from battery or boot
1288  * from 5V input.
1289  */
1290 static void mxs_setup_batt_detect(void)
1291 {
1292         debug("SPL: Starting battery voltage measurement logic\n");
1293
1294         mxs_lradc_init();
1295         mxs_lradc_enable_batt_measurement();
1296         early_delay(10);
1297 }
1298
1299 /**
1300  * mxs_ungate_power() - Ungate the POWER block
1301  *
1302  * This function ungates clock to the power block. In case the power block
1303  * was still gated at this point, it will not be possible to configure the
1304  * block and therefore the power initialization would fail. This function
1305  * is only needed on i.MX233, on i.MX28 the power block is always ungated.
1306  */
1307 static void mxs_ungate_power(void)
1308 {
1309 #ifdef CONFIG_SOC_MX23
1310         writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
1311 #endif
1312 }
1313
1314 #ifdef CONFIG_CONFIG_MACH_MX28EVK
1315 #define auto_restart 1
1316 #else
1317 #define auto_restart 0
1318 #endif
1319
1320 /**
1321  * mxs_power_init() - The power block init main function
1322  *
1323  * This function calls all the power block initialization functions in
1324  * proper sequence to start the power block.
1325  */
1326 #define VDDX_VAL(v)     (v) / 1000, (v) / 100 % 10
1327
1328 void mxs_power_init(void)
1329 {
1330         debug("SPL: Initialising Power Block\n");
1331
1332         mxs_ungate_power();
1333
1334         mxs_power_clock2xtal();
1335         if (mxs_power_set_auto_restart(auto_restart)) {
1336                 serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n");
1337         }
1338         mxs_power_set_linreg();
1339
1340         if (!fixed_batt_supply) {
1341                 mxs_power_setup_5v_detect();
1342                 mxs_setup_batt_detect();
1343         }
1344
1345         mxs_power_configure_power_source();
1346         mxs_enable_output_rail_protection();
1347
1348         debug("SPL: Setting VDDIO to %uV%u (brownout @ %uv%02u)\n",
1349                 VDDX_VAL(VDDIO_VAL), VDDX_VAL(VDDIO_VAL - VDDIO_BO_VAL));
1350         mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
1351         debug("SPL: Setting VDDD to %uV%u (brownout @ %uv%02u)\n",
1352                 VDDX_VAL(VDDD_VAL), VDDX_VAL(VDDD_VAL - VDDD_BO_VAL));
1353         mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
1354         debug("SPL: Setting VDDA to %uV%u (brownout @ %uv%02u)\n",
1355                 VDDX_VAL(VDDA_VAL), VDDX_VAL(VDDA_VAL - VDDA_BO_VAL));
1356         mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
1357 #ifdef CONFIG_SOC_MX23
1358         debug("SPL: Setting VDDMEM to %uV%u (brownout @ %uv%02u)\n",
1359                 VDDX_VAL(VDDMEM_VAL), VDDX_VAL(VDDMEM_VAL - VDDMEM_BO_VAL));
1360         mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
1361 #else
1362         clrbits_le32(&power_regs->hw_power_vddmemctrl,
1363                 POWER_VDDMEMCTRL_ENABLE_LINREG);
1364 #endif
1365         writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ |
1366                 POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ |
1367                 POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
1368                 POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
1369         if (!fixed_batt_supply)
1370                 writel(POWER_5VCTRL_PWDN_5VBRNOUT,
1371                         &power_regs->hw_power_5vctrl_set);
1372 }
1373
1374 #ifdef  CONFIG_SPL_MXS_PSWITCH_WAIT
1375 /**
1376  * mxs_power_wait_pswitch() - Wait for power switch to be pressed
1377  *
1378  * This function waits until the power-switch was pressed to start booting
1379  * the board.
1380  */
1381 void mxs_power_wait_pswitch(void)
1382 {
1383         debug("SPL: Waiting for power switch input\n");
1384         while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK))
1385                 ;
1386 }
1387 #endif