am33xx: Update DT files, add am335x_gp_evm_config target
[karo-tx-uboot.git] / arch / arm / cpu / armv7 / am33xx / clock.c
1 /*
2  * clock.c
3  *
4  * Clock initialization for AM33XX boards.
5  * Derived from OMAP4 boards
6  *
7  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11 #include <common.h>
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sys_proto.h>
16 #include <asm/io.h>
17
18 static void setup_post_dividers(const struct dpll_regs *dpll_regs,
19                          const struct dpll_params *params)
20 {
21         /* Setup post-dividers */
22         if (params->m2 >= 0)
23                 writel(params->m2, dpll_regs->cm_div_m2_dpll);
24         if (params->m3 >= 0)
25                 writel(params->m3, dpll_regs->cm_div_m3_dpll);
26         if (params->m4 >= 0)
27                 writel(params->m4, dpll_regs->cm_div_m4_dpll);
28         if (params->m5 >= 0)
29                 writel(params->m5, dpll_regs->cm_div_m5_dpll);
30         if (params->m6 >= 0)
31                 writel(params->m6, dpll_regs->cm_div_m6_dpll);
32 }
33
34 static inline void do_lock_dpll(const struct dpll_regs *dpll_regs)
35 {
36         clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
37                         CM_CLKMODE_DPLL_DPLL_EN_MASK,
38                         DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT);
39 }
40
41 static inline void wait_for_lock(const struct dpll_regs *dpll_regs)
42 {
43         if (!wait_on_value(ST_DPLL_CLK_MASK, ST_DPLL_CLK_MASK,
44                            (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
45                 printf("DPLL locking failed for 0x%x\n",
46                        dpll_regs->cm_clkmode_dpll);
47                 hang();
48         }
49 }
50
51 static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs)
52 {
53         clrsetbits_le32(dpll_regs->cm_clkmode_dpll,
54                         CM_CLKMODE_DPLL_DPLL_EN_MASK,
55                         DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT);
56 }
57
58 static inline void wait_for_bypass(const struct dpll_regs *dpll_regs)
59 {
60         if (!wait_on_value(ST_DPLL_CLK_MASK, 0,
61                            (void *)dpll_regs->cm_idlest_dpll, LDELAY)) {
62                 printf("Bypassing DPLL failed 0x%x\n",
63                        dpll_regs->cm_clkmode_dpll);
64         }
65 }
66
67 static void bypass_dpll(const struct dpll_regs *dpll_regs)
68 {
69         do_bypass_dpll(dpll_regs);
70         wait_for_bypass(dpll_regs);
71 }
72
73 void do_setup_dpll(const struct dpll_regs *dpll_regs,
74                    const struct dpll_params *params)
75 {
76         u32 temp;
77
78         if (!params)
79                 return;
80
81         temp = readl(dpll_regs->cm_clksel_dpll);
82
83         bypass_dpll(dpll_regs);
84
85         /* Set M & N */
86         temp &= ~CM_CLKSEL_DPLL_M_MASK;
87         temp |= (params->m << CM_CLKSEL_DPLL_M_SHIFT) & CM_CLKSEL_DPLL_M_MASK;
88
89         temp &= ~CM_CLKSEL_DPLL_N_MASK;
90         temp |= (params->n << CM_CLKSEL_DPLL_N_SHIFT) & CM_CLKSEL_DPLL_N_MASK;
91
92         writel(temp, dpll_regs->cm_clksel_dpll);
93
94         setup_post_dividers(dpll_regs, params);
95
96         /* Wait till the DPLL locks */
97         do_lock_dpll(dpll_regs);
98         wait_for_lock(dpll_regs);
99 }
100
101 static void setup_dplls(void)
102 {
103         const struct dpll_params *params;
104
105         params = get_dpll_core_params();
106         do_setup_dpll(&dpll_core_regs, params);
107
108         params = get_dpll_mpu_params();
109         do_setup_dpll(&dpll_mpu_regs, params);
110
111         params = get_dpll_per_params();
112         do_setup_dpll(&dpll_per_regs, params);
113         writel(0x300, &cmwkup->clkdcoldodpllper);
114
115         params = get_dpll_ddr_params();
116         do_setup_dpll(&dpll_ddr_regs, params);
117 }
118
119 static inline void wait_for_clk_enable(u32 *clkctrl_addr)
120 {
121         u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
122         u32 bound = LDELAY;
123
124         while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
125                 (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
126                 clkctrl = readl(clkctrl_addr);
127                 idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
128                          MODULE_CLKCTRL_IDLEST_SHIFT;
129                 if (--bound == 0) {
130                         printf("Clock enable failed for 0x%p idlest 0x%x\n",
131                                clkctrl_addr, clkctrl);
132                         return;
133                 }
134         }
135 }
136
137 static inline void enable_clock_module(u32 *const clkctrl_addr, u32 enable_mode,
138                                        u32 wait_for_enable)
139 {
140         clrsetbits_le32(clkctrl_addr, MODULE_CLKCTRL_MODULEMODE_MASK,
141                         enable_mode << MODULE_CLKCTRL_MODULEMODE_SHIFT);
142         debug("Enable clock module - %p\n", clkctrl_addr);
143         if (wait_for_enable)
144                 wait_for_clk_enable(clkctrl_addr);
145 }
146
147 static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode)
148 {
149         clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK,
150                         enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT);
151         debug("Enable clock domain - %p\n", clkctrl_reg);
152 }
153
154 void do_enable_clocks(u32 *const *clk_domains,
155                       u32 *const *clk_modules_explicit_en, u8 wait_for_enable)
156 {
157         u32 i, max = 100;
158
159         /* Put the clock domains in SW_WKUP mode */
160         for (i = 0; (i < max) && clk_domains[i]; i++) {
161                 enable_clock_domain(clk_domains[i],
162                                     CD_CLKCTRL_CLKTRCTRL_SW_WKUP);
163         }
164
165         /* Clock modules that need to be put in SW_EXPLICIT_EN mode */
166         for (i = 0; (i < max) && clk_modules_explicit_en[i]; i++) {
167                 enable_clock_module(clk_modules_explicit_en[i],
168                                     MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN,
169                                     wait_for_enable);
170         };
171 }
172
173 /*
174  * Before scaling up the clocks we need to have the PMIC scale up the
175  * voltages first.  This will be dependent on which PMIC is in use
176  * and in some cases we may not be scaling things up at all and thus not
177  * need to do anything here.
178  */
179 __weak void scale_vcores(void)
180 {
181 }
182
183 void prcm_init()
184 {
185         enable_basic_clocks();
186         scale_vcores();
187         setup_dplls();
188 }