arch/arm/cpu/armv7/am33xx/clock.c

   1 /*
   2  * clock.c
   3  *
   4  * clocks for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/io.h>
  24
  25 #define PRCM_MOD_EN             0x2
  26 #define PRCM_FORCE_WAKEUP       0x2
  27 #define PRCM_FUNCTL             0x0
  28
  29 #define PRCM_EMIF_CLK_ACTIVITY  BIT(2)
  30 #define PRCM_L3_GCLK_ACTIVITY   BIT(4)
  31
  32 #define PLL_BYPASS_MODE         0x4
  33 #define ST_MN_BYPASS            0x00000100
  34 #define ST_DPLL_CLK             0x00000001
  35 #define CLK_SEL_MASK            0x7ffff
  36 #define CLK_DIV_MASK            0x1f
  37 #define CLK_DIV2_MASK           0x7f
  38 #define CLK_SEL_SHIFT           0x8
  39 #define CLK_MODE_SEL            0x7
  40 #define CLK_MODE_MASK           0xfffffff8
  41 #define CLK_DIV_SEL             0xFFFFFFE0
  42 #define CPGMAC0_IDLE            0x30000
  43 #define DPLL_CLKDCOLDO_GATE_CTRL        0x300
  44
  45 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  46 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  47 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  48 const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
  49
  50 static void enable_interface_clocks(void)
  51 {
  52         /* Enable all the Interconnect Modules */
  53         writel(PRCM_MOD_EN, &cmper->l3clkctrl);
  54         while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
  55                 ;
  56
  57         writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
  58         while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
  59                 ;
  60
  61         writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
  62         while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
  63                 ;
  64
  65         writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
  66         while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
  67                 ;
  68
  69         writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
  70         while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
  71                 ;
  72
  73         writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
  74         while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
  75                 ;
  76
  77         writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
  78         while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
  79                 ;
  80 }
  81
  82 /*
  83  * Force power domain wake up transition
  84  * Ensure that the corresponding interface clock is active before
  85  * using the peripheral
  86  */
  87 static void power_domain_wkup_transition(void)
  88 {
  89         writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
  90         writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
  91         writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
  92         writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
  93         writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
  94 }
  95
  96 /*
  97  * Enable the peripheral clock for required peripherals
  98  */
  99 static void enable_per_clocks(void)
 100 {
 101         /* Enable the control module though RBL would have done it*/
 102         writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
 103         while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
 104                 ;
 105
 106         /* Enable the module clock */
 107         writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
 108         while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 109                 ;
 110
 111         /* Select the Master osc 24 MHZ as Timer2 clock source */
 112         writel(0x1, &cmdpll->clktimer2clk);
 113
 114         /* UART0 */
 115         writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 116         while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 117                 ;
 118
 119         /* UART1 */
 120 #ifdef CONFIG_SERIAL2
 121         writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
 122         while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
 123                 ;
 124 #endif /* CONFIG_SERIAL2 */
 125
 126         /* UART2 */
 127 #ifdef CONFIG_SERIAL3
 128         writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
 129         while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
 130                 ;
 131 #endif /* CONFIG_SERIAL3 */
 132
 133         /* UART3 */
 134 #ifdef CONFIG_SERIAL4
 135         writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
 136         while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
 137                 ;
 138 #endif /* CONFIG_SERIAL4 */
 139
 140         /* UART4 */
 141 #ifdef CONFIG_SERIAL5
 142         writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
 143         while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
 144                 ;
 145 #endif /* CONFIG_SERIAL5 */
 146
 147         /* UART5 */
 148 #ifdef CONFIG_SERIAL6
 149         writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
 150         while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
 151                 ;
 152 #endif /* CONFIG_SERIAL6 */
 153
 154         /* MMC0*/
 155         writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 156         while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
 157                 ;
 158
 159         /* i2c0 */
 160         writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
 161         while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
 162                 ;
 163
 164         /* gpio1 module */
 165         writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
 166         while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
 167                 ;
 168
 169         /* gpio2 module */
 170         writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
 171         while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
 172                 ;
 173
 174         /* gpio3 module */
 175         writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
 176         while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
 177                 ;
 178
 179         /* i2c1 */
 180         writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
 181         while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
 182                 ;
 183
 184         /* Ethernet */
 185         writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
 186         while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
 187                 ;
 188
 189         /* spi0 */
 190         writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
 191         while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
 192                 ;
 193
 194         /* RTC */
 195         writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
 196         while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
 197                 ;
 198
 199         /* MUSB */
 200         writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
 201         while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
 202                 ;
 203 }
 204
 205 static void mpu_pll_config(void)
 206 {
 207         u32 clkmode, clksel, div_m2;
 208
 209         clkmode = readl(&cmwkup->clkmoddpllmpu);
 210         clksel = readl(&cmwkup->clkseldpllmpu);
 211         div_m2 = readl(&cmwkup->divm2dpllmpu);
 212
 213         /* Set the PLL to bypass Mode */
 214         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 215         while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
 216                 ;
 217
 218         clksel = clksel & (~CLK_SEL_MASK);
 219         clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
 220         writel(clksel, &cmwkup->clkseldpllmpu);
 221
 222         div_m2 = div_m2 & ~CLK_DIV_MASK;
 223         div_m2 = div_m2 | MPUPLL_M2;
 224         writel(div_m2, &cmwkup->divm2dpllmpu);
 225
 226         clkmode = clkmode | CLK_MODE_SEL;
 227         writel(clkmode, &cmwkup->clkmoddpllmpu);
 228
 229         while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
 230                 ;
 231 }
 232
 233 static void core_pll_config(void)
 234 {
 235         u32 clkmode, clksel, div_m4, div_m5, div_m6;
 236
 237         clkmode = readl(&cmwkup->clkmoddpllcore);
 238         clksel = readl(&cmwkup->clkseldpllcore);
 239         div_m4 = readl(&cmwkup->divm4dpllcore);
 240         div_m5 = readl(&cmwkup->divm5dpllcore);
 241         div_m6 = readl(&cmwkup->divm6dpllcore);
 242
 243         /* Set the PLL to bypass Mode */
 244         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
 245
 246         while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
 247                 ;
 248
 249         clksel = clksel & (~CLK_SEL_MASK);
 250         clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
 251         writel(clksel, &cmwkup->clkseldpllcore);
 252
 253         div_m4 = div_m4 & ~CLK_DIV_MASK;
 254         div_m4 = div_m4 | COREPLL_M4;
 255         writel(div_m4, &cmwkup->divm4dpllcore);
 256
 257         div_m5 = div_m5 & ~CLK_DIV_MASK;
 258         div_m5 = div_m5 | COREPLL_M5;
 259         writel(div_m5, &cmwkup->divm5dpllcore);
 260
 261         div_m6 = div_m6 & ~CLK_DIV_MASK;
 262         div_m6 = div_m6 | COREPLL_M6;
 263         writel(div_m6, &cmwkup->divm6dpllcore);
 264
 265         clkmode = clkmode | CLK_MODE_SEL;
 266         writel(clkmode, &cmwkup->clkmoddpllcore);
 267
 268         while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
 269                 ;
 270 }
 271
 272 static void per_pll_config(void)
 273 {
 274         u32 clkmode, clksel, div_m2;
 275
 276         clkmode = readl(&cmwkup->clkmoddpllper);
 277         clksel = readl(&cmwkup->clkseldpllper);
 278         div_m2 = readl(&cmwkup->divm2dpllper);
 279
 280         /* Set the PLL to bypass Mode */
 281         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
 282
 283         while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
 284                 ;
 285
 286         clksel = clksel & (~CLK_SEL_MASK);
 287         clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
 288         writel(clksel, &cmwkup->clkseldpllper);
 289
 290         div_m2 = div_m2 & ~CLK_DIV2_MASK;
 291         div_m2 = div_m2 | PERPLL_M2;
 292         writel(div_m2, &cmwkup->divm2dpllper);
 293
 294         clkmode = clkmode | CLK_MODE_SEL;
 295         writel(clkmode, &cmwkup->clkmoddpllper);
 296
 297         while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 298                 ;
 299
 300         writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
 301 }
 302
 303 void ddr_pll_config(unsigned int ddrpll_m)
 304 {
 305         u32 clkmode, clksel, div_m2;
 306
 307         clkmode = readl(&cmwkup->clkmoddpllddr);
 308         clksel = readl(&cmwkup->clkseldpllddr);
 309         div_m2 = readl(&cmwkup->divm2dpllddr);
 310
 311         /* Set the PLL to bypass Mode */
 312         clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
 313         writel(clkmode, &cmwkup->clkmoddpllddr);
 314
 315         /* Wait till bypass mode is enabled */
 316         while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
 317                                 != ST_MN_BYPASS)
 318                 ;
 319
 320         clksel = clksel & (~CLK_SEL_MASK);
 321         clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
 322         writel(clksel, &cmwkup->clkseldpllddr);
 323
 324         div_m2 = div_m2 & CLK_DIV_SEL;
 325         div_m2 = div_m2 | DDRPLL_M2;
 326         writel(div_m2, &cmwkup->divm2dpllddr);
 327
 328         clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
 329         writel(clkmode, &cmwkup->clkmoddpllddr);
 330
 331         /* Wait till dpll is locked */
 332         while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
 333                 ;
 334 }
 335
 336 void enable_emif_clocks(void)
 337 {
 338         /* Enable the  EMIF_FW Functional clock */
 339         writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 340         /* Enable EMIF0 Clock */
 341         writel(PRCM_MOD_EN, &cmper->emifclkctrl);
 342         /* Poll if module is functional */
 343         while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 344                 ;
 345 }
 346
 347 /*
 348  * Configure the PLL/PRCM for necessary peripherals
 349  */
 350 void pll_init()
 351 {
 352         mpu_pll_config();
 353         core_pll_config();
 354         per_pll_config();
 355
 356         /* Enable the required interconnect clocks */
 357         enable_interface_clocks();
 358
 359         /* Power domain wake up transition */
 360         power_domain_wkup_transition();
 361
 362         /* Enable the required peripherals */
 363         enable_per_clocks();
 364 }