arch/arm/cpu/armv7/am33xx/clock.c

   1 /*
   2  * clock.c
   3  *
   4  * clocks for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/io.h>
  24
  25 #define PRCM_MOD_EN             0x2
  26 #define PRCM_FORCE_WAKEUP       0x2
  27 #define PRCM_FUNCTL             0x0
  28
  29 #define PRCM_EMIF_CLK_ACTIVITY  BIT(2)
  30 #define PRCM_L3_GCLK_ACTIVITY   BIT(4)
  31
  32 #define PLL_BYPASS_MODE         0x4
  33 #define ST_MN_BYPASS            0x00000100
  34 #define ST_DPLL_CLK             0x00000001
  35 #define CLK_SEL_MASK            0x7ffff
  36 #define CLK_DIV_MASK            0x1f
  37 #define CLK_DIV2_MASK           0x7f
  38 #define CLK_SEL_SHIFT           0x8
  39 #define CLK_MODE_SEL            0x7
  40 #define CLK_MODE_MASK           0xfffffff8
  41 #define CLK_DIV_SEL             0xFFFFFFE0
  42 #define CPGMAC0_IDLE            0x30000
  43
  44 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  45 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  46 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  47
  48 static void enable_interface_clocks(void)
  49 {
  50         /* Enable all the Interconnect Modules */
  51         writel(PRCM_MOD_EN, &cmper->l3clkctrl);
  52         while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
  53                 ;
  54
  55         writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
  56         while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
  57                 ;
  58
  59         writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
  60         while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
  61                 ;
  62
  63         writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
  64         while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
  65                 ;
  66
  67         writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
  68         while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
  69                 ;
  70
  71         writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
  72         while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
  73                 ;
  74
  75         writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
  76         while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
  77                 ;
  78 }
  79
  80 /*
  81  * Force power domain wake up transition
  82  * Ensure that the corresponding interface clock is active before
  83  * using the peripheral
  84  */
  85 static void power_domain_wkup_transition(void)
  86 {
  87         writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
  88         writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
  89         writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
  90         writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
  91         writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
  92 }
  93
  94 /*
  95  * Enable the peripheral clock for required peripherals
  96  */
  97 static void enable_per_clocks(void)
  98 {
  99         /* Enable the control module though RBL would have done it*/
 100         writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
 101         while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
 102                 ;
 103
 104         /* Enable the module clock */
 105         writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
 106         while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 107                 ;
 108
 109         /* Select the Master osc 24 MHZ as Timer2 clock source */
 110         writel(0x1, &cmdpll->clktimer2clk);
 111
 112         /* UART0 */
 113         writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 114         while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 115                 ;
 116
 117         /* MMC0*/
 118         writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 119         while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
 120                 ;
 121
 122         /* i2c0 */
 123         writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
 124         while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
 125                 ;
 126
 127         /* gpio1 module */
 128         writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
 129         while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
 130                 ;
 131
 132         /* gpio2 module */
 133         writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
 134         while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
 135                 ;
 136
 137         /* gpio3 module */
 138         writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
 139         while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
 140                 ;
 141
 142         /* i2c1 */
 143         writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
 144         while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
 145                 ;
 146
 147         /* Ethernet */
 148         writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
 149         while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
 150                 ;
 151 }
 152
 153 static void mpu_pll_config(void)
 154 {
 155         u32 clkmode, clksel, div_m2;
 156
 157         clkmode = readl(&cmwkup->clkmoddpllmpu);
 158         clksel = readl(&cmwkup->clkseldpllmpu);
 159         div_m2 = readl(&cmwkup->divm2dpllmpu);
 160
 161         /* Set the PLL to bypass Mode */
 162         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 163         while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
 164                 ;
 165
 166         clksel = clksel & (~CLK_SEL_MASK);
 167         clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
 168         writel(clksel, &cmwkup->clkseldpllmpu);
 169
 170         div_m2 = div_m2 & ~CLK_DIV_MASK;
 171         div_m2 = div_m2 | MPUPLL_M2;
 172         writel(div_m2, &cmwkup->divm2dpllmpu);
 173
 174         clkmode = clkmode | CLK_MODE_SEL;
 175         writel(clkmode, &cmwkup->clkmoddpllmpu);
 176
 177         while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
 178                 ;
 179 }
 180
 181 static void core_pll_config(void)
 182 {
 183         u32 clkmode, clksel, div_m4, div_m5, div_m6;
 184
 185         clkmode = readl(&cmwkup->clkmoddpllcore);
 186         clksel = readl(&cmwkup->clkseldpllcore);
 187         div_m4 = readl(&cmwkup->divm4dpllcore);
 188         div_m5 = readl(&cmwkup->divm5dpllcore);
 189         div_m6 = readl(&cmwkup->divm6dpllcore);
 190
 191         /* Set the PLL to bypass Mode */
 192         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
 193
 194         while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
 195                 ;
 196
 197         clksel = clksel & (~CLK_SEL_MASK);
 198         clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
 199         writel(clksel, &cmwkup->clkseldpllcore);
 200
 201         div_m4 = div_m4 & ~CLK_DIV_MASK;
 202         div_m4 = div_m4 | COREPLL_M4;
 203         writel(div_m4, &cmwkup->divm4dpllcore);
 204
 205         div_m5 = div_m5 & ~CLK_DIV_MASK;
 206         div_m5 = div_m5 | COREPLL_M5;
 207         writel(div_m5, &cmwkup->divm5dpllcore);
 208
 209         div_m6 = div_m6 & ~CLK_DIV_MASK;
 210         div_m6 = div_m6 | COREPLL_M6;
 211         writel(div_m6, &cmwkup->divm6dpllcore);
 212
 213         clkmode = clkmode | CLK_MODE_SEL;
 214         writel(clkmode, &cmwkup->clkmoddpllcore);
 215
 216         while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
 217                 ;
 218 }
 219
 220 static void per_pll_config(void)
 221 {
 222         u32 clkmode, clksel, div_m2;
 223
 224         clkmode = readl(&cmwkup->clkmoddpllper);
 225         clksel = readl(&cmwkup->clkseldpllper);
 226         div_m2 = readl(&cmwkup->divm2dpllper);
 227
 228         /* Set the PLL to bypass Mode */
 229         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
 230
 231         while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
 232                 ;
 233
 234         clksel = clksel & (~CLK_SEL_MASK);
 235         clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
 236         writel(clksel, &cmwkup->clkseldpllper);
 237
 238         div_m2 = div_m2 & ~CLK_DIV2_MASK;
 239         div_m2 = div_m2 | PERPLL_M2;
 240         writel(div_m2, &cmwkup->divm2dpllper);
 241
 242         clkmode = clkmode | CLK_MODE_SEL;
 243         writel(clkmode, &cmwkup->clkmoddpllper);
 244
 245         while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 246                 ;
 247 }
 248
 249 static void ddr_pll_config(void)
 250 {
 251         u32 clkmode, clksel, div_m2;
 252
 253         clkmode = readl(&cmwkup->clkmoddpllddr);
 254         clksel = readl(&cmwkup->clkseldpllddr);
 255         div_m2 = readl(&cmwkup->divm2dpllddr);
 256
 257         /* Set the PLL to bypass Mode */
 258         clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
 259         writel(clkmode, &cmwkup->clkmoddpllddr);
 260
 261         /* Wait till bypass mode is enabled */
 262         while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
 263                                 != ST_MN_BYPASS)
 264                 ;
 265
 266         clksel = clksel & (~CLK_SEL_MASK);
 267         clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
 268         writel(clksel, &cmwkup->clkseldpllddr);
 269
 270         div_m2 = div_m2 & CLK_DIV_SEL;
 271         div_m2 = div_m2 | DDRPLL_M2;
 272         writel(div_m2, &cmwkup->divm2dpllddr);
 273
 274         clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
 275         writel(clkmode, &cmwkup->clkmoddpllddr);
 276
 277         /* Wait till dpll is locked */
 278         while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
 279                 ;
 280 }
 281
 282 void enable_emif_clocks(void)
 283 {
 284         /* Enable the  EMIF_FW Functional clock */
 285         writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 286         /* Enable EMIF0 Clock */
 287         writel(PRCM_MOD_EN, &cmper->emifclkctrl);
 288         /* Poll for emif_gclk  & L3_G clock  are active */
 289         while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
 290                         PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
 291                         PRCM_L3_GCLK_ACTIVITY))
 292                 ;
 293         /* Poll if module is functional */
 294         while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 295                 ;
 296 }
 297
 298 /*
 299  * Configure the PLL/PRCM for necessary peripherals
 300  */
 301 void pll_init()
 302 {
 303         mpu_pll_config();
 304         core_pll_config();
 305         per_pll_config();
 306         ddr_pll_config();
 307
 308         /* Enable the required interconnect clocks */
 309         enable_interface_clocks();
 310
 311         /* Power domain wake up transition */
 312         power_domain_wkup_transition();
 313
 314         /* Enable the required peripherals */
 315         enable_per_clocks();
 316 }