arch/arm/cpu/armv7/am33xx/clock.c

   1 /*
   2  * clock.c
   3  *
   4  * clocks for AM33XX based boards
   5  *
   6  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/io.h>
  24
  25 #define PRCM_MOD_EN             0x2
  26 #define PRCM_FORCE_WAKEUP       0x2
  27
  28 #define PRCM_EMIF_CLK_ACTIVITY  BIT(2)
  29 #define PRCM_L3_GCLK_ACTIVITY   BIT(4)
  30
  31 #define PLL_BYPASS_MODE         0x4
  32 #define ST_MN_BYPASS            0x00000100
  33 #define ST_DPLL_CLK             0x00000001
  34 #define CLK_SEL_MASK            0x7ffff
  35 #define CLK_DIV_MASK            0x1f
  36 #define CLK_DIV2_MASK           0x7f
  37 #define CLK_SEL_SHIFT           0x8
  38 #define CLK_MODE_SEL            0x7
  39 #define CLK_MODE_MASK           0xfffffff8
  40 #define CLK_DIV_SEL             0xFFFFFFE0
  41
  42
  43 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  44 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  45 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  46
  47 static void enable_interface_clocks(void)
  48 {
  49         /* Enable all the Interconnect Modules */
  50         writel(PRCM_MOD_EN, &cmper->l3clkctrl);
  51         while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
  52                 ;
  53
  54         writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
  55         while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
  56                 ;
  57
  58         writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
  59         while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
  60                 ;
  61
  62         writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
  63         while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
  64                 ;
  65
  66         writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
  67         while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
  68                 ;
  69
  70         writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
  71         while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
  72                 ;
  73 }
  74
  75 /*
  76  * Force power domain wake up transition
  77  * Ensure that the corresponding interface clock is active before
  78  * using the peripheral
  79  */
  80 static void power_domain_wkup_transition(void)
  81 {
  82         writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
  83         writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
  84         writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
  85         writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
  86         writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
  87 }
  88
  89 /*
  90  * Enable the peripheral clock for required peripherals
  91  */
  92 static void enable_per_clocks(void)
  93 {
  94         /* Enable the control module though RBL would have done it*/
  95         writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
  96         while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
  97                 ;
  98
  99         /* Enable the module clock */
 100         writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
 101         while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 102                 ;
 103
 104         /* UART0 */
 105         writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 106         while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 107                 ;
 108 }
 109
 110 static void mpu_pll_config(void)
 111 {
 112         u32 clkmode, clksel, div_m2;
 113
 114         clkmode = readl(&cmwkup->clkmoddpllmpu);
 115         clksel = readl(&cmwkup->clkseldpllmpu);
 116         div_m2 = readl(&cmwkup->divm2dpllmpu);
 117
 118         /* Set the PLL to bypass Mode */
 119         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 120         while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
 121                 ;
 122
 123         clksel = clksel & (~CLK_SEL_MASK);
 124         clksel = clksel | ((MPUPLL_M << CLK_SEL_SHIFT) | MPUPLL_N);
 125         writel(clksel, &cmwkup->clkseldpllmpu);
 126
 127         div_m2 = div_m2 & ~CLK_DIV_MASK;
 128         div_m2 = div_m2 | MPUPLL_M2;
 129         writel(div_m2, &cmwkup->divm2dpllmpu);
 130
 131         clkmode = clkmode | CLK_MODE_SEL;
 132         writel(clkmode, &cmwkup->clkmoddpllmpu);
 133
 134         while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
 135                 ;
 136 }
 137
 138 static void core_pll_config(void)
 139 {
 140         u32 clkmode, clksel, div_m4, div_m5, div_m6;
 141
 142         clkmode = readl(&cmwkup->clkmoddpllcore);
 143         clksel = readl(&cmwkup->clkseldpllcore);
 144         div_m4 = readl(&cmwkup->divm4dpllcore);
 145         div_m5 = readl(&cmwkup->divm5dpllcore);
 146         div_m6 = readl(&cmwkup->divm6dpllcore);
 147
 148         /* Set the PLL to bypass Mode */
 149         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
 150
 151         while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
 152                 ;
 153
 154         clksel = clksel & (~CLK_SEL_MASK);
 155         clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
 156         writel(clksel, &cmwkup->clkseldpllcore);
 157
 158         div_m4 = div_m4 & ~CLK_DIV_MASK;
 159         div_m4 = div_m4 | COREPLL_M4;
 160         writel(div_m4, &cmwkup->divm4dpllcore);
 161
 162         div_m5 = div_m5 & ~CLK_DIV_MASK;
 163         div_m5 = div_m5 | COREPLL_M5;
 164         writel(div_m5, &cmwkup->divm5dpllcore);
 165
 166         div_m6 = div_m6 & ~CLK_DIV_MASK;
 167         div_m6 = div_m6 | COREPLL_M6;
 168         writel(div_m6, &cmwkup->divm6dpllcore);
 169
 170         clkmode = clkmode | CLK_MODE_SEL;
 171         writel(clkmode, &cmwkup->clkmoddpllcore);
 172
 173         while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
 174                 ;
 175 }
 176
 177 static void per_pll_config(void)
 178 {
 179         u32 clkmode, clksel, div_m2;
 180
 181         clkmode = readl(&cmwkup->clkmoddpllper);
 182         clksel = readl(&cmwkup->clkseldpllper);
 183         div_m2 = readl(&cmwkup->divm2dpllper);
 184
 185         /* Set the PLL to bypass Mode */
 186         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
 187
 188         while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
 189                 ;
 190
 191         clksel = clksel & (~CLK_SEL_MASK);
 192         clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
 193         writel(clksel, &cmwkup->clkseldpllper);
 194
 195         div_m2 = div_m2 & ~CLK_DIV2_MASK;
 196         div_m2 = div_m2 | PERPLL_M2;
 197         writel(div_m2, &cmwkup->divm2dpllper);
 198
 199         clkmode = clkmode | CLK_MODE_SEL;
 200         writel(clkmode, &cmwkup->clkmoddpllper);
 201
 202         while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 203                 ;
 204 }
 205
 206 static void ddr_pll_config(void)
 207 {
 208         u32 clkmode, clksel, div_m2;
 209
 210         clkmode = readl(&cmwkup->clkmoddpllddr);
 211         clksel = readl(&cmwkup->clkseldpllddr);
 212         div_m2 = readl(&cmwkup->divm2dpllddr);
 213
 214         /* Set the PLL to bypass Mode */
 215         clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
 216         writel(clkmode, &cmwkup->clkmoddpllddr);
 217
 218         /* Wait till bypass mode is enabled */
 219         while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
 220                                 != ST_MN_BYPASS)
 221                 ;
 222
 223         clksel = clksel & (~CLK_SEL_MASK);
 224         clksel = clksel | ((DDRPLL_M << CLK_SEL_SHIFT) | DDRPLL_N);
 225         writel(clksel, &cmwkup->clkseldpllddr);
 226
 227         div_m2 = div_m2 & CLK_DIV_SEL;
 228         div_m2 = div_m2 | DDRPLL_M2;
 229         writel(div_m2, &cmwkup->divm2dpllddr);
 230
 231         clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
 232         writel(clkmode, &cmwkup->clkmoddpllddr);
 233
 234         /* Wait till dpll is locked */
 235         while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
 236                 ;
 237 }
 238
 239 void enable_emif_clocks(void)
 240 {
 241         /* Enable the  EMIF_FW Functional clock */
 242         writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 243         /* Enable EMIF0 Clock */
 244         writel(PRCM_MOD_EN, &cmper->emifclkctrl);
 245         /* Poll for emif_gclk  & L3_G clock  are active */
 246         while ((readl(&cmper->l3clkstctrl) & (PRCM_EMIF_CLK_ACTIVITY |
 247                         PRCM_L3_GCLK_ACTIVITY)) != (PRCM_EMIF_CLK_ACTIVITY |
 248                         PRCM_L3_GCLK_ACTIVITY))
 249                 ;
 250         /* Poll if module is functional */
 251         while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 252                 ;
 253 }
 254
 255 /*
 256  * Configure the PLL/PRCM for necessary peripherals
 257  */
 258 void pll_init()
 259 {
 260         mpu_pll_config();
 261         core_pll_config();
 262         per_pll_config();
 263         ddr_pll_config();
 264
 265         /* Enable the required interconnect clocks */
 266         enable_interface_clocks();
 267
 268         /* Power domain wake up transition */
 269         power_domain_wkup_transition();
 270
 271         /* Enable the required peripherals */
 272         enable_per_clocks();
 273 }