arch/arm/cpu/armv7/am33xx/clock_am33xx.c

   1 /*
   2  * clock_am33xx.c
   3  *
   4  * clocks for AM33XX based boards
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <common.h>
  20 #include <asm/arch/cpu.h>
  21 #include <asm/arch/clock.h>
  22 #include <asm/arch/hardware.h>
  23 #include <asm/io.h>
  24
  25 #define PRCM_MOD_EN             0x2
  26 #define PRCM_FORCE_WAKEUP       0x2
  27 #define PRCM_FUNCTL             0x0
  28
  29 #define PRCM_EMIF_CLK_ACTIVITY  BIT(2)
  30 #define PRCM_L3_GCLK_ACTIVITY   BIT(4)
  31
  32 #define PLL_BYPASS_MODE         0x4
  33 #define ST_MN_BYPASS            0x00000100
  34 #define ST_DPLL_CLK             0x00000001
  35 #define CLK_SEL_MASK            0x7ffff
  36 #define CLK_DIV_MASK            0x1f
  37 #define CLK_DIV2_MASK           0x7f
  38 #define CLK_SEL_SHIFT           0x8
  39 #define CLK_MODE_SEL            0x7
  40 #define CLK_MODE_MASK           0xfffffff8
  41 #define CLK_DIV_SEL             0xFFFFFFE0
  42 #define CPGMAC0_IDLE            0x30000
  43 #define DPLL_CLKDCOLDO_GATE_CTRL        0x300
  44
  45 #define OSC     (V_OSCK/1000000)
  46
  47 #define MPUPLL_M        CONFIG_SYS_MPUCLK
  48 #define MPUPLL_N        (OSC-1)
  49 #define MPUPLL_M2       1
  50
  51 /* Core PLL Fdll = 1 GHZ, */
  52 #define COREPLL_M       1000
  53 #define COREPLL_N       (OSC-1)
  54
  55 #define COREPLL_M4      10      /* CORE_CLKOUTM4 = 200 MHZ */
  56 #define COREPLL_M5      8       /* CORE_CLKOUTM5 = 250 MHZ */
  57 #define COREPLL_M6      4       /* CORE_CLKOUTM6 = 500 MHZ */
  58
  59 /*
  60  * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
  61  * frequency needs to be set to 960 MHZ. Hence,
  62  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
  63  */
  64 #define PERPLL_M        960
  65 #define PERPLL_N        (OSC-1)
  66 #define PERPLL_M2       5
  67
  68 /* DDR Freq is 266 MHZ for now */
  69 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
  70 #define DDRPLL_M        266
  71 #define DDRPLL_N        (OSC-1)
  72 #define DDRPLL_M2       1
  73
  74 const struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
  75 const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
  76 const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
  77 const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC;
  78
  79 static void enable_interface_clocks(void)
  80 {
  81         /* Enable all the Interconnect Modules */
  82         writel(PRCM_MOD_EN, &cmper->l3clkctrl);
  83         while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN)
  84                 ;
  85
  86         writel(PRCM_MOD_EN, &cmper->l4lsclkctrl);
  87         while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN)
  88                 ;
  89
  90         writel(PRCM_MOD_EN, &cmper->l4fwclkctrl);
  91         while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN)
  92                 ;
  93
  94         writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl);
  95         while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN)
  96                 ;
  97
  98         writel(PRCM_MOD_EN, &cmper->l3instrclkctrl);
  99         while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN)
 100                 ;
 101
 102         writel(PRCM_MOD_EN, &cmper->l4hsclkctrl);
 103         while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN)
 104                 ;
 105
 106         writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl);
 107         while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN)
 108                 ;
 109 }
 110
 111 /*
 112  * Force power domain wake up transition
 113  * Ensure that the corresponding interface clock is active before
 114  * using the peripheral
 115  */
 116 static void power_domain_wkup_transition(void)
 117 {
 118         writel(PRCM_FORCE_WAKEUP, &cmper->l3clkstctrl);
 119         writel(PRCM_FORCE_WAKEUP, &cmper->l4lsclkstctrl);
 120         writel(PRCM_FORCE_WAKEUP, &cmwkup->wkclkstctrl);
 121         writel(PRCM_FORCE_WAKEUP, &cmper->l4fwclkstctrl);
 122         writel(PRCM_FORCE_WAKEUP, &cmper->l3sclkstctrl);
 123 }
 124
 125 /*
 126  * Enable the peripheral clock for required peripherals
 127  */
 128 static void enable_per_clocks(void)
 129 {
 130         /* Enable the control module though RBL would have done it*/
 131         writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl);
 132         while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN)
 133                 ;
 134
 135         /* Enable the module clock */
 136         writel(PRCM_MOD_EN, &cmper->timer2clkctrl);
 137         while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN)
 138                 ;
 139
 140         /* Select the Master osc 24 MHZ as Timer2 clock source */
 141         writel(0x1, &cmdpll->clktimer2clk);
 142
 143         /* UART0 */
 144         writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl);
 145         while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN)
 146                 ;
 147
 148         /* UART1 */
 149 #ifdef CONFIG_SERIAL2
 150         writel(PRCM_MOD_EN, &cmper->uart1clkctrl);
 151         while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN)
 152                 ;
 153 #endif /* CONFIG_SERIAL2 */
 154
 155         /* UART2 */
 156 #ifdef CONFIG_SERIAL3
 157         writel(PRCM_MOD_EN, &cmper->uart2clkctrl);
 158         while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN)
 159                 ;
 160 #endif /* CONFIG_SERIAL3 */
 161
 162         /* UART3 */
 163 #ifdef CONFIG_SERIAL4
 164         writel(PRCM_MOD_EN, &cmper->uart3clkctrl);
 165         while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN)
 166                 ;
 167 #endif /* CONFIG_SERIAL4 */
 168
 169         /* UART4 */
 170 #ifdef CONFIG_SERIAL5
 171         writel(PRCM_MOD_EN, &cmper->uart4clkctrl);
 172         while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN)
 173                 ;
 174 #endif /* CONFIG_SERIAL5 */
 175
 176         /* UART5 */
 177 #ifdef CONFIG_SERIAL6
 178         writel(PRCM_MOD_EN, &cmper->uart5clkctrl);
 179         while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN)
 180                 ;
 181 #endif /* CONFIG_SERIAL6 */
 182
 183         /* GPMC */
 184         writel(PRCM_MOD_EN, &cmper->gpmcclkctrl);
 185         while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN)
 186                 ;
 187
 188         /* ELM */
 189         writel(PRCM_MOD_EN, &cmper->elmclkctrl);
 190         while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN)
 191                 ;
 192
 193         /* MMC0*/
 194         writel(PRCM_MOD_EN, &cmper->mmc0clkctrl);
 195         while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN)
 196                 ;
 197
 198         /* MMC1 */
 199         writel(PRCM_MOD_EN, &cmper->mmc1clkctrl);
 200         while (readl(&cmper->mmc1clkctrl) != PRCM_MOD_EN)
 201                 ;
 202
 203         /* i2c0 */
 204         writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl);
 205         while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN)
 206                 ;
 207
 208         /* gpio1 module */
 209         writel(PRCM_MOD_EN, &cmper->gpio1clkctrl);
 210         while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN)
 211                 ;
 212
 213         /* gpio2 module */
 214         writel(PRCM_MOD_EN, &cmper->gpio2clkctrl);
 215         while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN)
 216                 ;
 217
 218         /* gpio3 module */
 219         writel(PRCM_MOD_EN, &cmper->gpio3clkctrl);
 220         while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN)
 221                 ;
 222
 223         /* i2c1 */
 224         writel(PRCM_MOD_EN, &cmper->i2c1clkctrl);
 225         while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN)
 226                 ;
 227
 228         /* Ethernet */
 229         writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl);
 230         while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL)
 231                 ;
 232
 233         /* spi0 */
 234         writel(PRCM_MOD_EN, &cmper->spi0clkctrl);
 235         while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN)
 236                 ;
 237
 238         /* RTC */
 239         writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl);
 240         while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN)
 241                 ;
 242
 243         /* MUSB */
 244         writel(PRCM_MOD_EN, &cmper->usb0clkctrl);
 245         while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN)
 246                 ;
 247 }
 248
 249 void mpu_pll_config_val(int mpull_m)
 250 {
 251         u32 clkmode, clksel, div_m2;
 252
 253         clkmode = readl(&cmwkup->clkmoddpllmpu);
 254         clksel = readl(&cmwkup->clkseldpllmpu);
 255         div_m2 = readl(&cmwkup->divm2dpllmpu);
 256
 257         /* Set the PLL to bypass Mode */
 258         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllmpu);
 259         while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS)
 260                 ;
 261
 262         clksel = clksel & (~CLK_SEL_MASK);
 263         clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N);
 264         writel(clksel, &cmwkup->clkseldpllmpu);
 265
 266         div_m2 = div_m2 & ~CLK_DIV_MASK;
 267         div_m2 = div_m2 | MPUPLL_M2;
 268         writel(div_m2, &cmwkup->divm2dpllmpu);
 269
 270         clkmode = clkmode | CLK_MODE_SEL;
 271         writel(clkmode, &cmwkup->clkmoddpllmpu);
 272
 273         while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK)
 274                 ;
 275 }
 276
 277 static void mpu_pll_config(void)
 278 {
 279         mpu_pll_config_val(CONFIG_SYS_MPUCLK);
 280 }
 281
 282 static void core_pll_config(void)
 283 {
 284         u32 clkmode, clksel, div_m4, div_m5, div_m6;
 285
 286         clkmode = readl(&cmwkup->clkmoddpllcore);
 287         clksel = readl(&cmwkup->clkseldpllcore);
 288         div_m4 = readl(&cmwkup->divm4dpllcore);
 289         div_m5 = readl(&cmwkup->divm5dpllcore);
 290         div_m6 = readl(&cmwkup->divm6dpllcore);
 291
 292         /* Set the PLL to bypass Mode */
 293         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
 294
 295         while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
 296                 ;
 297
 298         clksel = clksel & (~CLK_SEL_MASK);
 299         clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
 300         writel(clksel, &cmwkup->clkseldpllcore);
 301
 302         div_m4 = div_m4 & ~CLK_DIV_MASK;
 303         div_m4 = div_m4 | COREPLL_M4;
 304         writel(div_m4, &cmwkup->divm4dpllcore);
 305
 306         div_m5 = div_m5 & ~CLK_DIV_MASK;
 307         div_m5 = div_m5 | COREPLL_M5;
 308         writel(div_m5, &cmwkup->divm5dpllcore);
 309
 310         div_m6 = div_m6 & ~CLK_DIV_MASK;
 311         div_m6 = div_m6 | COREPLL_M6;
 312         writel(div_m6, &cmwkup->divm6dpllcore);
 313
 314         clkmode = clkmode | CLK_MODE_SEL;
 315         writel(clkmode, &cmwkup->clkmoddpllcore);
 316
 317         while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
 318                 ;
 319 }
 320
 321 static void per_pll_config(void)
 322 {
 323         u32 clkmode, clksel, div_m2;
 324
 325         clkmode = readl(&cmwkup->clkmoddpllper);
 326         clksel = readl(&cmwkup->clkseldpllper);
 327         div_m2 = readl(&cmwkup->divm2dpllper);
 328
 329         /* Set the PLL to bypass Mode */
 330         writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllper);
 331
 332         while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS)
 333                 ;
 334
 335         clksel = clksel & (~CLK_SEL_MASK);
 336         clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N);
 337         writel(clksel, &cmwkup->clkseldpllper);
 338
 339         div_m2 = div_m2 & ~CLK_DIV2_MASK;
 340         div_m2 = div_m2 | PERPLL_M2;
 341         writel(div_m2, &cmwkup->divm2dpllper);
 342
 343         clkmode = clkmode | CLK_MODE_SEL;
 344         writel(clkmode, &cmwkup->clkmoddpllper);
 345
 346         while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK)
 347                 ;
 348
 349         writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper);
 350 }
 351
 352 void ddr_pll_config(unsigned int ddrpll_m)
 353 {
 354         u32 clkmode, clksel, div_m2;
 355
 356         clkmode = readl(&cmwkup->clkmoddpllddr);
 357         clksel = readl(&cmwkup->clkseldpllddr);
 358         div_m2 = readl(&cmwkup->divm2dpllddr);
 359
 360         /* Set the PLL to bypass Mode */
 361         clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE;
 362         writel(clkmode, &cmwkup->clkmoddpllddr);
 363
 364         /* Wait till bypass mode is enabled */
 365         while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)
 366                                 != ST_MN_BYPASS)
 367                 ;
 368
 369         clksel = clksel & (~CLK_SEL_MASK);
 370         clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N);
 371         writel(clksel, &cmwkup->clkseldpllddr);
 372
 373         div_m2 = div_m2 & CLK_DIV_SEL;
 374         div_m2 = div_m2 | DDRPLL_M2;
 375         writel(div_m2, &cmwkup->divm2dpllddr);
 376
 377         clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL;
 378         writel(clkmode, &cmwkup->clkmoddpllddr);
 379
 380         /* Wait till dpll is locked */
 381         while ((readl(&cmwkup->idlestdpllddr) & ST_DPLL_CLK) != ST_DPLL_CLK)
 382                 ;
 383 }
 384
 385 void enable_emif_clocks(void)
 386 {
 387         /* Enable the  EMIF_FW Functional clock */
 388         writel(PRCM_MOD_EN, &cmper->emiffwclkctrl);
 389         /* Enable EMIF0 Clock */
 390         writel(PRCM_MOD_EN, &cmper->emifclkctrl);
 391         /* Poll if module is functional */
 392         while ((readl(&cmper->emifclkctrl)) != PRCM_MOD_EN)
 393                 ;
 394 }
 395
 396 /*
 397  * Configure the PLL/PRCM for necessary peripherals
 398  */
 399 void pll_init()
 400 {
 401         mpu_pll_config();
 402         core_pll_config();
 403         per_pll_config();
 404
 405         /* Enable the required interconnect clocks */
 406         enable_interface_clocks();
 407
 408         /* Power domain wake up transition */
 409         power_domain_wkup_transition();
 410
 411         /* Enable the required peripherals */
 412         enable_per_clocks();
 413 }