2 * DDR Configuration for AM33xx devices.
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/ddr_defs.h>
11 #include <asm/arch/sys_proto.h>
16 * Base address for EMIF instances
18 static struct emif_reg_struct *emif_reg[2] = {
19 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
20 (struct emif_reg_struct *)EMIF4_1_CFG_BASE,
24 * Base addresses for DDR PHY cmd/data regs
26 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
27 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
28 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2,
31 static struct ddr_data_regs *ddr_data_reg[2] = {
32 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
33 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2,
37 * Base address for ddr io control instances
39 static struct ddr_cmdtctrl *ioctrl_reg =
40 (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR;
42 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
46 mr_addr |= cs << EMIF_REG_CS_SHIFT;
47 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
49 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
50 debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
51 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) &&
52 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
53 ((mr & 0xff000000) >> 24) == (mr & 0xff))
59 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
61 mr_addr |= cs << EMIF_REG_CS_SHIFT;
62 writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
63 writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
66 static void configure_mr(int nr, u32 cs)
70 while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
72 set_mr(nr, cs, LPDDR2_MR10, 0x56);
74 set_mr(nr, cs, LPDDR2_MR1, 0x43);
75 set_mr(nr, cs, LPDDR2_MR2, 0x2);
77 mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
78 set_mr(nr, cs, mr_addr, 0x2);
82 * Configure EMIF4D5 registers and MR registers For details about these magic
83 * values please see the EMIF registers section of the TRM.
85 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
87 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
88 writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
89 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
91 writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
92 writel(regs->emif_rd_wr_lvl_rmp_win,
93 &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
94 writel(regs->emif_rd_wr_lvl_rmp_ctl,
95 &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
96 writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
97 writel(regs->emif_rd_wr_exec_thresh,
98 &emif_reg[nr]->emif_rd_wr_exec_thresh);
101 * for most SOCs these registers won't need to be changed so only
102 * write to these registers if someone explicitly has set the
105 if(regs->emif_cos_config) {
106 writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
107 writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
108 writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
109 writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
113 * Sequence to ensure that the PHY is in a known state prior to
114 * startting hardware leveling. Also acts as to latch some state from
115 * the EMIF into the PHY.
117 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
118 writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
119 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
121 clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
122 EMIF_REG_INITREF_DIS_MASK);
124 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
125 writel(regs->sdram_config, &cstat->emif_sdram_config);
126 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
127 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
129 /* Perform hardware leveling for DDR3 */
130 if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) {
132 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
133 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
134 writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
135 0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
137 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
139 /* Enable read leveling */
140 writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
143 * Enable full read and write leveling. Wait for read and write
144 * leveling bit to clear RDWRLVLFULL_START bit 31
146 while ((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000)
150 /* Check the timeout register to see if leveling is complete */
151 if ((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
152 puts("DDR3 H/W leveling incomplete with errors\n");
164 void config_sdram(const struct emif_regs *regs, int nr)
166 if (regs->zq_config) {
167 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
168 writel(regs->sdram_config, &cstat->emif_sdram_config);
169 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
170 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
171 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
173 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
174 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
175 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
181 void set_sdram_timings(const struct emif_regs *regs, int nr)
183 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
184 writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
185 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
186 writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
187 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
188 writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
192 * Configure EXT PHY registers for software leveling
194 static void ext_phy_settings_swlvl(const struct emif_regs *regs, int nr)
196 u32 *ext_phy_ctrl_base = 0;
197 u32 *emif_ext_phy_ctrl_base = 0;
198 __maybe_unused const u32 *ext_phy_ctrl_const_regs;
200 __maybe_unused u32 size;
202 ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
203 emif_ext_phy_ctrl_base =
204 (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
206 /* Configure external phy control timing registers */
207 for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
208 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
209 /* Update shadow registers */
210 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
215 * External phy 6-24 registers do not change with ddr frequency.
216 * These only need to be set on DDR2 on AM43xx.
218 emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
223 for (i = 0; i < size; i++) {
224 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
225 /* Update shadow registers */
226 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
232 * Configure EXT PHY registers for hardware leveling
234 static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr)
237 * Enable hardware leveling on the EMIF. For details about these
238 * magic values please see the EMIF registers section of the TRM.
240 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
241 writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
242 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
243 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
244 writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
245 writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
246 writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
247 writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
248 writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
249 writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
250 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
251 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
252 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
253 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
254 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
255 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
256 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
257 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
258 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
259 writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
260 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
261 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
262 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
263 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
264 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
265 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
266 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
267 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
268 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
269 writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
270 writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
271 writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
274 * Sequence to ensure that the PHY is again in a known state after
277 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
278 writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
279 writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
285 void config_ddr_phy(const struct emif_regs *regs, int nr)
288 * Disable initialization and refreshes for now until we
289 * finish programming EMIF regs.
290 * Also set time between rising edge of DDR_RESET to rising
291 * edge of DDR_CKE to > 500us per memory spec.
293 #ifndef CONFIG_AM43XX
294 setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
295 EMIF_REG_INITREF_DIS_MASK);
298 writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
300 writel(regs->emif_ddr_phy_ctlr_1,
301 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
302 writel(regs->emif_ddr_phy_ctlr_1,
303 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
305 if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5) {
306 if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3)
307 ext_phy_settings_hwlvl(regs, nr);
309 ext_phy_settings_swlvl(regs, nr);
314 * Configure DDR CMD control registers
316 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
321 writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
322 writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
324 writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
325 writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
327 writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
328 writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
332 * Configure DDR DATA registers
334 void config_ddr_data(const struct ddr_data *data, int nr)
341 for (i = 0; i < DDR_DATA_REGS_NR; i++) {
342 writel(data->datardsratio0,
343 &(ddr_data_reg[nr]+i)->dt0rdsratio0);
344 writel(data->datawdsratio0,
345 &(ddr_data_reg[nr]+i)->dt0wdsratio0);
346 writel(data->datawiratio0,
347 &(ddr_data_reg[nr]+i)->dt0wiratio0);
348 writel(data->datagiratio0,
349 &(ddr_data_reg[nr]+i)->dt0giratio0);
350 writel(data->datafwsratio0,
351 &(ddr_data_reg[nr]+i)->dt0fwsratio0);
352 writel(data->datawrsratio0,
353 &(ddr_data_reg[nr]+i)->dt0wrsratio0);
357 void config_io_ctrl(const struct ctrl_ioregs *ioregs)
362 writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
363 writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
364 writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
365 writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
366 writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
368 writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
369 writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
370 writel(ioregs->emif_sdram_config_ext,
371 &ioctrl_reg->emif_sdram_config_ext);