arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated -
   5 http://www.ti.com/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/io.h>
  22 #include <asm/emif.h>
  23
  24 /**
  25  * Base address for EMIF instances
  26  */
  27 static struct emif_reg_struct *emif_reg = {
  28                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
  29
  30 /**
  31  * Base address for DDR instance
  32  */
  33 static struct ddr_regs *ddr_reg[2] = {
  34                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR,
  35                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
  36
  37 /**
  38  * Base address for ddr io control instances
  39  */
  40 static struct ddr_cmdtctrl *ioctrl_reg = {
  41                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  42
  43 /**
  44  * Configure SDRAM
  45  */
  46 void config_sdram(const struct emif_regs *regs)
  47 {
  48         if (regs->zq_config) {
  49                 /*
  50                  * A value of 0x2800 for the REF CTRL will give us
  51                  * about 570us for a delay, which will be long enough
  52                  * to configure things.
  53                  */
  54                 writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
  55                 writel(regs->zq_config, &emif_reg->emif_zq_config);
  56                 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
  57         }
  58         writel(regs->sdram_config, &emif_reg->emif_sdram_config);
  59         writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
  60         writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
  61 }
  62
  63 /**
  64  * Set SDRAM timings
  65  */
  66 void set_sdram_timings(const struct emif_regs *regs)
  67 {
  68         writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
  69         writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
  70         writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
  71         writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
  72         writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
  73         writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
  74 }
  75
  76 /**
  77  * Configure DDR PHY
  78  */
  79 void config_ddr_phy(const struct emif_regs *regs)
  80 {
  81         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
  82         writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
  83 }
  84
  85 /**
  86  * Configure DDR CMD control registers
  87  */
  88 void config_cmd_ctrl(const struct cmd_control *cmd)
  89 {
  90         writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
  91         writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
  92         writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
  93
  94         writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
  95         writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
  96         writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
  97
  98         writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
  99         writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
 100         writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
 101 }
 102
 103 /**
 104  * Configure DDR DATA registers
 105  */
 106 void config_ddr_data(int macrono, const struct ddr_data *data)
 107 {
 108         writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
 109         writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
 110         writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
 111         writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
 112         writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
 113         writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
 114         writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
 115         writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 116 }
 117
 118 void config_io_ctrl(unsigned long val)
 119 {
 120         writel(val, &ioctrl_reg->cm0ioctl);
 121         writel(val, &ioctrl_reg->cm1ioctl);
 122         writel(val, &ioctrl_reg->cm2ioctl);
 123         writel(val, &ioctrl_reg->dt0ioctl);
 124         writel(val, &ioctrl_reg->dt1ioctl);
 125 }