arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/cpu.h>
  10 #include <asm/arch/ddr_defs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13 #include <asm/emif.h>
  14
  15 /**
  16  * Base address for EMIF instances
  17  */
  18 static struct emif_reg_struct *emif_reg[2] = {
  19                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  20                                 (struct emif_reg_struct *)EMIF4_1_CFG_BASE,
  21 };
  22
  23 /**
  24  * Base addresses for DDR PHY cmd/data regs
  25  */
  26 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  27                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  28                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2,
  29 };
  30
  31 static struct ddr_data_regs *ddr_data_reg[2] = {
  32                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  33                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2,
  34 };
  35
  36 /**
  37  * Base address for ddr io control instances
  38  */
  39 static struct ddr_cmdtctrl *ioctrl_reg =
  40                                 (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR;
  41
  42 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  43 {
  44         u32 mr;
  45
  46         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  47         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  48
  49         mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  50         debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  51         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  52             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  53             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  54                 return mr & 0xff;
  55         else
  56                 return mr;
  57 }
  58
  59 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  60 {
  61         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  62         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  63         writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  64 }
  65
  66 static void configure_mr(int nr, u32 cs)
  67 {
  68         u32 mr_addr;
  69
  70         while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  71                 ;
  72         set_mr(nr, cs, LPDDR2_MR10, 0x56);
  73
  74         set_mr(nr, cs, LPDDR2_MR1, 0x43);
  75         set_mr(nr, cs, LPDDR2_MR2, 0x2);
  76
  77         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  78         set_mr(nr, cs, mr_addr, 0x2);
  79 }
  80
  81 /*
  82  * Configure EMIF4D5 registers and MR registers For details about these magic
  83  * values please see the EMIF registers section of the TRM.
  84  */
  85 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  86 {
  87         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  88         writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  89         writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  90
  91         writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  92         writel(regs->emif_rd_wr_lvl_rmp_win,
  93                &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  94         writel(regs->emif_rd_wr_lvl_rmp_ctl,
  95                &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  96         writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  97         writel(regs->emif_rd_wr_exec_thresh,
  98                &emif_reg[nr]->emif_rd_wr_exec_thresh);
  99
 100         /*
 101          * for most SOCs these registers won't need to be changed so only
 102          * write to these registers if someone explicitly has set the
 103          * register's value.
 104          */
 105         if(regs->emif_cos_config) {
 106                 writel(regs->emif_prio_class_serv_map, &emif_reg[nr]->emif_prio_class_serv_map);
 107                 writel(regs->emif_connect_id_serv_1_map, &emif_reg[nr]->emif_connect_id_serv_1_map);
 108                 writel(regs->emif_connect_id_serv_2_map, &emif_reg[nr]->emif_connect_id_serv_2_map);
 109                 writel(regs->emif_cos_config, &emif_reg[nr]->emif_cos_config);
 110         }
 111
 112         /*
 113          * Sequence to ensure that the PHY is in a known state prior to
 114          * startting hardware leveling.  Also acts as to latch some state from
 115          * the EMIF into the PHY.
 116          */
 117         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 118         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 119         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 120
 121         clrbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 122                         EMIF_REG_INITREF_DIS_MASK);
 123
 124         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 125         writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 126         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 127         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 128
 129         /* Perform hardware leveling. */
 130         udelay(1000);
 131         writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
 132                0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 133         writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw) |
 134                0x100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 135
 136         writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
 137
 138         /* Enable read leveling */
 139         writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
 140
 141         /*
 142          * Enable full read and write leveling.  Wait for read and write
 143          * leveling bit to clear RDWRLVLFULL_START bit 31
 144          */
 145         while((readl(&emif_reg[nr]->emif_rd_wr_lvl_ctl) & 0x80000000) != 0)
 146                 ;
 147
 148         /* Check the timeout register to see if leveling is complete */
 149         if((readl(&emif_reg[nr]->emif_status) & 0x70) != 0)
 150                 puts("DDR3 H/W leveling incomplete with errors\n");
 151
 152         if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2) {
 153                 configure_mr(nr, 0);
 154                 configure_mr(nr, 1);
 155         }
 156 }
 157
 158 /**
 159  * Configure SDRAM
 160  */
 161 void config_sdram(const struct emif_regs *regs, int nr)
 162 {
 163         if (regs->zq_config) {
 164                 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 165                 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 166                 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 167                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 168                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 169         }
 170         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 171         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 172         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 173 }
 174
 175 /**
 176  * Set SDRAM timings
 177  */
 178 void set_sdram_timings(const struct emif_regs *regs, int nr)
 179 {
 180         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
 181         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
 182         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
 183         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
 184         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
 185         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 186 }
 187
 188 /*
 189  * Configure EXT PHY registers for hardware leveling
 190  */
 191 static void ext_phy_settings(const struct emif_regs *regs, int nr)
 192 {
 193         /*
 194          * Enable hardware leveling on the EMIF.  For details about these
 195          * magic values please see the EMIF registers section of the TRM.
 196          */
 197         writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 198         writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw);
 199         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22);
 200         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw);
 201         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
 202         writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23_shdw);
 203         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24);
 204         writel(0x40010080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_24_shdw);
 205         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25);
 206         writel(0x08102040, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_25_shdw);
 207         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26);
 208         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_26_shdw);
 209         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27);
 210         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_27_shdw);
 211         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28);
 212         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_28_shdw);
 213         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29);
 214         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_29_shdw);
 215         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30);
 216         writel(0x00200020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_30_shdw);
 217         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31);
 218         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_31_shdw);
 219         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32);
 220         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_32_shdw);
 221         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33);
 222         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_33_shdw);
 223         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34);
 224         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw);
 225         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35);
 226         writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw);
 227         writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36);
 228         writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
 229
 230         /*
 231          * Sequence to ensure that the PHY is again in a known state after
 232          * hardware leveling.
 233          */
 234         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 235         writel(0x2411, &emif_reg[nr]->emif_iodft_tlgc);
 236         writel(0x2011, &emif_reg[nr]->emif_iodft_tlgc);
 237 }
 238
 239 /**
 240  * Configure DDR PHY
 241  */
 242 void config_ddr_phy(const struct emif_regs *regs, int nr)
 243 {
 244         /*
 245          * Disable initialization and refreshes for now until we
 246          * finish programming EMIF regs.
 247          * Also set time between rising edge of DDR_RESET to rising
 248          * edge of DDR_CKE to > 500us per memory spec.
 249          */
 250 #ifndef CONFIG_AM43XX
 251         setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 252                      EMIF_REG_INITREF_DIS_MASK);
 253 #endif
 254         if (regs->zq_config)
 255                 writel(0x80003100, &emif_reg[nr]->emif_sdram_ref_ctrl);
 256
 257         writel(regs->emif_ddr_phy_ctlr_1,
 258                 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 259         writel(regs->emif_ddr_phy_ctlr_1,
 260                 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 261
 262         if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
 263                 ext_phy_settings(regs, nr);
 264 }
 265
 266 /**
 267  * Configure DDR CMD control registers
 268  */
 269 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 270 {
 271         if (!cmd)
 272                 return;
 273
 274         writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 275         writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 276
 277         writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
 278         writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 279
 280         writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
 281         writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 282 }
 283
 284 /**
 285  * Configure DDR DATA registers
 286  */
 287 void config_ddr_data(const struct ddr_data *data, int nr)
 288 {
 289         int i;
 290
 291         if (!data)
 292                 return;
 293
 294         for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 295                 writel(data->datardsratio0,
 296                         &(ddr_data_reg[nr]+i)->dt0rdsratio0);
 297                 writel(data->datawdsratio0,
 298                         &(ddr_data_reg[nr]+i)->dt0wdsratio0);
 299                 writel(data->datawiratio0,
 300                         &(ddr_data_reg[nr]+i)->dt0wiratio0);
 301                 writel(data->datagiratio0,
 302                         &(ddr_data_reg[nr]+i)->dt0giratio0);
 303                 writel(data->datafwsratio0,
 304                         &(ddr_data_reg[nr]+i)->dt0fwsratio0);
 305                 writel(data->datawrsratio0,
 306                         &(ddr_data_reg[nr]+i)->dt0wrsratio0);
 307         }
 308 }
 309
 310 void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 311 {
 312         if (!ioregs)
 313                 return;
 314
 315         writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
 316         writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
 317         writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
 318         writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
 319         writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
 320 #ifdef CONFIG_AM43XX
 321         writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
 322         writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
 323         writel(ioregs->emif_sdram_config_ext,
 324                &ioctrl_reg->emif_sdram_config_ext);
 325 #endif
 326 }