arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated -
   5 http://www.ti.com/
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13  * kind, whether express or implied; without even the implied warranty
  14  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/ddr_defs.h>
  20 #include <asm/io.h>
  21 #include <asm/emif.h>
  22
  23 /**
  24  * Base address for EMIF instances
  25  */
  26 static struct emif_reg_struct *emif_reg = {
  27                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE};
  28
  29 /**
  30  * Base address for DDR instance
  31  */
  32 static struct ddr_regs *ddr_reg[2] = {
  33                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR,
  34                                 (struct ddr_regs *)DDR_PHY_BASE_ADDR2};
  35
  36 /**
  37  * Base address for ddr io control instances
  38  */
  39 static struct ddr_cmdtctrl *ioctrl_reg = {
  40                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  41
  42 /**
  43  * As a convention, all functions here return 0 on success
  44  * -1 on failure.
  45  */
  46
  47 /**
  48  * Configure SDRAM
  49  */
  50 int config_sdram(struct sdram_config *cfg)
  51 {
  52         writel(cfg->sdrcr, &emif_reg->emif_sdram_config);
  53         writel(cfg->sdrcr2, &emif_reg->emif_lpddr2_nvm_config);
  54         writel(cfg->refresh, &emif_reg->emif_sdram_ref_ctrl);
  55         writel(cfg->refresh_sh, &emif_reg->emif_sdram_ref_ctrl_shdw);
  56
  57         return 0;
  58 }
  59
  60 /**
  61  * Set SDRAM timings
  62  */
  63 int set_sdram_timings(struct sdram_timing *t)
  64 {
  65         writel(t->time1, &emif_reg->emif_sdram_tim_1);
  66         writel(t->time1_sh, &emif_reg->emif_sdram_tim_1_shdw);
  67         writel(t->time2, &emif_reg->emif_sdram_tim_2);
  68         writel(t->time2_sh, &emif_reg->emif_sdram_tim_2_shdw);
  69         writel(t->time3, &emif_reg->emif_sdram_tim_3);
  70         writel(t->time3_sh, &emif_reg->emif_sdram_tim_3_shdw);
  71
  72         return 0;
  73 }
  74
  75 /**
  76  * Configure DDR PHY
  77  */
  78 int config_ddr_phy(struct ddr_phy_control *p)
  79 {
  80         writel(p->reg, &emif_reg->emif_ddr_phy_ctrl_1);
  81         writel(p->reg_sh, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
  82
  83         return 0;
  84 }
  85
  86 /**
  87  * Configure DDR CMD control registers
  88  */
  89 int config_cmd_ctrl(struct cmd_control *cmd)
  90 {
  91         writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
  92         writel(cmd->cmd0csforce, &ddr_reg[0]->cm0csforce);
  93         writel(cmd->cmd0csdelay, &ddr_reg[0]->cm0csdelay);
  94         writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
  95         writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
  96
  97         writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
  98         writel(cmd->cmd1csforce, &ddr_reg[0]->cm1csforce);
  99         writel(cmd->cmd1csdelay, &ddr_reg[0]->cm1csdelay);
 100         writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
 101         writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
 102
 103         writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
 104         writel(cmd->cmd2csforce, &ddr_reg[0]->cm2csforce);
 105         writel(cmd->cmd2csdelay, &ddr_reg[0]->cm2csdelay);
 106         writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
 107         writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
 108
 109         return 0;
 110 }
 111
 112 /**
 113  * Configure DDR DATA registers
 114  */
 115 int config_ddr_data(int macrono, struct ddr_data *data)
 116 {
 117         writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
 118         writel(data->datardsratio1, &ddr_reg[macrono]->dt0rdsratio1);
 119
 120         writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
 121         writel(data->datawdsratio1, &ddr_reg[macrono]->dt0wdsratio1);
 122
 123         writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
 124         writel(data->datawiratio1, &ddr_reg[macrono]->dt0wiratio1);
 125         writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
 126         writel(data->datagiratio1, &ddr_reg[macrono]->dt0giratio1);
 127
 128         writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
 129         writel(data->datafwsratio1, &ddr_reg[macrono]->dt0fwsratio1);
 130
 131         writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
 132         writel(data->datawrsratio1, &ddr_reg[macrono]->dt0wrsratio1);
 133
 134         writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
 135
 136         return 0;
 137 }
 138
 139 int config_io_ctrl(struct ddr_ioctrl *ioctrl)
 140 {
 141         writel(ioctrl->cmd1ctl, &ioctrl_reg->cm0ioctl);
 142         writel(ioctrl->cmd2ctl, &ioctrl_reg->cm1ioctl);
 143         writel(ioctrl->cmd3ctl, &ioctrl_reg->cm2ioctl);
 144         writel(ioctrl->data1ctl, &ioctrl_reg->dt0ioctl);
 145         writel(ioctrl->data2ctl, &ioctrl_reg->dt1ioctl);
 146
 147         return 0;
 148 }